February 1998 ML4621 Data Quantizer GENERAL DESCRIPTION FEATURES The ML4621 data quantizer is a low noise, wideband monolithic IC designed specifically for signal recovery applications in fiber-optic receiver systems. It contains a two stage wideband limiting amplifier which is capable of accepting an input signal as low as 2mV with a 55dB dynamic range. This high level of sensitivity is achieved by using a DC restoration feedback loop which nulls any offset voltage produced in the limiting amplifier. ■ 50MHz minimum bandwidth for data rates of up to 100MBd ■ Can be powered by either 5V providing TTL level outputs, or -5.2V providing ECL level outputs ■ Low noise design: 25µV RMS over 50MHz noise bandwidth The output stage is a high speed comparator circuit with both TTL and ECL outputs. An enable pin is included for added control. ■ Adjustable link monitor function ■ Wide 55dB input dynamic range The minimum signal discriminator circuit provides a link monitor function with a user selectable reference voltage. This circuit monitors the peaks of the input signal and provides a logic level output indicating when the input falls below an acceptable level. This output can be used to disable the quantizer and/or drive an LED, providing a visible link status. ■ 10ns minimum input pulse BLOCK DIAGRAM (Pin Configuration Shown is for PLCC Version) 10 9 CF1 6 5 VIN+ VIN– VDC 8 23 22 VREF VTHADJ w e N r o f 4 2 6 4 L /M 2 2 6 4 L M s n ig s De e e S e s a e l P A1 DC AMP 12 CF2 11 VOUT+ 13 VOUT– 14 CMP+ 17 CMP– 16 ECL+ ECL– VCC TTL 28 19 TTL OUT TTL CMP ECL CMP A2 VCC 20 CMP ENABLE 3 FILTER REF ECL LINK MON MINIMUM SIGNAL DISCRIMINATOR THRESHOLD GENERATOR 27 INOM 26 ISET 1 TTL LINK MON 2 24 CPEAK GND TTL 18 GND 21 1 ML4621 PIN CONFIGURATION ML4621 24-Pin Narrow DIP (P24N) ECL LINK MON 1 24 VCC TTL LINK MON 2 23 INOM CMP ENABLE 3 22 ISET VIN– 4 21 CPEAK VIN+ 5 20 VREF VDC 6 19 VTH ADJ CF2 7 18 GND CF1 8 17 TTL OUT VOUT– 9 16 VCC TTL VOUT+ 10 15 GND TTL CMP+ 11 14 ECL+ CMP– 12 13 ECL– TOP VIEW 26 ISET VIN– 5 25 NC VIN+ 6 24 CPEAK NC 7 23 VREF VDC 8 22 VTH ADJ CF2 9 21 GND GND TTL 18 ECL+ 17 ECL– 16 NC 15 19 VCC TTL CMP– 14 VOUT– 11 CMP+ 13 20 TTL OUT VOUT+ 12 CF1 10 TOP VIEW 2 27 INOM 28 VCC 1 ECL LINK MON 2 TTL LINK MON 3 CMP ENABLE 4 NC ML4621 28-Pin PLCC (Q28) ML4621 PIN DESCRIPTION (Pin Number in Parenthesis is for DIP Version) PIN NAME 1 (1) ECL LINK MON ECL link monitor output. Signal is low when the VIN+ and VIN– inputs exceed the minimum threshold set by a voltage on VTH ADJ. Signal is high when input signal level is below that threshold. 2 (2) TTL LINK MON TTL link monitor output. Same logic function as the ECL LINK MON. Capable of driving a 10mA LED indicator. This pin is normally tied to CMP ENABLE. 3 (3) 5 (4) 6 (5) 8 (6) 9 (7) CMP ENABLE V IN – VIN+ VDC CF2 FUNCTION Low voltage at this TTL input enables both the ECL and TTL outputs. A high TTL voltage disables the comparator output with ECL+ high, ECL– low, and TTL OUT high. This input should be capacitively coupled to the input source or to ground. (Input resistance is approximately 8kΩ). This input should be capacitively coupled to the input source or to ground. (Input resistance is approximately 8kΩ). An external capacitor on this pin integrates an error signal which nulls the offset of the input amplifier. If the DC feedback loop is not being used, this pin should be connected to VREF. A capacitor from this pin to ground controls the maximum bandwidth of the amplifier to accommodate lower operating frequencies. 10 (8) CF1 The capacitor on this pin should match the one on CF2. 11 (9) VOUT- Negative output of the amplifier, which is normally tied to CMP–. 12 (10) VOUT+ Positive output of the amplifier, which is normally tied to CMP+. 13 (11) CMP+ Comparator input pin. Open base configuration relies on the DC bias of the amp output to set proper DC operating voltage. Reestablish voltage if filtering is used between VOUT+ and CMP+. PIN NAME FUNCTION 14(12) CMP– Comparator input pin. Open base configuration relies on the DC bias of the amp output to set the proper DC operating voltage. Reestablish voltage if filtering is used between VOUT– and CMP–. 16(13) ECL– ECL comparator negative output. 17(14) ECL+ ECL comparator positive outout. 18(15) GND TTL Negative supply for the TTL comparator stage. If the TTL output is not necessary, connect GND TTL and VCC TTL to VCC. 19(16) VCC TTL Positive supply for the TTL comparator stage. If the TTL output is not necessary, connect GND TTL and VCC TTL to VCC. 20(17) TTL OUT TTL data output (totem pole type output stage). 21(18) GND Negative supply. Connect to – 5.2V for ECL operation, or to source ground for TTL operation. 22(19) VTH ADJ This input sets the minimum amplitude of the input signal required to cause the link monitors to go low. 23(20) V REF A 2.5V reference with respect to GND. 24(21) CPEAK A capacitor from this pin to GND determines the link monitor response time. 26(22) I SET Current into an internal diode connected between this pin and GND is turned around and pulled from CPEAK. This pin is normally connected to INOM. 27(23) I NOM Sets a current of approximately 125µA when connected to ISET. 28(24) VCC Positive supply. Connect to source ground for ECL operation, or to 5V for TTL operation. 3 ML4621 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Lead Temperature (Soldering, 10 sec) ..................... 260°C Thermal Resistance (θJA) 24 Pin Narrow PDIP ......................................... 54°C/W 28 Pin PLCC ..................................................... 68°C/W VCC – GND ................................................ –0.3V to 7.0V VCC TTL – GND TTL ................................... –0.3V to 7.0V GND ............................................... –0.3V to VCC + 0.3V Junction Temperature .............................................. 150°C Storage Temperature Range ..................... –65°C to 150°C OPERATING CONDITIONS Temperature Range ....................................... 0°C to 70°C –5.2V Supply Range ...................................... –5.2V ± 5% +5V Supply Range ......................................... 5.0V ± 5% ELECTRICAL CHARACTERISTICS Unless otherwise specified, VCC = 5V ± 5%, GND = 0V, TA = Operating Temperature Range (Note 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS I CC1 VCC Supply Current VCC TTL = GND TTL = VCC 65 100 mA I CC2 VCC Supply Current (TTL OUT Enabled) VCC TTL = VCC GND TTL = GND 70 110 mA IVREF VREF Output Current –5.0 0.5 mA VREF Reference Voltage 2.40 2.65 V AV A1, A2 Amplifier Gain VIN Input Signal Range 2 1400 mVP-P External Voltage at VTH ADJ to set VTH 1 2.5 V VTH ADJ Range VIN = 5mV 2.55 VOS Input Offset VDC = VREF (DC Loop Inactive) EN Input Referred Noise 50MHz BW BW 3dB Bandwidth VIN PW RIN 75 50 Minimum Input Pulsewidth V/V 3 mV 25 µV 65 MHz 10 ns 8 kΩ Input Resistance VIN+, VIN– tPD AMP Amplifier Propagation Delay Time From VIN+, VIN– to VOUT+, VOUT– VIN+, = 10mVP-P 4 8 ns tPD ECL ECL Comparator Propagation Delay Time From CMP+, CMP– to ECL+, ECL– VIN+, = 10mVP-P 4 8 ns tPD TTL TTL Comparator Propagation Delay Time From ECL+, ECL– to TTL OUT VIN+, = 10mVP-P 4 8 ns RVTH ADJ VTH ADJ Input Resistance IVOUT VOUT+, VOUT– Output Current I CMP CMP+, CMP– Leakage Current 6.8 kΩ 3 25 VCM CMP CMP+, CMP– Common Mode Range mA µA GND + 2 VCC – 1 V ECL VOH ECL+, ECL– Output High Voltage With 200Ω Load Tied to VCC – 2V TA = 25ºC 3.90 4.30 V ECL VOL ECL+, ECL– Output Low Voltage With 200Ω Load Tied to VCC – 2V TA = 25ºC 3.11 3.38 V 4 ML4621 ELECTRICAL CHARACTERISTICS SYMBOL AV ECL PARAMETER (Continued) CONDITIONS ECL CMP Gain TYP MAX 100 TTL VOH TTL Output High Voltage VCC TTL = 5V, IOH = –50µA TTL VOL TTL Output Low Voltage VCC TTL = 5V, IOL = 2mA TTL VIH TTL Input High Voltage Level TTL VIL TTL Input Low Voltage Level TTL IIH TTL Input High Current Level VIH = 2.4V TTL IIL TTL Input Low Current Level VIH = 0.4V INOM MIN V/V 2.4 V 0.4 2.0 INOM = ISET UNITS V V 0.8 V –50 50 µA –1.6 0 mA 125 µA Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions. 5 ML4621 FUNCTIONAL DESCRIPTION the stability of the feedback loop. The value of this capacitor should be at least 100 times smaller than the input coupling capacitors to avoid stability problems using the ML4621. AMPLIFIER The quantizer has a two stage limiting amplifier with an input common mode range of (GND + 1.8V) to (VCC – 1.5V). Maximum sensitivity is achieved through the use of a DC restoration feedback loop and AC coupling on the input. The input DC bias voltage is set by an on-chip network at about 1.9V when it is AC coupled. These coupling capacitors, in conjunction with the input impedance of the amplifier, establish a highpass filter with a 3dB corner frequency, fL, at: 1 fL = 2π ¥ 8000 ¥ C The output of the ML4621 amplifier is isolated from the comparator and made available to the user. This allows the user to add circuitry between the amplifier and the comparator for wave shaping and other signal conditioning. COMPARATOR (1) Two types of comparators are employed in the output section of these quantizers. The high speed ECL comparator is used to provide the ECL level outputs, and in turn drives the TTL comparator. The enable pin, CMP ENABLE, is provided to control the ECL comparator. When CMP ENABLE is low the comparators function normally. When it is high it forces ECL+ high, ECL– low, and TTL OUT high. The CMP ENABLE pin can be controlled with TTL level signals when the quantizer is powered by 5V and ground. Two capacitors of equal value are required since the amplifier has a differential input. One of the coupling capacitors can be tied to VCC as shown in Figure 1 if the signal driving the input is single ended. The high corner frequency can also be adjusted by attaching capacitors to CF1 and CF2. The equation for adjusting this corner is: fH = 1 2π ¥ 425 ¥ C (2) LINK MONITOR The offset voltage within the amplifier will be present at the amplifier’s output even though the input is AC coupled. This is represented by VOS in Figure 2. In order to reduce this error a DC feedback loop is incorporated. This negative feedback loop nulls the offset voltage, forcing VOS to be zero. An external capacitor at VDC is used to store the offset voltage. Although the value of this capacitor is noncritical, the pole it creates can affect This function is implemented by the minimum signal discriminator and the threshold generator circuits. The purpose of this function is to monitor the input signal and provide a status signal indicating when the input falls below a preset voltage level. This is done by peak detecting the output of the amplifier section and comparing this level with the voltage at VTHADJ. 470Ω 5V 0.001µF ISET INOM VCC VIN+ 7 NC 8 VDC 9 CF2 GND 10 CF1 TTL OUT 11 VOUT– VCC TTL NC CPEAK VREF VTH ADJ GND TTL ECL+ ECL– NC ML4621 CMP– 18pF VIN– 6 CMP+ 18pF 1 28 27 26 5 VOUT+ 0.5µF 2 ECL LINK MON 0.1µF 3 CMP ENABLE NC 4 TTL LINK MON 5V 25 24 23 22 21 20 19 12 13 14 15 16 17 18 Figure 1. ML4621 Configured for 20MHz Bandwidth with TTL Output 6 0.1µF ML4621 FUNCTIONAL DESCRIPTION (Continued) VREF VOUT+ REF R1 VTHADJ THRESHOLD GENERATOR VOS R2 VOUT– Figure 2. Figure 3. The equation which determines the droop rate of the peak detector is: dV IISET = dt C (3) In this equation C is the peak capacitor at CPEAK. On the ML4621 the droop rate of the peak detector can be adjusted two ways: 1) By adjusting the value of the peak capacitor at CPEAK. 2) By adjusting the charge current into the peak capacitor at ISET. The charge current, IISET, can be controlled externally by connecting a resistor, REXT, between ISET and VCC. IISET will then be: IISET = VCC – 0.7 REXT + 1700 (4) For convenience an on-chip current source of 125µA is available by connecting INOM to ISET. The threshold generator level-shifts the reference voltage at VTHADJ through a circuit which has a temperature coefficient matching that of the limiting amplifier. The relationship between VTHADJ and VTH (the minimum peak voltage at the input which will trigger the link monitor) is: b g VTHADJ = 600 ¥ VTH + 0.7 Since the ML4621 has a relatively low input impedance of 6.8kΩ and is offset by one diode drop, the equation which accounts for the load and offset is: VTH ADJ = cb g b gh 6800 ¥ bR + R g + R ¥ R R 2 ¥ 6800 ¥ VREF + 0.7 ¥ R1 1 2 1 (6) 2 THRESHOLD ADJUSTMENT EXAMPLE To make the link monitor trigger when the received optical power goes below 1µW (-30dBm), you first need to calculate the resultant voltage at VIN+ and VIN–. If a Hewlett-Packard HFBR-24X6 fiber-optic receiver with a responsive level of 8mV/µW is used, the peak-to-peak voltage would be: 1µW ¥ 8mV = 8mVP -P µW (7) Then the link monitor should trigger at some point slightly lower than 4mV peak. Setting VTH in Equation 5 to 3mV and solving for VTHADJ yields: VTHADJ = (600 × 0.003) + 0.7 = 2.5V (8) This is a convenient value since the reference voltage supplied by the quantizer, VREF, is 2.5V. The link monitor has about 0.4mV (peak) hysteresis built-in. More hysteresis can be induced by connecting a resistor between TTL LINK MON and VTHADJ creating a positive feedback loop. (5) The on-chip reference voltage, VREF, can be tied directly to VTHADJ to set the threshold level. This will set the minimum input signal on the ML4621 at about 3mV (peak). A lower threshold level can be set by dividing down VREF with a resistor string, as in Figure 3. Refer to Micro Linear’s Application Note 6 for more detail. 7 ML4621 PHYSICAL DIMENSIONS inches (millimeters) Package: P24N 24-Pin Narrow PDIP 1.240 - 1.260 (31.49 - 32.01) 24 0.240 - 0.270 0.295 - 0.325 (6.09 - 6.86) (7.49 - 8.26) PIN 1 ID 0.070 MIN (1.77 MIN) (4 PLACES) 1 0.050 - 0.065 (1.27 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN) 0.170 MAX (4.32 MAX) 0.016 - 0.022 (0.40 - 0.56) 0.125 MIN (3.18 MIN) SEATING PLANE 0.008 - 0.012 (0.20 - 0.31) 0º - 15º Package: Q28 28-Pin PLCC 0.485 - 0.495 (12.32 - 12.57) 0.042 - 0.056 (1.07 - 1.42) 0.450 - 0.456 (11.43 - 11.58) 0.025 - 0.045 (0.63 - 1.14) (RADIUS) 1 0.042 - 0.048 (1.07 - 1.22) PIN 1 ID 8 22 0.300 BSC (7.62 BSC) 0.450 - 0.456 0.485 - 0.495 (11.43 - 11.58) (12.32 - 12.57) 0.390 - 0.430 (9.90 - 10.92) 15 0.009 - 0.011 (0.23 - 0.28) 0.050 BSC (1.27 BSC) 0.026 - 0.032 (0.66 - 0.81) 0.013 - 0.021 (0.33 - 0.53) 0.165 - 0.180 (4.06 - 4.57) 0.148 - 0.156 (3.76 - 3.96) 0.099 - 0.110 (2.51 - 2.79) SEATING PLANE ORDERING INFORMATION © Micro Linear 1998. PART NUMBER TEMPERATURE RANGE PACKAGE ML4621CP ML4621CQ 0°C to 70°C 0°C to 70°C 24 Pin Narrow PDIP (P24N) 28 Pin PLCC (Q28) is a registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners. Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798. Japan: 2,598,946; 2,619,299; 2,704,176. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application. 8 2092 Concourse Drive San Jose, CA 95131 Tel: (408) 433-5200 Fax: (408) 432-0295 www.microlinear.com 2/27/98 Printed in U.S.A.