Freescale Semiconductor Data Sheet: Technical Data K60 Sub-Family Document Number: K60P144M150SF3 Rev. 4, 10/2012 K60P144M150SF3 Supports the following: MK60FX512VLQ15, MK60FN1M0VLQ15, MK60FX512VMD15, MK60FN1M0VMD15 Features • Operating Characteristics – Voltage range: 1.71 to 3.6 V – Flash write voltage range: 1.71 to 3.6 V – Temperature range (ambient): -40 to 105°C • Performance – Up to 150 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz • Memories and memory interfaces – Up to 1024 KB program flash memory on nonFlexMemory devices – Up to 512 KB program flash memory on FlexMemory devices – Up to 512 KB FlexNVM on FlexMemory devices – 16 KB FlexRAM on FlexMemory devices – Up to 128 KB RAM – Serial programming interface (EzPort) – FlexBus external bus interface – NAND flash controller interface • Clocks – 3 to 32 MHz crystal oscillator – 32 kHz crystal oscillator – Multi-purpose clock generator • System peripherals – Multiple low-power modes to provide power optimization based on application requirements – Memory protection unit with multi-master protection – 32-channel DMA controller, supporting up to 128 request sources – External watchdog monitor – Software watchdog – Low-leakage wakeup unit • Security and integrity modules – Hardware CRC module to support fast cyclic redundancy checks – Hardware random-number generator – Hardware encryption supporting DES, 3DES, AES, MD5, SHA-1, and SHA-256 algorithms – 128-bit unique identification (ID) number per chip • Human-machine interface – Low-power hardware touch sensor interface (TSI) – General-purpose input/output • Analog modules – Four 16-bit SAR ADCs – Programmable gain amplifier (PGA) (up to x64) integrated into each ADC – Two 12-bit DACs – Four analog comparators (CMP) containing a 6-bit DAC and programmable reference input – Voltage reference • Timers – Programmable delay block – Two 8-channel motor control/general purpose/PWM timers – Two 2-channel quadrature decoder/general purpose timers – IEEE 1588 timers – Periodic interrupt timers – 16-bit low-power timer – Carrier modulator transmitter – Real-time clock Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2012 Freescale Semiconductor, Inc. • Communication interfaces – Ethernet controller with MII and RMII interface to external PHY and hardware IEEE 1588 capability – USB high-/full-/low-speed On-the-Go controller with ULPI interface – USB full-/low-speed On-the-Go controller with on-chip transceiver – Two Controller Area Network (CAN) modules – Three SPI modules – Two I2C modules – Six UART modules – Secure Digital host controller (SDHC) – Two I2S modules K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 2 Freescale Semiconductor, Inc. Table of Contents 1 Ordering parts...........................................................................5 5.4.2 Thermal attributes...............................................23 1.1 Determining valid orderable parts......................................5 5.5 Power sequencing.............................................................24 2 Part identification......................................................................5 6 Peripheral operating requirements and behaviors....................24 2.1 Description.........................................................................5 6.1 Core modules....................................................................24 2.2 Format...............................................................................5 6.1.1 Debug trace timing specifications.......................25 2.3 Fields.................................................................................5 6.1.2 JTAG electricals..................................................25 2.4 Example............................................................................6 6.2 System modules................................................................28 3 Terminology and guidelines......................................................6 6.3 Clock modules...................................................................28 3.1 Definition: Operating requirement......................................6 6.3.1 MCG specifications.............................................28 3.2 Definition: Operating behavior...........................................6 6.3.2 Oscillator electrical specifications.......................31 3.3 Definition: Attribute............................................................7 6.3.3 32 kHz Oscillator Electrical Characteristics........33 3.4 Definition: Rating...............................................................7 6.4 Memories and memory interfaces.....................................34 3.5 Result of exceeding a rating..............................................8 6.4.1 Flash (FTFE) electrical specifications.................34 3.6 Relationship between ratings and operating 6.4.2 EzPort Switching Specifications.........................38 requirements......................................................................8 6.4.3 NFC specifications..............................................39 3.7 Guidelines for ratings and operating requirements............9 6.4.4 Flexbus Switching Specifications........................42 3.8 Definition: Typical value.....................................................9 6.5 Security and integrity modules..........................................45 3.9 Typical value conditions....................................................10 6.6 Analog...............................................................................45 4 Ratings......................................................................................10 6.6.1 ADC electrical specifications..............................45 4.1 Thermal handling ratings...................................................10 6.6.2 CMP and 6-bit DAC electrical specifications......53 4.2 Moisture handling ratings..................................................11 6.6.3 12-bit DAC electrical characteristics...................56 4.3 ESD handling ratings.........................................................11 6.6.4 Voltage reference electrical specifications..........59 4.4 Voltage and current operating ratings...............................11 6.7 Timers................................................................................60 5 General.....................................................................................12 6.8 Communication interfaces.................................................60 5.1 AC electrical characteristics..............................................12 6.8.1 Ethernet switching specifications........................60 5.2 Nonswitching electrical specifications...............................12 6.8.2 USB electrical specifications...............................62 5.2.1 Voltage and current operating requirements......12 6.8.3 USB DCD electrical specifications......................62 5.2.2 LVD and POR operating requirements...............13 6.8.4 USB VREG electrical specifications...................63 5.2.3 Voltage and current operating behaviors............14 6.8.5 ULPI timing specifications...................................63 5.2.4 Power mode transition operating behaviors.......15 6.8.6 CAN switching specifications..............................64 5.2.5 Power consumption operating behaviors............16 6.8.7 DSPI switching specifications (limited voltage 5.2.6 EMC radiated emissions operating behaviors....19 5.2.7 Designing with radiated emissions in mind.........20 5.2.8 Capacitance attributes........................................20 5.3 Switching specifications.....................................................20 range).................................................................65 6.8.8 DSPI switching specifications (full voltage range).................................................................66 6.8.9 I2C switching specifications................................68 5.3.1 Device clock specifications.................................20 6.8.10 UART switching specifications............................68 5.3.2 General switching specifications.........................21 6.8.11 SDHC specifications...........................................68 5.4 Thermal specifications.......................................................23 6.8.12 I2S/SAI Switching Specifications........................70 5.4.1 Thermal operating requirements.........................23 6.9 Human-machine interfaces (HMI)......................................76 K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 3 6.9.1 TSI electrical specifications................................76 8.1 Pins with active pull control after reset..............................77 7 Dimensions...............................................................................77 8.2 K60 Signal Multiplexing and Pin Assignments..................78 7.1 Obtaining package dimensions.........................................77 8.3 K60 Pinouts.......................................................................84 8 Pinout........................................................................................77 9 Revision History........................................................................86 K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 4 Freescale Semiconductor, Inc. Ordering parts 1 Ordering parts 1.1 Determining valid orderable parts Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to www.freescale.com and perform a part number search for the following device numbers: PK60 and MK60. 2 Part identification 2.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 2.2 Format Part numbers for this device have the following format: Q K## A M FFF T PP CC N 2.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow • P = Prequalification K## Kinetis family • K60 A Key attribute • F = Cortex-M4 w/ DSP and FPU M Flash memory type • N = Program flash only • X = Program flash and FlexMemory FFF Program flash memory size • 512 = 512 KB • 1M0 = 1 MB Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 5 Terminology and guidelines Field Description Values T Temperature range (°C) • V = –40 to 105 • C = –40 to 85 PP Package identifier • LQ = 144 LQFP (20 mm x 20 mm) • MD = 144 MAPBGA (13 mm x 13 mm) CC Maximum CPU frequency (MHz) • 15 = 150 MHz N Packaging type • R = Tape and reel • (Blank) = Trays 2.4 Example This is an example part number: MK60FN1M0VLQ15 3 Terminology and guidelines 3.1 Definition: Operating requirement An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. 3.1.1 Example This is an example of an operating requirement, which you must meet for the accompanying operating behaviors to be guaranteed: Symbol VDD Description 1.0 V core supply voltage Min. 0.9 Max. 1.1 Unit V K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 6 Freescale Semiconductor, Inc. Terminology and guidelines 3.2 Definition: Operating behavior An operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. 3.2.1 Example This is an example of an operating behavior, which is guaranteed if you meet the accompanying operating requirements: Symbol IWP Description Min. Digital I/O weak pullup/ 10 pulldown current Max. 130 Unit µA 3.3 Definition: Attribute An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 3.3.1 Example This is an example of an attribute: Symbol CIN_D Description Input capacitance: digital pins Min. — Max. 7 Unit pF 3.4 Definition: Rating A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: • Operating ratings apply during operation of the chip. • Handling ratings apply when the chip is not powered. K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 7 Terminology and guidelines 3.4.1 Example This is an example of an operating rating: Symbol VDD Description Min. 1.0 V core supply voltage Max. –0.3 Unit 1.2 V 3.5 Result of exceeding a rating 40 Failures in time (ppm) 30 The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. 20 10 0 Operating rating Measured characteristic 3.6 Relationship between ratings and operating requirements ra pe tin gr g tin ( in. t (m ) n. mi a gr tin ra pe ) O O t (m e ir qu e n me gr tin O ra pe ax .) e ir qu e n me a gr tin ra pe g tin ax (m .) O Fatal range Degraded operating range Normal operating range Degraded operating range Fatal range Expected permanent failure - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Correct operation - No permanent failure - Possible decreased life - Possible incorrect operation Expected permanent failure –∞ ∞ Operating (power on) n Ha ng dli ng ati ) in. (m r nd Ha g lin ing rat ax (m .) Fatal range Handling range Fatal range Expected permanent failure No permanent failure Expected permanent failure –∞ Handling (power off) ∞ K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 8 Freescale Semiconductor, Inc. Terminology and guidelines 3.7 Guidelines for ratings and operating requirements Follow these guidelines for ratings and operating requirements: • Never exceed any of the chip’s ratings. • During normal operation, don’t exceed any of the chip’s operating requirements. • If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 3.8 Definition: Typical value A typical value is a specified value for a technical characteristic that: • Lies within the range of values specified by the operating behavior • Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. 3.8.1 Example 1 This is an example of an operating behavior that includes a typical value: Symbol IWP Description Digital I/O weak pullup/pulldown current Min. 10 Typ. 70 Max. 130 Unit µA 3.8.2 Example 2 This is an example of a chart that shows typical values for various voltage and temperature conditions: K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 9 Ratings 5000 4500 4000 TJ IDD_STOP (μA) 3500 150 °C 3000 105 °C 2500 25 °C 2000 –40 °C 1500 1000 500 0 0.90 0.95 1.00 1.05 1.10 VDD (V) 3.9 Typical value conditions Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD 3.3 V supply voltage 3.3 V 4 Ratings 4.1 Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 10 Freescale Semiconductor, Inc. Ratings 4.2 Moisture handling ratings Symbol MSL Description Moisture sensitivity level Min. Max. Unit Notes — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 4.3 ESD handling ratings Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 Latch-up current at ambient temperature of 105°C -100 +100 mA ILAT 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 4.4 Voltage and current operating ratings Symbol Description Min. Max. Unit VDD Digital supply voltage1 –0.3 3.8 V IDD Digital supply current — 300 mA VDIO Digital input voltage (except RESET, EXTAL0/XTAL0, and EXTAL1/XTAL1) 2 –0.3 5.5 V VAIO Analog3, RESET, EXTAL0/XTAL0, and EXTAL1/XTAL1 input voltage –0.3 VDD + 0.3 V Maximum current single pin limit (applies to all digital pins) –25 25 mA ID VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V VUSB_DP USB_DP input voltage –0.3 3.63 V VUSB_DM USB_DM input voltage –0.3 3.63 V VREGIN USB regulator input –0.3 6.0 V RTC battery supply voltage –0.3 3.8 V VBAT 1. It applies for all port pins. 2. It covers digital pins. 3. Analog pins are defined as pins that do not have an associated general purpose I/O port function. K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 11 General 5 General 5.1 AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. Figure 1. Input signal measurement reference All digital I/O switching characteristics assume: 1. output pins • have CL=30pF loads, • are configured for fast slew rate (PORTx_PCRn[SRE]=0), and • are configured for high drive strength (PORTx_PCRn[DSE]=1) 2. input pins • have their passive filter disabled (PORTx_PCRn[PFE]=0) 5.2 Nonswitching electrical specifications 5.2.1 Voltage and current operating requirements Table 1. Voltage and current operating requirements Symbol Description Min. Max. Unit VDD VDDA Supply voltage 2.0 3.6 V Analog supply voltage 1.71 3.6 V VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V 1.71 3.6 V VBAT RTC battery supply voltage Notes Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 12 Freescale Semiconductor, Inc. General Table 1. Voltage and current operating requirements (continued) Symbol Min. Max. Unit • 2.7 V ≤ VDD ≤ 3.6 V 0.7 × VDD — V • 1.7 V ≤ VDD ≤ 2.7 V 0.75 × VDD — V • 2.7 V ≤ VDD ≤ 3.6 V — 0.35 × VDD V • 1.7 V ≤ VDD ≤ 2.7 V — 0.3 × VDD V VHYS Input hysteresis (digital pins) 0.06 × VDD — V IICDIO Digital pin negative DC injection current — single pin -5 — mA VIH VIL Description Input high voltage (digital pins) Input low voltage (digital pins) 1 • VIN < VSS-0.3V IICAIO IICcont Analog2, EXTAL0/XTAL0, and EXTAL1/XTAL1 pin DC injection current — single pin 3 mA • VIN < VSS-0.3V (Negative current injection) -5 — • VIN > VDD+0.3V (Positive current injection) — +5 -25 — — +25 1.2 — V VPOR_VBAT — V Contiguous pin DC injection current —regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins • Negative current injection • Positive current injection VRAM VRFVBAT Notes VDD voltage required to retain RAM VBAT voltage required to retain the VBAT register file mA 1. All 5 V tolerant digital I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN greater than VDIO_MIN (=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IIC|. 2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. 3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is greater than VAIO_MIN (=VSS-0.3V) and VIN is less than VAIO_MAX(=VDD+0.3V) is observed, then there is no need to provide current limiting resistors at the pads. If these limits cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VAIO_MIN-VIN)/|IIC|. The positive injection current limiting resistor is calculated as R=(VIN-VAIO_MAX)/|IIC|. Select the larger of these two calculated resistances. 5.2.2 LVD and POR operating requirements Table 2. LVD and POR operating requirements Symbol Description Min. Typ. Max. Unit VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V VLVDH Falling low-voltage detect threshold — high range (LVDV=01) 2.48 2.56 2.64 V Notes Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 13 General Table 2. LVD and POR operating requirements (continued) Symbol Description Min. Typ. Max. Unit Low-voltage warning thresholds — high range 1 VLVW1H • Level 1 falling (LVWV=00) 2.62 2.70 2.78 V VLVW2H • Level 2 falling (LVWV=01) 2.72 2.80 2.88 V VLVW3H • Level 3 falling (LVWV=10) 2.82 2.90 2.98 V VLVW4H • Level 4 falling (LVWV=11) 2.92 3.00 3.08 V — ±80 — mV 1.54 1.60 1.66 V VHYSH Low-voltage inhibit reset/recover hysteresis — high range VLVDL Falling low-voltage detect threshold — low range (LVDV=00) Low-voltage warning thresholds — low range 1 VLVW1L • Level 1 falling (LVWV=00) 1.74 1.80 1.86 V VLVW2L • Level 2 falling (LVWV=01) 1.84 1.90 1.96 V VLVW3L • Level 3 falling (LVWV=10) 1.94 2.00 2.06 V VLVW4L • Level 4 falling (LVWV=11) 2.04 2.10 2.16 V — ±60 — mV VHYSL Low-voltage inhibit reset/recover hysteresis — low range Notes VBG Bandgap voltage reference 0.97 1.00 1.03 V tLPO Internal low power oscillator period 900 1000 1100 μs factory trimmed 1. Rising thresholds are falling threshold + hysteresis voltage Table 3. VBAT power operating requirements Symbol Description VPOR_VBAT Falling VBAT supply POR detect voltage Min. Typ. Max. Unit 0.8 1.1 1.5 V Notes 5.2.3 Voltage and current operating behaviors Table 4. Voltage and current operating behaviors Symbol VOH Description Min. Max. Unit • 2.7 V ≤ VDD ≤ 3.6 V, IOH = -9mA VDD – 0.5 — V • 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA VDD – 0.5 — V • 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA VDD – 0.5 — V • 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA VDD – 0.5 — V Notes Output high voltage — high drive strength Output high voltage — low drive strength Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 14 Freescale Semiconductor, Inc. General Table 4. Voltage and current operating behaviors (continued) Symbol Min. Max. Unit Output high current total for all ports — 100 mA Output high current total for fast digital ports — 100 mA • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 9mA — 0.5 V • 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3mA — 0.5 V • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2mA — 0.5 V • 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6mA — 0.5 V Output low current total for all ports — 100 mA Output low current total for fast digital ports — 100 mA IIN Input leakage current (per pin) for full temperature range — 1 μA 1 IIN Input leakage current (per pin) at 25°C — 0.025 μA 1 IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA RPU Internal pullup resistors 20 50 kΩ 2 RPD Internal pulldown resistors 20 50 kΩ 3 IOHT IOHT_io60 VOL Description Notes Output low voltage — high drive strength Output low voltage — low drive strength IOLT IOLT_io60 1. Measured at VDD=3.6V 2. Measured at VDD supply voltage = VDD min and Vinput = VSS 3. Measured at VDD supply voltage = VDD min and Vinput = VDD 5.2.4 Power mode transition operating behaviors All specifications except tPOR, and VLLSx→RUN recovery times in the following table assume this clock configuration: • • • • CPU and system clocks = 150 MHz Bus clock = 75 MHz FlexBus clock = 50 MHz Flash clock = 25 MHz Table 5. Power mode transition operating behaviors Symbol tPOR Description After a POR event, amount of time from the point VDD reaches 1.71 V to execution of the first instruction across the operating temperature range of the chip. • VLLS1 → RUN • VLLS2 → RUN Min. Max. Unit Notes — 300 μs 1 — 160 μs — 114 μs Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 15 General Table 5. Power mode transition operating behaviors (continued) Symbol Description • VLLS3 → RUN • LLS → RUN • VLPS → RUN • STOP → RUN Min. Max. Unit — 114 μs — 5.0 μs — 5 μs — 4.8 μs Notes 1. Normal boot (FTFE_FOPT[LPBOOT]=1) 5.2.5 Power consumption operating behaviors Table 6. Power consumption operating behaviors Symbol IDDA IDD_RUN IDD_RUN Description Analog supply current Min. Typ. Max. Unit Notes — — See note mA 1 Run mode current — all peripheral clocks disabled, code executing from flash 2 • @ 1.8V — 59.6 180 mA • @ 3.0V — 59.6 185 mA Run mode current — all peripheral clocks enabled, code executing from flash 3 • @ 1.8V — 89.9 205 mA • @ 3.0V — 89.9 210 mA IDD_WAIT Wait mode high frequency current at 3.0 V — all peripheral clocks disabled — 40.9 95 mA 2 IDD_WAIT Wait mode reduced frequency current at 3.0 V — all peripheral clocks disabled — 19.6 65 mA 4 IDD_STOP Stop mode current at 3.0 V • @ –40 to 25°C — 1.3 3.8 mA • @ 70°C — 3.0 27 mA • @ 105°C — 7.5 42 mA IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks disabled — 1.4 32 mA 5 IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks enabled — 2.2 38 mA 6 IDD_VLPW Very-low-power wait mode current at 3.0 V — 0.926 22 mA 7 Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 16 Freescale Semiconductor, Inc. General Table 6. Power consumption operating behaviors (continued) Symbol Description IDD_VLPS Very-low-power stop mode current at 3.0 V IDD_LLS IDD_VLLS3 IDD_VLLS2 IDD_VLLS1 IDD_VBAT Min. Typ. Max. Unit • @ –40 to 25°C — 0.25 1.3 mA • @ 70°C — 0.85 7.6 mA • @ 105°C — 2.4 12.54 mA Low leakage stop mode current at 3.0 V Notes 8 • @ –40 to 25°C — 0.25 1.3 mA • @ 70°C — 0.85 7.6 mA • @ 105°C — 2.4 12.54 mA Very low-leakage stop mode 3 current at 3.0 V 8 • @ –40 to 25°C — 5.6 20 μA • @ 70°C — 30.1 137 μA • @ 105°C — 120.8 246 μA • @ –40 to 25°C — 3.2 14 μA • @ 70°C — 11.8 40 μA • @ 105°C — 51.2 60 μA • @ –40 to 25°C — 2.8 12 μA • @ 70°C — 8.7 29 μA • @ 105°C — 39.3 43 μA Very low-leakage stop mode 2 current at 3.0 V Very low-leakage stop mode 1 current at 3.0 V Average current when CPU is not accessing RTC registers at 3.0 V 9 • @ –40 to 25°C — 0.91 1.1 μA • @ 70°C — 1.5 1.85 μA • @ 105°C — 4.3 4.3 μA 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. 150 MHz core and system clock, 75 MHz bus, 50 MHz FlexBus clock, and 25 MHz flash clock. MCG configured for PEE mode. All peripheral clocks disabled. 3. 150 MHz core and system clock, 75 MHz bus, 50 MHz FlexBus clock, and 25 MHz flash clock. MCG configured for PEE mode. All peripheral clocks enabled, but peripherals are not in active operation. 4. 25 MHz core and system clock, 25 MHz bus clock, and 12.5 MHz FlexBus and flash clock. MCG configured for FEI mode. 5. 4 MHz core, system, 2 MHz FlexBus, and 2 MHz bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. 6. 4 MHz core, system, 2 MHz FlexBus, and 2 MHz bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. 7. 4 MHz core, system, 2 MHz FlexBus, and 2 MHz bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. 8. Data reflects devices with 128 KB of RAM. For devices with 64 KB of RAM, power consumption is reduced by 2 μA. 9. Includes 32kHz oscillator current and RTC operation. K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 17 General 5.2.5.1 Diagram: Typical IDD_RUN operating behavior The following data was measured under these conditions: • MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at greater than 50 MHz frequencies. MCG in PEE mode is greater than 100 MHz frequencies. • USB regulator disabled • No GPIOs toggled • Code execution from flash with cache enabled • For the ALLOFF curve, all peripheral clocks are disabled except FTFL Figure 2. Run mode supply current vs. core frequency K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 18 Freescale Semiconductor, Inc. General Figure 3. VLPR mode supply current vs. core frequency 5.2.6 EMC radiated emissions operating behaviors Table 7. EMC radiated emissions operating behaviors for 256MAPBGA Symbol Description Frequency band (MHz) Typ. Unit Notes 1,2 VRE1 Radiated emissions voltage, band 1 0.15–50 21 dBμV VRE2 Radiated emissions voltage, band 2 50–150 24 dBμV VRE3 Radiated emissions voltage, band 3 150–500 29 dBμV VRE4 Radiated emissions voltage, band 4 500–1000 28 dBμV 1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 2. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 72 MHz, fBUS = 72MHz K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 19 General 5.2.7 Designing with radiated emissions in mind To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. Go to www.freescale.com. 2. Perform a keyword search for “EMC design.” 5.2.8 Capacitance attributes Table 8. Capacitance attributes Symbol Description Min. Max. Unit CIN_A Input capacitance: analog pins — 7 pF CIN_D Input capacitance: digital pins — 7 pF Input capacitance: fast digital pins — 9 pF CIN_D_io60 5.3 Switching specifications 5.3.1 Device clock specifications Table 9. Device clock specifications Symbol Description Min. Max. Unit System and core clock — 150 MHz fSYS_USBFS System and core clock when Full Speed USB in operation 20 — MHz fSYS_USBHS System and core clock when High Speed USB in operation 60 — MHz fENET System and core clock when ethernet in operation Notes Normal run mode fSYS • 10 Mbps • 100 Mbps MHz 5 — 50 — Bus clock — 75 MHz FlexBus clock — 50 MHz fFLASH Flash clock — 25 MHz fLPTMR LPTMR clock — 25 MHz — 4 MHz fBUS FB_CLK VLPR fSYS System and core clock mode1 Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 20 Freescale Semiconductor, Inc. General Table 9. Device clock specifications (continued) Symbol Min. Max. Unit Bus clock — 4 MHz FlexBus clock — 4 MHz fFLASH Flash clock — 0.5 MHz fLPTMR LPTMR clock — 4 MHz fBUS FB_CLK Description Notes 1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any other module. 5.3.2 General switching specifications These general purpose specifications apply to all signals configured for GPIO, UART, CAN, CMT, IEEE 1588 timer, and I2C signals. Table 10. General switching specifications Symbol Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter disabled) — Synchronous path 1.5 — Bus clock cycles 1, 2 GPIO pin interrupt pulse width (digital glitch filter disabled, analog filter enabled) — Asynchronous path 100 — ns 3 GPIO pin interrupt pulse width (digital glitch filter disabled, analog filter disabled) — Asynchronous path 16 — ns 3 External reset pulse width (digital glitch filter disabled) 100 — ns 3 2 — Bus clock cycles Mode select (EZP_CS) hold time after reset deassertion Port rise and fall time (high drive strength) 4 • Slew disabled • 1.71 ≤ VDD ≤ 2.7V — 14 ns • 2.7 ≤ VDD ≤ 3.6V — 8 ns • 1.71 ≤ VDD ≤ 2.7V — 36 ns • 2.7 ≤ VDD ≤ 3.6V — 24 ns • Slew enabled Port rise and fall time (low drive strength) 5 • Slew disabled • 1.71 ≤ VDD ≤ 2.7V — 14 ns • 2.7 ≤ VDD ≤ 3.6V — 8 ns • 1.71 ≤ VDD ≤ 2.7V — 36 ns • 2.7 ≤ VDD ≤ 3.6V — 24 ns • Slew enabled Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 21 General Table 10. General switching specifications (continued) Symbol tio50 Description Min. Max. Unit Port rise and fall time (high drive strength) Notes 6 • Slew disabled • 1.71 ≤ VDD ≤ 2.7V — 7 ns — • 2.7 ≤ VDD ≤ 3.6V — 3 ns — • 1.71 ≤ VDD ≤ 2.7V — 28 ns — • 2.7 ≤ VDD ≤ 3.6V — 14 ns — • Slew enabled tio50 Port rise and fall time (low drive strength) 7 • Slew disabled • 1.71 ≤ VDD ≤ 2.7V — 18 ns — • 2.7 ≤ VDD ≤ 3.6V — 9 ns — • 1.71 ≤ VDD ≤ 2.7V — 48 ns — • 2.7 ≤ VDD ≤ 3.6V — 24 ns — • Slew enabled tio60 Port rise and fall time (high drive strength) 6 • Slew disabled • 1.71 ≤ VDD ≤ 2.7V — 6 ns — • 2.7 ≤ VDD ≤ 3.6V — 3 ns — • 1.71 ≤ VDD ≤ 2.7V — 28 ns — • 2.7 ≤ VDD ≤ 3.6V — 14 ns — • Slew enabled tio60 Port rise and fall time (low drive strength) 7 • Slew disabled • 1.71 ≤ VDD ≤ 2.7V — 18 ns — • 2.7 ≤ VDD ≤ 3.6V — 6 ns — • 1.71 ≤ VDD ≤ 2.7V — 48 ns — • 2.7 ≤ VDD ≤ 3.6V — 24 ns — • Slew enabled 1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. The greater synchronous and asynchronous timing must be met. 3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and VLLSx modes. 4. 75pF load 5. 15pF load 6. 25pF load 7. 15pF load K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 22 Freescale Semiconductor, Inc. General 5.4 Thermal specifications 5.4.1 Thermal operating requirements Table 11. Thermal operating requirements Symbol Description Min. Max. Unit TJ Die junction temperature –40 125 °C TA Ambient temperature –40 105 °C 5.4.2 Thermal attributes Board type Symbol Description 144 LQFP Single-layer (1s) RθJA Thermal 45 resistance, junction to ambient (natural convection) Four-layer (2s2p) RθJA Single-layer (1s) 144 MAPBGA Unit Notes 50 °C/W 1 Thermal 36 resistance, junction to ambient (natural convection) 30 °C/W 1 RθJMA Thermal 36 resistance, junction to ambient (200 ft./ min. air speed) 41 °C/W 1 Four-layer (2s2p) RθJMA Thermal 30 resistance, junction to ambient (200 ft./ min. air speed) 27 °C/W 1 — RθJB Thermal resistance, junction to board 24 17 °C/W 2 — RθJC Thermal resistance, junction to case 9 10 °C/W 3 Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 23 Peripheral operating requirements and behaviors Board type Symbol Description — ΨJT Thermal 2 characterization parameter, junction to package top outside center (natural convection) 1. 2. 3. 4. 144 LQFP 144 MAPBGA 2 Unit Notes °C/W 4 Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions—Forced Convection (Moving Air). Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions—Junction-to-Board. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air). 5.5 Power sequencing Voltage supplies must be sequenced in the proper order to avoid damaging internal diodes. There is no limit on how long after one supply powers up before the next supply must power up. Note that VDD and VDD_INT can use the same power source. The power-up sequence is: 1. 2. 3. 4. VDD VDD_INT VDDA VDD_DDR The power-down sequence is the reverse: 1. 2. 3. 4. VDD_DDR VDDA VDD_INT VDD 6 Peripheral operating requirements and behaviors 6.1 Core modules K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 24 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.1.1 Debug trace timing specifications Table 12. Debug trace operating behaviors Symbol Description Min. Max. Unit Tcyc Clock period Frequency dependent MHz Twl Low pulse width 2 — ns Twh High pulse width 2 — ns Tr Clock and data rise time — 3 ns Tf Clock and data fall time — 3 ns Ts Data setup 3 — ns Th Data hold 2 — ns Figure 4. TRACE_CLKOUT specifications TRACE_CLKOUT Ts Th Ts Th TRACE_D[3:0] Figure 5. Trace data specifications 6.1.2 JTAG electricals Table 13. JTAG limited voltage range electricals Symbol J1 J2 Description Min. Max. Unit Operating voltage 2.7 3.6 V TCLK frequency of operation MHz • Boundary Scan 0 10 • JTAG and CJTAG 0 25 • Serial Wire Debug 0 50 1/J1 — TCLK cycle period ns Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 25 Peripheral operating requirements and behaviors Table 13. JTAG limited voltage range electricals (continued) Symbol Min. Max. Unit • Boundary Scan 50 — ns • JTAG and CJTAG 20 — ns • Serial Wire Debug 10 — ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 2.4 — ns J7 TCLK low to boundary scan output data valid — 25 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1 — ns J11 TCLK low to TDO data valid — 17 ns J12 TCLK low to TDO high-Z — 17 ns J13 TRST assert time 100 — ns J14 TRST setup time (negation) to TCLK high 8 — ns J3 Description TCLK clock pulse width Table 14. JTAG full voltage range electricals Symbol J1 Description Min. Max. Unit Operating voltage 1.71 3.6 V TCLK frequency of operation MHz • Boundary Scan 0 10 • JTAG and CJTAG 0 20 • Serial Wire Debug 0 40 1/J1 — ns • Boundary Scan 50 — ns • JTAG and CJTAG 25 — ns • Serial Wire Debug 12.5 — ns J2 TCLK cycle period J3 TCLK clock pulse width J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 2.4 — ns J7 TCLK low to boundary scan output data valid — 25 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1.4 — ns J11 TCLK low to TDO data valid — 22.1 ns J12 TCLK low to TDO high-Z — 22.1 ns Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 26 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 14. JTAG full voltage range electricals (continued) Symbol Description Min. Max. Unit J13 TRST assert time 100 — ns J14 TRST setup time (negation) to TCLK high 8 — ns J2 J3 J3 TCLK (input) J4 J4 Figure 6. Test clock input timing TCLK J5 Data inputs J6 Input data valid J7 Data outputs Output data valid J8 Data outputs J7 Data outputs Output data valid Figure 7. Boundary scan (JTAG) timing K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 27 Peripheral operating requirements and behaviors TCLK J9 TDI/TMS J10 Input data valid J11 TDO Output data valid J12 TDO J11 TDO Output data valid Figure 8. Test Access Port timing TCLK J14 J13 TRST Figure 9. TRST timing 6.2 System modules There are no specifications necessary for the device's system modules. 6.3 Clock modules K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 28 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.3.1 MCG specifications Table 15. MCG specifications Symbol Description Min. Typ. Max. Unit — 32.768 — kHz 31.25 — 39.0625 kHz Δfdco_res_t Resolution of trimmed average DCO output frequency at fixed voltage and temperature — using SCTRIM and SCFTRIM — ± 0.3 ± 0.6 %fdco 1 Δfdco_res_t Resolution of trimmed average DCO output frequency at fixed voltage and temperature — using SCTRIM only — ± 0.2 ± 0.5 %fdco 1 fints_ft Internal reference frequency (slow clock) — factory trimmed at nominal VDD and 25 °C fints_t Internal reference frequency (slow clock) — user trimmed Notes Δfdco_t Total deviation of trimmed average DCO output frequency over voltage and temperature — ±7 — %fdco 1 Δfdco_t Total deviation of trimmed average DCO output frequency over fixed voltage and temperature range of 0–70°C — ± 4.5 — %fdco 1 4 MHz fintf_ft Internal reference frequency (fast clock) — factory trimmed at nominal VDD and 25°C fintf_t Internal reference frequency (fast clock) — user trimmed at nominal VDD and 25 °C 3 — 5 MHz floc_low Loss of external clock minimum frequency — RANGE = 00 (3/5) x fints_t — — kHz floc_high Loss of external clock minimum frequency — RANGE = 01, 10, or 11 (16/5) x fints_t — — kHz 31.25 — 39.0625 kHz 20 20.97 25 MHz 40 41.94 50 MHz 60 62.91 75 MHz 80 83.89 100 MHz — 23.99 — MHz — 47.97 — MHz — 71.99 — MHz — 95.98 — MHz FLL ffll_ref fdco FLL reference frequency range DCO output frequency range Low range (DRS=00) 2, 3 640 × ffll_ref Mid range (DRS=01) 1280 × ffll_ref Mid-high range (DRS=10) 1920 × ffll_ref High range (DRS=11) 2560 × ffll_ref fdco_t_DMX32 DCO output frequency Low range (DRS=00) 4, 5 732 × ffll_ref Mid range (DRS=01) 1464 × ffll_ref Mid-high range (DRS=10) 2197 × ffll_ref High range (DRS=11) 2929 × ffll_ref Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 29 Peripheral operating requirements and behaviors Table 15. MCG specifications (continued) Symbol Jcyc_fll Description FLL period jitter • fVCO = 48 MHz • fVCO = 98 MHz tfll_acquire FLL target frequency acquisition time Min. Typ. Max. Unit — 180 — — 150 — — — 1 ms 8 — 16 MHz Notes ps 6 PLL0,1 fpll_ref PLL reference frequency range fvcoclk_2x VCO output frequency fvcoclk PLL output frequency fvcoclk_90 180 90 PLL quadrature output frequency Ipll PLL0 operating current • VCO @ 180 MHz (fosc_hi_1 = 32 MHz, fpll_ref = 8 MHz, VDIV multiplier = 22) Ipll PLL0 operating current • VCO @ 360 MHz (fosc_hi_1 = 32 MHz, fpll_ref = 8 MHz, VDIV multiplier = 45) Ipll PLL1 operating current • VCO @ 180 MHz (fosc_hi_1 = 32 MHz, fpll_ref = 8 MHz, VDIV multiplier = 22) Ipll PLL1 operating current • VCO @ 360 MHz (fosc_hi_1 = 32 MHz, fpll_ref = 8 MHz, VDIV multiplier = 45) tpll_lock Lock detector detection time Jcyc_pll PLL period jitter (RMS) Jacc_pll 90 — — — 360 180 180 MHz MHz MHz — 2.8 — mA — 4.7 — mA — 2.3 — mA — 3.6 — mA — — 100 × 10-6 + 1075(1/ fpll_ref) s 7 7 7 7 8 9 • fvco = 180 MHz — 100 — ps • fvco = 360 MHz — 75 — ps PLL accumulated jitter over 1µs (RMS) 10 • fvco = 180 MHz — 600 — ps • fvco = 360 MHz — 300 — ps 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (Δfdco_t) over voltage and temperature should be considered. 4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 7. Excludes any oscillator currents that are also consuming power while PLL is in operation. 8. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 30 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 9. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 10. Accumulated jitter depends on VCO frequency and VDIV. 6.3.2 Oscillator electrical specifications This section provides the electrical characteristics of the module. 6.3.2.1 Oscillator DC electrical specifications Table 16. Oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 — 3.6 V IDDOSC IDDOSC Supply current — low-power mode (HGO=0) Notes 1 • 32 kHz — 500 — nA • 4 MHz — 200 — μA • 8 MHz (RANGE=01) — 300 — μA • 16 MHz — 950 — μA • 24 MHz — 1.2 — mA • 32 MHz — 1.5 — mA Supply current — high gain mode (HGO=1) 1 • 32 kHz — 25 — μA • 4 MHz — 400 — μA • 8 MHz (RANGE=01) — 500 — μA • 16 MHz — 2.5 — mA • 24 MHz — 3 — mA • 32 MHz — 4 — mA Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 RF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ 2, 4 Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 31 Peripheral operating requirements and behaviors Table 16. Oscillator DC electrical specifications (continued) Symbol RS Description Min. Typ. Max. Unit Series resistor — low-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — low-frequency, high-gain mode (HGO=1) — 200 — kΩ Series resistor — high-frequency, low-power mode (HGO=0) — — — kΩ Notes Series resistor — high-frequency, high-gain mode (HGO=1) Vpp5 1. 2. 3. 4. 5. — 0 — kΩ Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, high-gain mode (HGO=1) — VDD — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, high-gain mode (HGO=1) — VDD — V VDD=3.3 V, Temperature =25 °C See crystal or resonator manufacturer's recommendation Cx,Cy can be provided by using either the integrated capacitors or by using external components. When low power mode is selected, RF is integrated and must not be attached externally. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. 6.3.2.2 Symbol Oscillator frequency specifications Table 17. Oscillator frequency specifications Description Min. Typ. Max. Unit fosc_lo Oscillator crystal or resonator frequency — low frequency mode (MCG_C2[RANGE]=00) 32 — 40 kHz fosc_hi_1 Oscillator crystal or resonator frequency — high frequency mode (low range) (MCG_C2[RANGE]=01) 3 — 8 MHz fosc_hi_2 Oscillator crystal or resonator frequency — high frequency mode (high range) (MCG_C2[RANGE]=1x) 8 — 32 MHz fec_extal Input clock frequency (external clock mode) — — 60 MHz tdc_extal Input clock duty cycle (external clock mode) 40 50 60 % Notes 1 2, 3 Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 32 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 17. Oscillator frequency specifications (continued) Symbol tcst Description Min. Typ. Max. Unit Notes Crystal startup time — 32 kHz low-frequency, low-power mode (HGO=0) — 1000 — ms 4, 5 Crystal startup time — 32 kHz low-frequency, high-gain mode (HGO=1) — 500 — ms Crystal startup time — 8 MHz high-frequency (MCG_C2[RANGE]=01), low-power mode (HGO=0) — 0.6 — ms Crystal startup time — 8 MHz high-frequency (MCG_C2[RANGE]=01), high-gain mode (HGO=1) — 1 — ms 1. Frequencies less than 8 MHz are not in the PLL range. 2. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL. 3. When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it remains within the limits of the DCO input clock frequency. 4. Proper PC board layout procedures must be followed to achieve specifications. 5. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set. NOTE The 32 kHz oscillator works in low power mode bu default and cannot be moved into high power/gain mode. 6.3.3 32 kHz Oscillator Electrical Characteristics This section describes the module electrical characteristics. 6.3.3.1 32 kHz oscillator DC electrical specifications Table 18. 32kHz oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit VBAT Supply voltage 1.71 — 3.6 V Internal feedback resistor — 100 — MΩ Cpara Parasitical capacitance of EXTAL32 and XTAL32 — 5 7 pF Vpp1 Peak-to-peak amplitude of oscillation — 0.6 — V RF 1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to required oscillator components and must not be connected to any other devices. K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 33 Peripheral operating requirements and behaviors 6.3.3.2 Symbol fosc_lo tstart 32kHz oscillator frequency specifications Table 19. 32kHz oscillator frequency specifications Description Min. Typ. Max. Unit Oscillator crystal — 32.768 — kHz Crystal start-up time — 1000 — ms 1 700 — VBAT mV 2, 3 vec_extal32 Externally provided input clock amplitude Notes 1. Proper PC board layout procedures must be followed to achieve specifications. 2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The oscillator remains enabled and XTAL32 must be left unconnected. 3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied clock must be within the range of VSS to VBAT. 6.4 Memories and memory interfaces 6.4.1 Flash (FTFE) electrical specifications This section describes the electrical characteristics of the FTFE module. 6.4.1.1 Flash timing specifications — program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Table 20. NVM program/erase timing specifications Symbol Description Min. Typ. Max. Unit thvpgm8 thversscr Notes Program Phrase high-voltage time — 7.5 18 μs Erase Flash Sector high-voltage time — 13 113 ms 1 thversblk128k Erase Flash Block high-voltage time for 128 KB — 104 1808 ms 1 thversblk256k Erase Flash Block high-voltage time for 256 KB — 208 3616 ms 1 Notes 1. Maximum time based on expectations at cycling end-of-life. 6.4.1.2 Symbol Flash timing specifications — commands Table 21. Flash command timing specifications Description Min. Typ. Max. Unit Read 1s Block execution time trd1blk128k • 128 KB data flash — — 0.5 ms trd1blk256k • 256 KB program flash — — 1.0 ms Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 34 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 21. Flash command timing specifications (continued) Symbol Description Min. Typ. Max. Unit Notes trd1sec4k Read 1s Section execution time (4 KB flash) — — 100 μs 1 tpgmchk Program Check execution time — — 80 μs 1 trdrsrc Read Resource execution time — — 40 μs 1 tpgm8 Program Phrase execution time — 70 150 μs Erase Flash Block execution time 2 tersblk128k • 128 KB data flash — 110 925 ms tersblk256k • 256 KB program flash — 220 1850 ms Erase Flash Sector execution time — 15 115 ms Program Section execution time (4KB flash) — 20 — ms trd1all Read 1s All Blocks execution time — — 1.0 ms trdonce Read Once execution time — — 30 μs Program Once execution time — 70 — μs tersall Erase All Blocks execution time — 650 5600 ms 2 tvfykey Verify Backdoor Access Key execution time — — 30 μs 1 tersscr tpgmsec4k tpgmonce 2 1 Swap Control execution time tswapx01 • control code 0x01 — 200 — μs tswapx02 • control code 0x02 — 70 150 μs tswapx04 • control code 0x04 — 70 150 μs tswapx08 • control code 0x08 — — 30 μs Program Partition for EEPROM execution time tpgmpart64k • 64 KB FlexNVM — 235 — ms tpgmpart256k • 256 KB FlexNVM — 240 — ms • Control Code 0xFF — 205 — μs tsetram64k • 64 KB EEPROM backup — 1.6 2.5 ms tsetram128k • 128 KB EEPROM backup — 2.7 3.8 ms tsetram256k • 256 KB EEPROM backup — 4.8 6.2 ms — 140 225 μs Set FlexRAM Function execution time: tsetramff teewr8bers Byte-write to erased FlexRAM location execution time 3 Byte-write to FlexRAM execution time: teewr8b64k • 64 KB EEPROM backup — 400 1700 μs teewr8b128k • 128 KB EEPROM backup — 450 1800 μs teewr8b256k • 256 KB EEPROM backup — 525 2000 μs — 140 225 μs teewr16bers 16-bit write to erased FlexRAM location execution time Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 35 Peripheral operating requirements and behaviors Table 21. Flash command timing specifications (continued) Symbol Description Min. Typ. Max. Unit Notes 16-bit write to FlexRAM execution time: teewr16b64k • 64 KB EEPROM backup — 400 1700 μs teewr16b128k • 128 KB EEPROM backup — 450 1800 μs teewr16b256k • 256 KB EEPROM backup — 525 2000 μs — 180 275 μs teewr32bers 32-bit write to erased FlexRAM location execution time 32-bit write to FlexRAM execution time: teewr32b64k • 64 KB EEPROM backup — 475 1850 μs teewr32b128k • 128 KB EEPROM backup — 525 2000 μs teewr32b256k • 256 KB EEPROM backup — 600 2200 μs 1. Assumes 25MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased. 6.4.1.3 Flash high voltage current behaviors Table 22. Flash high voltage current behaviors Symbol Description IDD_PGM IDD_ERS 6.4.1.4 Symbol Min. Typ. Max. Unit Average current adder during high voltage flash programming operation — 3.5 7.5 mA Average current adder during high voltage flash erase operation — 1.5 4.0 mA Reliability specifications Table 23. NVM reliability specifications Description Typ.1 Max. Unit 50 — years 20 100 — years 10 K 50 K — cycles Min. Notes Program Flash tnvmretp10k Data retention after up to 10 K cycles tnvmretp1k Data retention after up to 1 K cycles nnvmcycp Cycling endurance 5 2 Data Flash tnvmretd10k Data retention after up to 10 K cycles 5 50 — years tnvmretd1k 20 100 — years Data retention after up to 1 K cycles Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 36 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 23. NVM reliability specifications (continued) Symbol Description Min. Typ.1 Max. Unit Notes nnvmcycd Cycling endurance 10 K 50 K — cycles 2 FlexRAM as EEPROM tnvmretee100 Data retention up to 100% of write endurance 5 50 — years tnvmretee10 Data retention up to 10% of write endurance 20 100 — years 20 K 50 K — cycles nnvmcycee Cycling endurance for EEPROM backup Write endurance 2 3 nnvmwree16 • EEPROM backup to FlexRAM ratio = 16 70 K 175 K — writes nnvmwree128 • EEPROM backup to FlexRAM ratio = 128 630 K 1.6 M — writes nnvmwree512 • EEPROM backup to FlexRAM ratio = 512 2.5 M 6.4 M — writes nnvmwree2k • EEPROM backup to FlexRAM ratio = 2,048 10 M 25 M — writes nnvmwree4k • EEPROM backup to FlexRAM ratio = 4,096 20 M 50 M — writes 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C. 3. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the cycling endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup per subsystem. Minimum and typical values assume all byte-writes to FlexRAM. 6.4.1.5 Write endurance to FlexRAM for EEPROM When the FlexNVM partition code is not set to full data flash, the EEPROM data set size can be set to any of several non-zero values. The bytes not assigned to data flash via the FlexNVM partition code are used by the FTFE to obtain an effective endurance increase for the EEPROM data. The built-in EEPROM record management system raises the number of program/erase cycles that can be attained prior to device wear-out by cycling the EEPROM data through a larger EEPROM NVM storage space. While different partitions of the FlexNVM are available, the intention is that a single choice for the FlexNVM partition code and EEPROM data set size is used throughout the entire lifetime of a given application. The EEPROM endurance equation and graph shown below assume that only one configuration is ever used. Writes_subsystem = EEPROM – 2 × EEESPLIT × EEESIZE EEESPLIT × EEESIZE × Write_efficiency × nnvmcycee where • Writes_subsystem — minimum number of writes to each FlexRAM location for subsystem (each subsystem can have different endurance) K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 37 Peripheral operating requirements and behaviors • EEPROM — allocated FlexNVM for each EEPROM subsystem based on DEPART; entered with Program Partition command • EEESPLIT — FlexRAM split factor for subsystem; entered with the Program Partition command • EEESIZE — allocated FlexRAM based on DEPART; entered with Program Partition command • Write_efficiency — • 0.25 for 8-bit writes to FlexRAM • 0.50 for 16-bit or 32-bit writes to FlexRAM • nnvmcycee — EEPROM-backup cycling endurance Figure 10. EEPROM backup writes to FlexRAM 6.4.2 EzPort Switching Specifications Table 24. EzPort switching specifications Num Description Min. Max. Unit Operating voltage 1.71 3.6 V Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 38 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 24. EzPort switching specifications (continued) Num Description Min. Max. Unit EP1 EZP_CK frequency of operation (all commands except READ) — fSYS/2 MHz EP1a EZP_CK frequency of operation (READ command) — fSYS/8 MHz EP2 EZP_CS negation to next EZP_CS assertion 2 x tEZP_CK — ns EP3 EZP_CS input valid to EZP_CK high (setup) 5 — ns EP4 EZP_CK high to EZP_CS input invalid (hold) 5 — ns EP5 EZP_D input valid to EZP_CK high (setup) 2 — ns EP6 EZP_CK high to EZP_D input invalid (hold) 5 — ns EP7 EZP_CK low to EZP_Q output valid — 16 ns EP8 EZP_CK low to EZP_Q output invalid (hold) 0 — ns EP9 EZP_CS negation to EZP_Q tri-state — 12 ns EZP_CK EP3 EP2 EP4 EZP_CS EP9 EP7 EP8 EZP_Q (output) EP5 EP6 EZP_D (input) Figure 11. EzPort Timing Diagram 6.4.3 NFC specifications The NAND flash controller (NFC) implements the interface to standard NAND flash memory devices. This section describes the timing parameters of the NFC. In the following table: • TH is the flash clock high time and • TL is flash clock low time, K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 39 Peripheral operating requirements and behaviors which are defined as: T NFC = T L + T H = T input clock SCALER The SCALER value is derived from the fractional divider specified in the SIM's CLKDIV4 register: SCALER = SIM_CLKDIV4[NFCFRAC] + 1 SIM_CLKDIV4[NFCDIV] + 1 In case the reciprocal of SCALER is an integer, the duty cycle of NFC clock is 50%, means TH = TL. In case the reciprocal of SCALER is not an integer: T L = (1 + SCALER / 2) x T H = (1 – SCALER / 2) x T NFC 2 T NFC 2 For example, if SCALER is 0.2, then TH = TL = TNFC/2. TNFC TH TL However, if SCALER is 0.667, then TL = 2/3 x TNFC and TH = 1/3 x TNFC. TNFC TH TL NOTE The reciprocal of SCALER must be a multiple of 0.5. For example, 1, 1.5, 2, 2.5, etc. Table 25. NFC specifications Num Description Min. Max. Unit tCLS NFC_CLE setup time 2TH + TL – 1 — ns tCLH NFC_CLE hold time TH + TL – 1 — ns tCS NFC_CEn setup time 2TH + TL – 1 — ns tCH NFC_CEn hold time TH + TL — ns tWP NFC_WP pulse width TL – 1 — ns tALS NFC_ALE setup time 2TH + TL — ns Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 40 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 25. NFC specifications (continued) Num Description Min. Max. Unit tALH NFC_ALE hold time TH + TL — ns tDS Data setup time TL – 1 — ns tDH Data hold time TH – 1 — ns tWC Write cycle time TH + TL – 1 — ns tWH NFC_WE hold time TH – 1 — ns tRR Ready to NFC_RE low 4TH + 3TL + 90 — ns tRP NFC_RE pulse width TL + 1 — ns tRC Read cycle time TL + TH – 1 — ns tREH NFC_RE high hold time TH – 1 — ns tIS Data input setup time 11 — ns NFC_CLE tCLS tCLH NFC_CEn tCS tWP tCH NFC_WE tDS tDH NFC_IOn Figure 12. Command latch cycle timing NFC_ALE tALS tALH NFC_CEn tCS tWP tCH NFC_WE tDS NFC_IOn tDH address Figure 13. Address latch cycle timing K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 41 Peripheral operating requirements and behaviors tCS tCH tWC NFC_CEn tWP tWH tDS tDH NFC_WE NFC_IOn data data data Figure 14. Write data latch cycle timing tCH tRC NFC_CEn tREH tRP NFC_RE tIS NFC_IOn data data data tRR NFC_RB Figure 15. Read data latch cycle timing in non-fast mode tCH tRC NFC_CEn tRP tREH NFC_RE tIS NFC_IOn data data data tRR NFC_RB Figure 16. Read data latch cycle timing in fast mode 6.4.4 Flexbus Switching Specifications All processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be the same as the internal system bus frequency or an integer divider of that frequency. K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 42 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors The following timing numbers indicate when data is latched or driven onto the external bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be derived from these values. Table 26. Flexbus limited voltage range switching specifications Num Description Min. Max. Unit Notes Operating voltage 2.7 3.6 V Frequency of operation — FB_CLK MHz FB1 Clock period 20 — ns FB2 Address, data, and control output valid — 11.5 ns 1 FB3 Address, data, and control output hold 0.5 — ns 1 FB4 Data and FB_TA input setup 8.5 — ns 2 FB5 Data and FB_TA input hold 0.5 — ns 2 1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE, and FB_TS. 2. Specification is valid for all FB_AD[31:0] and FB_TA. Table 27. Flexbus full voltage range switching specifications Num Description Min. Max. Unit Operating voltage 1.71 3.6 V Frequency of operation Notes — FB_CLK MHz 1/FB_CLK — ns Address, data, and control output valid — 13.5 ns 1 FB3 Address, data, and control output hold 0 — ns 1 FB4 Data and FB_TA input setup 13.7 — ns 2 FB5 Data and FB_TA input hold 0.5 — ns 2 FB1 Clock period FB2 1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE, and FB_TS. 2. Specification is valid for all FB_AD[31:0] and FB_TA. K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 43 Peripheral operating requirements and behaviors FB1 FB_CLK FB3 FB5 FB_A[Y] Address FB4 FB2 FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB4 FB_BEn FB5 AA=1 FB_TA FB_TSIZ[1:0] AA=0 TSIZ Figure 17. FlexBus read timing diagram K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 44 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors FB1 FB_CLK FB2 FB3 FB_A[Y] FB_D[X] Address Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB4 FB_BEn FB5 AA=1 FB_TA FB_TSIZ[1:0] AA=0 TSIZ Figure 18. FlexBus write timing diagram 6.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. 6.6 Analog K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 45 Peripheral operating requirements and behaviors 6.6.1 ADC electrical specifications The 16-bit accuracy specifications listed in Table 28 and Table 29 are achievable on the differential pins ADCx_DP0, ADCx_DM0. The ADCx_DP2 and ADCx_DM2 ADC inputs are connected to the PGA outputs and are not direct device pins. Accuracy specifications for these pins are defined in Table 30 and Table 31. All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 6.6.1.1 16-bit ADC operating conditions Table 28. 16-bit ADC operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit VDDA Supply voltage Absolute 1.71 — 3.6 V ΔVDDA Supply voltage Delta to VDD (VDD-VDDA) -100 0 +100 mV 2 ΔVSSA Ground voltage Delta to VSS (VSS - VSSA) -100 0 +100 mV 2 VREFH ADC reference voltage high 1.13 VDDA VDDA V VREFL ADC reference voltage low VSSA VSSA VSSA V VADIN Input voltage • 16-bit differential mode VREFL — 31/32 * VREFH V • All other modes VREFL — VREFL — VREFH V • 16-bit mode — 8 10 pF • 8-/10-/12-bit modes — 4 5 — 2 5 VADIN Input voltage CADIN Input capacitance RADIN RAS Input resistance Notes VREFH kΩ Analog source resistance 13-/12-bit modes fADCK < 4 MHz — — 5 kΩ fADCK ADC conversion clock frequency ≤ 13-bit mode 1.0 — 18.0 MHz 4 fADCK ADC conversion clock frequency 16-bit mode 2.0 — 12.0 MHz 4 Crate ADC conversion rate ≤ 13 bit modes No ADC hardware averaging 3 5 20.000 — 818.330 Ksps Continuous conversions enabled, subsequent conversion time Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 46 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 28. 16-bit ADC operating conditions (continued) Symbol Crate Description Conditions ADC conversion rate 16-bit mode Min. Typ.1 Max. Unit Notes 5 No ADC hardware averaging 37.037 — 461.467 Ksps Continuous conversions enabled, subsequent conversion time 1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2. DC potential difference. 3. This resistance is external to MCU. The analog source resistance must be kept as low as possible to achieve the best results. The results in this data sheet were derived from a system which has < 8 Ω analog source resistance. The RAS/CAS time constant should be kept to < 1ns. 4. To use the maximum ADC conversion clock frequency, the ADHSC bit must be set and the ADLPC bit must be clear. 5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT Z ADIN SIMPLIFIED CHANNEL SELECT CIRCUIT Pad leakage due to input protection Z AS R AS ADC SAR ENGINE R ADIN V ADIN C AS V AS R ADIN INPUT PIN R ADIN INPUT PIN R ADIN INPUT PIN C ADIN Figure 19. ADC input impedance equivalency diagram 6.6.1.2 16-bit ADC electrical characteristics Table 29. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) Symbol Description IDDA_ADC Supply current Conditions1 Min. Typ.2 Max. Unit Notes 0.215 — 1.7 mA 3 Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 47 Peripheral operating requirements and behaviors Table 29. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol fADACK Description ADC asynchronous clock source Sample Time TUE DNL INL EFS Conditions1 Min. Typ.2 Max. Unit Notes • ADLPC = 1, ADHSC = 0 1.2 2.4 3.9 MHz • ADLPC = 1, ADHSC = 1 2.4 4.0 6.1 MHz tADACK = 1/ fADACK • ADLPC = 0, ADHSC = 0 3.0 5.2 7.3 MHz • ADLPC = 0, ADHSC = 1 4.4 6.2 9.5 MHz LSB4 5 LSB4 5 LSB4 5 LSB4 VADIN = VDDA See Reference Manual chapter for sample times Total unadjusted error • 12-bit modes — ±4 ±6.8 • <12-bit modes — ±1.4 ±2.1 Differential nonlinearity • 12-bit modes — ±0.7 -1.1 to +1.9 Integral nonlinearity Full-scale error -0.3 to 0.5 • <12-bit modes — ±0.2 • 12-bit modes — ±1.0 -2.7 to +1.9 -0.7 to +0.5 • <12-bit modes — ±0.5 • 12-bit modes — -4 -5.4 • <12-bit modes — -1.4 -1.8 5 EQ ENOB Quantization error • 16-bit modes — -1 to 0 — • ≤13-bit modes — — ±0.5 Effective number 16-bit differential mode of bits • Avg = 32 • Avg = 4 LSB4 6 12.8 14.5 — bits 11.9 13.8 — bits 12.2 13.9 — bits 11.4 13.1 — bits 16-bit single-ended mode • Avg = 32 • Avg = 4 SINAD THD Signal-to-noise plus distortion See ENOB Total harmonic distortion 16-bit differential mode 6.02 × ENOB + 1.76 • Avg = 32 16-bit single-ended mode • Avg = 32 SFDR Spurious free dynamic range dB 7 — –94 — dB — -85 — dB 16-bit differential mode • Avg = 32 16-bit single-ended mode • Avg = 32 7 82 95 — dB 78 90 — dB Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 48 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 29. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol Description EIL Input leakage error Conditions1 Min. Typ.2 Max. IIn × RAS Unit Notes mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) VTEMP25 Temp sensor slope Across the full temperature range of the device — 1.715 — mV/°C Temp sensor voltage 25 °C — 719 — mV 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power). For lowest power operation the ADLPC bit must be set, the HSC bit must be clear with 1 MHz ADC conversion clock speed. 4. 1 LSB = (VREFH - VREFL)/2N 5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz. 7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz. Figure 20. Typical ENOB vs. ADC_CLK for 16-bit differential mode K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 49 Peripheral operating requirements and behaviors Figure 21. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode 6.6.1.3 16-bit ADC with PGA operating conditions Table 30. 16-bit ADC with PGA operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit VDDA Supply voltage Absolute 1.71 — 3.6 V VREFPGA PGA ref voltage VADIN VCM RPGAD VREF_OU VREF_OU VREF_OU T T T V Notes 2, 3 Input voltage VSSA — VDDA V Input Common Mode range VSSA — VDDA V Gain = 1, 2, 4, 8 — 128 — kΩ IN+ to IN-4 Gain = 16, 32 — 64 — Gain = 64 — 32 — Differential input impedance RAS Analog source resistance — 100 — Ω 5 TS ADC sampling time 1.25 — — µs 6 Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 50 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 30. 16-bit ADC with PGA operating conditions (continued) Symbol Crate Description Conditions ADC conversion rate ≤ 13 bit modes Min. Typ.1 Max. Unit Notes 18.484 — 450 Ksps 7 37.037 — 250 Ksps 8 No ADC hardware averaging Continuous conversions enabled Peripheral clock = 50 MHz 16 bit modes No ADC hardware averaging Continuous conversions enabled Peripheral clock = 50 MHz 1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 6 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2. ADC must be configured to use the internal voltage reference (VREF_OUT) 3. PGA reference is internally connected to the VREF_OUT pin. If the user wishes to drive VREF_OUT with a voltage other than the output of the VREF module, the VREF module must be disabled. 4. For single ended configurations the input impedance of the driven input is RPGAD/2 5. The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop in PGA gain without affecting other performances. This is not dependent on ADC clock frequency. 6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs time should be allowed for Fin=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at 8 MHz ADC clock. 7. ADC clock = 18 MHz, ADLSMP = 1, ADLST = 00, ADHSC = 1 8. ADC clock = 12 MHz, ADLSMP = 1, ADLST = 01, ADHSC = 1 6.6.1.4 16-bit ADC with PGA characteristics Table 31. 16-bit ADC with PGA characteristics Symbol Description Conditions IDDA_PGA Supply current Low power (ADC_PGA[PGALPb]=0) IDC_PGA Input DC current Min. Typ.1 Max. Unit Notes — 420 644 μA 2 A 3 Gain =1, VREFPGA=1.2V, VCM=0.5V — 1.54 — μA Gain =64, VREFPGA=1.2V, VCM=0.1V — 0.57 — μA Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 51 Peripheral operating requirements and behaviors Table 31. 16-bit ADC with PGA characteristics (continued) Symbol G BW Description Gain4 Input signal bandwidth Min. Typ.1 Max. • PGAG=0 0.95 1 1.05 • PGAG=1 1.9 2 2.1 • PGAG=2 3.8 4 4.2 • PGAG=3 7.6 8 8.4 • PGAG=4 15.2 16 16.6 • PGAG=5 30.0 31.6 33.2 • PGAG=6 58.8 63.3 67.8 — — 4 kHz — — 40 kHz — -84 — dB VDDA= 3V ±100mV, fVDDA= 50Hz, 60Hz VCM= 500mVpp, fVCM= 50Hz, 100Hz Conditions • 16-bit modes • < 16-bit modes Power supply rejection ratio CMRR Common mode rejection ratio • Gain=1 — -84 — dB • Gain=64 — -85 — dB Input offset voltage • Chopping disabled (ADC_PGA[PGACHPb] =1) • Chopping enabled (ADC_PGA[PGACHPb] =0) — 2.4 — mV — 0.2 — mV — — 10 µs • Gain=1 • Gain=64 — 6 10 ppm/°C — 31 42 ppm/°C • Gain=1 • Gain=64 — 0.07 0.21 %/V — 0.14 0.31 %/V TGSW Gain switching settling time dG/dT Gain drift over full temperature range dG/dVDDA Gain drift over supply voltage EIL Input leakage error All modes Notes RAS < 100Ω PSRR VOFS Gain=1 Unit IIn × RAS mV Output offset = VOFS*(Gain+1) 5 VDDA from 1.71 to 3.6V IIn = leakage current (refer to the MCU's voltage and current operating ratings) VPP,DIFF SNR Maximum differential input signal swing Signal-to-noise ratio V 6 16-bit differential mode, Average=32 where VX = VREFPGA × 0.583 • Gain=1 80 90 — dB • Gain=64 52 66 — dB Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 52 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 31. 16-bit ADC with PGA characteristics (continued) Symbol THD SFDR ENOB SINAD Description Conditions Min. Typ.1 Max. Unit Notes 16-bit differential mode, Average=32, fin=100Hz Total harmonic distortion • Gain=1 85 100 — dB • Gain=64 49 95 — dB Spurious free dynamic range • Gain=1 85 105 — dB • Gain=64 53 88 — dB Effective number of bits • Gain=1, Average=4 11.6 13.4 — bits • Gain=1, Average=8 8.0 13.6 — bits • Gain=64, Average=4 7.2 9.6 — bits • Gain=64, Average=8 6.3 9.6 — bits • Gain=1, Average=32 12.8 14.5 — bits • Gain=2, Average=32 11.0 14.3 — bits • Gain=4, Average=32 7.9 13.8 — bits • Gain=8, Average=32 7.3 13.1 — bits • Gain=16, Average=32 6.8 12.5 — bits • Gain=32, Average=32 6.8 11.5 — bits • Gain=64, Average=32 7.5 10.6 — bits Signal-to-noise plus distortion ratio See ENOB 6.02 × ENOB + 1.76 16-bit differential mode, Average=32, fin=100Hz 16-bit differential mode,fin=100Hz dB 1. Typical values assume VDDA =3.0V, Temp=25°C, fADCK=6MHz unless otherwise stated. 2. This current is a PGA module adder, in addition to ADC conversion currents. 3. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong function of input common mode voltage (VCM) and the PGA gain. 4. Gain = 2PGAG 5. After changing the PGA gain setting, a minimum of 2 ADC+PGA conversions should be ignored. 6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the PGA reference voltage and gain setting. 6.6.2 CMP and 6-bit DAC electrical specifications Table 32. Comparator and 6-bit DAC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 — 3.6 V IDDHS Supply current, High-speed mode (EN=1, PMODE=1) — — 200 μA IDDLS Supply current, low-speed mode (EN=1, PMODE=0) — — 20 μA VAIN Analog input voltage VSS – 0.3 — VDD V VAIO Analog input offset voltage — — 20 mV Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 53 Peripheral operating requirements and behaviors Table 32. Comparator and 6-bit DAC electrical specifications (continued) Symbol VH Description Min. Typ. Max. Unit • CR0[HYSTCTR] = 00 — 5 — mV • CR0[HYSTCTR] = 01 — 10 — mV • CR0[HYSTCTR] = 10 — 20 — mV • CR0[HYSTCTR] = 11 — 30 — mV Analog comparator hysteresis1 VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns Analog comparator initialization delay2 — — 40 μs 6-bit DAC current adder (enabled) — 7 — μA IDAC6b INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 54 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 0.08 0.07 0.06 HYSTCTR Setting CM P Hystereris (V) 0.05 00 0.04 01 10 11 0.03 0.02 0.01 0 0.1 0.4 0.7 1 1.3 1.6 1.9 Vin level (V) 2.2 2.5 2.8 3.1 Figure 22. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0) K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 55 Peripheral operating requirements and behaviors 0.18 0.16 0.14 CMP P Hystereris (V) 0.12 HYSTCTR Setting 0.1 00 01 0 08 0.08 10 11 0.06 0.04 0.02 0 0.1 0.4 0.7 1 1.3 1.6 Vin level (V) 1.9 2.2 2.5 2.8 3.1 Figure 23. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1) 6.6.3 12-bit DAC electrical characteristics 6.6.3.1 Symbol 12-bit DAC operating requirements Table 33. 12-bit DAC operating requirements Desciption Min. Max. Unit VDDA Supply voltage 1.71 3.6 V VDACR Reference voltage 1.13 3.6 V TA Temperature Operating temperature range of the device CL Output load capacitance — 100 pF IL Output load current — 1 mA Notes 1 °C 2 1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREF_OUT) 2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 56 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.6.3.2 Symbol 12-bit DAC operating behaviors Table 34. 12-bit DAC operating behaviors Description IDDA_DACL Supply current — low-power mode Min. Typ. Max. Unit — — 150 μA — — 700 μA Notes P IDDA_DACH Supply current — high-speed mode P tDACLP Full-scale settling time (0x080 to 0xF7F) — low-power mode — 100 200 μs 1 tDACHP Full-scale settling time (0x080 to 0xF7F) — high-power mode — 15 30 μs 1 — 0.7 1 μs 1 — — 100 mV tCCDACLP Code-to-code settling time (0xBF8 to 0xC08) — low-power mode and high-speed mode Vdacoutl DAC output voltage range low — high-speed mode, no load, DAC set to 0x000 Vdacouth DAC output voltage range high — highspeed mode, no load, DAC set to 0xFFF VDACR −100 — VDACR mV INL Integral non-linearity error — high speed mode — — ±8 LSB 2 DNL Differential non-linearity error — VDACR > 2 V — — ±1 LSB 3 DNL Differential non-linearity error — VDACR = VREF_OUT — — ±1 LSB 4 — ±0.4 ±0.8 %FSR 5 Gain error — ±0.1 ±0.6 %FSR 5 Power supply rejection ratio, VDDA ≥ 2.4 V 60 — 90 dB TCO Temperature coefficient offset voltage — 3.7 — μV/C TGE Temperature coefficient gain error — 0.000421 — %FSR/C Rop Output resistance load = 3 kΩ — — 250 Ω SR Slew rate -80h→ F7Fh→ 80h VOFFSET Offset error EG PSRR 1. 2. 3. 4. 5. 6. V/μs • High power (SPHP) 1.2 1.7 — • Low power (SPLP) 0.05 0.12 — — — -80 CT Channel to channel cross talk BW 3dB bandwidth 6 dB kHz • High power (SPHP) 550 — — • Low power (SPLP) 40 — — Settling within ±1 LSB The INL is measured for 0 + 100 mV to VDACR −100 mV The DNL is measured for 0 + 100 mV to VDACR −100 mV The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to 0x800, temperature range is across the full range of the device K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 57 Peripheral operating requirements and behaviors Figure 24. Typical INL error vs. digital code K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 58 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Figure 25. Offset at half scale vs. temperature 6.6.4 Voltage reference electrical specifications Table 35. VREF full-range operating requirements Symbol Description Min. Max. Unit VDDA Supply voltage 1.71 3.6 V TA Temperature CL Output load capacitance Operating temperature range of the device °C 100 nF Notes 1, 2 1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external reference. 2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range of the device. K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 59 Peripheral operating requirements and behaviors Table 36. VREF full-range operating behaviors Symbol Description Min. Typ. Max. Unit Notes Vout Voltage reference output with factory trim at nominal VDDA and temperature=25C 1.1915 1.195 1.1977 V Vout Voltage reference output — factory trim 1.1584 — 1.2376 V Vout Voltage reference output — user trim 1.193 — 1.197 V Vstep Voltage reference trim step — 0.5 — mV Vtdrift Temperature drift (Vmax -Vmin across the full temperature range) — — 80 mV Ibg Bandgap only current — — 80 µA 1 Ihp High-power buffer current — — 1 mA 1 mV 1, 2 ΔVLOAD Load regulation • current = + 1.0 mA — 2 — • current = - 1.0 mA — 5 — Tstup Buffer startup time — — 100 µs Vvdrift Voltage drift (Vmax -Vmin across the full voltage range) — 2 — mV 1 1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register. 2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load Table 37. VREF limited-range operating requirements Symbol Description Min. Max. Unit TA Temperature 0 50 °C Notes Table 38. VREF limited-range operating behaviors Symbol Vout Description Voltage reference output with factory trim Min. Max. Unit 1.173 1.225 V Notes 6.7 Timers See General switching specifications. 6.8 Communication interfaces K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 60 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.8.1 Ethernet switching specifications The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. 6.8.1.1 MII signal switching specifications The following timing specs meet the requirements for MII style interfaces for a range of transceiver devices. Table 39. MII signal switching specifications Symbol — Description Min. RXCLK frequency Max. Unit — 25 MHz MII1 RXCLK pulse width high 35% 65% RXCLK MII2 RXCLK pulse width low 35% 65% RXCLK MII3 RXD[3:0], RXDV, RXER to RXCLK setup 5 — ns MII4 RXCLK to RXD[3:0], RXDV, RXER hold 5 — ns TXCLK frequency — 25 MHz 35% 65% TXCLK period period — MII5 TXCLK pulse width high period MII6 TXCLK pulse width low 35% 65% TXCLK period MII7 TXCLK to TXD[3:0], TXEN, TXER invalid 2 — ns MII8 TXCLK to TXD[3:0], TXEN, TXER valid — 25 ns MII6 MII5 TXCLK (input) MII8 MII7 TXD[n:0] Valid data TXEN Valid data TXER Valid data Figure 26. MII transmit signal timing diagram K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 61 Peripheral operating requirements and behaviors MII2 MII1 MII3 MII4 RXCLK (input) RXD[n:0] Valid data RXDV Valid data RXER Valid data Figure 27. MII receive signal timing diagram 6.8.1.2 RMII signal switching specifications The following timing specs meet the requirements for RMII style interfaces for a range of transceiver devices. Table 40. RMII signal switching specifications Num — Description EXTAL frequency (RMII input clock RMII_CLK) Min. Max. Unit — 50 MHz RMII1 RMII_CLK pulse width high 35% 65% RMII_CLK period RMII2 RMII_CLK pulse width low 35% 65% RMII_CLK period RMII3 RXD[1:0], CRS_DV, RXER to RMII_CLK setup 4 — ns RMII4 RMII_CLK to RXD[1:0], CRS_DV, RXER hold 2 — ns RMII7 RMII_CLK to TXD[1:0], TXEN invalid 4 — ns RMII8 RMII_CLK to TXD[1:0], TXEN valid — 15 ns 6.8.2 USB electrical specifications The USB electricals for the USB On-the-Go module conform to the standards documented by the Universal Serial Bus Implementers Forum. For the most up-to-date standards, visit http://www.usb.org. K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 62 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.8.3 USB DCD electrical specifications Table 41. USB DCD electrical specifications Symbol Description Min. Typ. Max. Unit VDP_SRC USB_DP source voltage (up to 250 μA) 0.5 — 0.7 V Threshold voltage for logic high 0.8 — 2.0 V 7 10 13 μA VLGC IDP_SRC USB_DP source current IDM_SINK USB_DM sink current 50 100 150 μA RDM_DWN D- pulldown resistance for data pin contact detect 14.25 — 24.8 kΩ VDAT_REF Data detect voltage 0.25 0.325 0.4 V 6.8.4 USB VREG electrical specifications Table 42. USB VREG electrical specifications Symbol Description Min. Typ.1 Max. Unit VREGIN Input supply voltage 2.7 — 5.5 V IDDon Quiescent current — Run mode, load current equal zero, input supply (VREGIN) > 3.6 V — 120 186 μA IDDstby Quiescent current — Standby mode, load current equal zero — 1.1 10 μA IDDoff Quiescent current — Shutdown mode — 650 — nA — — 4 μA • VREGIN = 5.0 V and temperature=25C • Across operating voltage and temperature ILOADrun Maximum load current — Run mode — — 120 mA ILOADstby Maximum load current — Standby mode — — 1 mA VReg33out Regulator output voltage — Input supply (VREGIN) > 3.6 V 3 3.3 3.6 V 2.1 2.8 3.6 V Regulator output voltage — Input supply (VREGIN) < 3.6 V, pass-through mode 2.1 — 3.6 V COUT External output capacitor 1.76 2.2 8.16 μF ESR External output capacitor equivalent series resistance 1 — 100 mΩ ILIM Short circuit current — 290 — mA • Run mode • Standby mode VReg33out Notes 2 1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated. 2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad. K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 63 Peripheral operating requirements and behaviors 6.8.5 ULPI timing specifications The ULPI interface is fully compliant with the industry standard UTMI+ Low Pin Interface. Control and data timing requirements for the ULPI pins are given in the following table. These timings apply to synchronous mode only. All timings are measured with respect to the clock as seen at the USB_CLKIN pin. Table 43. ULPI timing specifications Num Description Min. Typ. Max. Unit USB_CLKIN operating frequency — 60 — MHz USB_CLKIN duty cycle — 50 — % U1 USB_CLKIN clock period — 16.67 — ns U2 Input setup (control and data) 5 — — ns U3 Input hold (control and data) 1 — — ns U4 Output valid (control and data) — — 9.5 ns U5 Output hold (control and data) 1 — — ns U1 USB_CLKIN U2 U3 ULPI_DIR/ULPI_NXT (control input) ULPI_DATAn (input) U4 U5 ULPI_STP (control output) ULPI_DATAn (output) Figure 28. ULPI timing diagram K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 64 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.8.6 CAN switching specifications See General switching specifications. 6.8.7 DSPI switching specifications (limited voltage range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provide DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Table 44. Master mode DSPI timing (limited voltage range) Num Description Min. Max. Unit Operating voltage 2.7 3.6 V Frequency of operation — 30 MHz Notes DS1 DSPI_SCK output cycle time 2 x tBUS — ns DS2 DSPI_SCK output high/low time (tSCK/2) − 2 (tSCK/2) + 2 ns DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) − 2 — ns 1 DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) − 2 — ns 2 DS5 DSPI_SCK to DSPI_SOUT valid — 8.5 ns DS6 DSPI_SCK to DSPI_SOUT invalid −2 — ns DS7 DSPI_SIN to DSPI_SCK input setup 15 — ns DS8 DSPI_SCK to DSPI_SIN input hold 0 — ns 1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK]. 2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. DSPI_PCSn DS3 DS1 DS2 DS4 DSPI_SCK DS7 (CPOL=0) DSPI_SIN DS8 Data First data Last data DS5 DSPI_SOUT First data DS6 Data Last data Figure 29. DSPI classic SPI timing — master mode K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 65 Peripheral operating requirements and behaviors Table 45. Slave mode DSPI timing (limited voltage range) Num Description Operating voltage Min. Max. Unit 2.7 3.6 V 15 MHz 4 x tBUS — ns (tSCK/2) − 2 (tSCK/2) + 2 ns Frequency of operation DS9 DSPI_SCK input cycle time DS10 DSPI_SCK input high/low time DS11 DSPI_SCK to DSPI_SOUT valid — 10 ns DS12 DSPI_SCK to DSPI_SOUT invalid 0 — ns DS13 DSPI_SIN to DSPI_SCK input setup 2 — ns DS14 DSPI_SCK to DSPI_SIN input hold 7 — ns DS15 DSPI_SS active to DSPI_SOUT driven — 14 ns DS16 DSPI_SS inactive to DSPI_SOUT not driven — 14 ns DSPI_SS DS10 DS9 DSPI_SCK DS15 (CPOL=0) DSPI_SOUT DS12 First data DS13 DSPI_SIN DS16 DS11 Last data Data DS14 First data Data Last data Figure 30. DSPI classic SPI timing — slave mode 6.8.8 DSPI switching specifications (full voltage range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provides DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Table 46. Master mode DSPI timing (full voltage range) Num Description Operating voltage Frequency of operation DS1 DSPI_SCK output cycle time Min. Max. Unit Notes 1.71 — 3.6 V 1 15 MHz 4 x tBUS — ns Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 66 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 46. Master mode DSPI timing (full voltage range) (continued) Num Description Min. Max. Unit Notes DS2 DSPI_SCK output high/low time (tSCK/2) - 4 (tSCK/2) + 4 ns DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) − 4 — ns 2 DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) − 4 — ns 3 DS5 DSPI_SCK to DSPI_SOUT valid — 10 ns DS6 DSPI_SCK to DSPI_SOUT invalid -4.5 — ns DS7 DSPI_SIN to DSPI_SCK input setup 20.5 — ns DS8 DSPI_SCK to DSPI_SIN input hold 0 — ns 1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum frequency of operation is reduced. 2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK]. 3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. DSPI_PCSn DS3 DS1 DS2 DS4 DSPI_SCK DS8 DS7 (CPOL=0) DSPI_SIN Data First data Last data DS5 DSPI_SOUT First data DS6 Data Last data Figure 31. DSPI classic SPI timing — master mode Table 47. Slave mode DSPI timing (full voltage range) Num Description Operating voltage Frequency of operation Min. Max. Unit 1.71 3.6 V — 7.5 MHz 8 x tBUS — ns DS9 DSPI_SCK input cycle time DS10 DSPI_SCK input high/low time (tSCK/2) - 4 (tSCK/2) + 4 ns DS11 DSPI_SCK to DSPI_SOUT valid — 20 ns DS12 DSPI_SCK to DSPI_SOUT invalid 0 — ns DS13 DSPI_SIN to DSPI_SCK input setup 2 — ns DS14 DSPI_SCK to DSPI_SIN input hold 7 — ns DS15 DSPI_SS active to DSPI_SOUT driven — 19 ns DS16 DSPI_SS inactive to DSPI_SOUT not driven — 19 ns K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 67 Peripheral operating requirements and behaviors DSPI_SS DS10 DS9 DSPI_SCK DS15 (CPOL=0) DS12 DSPI_SOUT First data DS13 DS16 DS11 Data Last data DS14 DSPI_SIN First data Data Last data Figure 32. DSPI classic SPI timing — slave mode 6.8.9 I2C switching specifications See General switching specifications. 6.8.10 UART switching specifications See General switching specifications. 6.8.11 SDHC specifications The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. Table 48. SDHC switching specifications over a limited operating voltage range Num Symbol Description Min. Max. Unit 2.7 3.6 V Operating voltage Card input clock SD1 fpp Clock frequency (low speed) 0 400 kHz fpp Clock frequency (SD\SDIO full speed) 0 25 MHz fpp Clock frequency (MMC full speed) 0 20 MHz fOD Clock frequency (identification mode) 0 400 kHz SD2 tWL Clock low time 7 — ns SD3 tWH Clock high time 7 — ns SD4 tTLH Clock rise time — 3 ns SD5 tTHL Clock fall time — 3 ns Table continues on the next page... K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 68 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 48. SDHC switching specifications over a limited operating voltage range (continued) Num Symbol Description Min. Max. Unit SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK) SD6 tOD SDHC output delay (output valid) -5 6.5 ns SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK) SD7 tISU SDHC input setup time 5 — ns SD8 tIH SDHC input hold time 0 — ns Table 49. SDHC switching specifications over the full operating voltage range Num Symbol Description Min. Max. Unit Operating voltage 1.71 3.6 V Card input clock SD1 fpp Clock frequency (low speed) 0 400 kHz fpp Clock frequency (SD\SDIO full speed) 0 25 MHz fpp Clock frequency (MMC full speed) 0 20 MHz fOD Clock frequency (identification mode) 0 400 kHz SD2 tWL Clock low time 7 — ns SD3 tWH Clock high time 7 — ns SD4 tTLH Clock rise time — 3 ns SD5 tTHL Clock fall time — 3 ns SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK) SD6 tOD SDHC output delay (output valid) -5 6.5 ns SD7 tISU SDHC input setup time 5 — ns SD8 tIH SDHC input hold time 1.3 — ns SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK) SD3 SD2 SD1 SDHC_CLK SD6 Output SDHC_CMD Output SDHC_DAT[3:0] SD7 SD8 Input SDHC_CMD Input SDHC_DAT[3:0] Figure 33. SDHC timing K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 69 Peripheral operating requirements and behaviors 6.8.12 I2S/SAI Switching Specifications This section provides the AC timing for the I2S/SAI module in master mode (clocks are driven) and slave mode (clocks are input). All timing is given for noninverted serial clock polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP] is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the frame sync (FS) signal shown in the following figures. 6.8.12.1 Normal Run, Wait and Stop mode performance over a limited operating voltage range This section provides the operating performance over a limited operating voltage for the device in Normal Run, Wait and Stop modes. Table 50. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (limited voltage range) Num. Characteristic Min. Max. Unit Operating voltage 2.7 3.6 V S1 I2S_MCLK cycle time 40 — ns S2 I2S_MCLK pulse width high/low 45% 55% MCLK period S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 80 — ns S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output valid — 15 ns S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output invalid 0 — ns S7 I2S_TX_BCLK to I2S_TXD valid — 15 ns S8 I2S_TX_BCLK to I2S_TXD invalid 0 — ns S9 I2S_RXD/I2S_RX_FS input setup before I2S_RX_BCLK 15 — ns S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 — ns K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 70 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors S1 S2 S2 I2S_MCLK (output) S3 I2S_TX_BCLK/ I2S_RX_BCLK (output) S4 S4 S6 S5 I2S_TX_FS/ I2S_RX_FS (output) S10 S9 I2S_TX_FS/ I2S_RX_FS (input) S7 S8 S7 S8 I2S_TXD S9 S10 I2S_RXD Figure 34. I2S/SAI timing — master modes Table 51. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (limited voltage range) Num. Characteristic Min. Max. Unit Operating voltage 2.7 3.6 V S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 80 — ns S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low (input) 45% 55% MCLK period S13 I2S_TX_FS/I2S_RX_FS input setup before I2S_TX_BCLK/I2S_RX_BCLK 4.5 — ns S14 I2S_TX_FS/I2S_RX_FS input hold after I2S_TX_BCLK/I2S_RX_BCLK 2 — ns S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid — 21 — 15 • Multiple SAI Synchronous mode • All other modes ns S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 — ns S17 I2S_RXD setup before I2S_RX_BCLK 4.5 — ns S18 I2S_RXD hold after I2S_RX_BCLK 2 — ns — 25 ns S19 I2S_TX_FS input assertion to I2S_TXD output valid1 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 71 Peripheral operating requirements and behaviors S11 S12 I2S_TX_BCLK/ I2S_RX_BCLK (input) S12 S15 S16 I2S_TX_FS/ I2S_RX_FS (output) S13 I2S_TX_FS/ I2S_RX_FS (input) S19 S14 S15 S16 S15 S16 I2S_TXD S17 S18 I2S_RXD Figure 35. I2S/SAI timing — slave modes 6.8.12.2 Normal Run, Wait and Stop mode performance over the full operating voltage range This section provides the operating performance over the full operating voltage for the device in Normal Run, Wait and Stop modes. Table 52. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S1 I2S_MCLK cycle time 40 — ns S2 I2S_MCLK pulse width high/low 45% 55% MCLK period S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 80 — ns S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output valid — 15 ns S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output invalid -1.0 — ns S7 I2S_TX_BCLK to I2S_TXD valid — 15 ns S8 I2S_TX_BCLK to I2S_TXD invalid 0 — ns S9 I2S_RXD/I2S_RX_FS input setup before I2S_RX_BCLK 20.5 — ns S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 — ns K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 72 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors S1 S2 S2 I2S_MCLK (output) S3 I2S_TX_BCLK/ I2S_RX_BCLK (output) S4 S4 S6 S5 I2S_TX_FS/ I2S_RX_FS (output) S10 S9 I2S_TX_FS/ I2S_RX_FS (input) S7 S8 S7 S8 I2S_TXD S9 S10 I2S_RXD Figure 36. I2S/SAI timing — master modes Table 53. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 80 — ns S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low (input) 45% 55% MCLK period S13 I2S_TX_FS/I2S_RX_FS input setup before I2S_TX_BCLK/I2S_RX_BCLK 5.8 — ns S14 I2S_TX_FS/I2S_RX_FS input hold after I2S_TX_BCLK/I2S_RX_BCLK 2 — ns S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid — 24 — 20.6 • Multiple SAI Synchronous mode • All other modes ns S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 — ns S17 I2S_RXD setup before I2S_RX_BCLK 5.8 — ns S18 I2S_RXD hold after I2S_RX_BCLK 2 — ns — 25 ns S19 I2S_TX_FS input assertion to I2S_TXD output valid1 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 73 Peripheral operating requirements and behaviors S11 S12 I2S_TX_BCLK/ I2S_RX_BCLK (input) S12 S15 S16 I2S_TX_FS/ I2S_RX_FS (output) S13 I2S_TX_FS/ I2S_RX_FS (input) S19 S14 S15 S16 S15 S16 I2S_TXD S17 S18 I2S_RXD Figure 37. I2S/SAI timing — slave modes 6.8.12.3 VLPR, VLPW, and VLPS mode performance over the full operating voltage range This section provides the operating performance over the full operating voltage for the device in VLPR, VLPW, and VLPS modes. Table 54. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S1 I2S_MCLK cycle time 62.5 — ns S2 I2S_MCLK pulse width high/low 45% 55% MCLK period S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 250 — ns S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output valid — 45 ns S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output invalid 0 — ns S7 I2S_TX_BCLK to I2S_TXD valid — 45 ns S8 I2S_TX_BCLK to I2S_TXD invalid -1.6 — ns S9 I2S_RXD/I2S_RX_FS input setup before I2S_RX_BCLK 45 — ns S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 — ns K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 74 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors S1 S2 S2 I2S_MCLK (output) S3 I2S_TX_BCLK/ I2S_RX_BCLK (output) S4 S4 S6 S5 I2S_TX_FS/ I2S_RX_FS (output) S10 S9 I2S_TX_FS/ I2S_RX_FS (input) S7 S8 S7 S8 I2S_TXD S9 S10 I2S_RXD Figure 38. I2S/SAI timing — master modes Table 55. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 250 — ns S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low (input) 45% 55% MCLK period S13 I2S_TX_FS/I2S_RX_FS input setup before I2S_TX_BCLK/I2S_RX_BCLK 30 — ns S14 I2S_TX_FS/I2S_RX_FS input hold after I2S_TX_BCLK/I2S_RX_BCLK 3 — ns S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid — 63 ns S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 — ns S17 I2S_RXD setup before I2S_RX_BCLK 30 — ns S18 I2S_RXD hold after I2S_RX_BCLK 2 — ns — 72 ns S19 I2S_TX_FS input assertion to I2S_TXD output valid1 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 75 Peripheral operating requirements and behaviors S11 S12 I2S_TX_BCLK/ I2S_RX_BCLK (input) S12 S15 S16 I2S_TX_FS/ I2S_RX_FS (output) S13 I2S_TX_FS/ I2S_RX_FS (input) S19 S14 S15 S16 S15 S16 I2S_TXD S17 S18 I2S_RXD Figure 39. I2S/SAI timing — slave modes 6.9 Human-machine interfaces (HMI) 6.9.1 TSI electrical specifications Table 56. TSI electrical specifications Symbol Description Min. Typ. Max. Unit VDDTSI Operating voltage 1.71 — 3.6 V Target electrode capacitance range 1 20 500 pF 1 fREFmax Reference oscillator frequency — 8 15 MHz 2, 3 fELEmax Electrode oscillator frequency — 1 1.8 MHz 2, 4 Internal reference capacitor — 1 — pF Oscillator delta voltage — 600 — mV 2, 5 μA 2, 6 μA 2, 7 CELE CREF VDELTA IREF IELE Reference oscillator current source base current • 2 μA setting (REFCHRG = 0) • 32 μA setting (REFCHRG = 15) Electrode oscillator current source base current • 2 μA setting (EXTCHRG = 0) • 32 μA setting (EXTCHRG = 15) — 2 3 — 36 50 — 2 3 — 36 50 Notes Pres5 Electrode capacitance measurement precision — 8.3333 38400 fF/count 8 Pres20 Electrode capacitance measurement precision — 8.3333 38400 fF/count 9 Pres100 Electrode capacitance measurement precision — 8.3333 38400 fF/count 10 0.008 1.46 — fF/count 11 — — 16 bits Response time @ 20 pF 8 15 25 μs Current added in run mode — 55 — μA Low power mode current adder — 1.3 2.5 μA MaxSens Maximum sensitivity Res TCon20 ITSI_RUN ITSI_LP Resolution 12 13 K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 76 Freescale Semiconductor, Inc. Dimensions 1. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed. 2. Fixed external capacitance of 20 pF. 3. REFCHRG = 2, EXTCHRG=0. 4. REFCHRG = 0, EXTCHRG = 10. 5. VDD = 3.0 V. 6. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current. 7. The programmable current source value is generated by multiplying the SCANC[EXTCHRG] value and the base current. 8. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16. 9. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16. 10. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16. 11. Sensitivity defines the minimum capacitance change when a single count from the TSI module changes. Sensitivity depends on the configuration used. The documented values are provided as examples calculated for a specific configuration of operating conditions using the following equation: (Cref * Iext)/( Iref * PS * NSCN) The typical value is calculated with the following configuration: Iext = 6 μA (EXTCHRG = 2), PS = 128, NSCN = 2, Iref = 16 μA (REFCHRG = 7), Cref = 1.0 pF The minimum value is calculated with the following configuration: Iext = 2 μA (EXTCHRG = 0), PS = 128, NSCN = 32, Iref = 32 μA (REFCHRG = 15), Cref = 0.5 pF The highest possible sensitivity is the minimum value because it represents the smallest possible capacitance that can be measured by a single count. 12. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1 electrode, EXTCHRG = 7. 13. REFCHRG=0, EXTCHRG=4, PS=7, NSCN=0F, LPSCNITV=F, LPO is selected (1 kHz), and fixed external capacitance of 20 pF. Data is captured with an average of 7 periods window. 7 Dimensions 7.1 Obtaining package dimensions Package dimensions are provided in package drawings. To find a package drawing, go to www.freescale.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package Then use this document number 144-pin LQFP 98ASS23177W 144-pin MAPBGA 98ASA00222D 8 Pinout 8.1 Pins with active pull control after reset The following pins are actively pulled up or down after reset: K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 77 Pinout Table 57. Pins with active pull control after reset Pin Active pull direction after reset PTA0 pulldown PTA1 pullup PTA3 pullup PTA4 pullup RESET_b pullup 8.2 K60 Signal Multiplexing and Pin Assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. 144 144 LQFP MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 — L5 RTC_ WAKEUP_B RTC_ WAKEUP_B RTC_ WAKEUP_B — M5 NC NC NC — A10 NC NC NC — B10 NC NC NC — C10 NC NC NC 1 D3 PTE0 ADC1_SE4a ADC1_SE4a PTE0 SPI1_PCS1 UART1_TX SDHC0_D1 I2C1_SDA RTC_CLKOUT 2 D2 PTE1/ LLWU_P0 ADC1_SE5a ADC1_SE5a PTE1/ LLWU_P0 SPI1_SOUT UART1_RX SDHC0_D0 I2C1_SCL SPI1_SIN 3 D1 PTE2/ LLWU_P1 ADC1_SE6a ADC1_SE6a PTE2/ LLWU_P1 SPI1_SCK UART1_CTS_ SDHC0_DCLK b 4 E4 PTE3 ADC1_SE7a ADC1_SE7a PTE3 SPI1_SIN UART1_RTS_ SDHC0_CMD b 5 E5 VDD VDD VDD 6 F6 VSS VSS VSS 7 E3 PTE4/ LLWU_P2 DISABLED PTE4/ LLWU_P2 SPI1_PCS0 UART3_TX SDHC0_D3 8 E2 PTE5 DISABLED PTE5 SPI1_PCS2 UART3_RX SDHC0_D2 FTM3_CH0 9 E1 PTE6 DISABLED PTE6 SPI1_PCS3 UART3_CTS_ I2S0_MCLK b FTM3_CH1 10 F4 PTE7 DISABLED PTE7 UART3_RTS_ I2S0_RXD0 b FTM3_CH2 11 F3 PTE8 ADC2_SE16 ADC2_SE16 PTE8 I2S0_RXD1 UART5_TX I2S0_RX_FS FTM3_CH3 12 F2 PTE9 ADC2_SE17 ADC2_SE17 PTE9 I2S0_TXD1 UART5_RX I2S0_RX_ BCLK FTM3_CH4 13 F1 PTE10 DISABLED PTE10 UART5_CTS_ I2S0_TXD0 b EzPort SPI1_SOUT USB_SOF_ OUT FTM3_CH5 K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 78 Freescale Semiconductor, Inc. Pinout 144 144 LQFP MAP BGA Pin Name Default ALT0 ALT1 14 G4 PTE11 ADC3_SE16 ADC3_SE16 PTE11 15 G3 PTE12 ADC3_SE17 ADC3_SE17 PTE12 16 E6 VDD VDD VDD 17 F7 VSS VSS VSS 18 H3 VSS VSS VSS 19 H1 USB0_DP USB0_DP USB0_DP 20 H2 USB0_DM USB0_DM USB0_DM 21 G1 VOUT33 VOUT33 VOUT33 22 G2 VREGIN VREGIN VREGIN 23 J1 PGA2_DP/ ADC2_DP0/ ADC3_DP3/ ADC0_DP1 PGA2_DP/ ADC2_DP0/ ADC3_DP3/ ADC0_DP1 PGA2_DP/ ADC2_DP0/ ADC3_DP3/ ADC0_DP1 24 J2 PGA2_DM/ ADC2_DM0/ ADC3_DM3/ ADC0_DM1 PGA2_DM/ ADC2_DM0/ ADC3_DM3/ ADC0_DM1 PGA2_DM/ ADC2_DM0/ ADC3_DM3/ ADC0_DM1 25 K1 PGA3_DP/ ADC3_DP0/ ADC2_DP3/ ADC1_DP1 PGA3_DP/ ADC3_DP0/ ADC2_DP3/ ADC1_DP1 PGA3_DP/ ADC3_DP0/ ADC2_DP3/ ADC1_DP1 26 K2 PGA3_DM/ ADC3_DM0/ ADC2_DM3/ ADC1_DM1 PGA3_DM/ ADC3_DM0/ ADC2_DM3/ ADC1_DM1 PGA3_DM/ ADC3_DM0/ ADC2_DM3/ ADC1_DM1 27 L1 PGA0_DP/ ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3 28 L2 PGA0_DM/ ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3 29 M1 PGA1_DP/ ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3 30 M2 PGA1_DM/ ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3 31 H5 VDDA VDDA VDDA 32 G5 VREFH VREFH VREFH 33 G6 VREFL VREFL VREFL 34 H6 VSSA VSSA VSSA 35 K3 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 ALT2 ALT3 ALT4 ALT5 UART5_RTS_ I2S0_TX_FS b I2S0_TX_ BCLK ALT6 ALT7 EzPort FTM3_CH6 FTM3_CH7 K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 79 Pinout 144 144 LQFP MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort 36 J3 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 37 M3 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 38 L3 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 39 L4 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 40 M7 XTAL32 XTAL32 XTAL32 41 M6 EXTAL32 EXTAL32 EXTAL32 42 L6 VBAT VBAT VBAT 43 — VDD VDD VDD 44 — VSS VSS VSS 45 M4 PTE24 ADC0_SE17/ EXTAL1 ADC0_SE17/ EXTAL1 PTE24 CAN1_TX UART4_TX I2S1_TX_FS EWM_OUT_b I2S1_RXD1 46 K5 PTE25 ADC0_SE18/ XTAL1 ADC0_SE18/ XTAL1 PTE25 CAN1_RX UART4_RX I2S1_TX_ BCLK EWM_IN I2S1_TXD1 47 K4 PTE26 ADC3_SE5b ADC3_SE5b PTE26 ENET_1588_ CLKIN UART4_CTS_ I2S1_TXD0 b 48 J4 PTE27 ADC3_SE4b ADC3_SE4b PTE27 49 H4 PTE28 ADC3_SE7a ADC3_SE7a PTE28 50 J5 PTA0 JTAG_TCLK/ SWD_CLK/ EZP_CLK TSI0_CH1 PTA0 UART0_CTS_ FTM0_CH5 b/ UART0_COL_ b JTAG_TCLK/ SWD_CLK EZP_CLK 51 J6 PTA1 JTAG_TDI/ EZP_DI TSI0_CH2 PTA1 UART0_RX FTM0_CH6 JTAG_TDI EZP_DI 52 K6 PTA2 JTAG_TDO/ TSI0_CH3 TRACE_SWO/ EZP_DO PTA2 UART0_TX FTM0_CH7 JTAG_TDO/ EZP_DO TRACE_SWO 53 K7 PTA3 JTAG_TMS/ SWD_DIO TSI0_CH4 PTA3 UART0_RTS_ FTM0_CH0 b 54 L7 PTA4/ LLWU_P3 NMI_b/ EZP_CS_b TSI0_CH5 PTA4/ LLWU_P3 55 M8 PTA5 DISABLED 56 E7 VDD VDD VDD 57 G7 VSS VSS VSS 58 J7 PTA6 ADC3_SE6a ADC3_SE6a RTC_CLKOUT USB_CLKIN UART4_RTS_ I2S1_MCLK b JTAG_TMS/ SWD_DIO FTM0_CH1 NMI_b PTA5 USB_CLKIN FTM0_CH2 RMII0_RXER/ MII0_RXER CMP2_OUT PTA6 ULPI_CLK FTM0_CH3 I2S1_RXD0 CLKOUT I2S0_TX_ BCLK EZP_CS_b JTAG_TRST_ b TRACE_ CLKOUT K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 80 Freescale Semiconductor, Inc. Pinout 144 144 LQFP MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 59 J8 PTA7 ADC0_SE10 ADC0_SE10 PTA7 ULPI_DIR FTM0_CH4 I2S1_RX_ BCLK 60 K8 PTA8 ADC0_SE11 ADC0_SE11 PTA8 ULPI_NXT FTM1_CH0 I2S1_RX_FS FTM1_QD_ PHA TRACE_D2 61 L8 PTA9 ADC3_SE5a ADC3_SE5a PTA9 ULPI_STP FTM1_CH1 MII0_RXD3 FTM1_QD_ PHB TRACE_D1 62 M9 PTA10 ADC3_SE4a ADC3_SE4a PTA10 ULPI_DATA0 FTM2_CH0 MII0_RXD2 FTM2_QD_ PHA TRACE_D0 63 L9 PTA11 ADC3_SE15 ADC3_SE15 PTA11 ULPI_DATA1 FTM2_CH1 MII0_RXCLK FTM2_QD_ PHB 64 K9 PTA12 CMP2_IN0 CMP2_IN0 PTA12 CAN0_TX FTM1_CH0 RMII0_RXD1/ MII0_RXD1 I2S0_TXD0 FTM1_QD_ PHA 65 J9 PTA13/ LLWU_P4 CMP2_IN1 CMP2_IN1 PTA13/ LLWU_P4 CAN0_RX FTM1_CH1 RMII0_RXD0/ MII0_RXD0 I2S0_TX_FS FTM1_QD_ PHB 66 L10 PTA14 CMP3_IN0 CMP3_IN0 PTA14 SPI0_PCS0 UART0_TX RMII0_CRS_ DV/ MII0_RXDV I2S0_RX_ BCLK I2S0_TXD1 67 L11 PTA15 CMP3_IN1 CMP3_IN1 PTA15 SPI0_SCK UART0_RX RMII0_TXEN/ MII0_TXEN I2S0_RXD0 68 K10 PTA16 CMP3_IN2 CMP3_IN2 PTA16 SPI0_SOUT UART0_CTS_ RMII0_TXD0/ b/ MII0_TXD0 UART0_COL_ b I2S0_RX_FS 69 K11 PTA17 ADC1_SE17 ADC1_SE17 PTA17 SPI0_SIN UART0_RTS_ RMII0_TXD1/ b MII0_TXD1 I2S0_MCLK 70 E8 VDD VDD VDD 71 G8 VSS VSS VSS 72 M12 PTA18 EXTAL0 EXTAL0 PTA18 FTM0_FLT2 FTM_CLKIN0 73 M11 PTA19 XTAL0 XTAL0 PTA19 FTM1_FLT0 FTM_CLKIN1 LPTMR0_ ALT1 74 L12 RESET_b RESET_b RESET_b 75 K12 PTA24 CMP3_IN4 CMP3_IN4 PTA24 ULPI_DATA2 MII0_TXD2 FB_A29 76 J12 PTA25 CMP3_IN5 CMP3_IN5 PTA25 ULPI_DATA3 MII0_TXCLK FB_A28 77 J11 PTA26 ADC2_SE15 ADC2_SE15 PTA26 ULPI_DATA4 MII0_TXD3 FB_A27 78 J10 PTA27 ADC2_SE14 ADC2_SE14 PTA27 ULPI_DATA5 MII0_CRS FB_A26 79 H12 PTA28 ADC2_SE13 ADC2_SE13 PTA28 ULPI_DATA6 MII0_TXER FB_A25 80 H11 PTA29 ADC2_SE12 ADC2_SE12 PTA29 ULPI_DATA7 MII0_COL FB_A24 81 H10 PTB0/ LLWU_P5 ADC0_SE8/ ADC1_SE8/ ADC2_SE8/ ADC3_SE8/ TSI0_CH0 ADC0_SE8/ ADC1_SE8/ ADC2_SE8/ ADC3_SE8/ TSI0_CH0 PTB0/ LLWU_P5 I2C0_SCL FTM1_CH0 RMII0_MDIO/ MII0_MDIO FTM1_QD_ PHA 82 H9 PTB1 ADC0_SE9/ ADC1_SE9/ ADC2_SE9/ ADC3_SE9/ TSI0_CH6 ADC0_SE9/ ADC1_SE9/ ADC2_SE9/ ADC3_SE9/ TSI0_CH6 PTB1 I2C0_SDA FTM1_CH1 RMII0_MDC/ MII0_MDC FTM1_QD_ PHB EzPort TRACE_D3 I2S0_RXD1 K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 81 Pinout 144 144 LQFP MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 83 G12 PTB2 ADC0_SE12/ TSI0_CH7 ADC0_SE12/ TSI0_CH7 PTB2 I2C0_SCL UART0_RTS_ ENET0_1588_ b TMR0 FTM0_FLT3 84 G11 PTB3 ADC0_SE13/ TSI0_CH8 ADC0_SE13/ TSI0_CH8 PTB3 I2C0_SDA UART0_CTS_ ENET0_1588_ b/ TMR1 UART0_COL_ b FTM0_FLT0 85 G10 PTB4 ADC1_SE10 ADC1_SE10 PTB4 ENET0_1588_ TMR2 FTM1_FLT0 86 G9 PTB5 ADC1_SE11 ADC1_SE11 PTB5 ENET0_1588_ TMR3 FTM2_FLT0 87 F12 PTB6 ADC1_SE12 ADC1_SE12 PTB6 FB_AD23 88 F11 PTB7 ADC1_SE13 ADC1_SE13 PTB7 FB_AD22 89 F10 PTB8 DISABLED PTB8 90 F9 PTB9 DISABLED PTB9 91 E12 PTB10 ADC1_SE14 ADC1_SE14 92 E11 PTB11 ADC1_SE15 ADC1_SE15 93 H7 VSS VSS VSS 94 F5 VDD VDD VDD 95 E10 PTB16 TSI0_CH9 96 E9 PTB17 97 D12 98 UART3_RTS_ b FB_AD21 SPI1_PCS1 UART3_CTS_ b FB_AD20 PTB10 SPI1_PCS0 UART3_RX I2S1_TX_ BCLK FB_AD19 FTM0_FLT1 PTB11 SPI1_SCK UART3_TX I2S1_TX_FS FB_AD18 FTM0_FLT2 TSI0_CH9 PTB16 SPI1_SOUT UART0_RX I2S1_TXD0 FB_AD17 EWM_IN TSI0_CH10 TSI0_CH10 PTB17 SPI1_SIN UART0_TX I2S1_TXD1 FB_AD16 EWM_OUT_b PTB18 TSI0_CH11 TSI0_CH11 PTB18 CAN0_TX FTM2_CH0 I2S0_TX_ BCLK FB_AD15 FTM2_QD_ PHA D11 PTB19 TSI0_CH12 TSI0_CH12 PTB19 CAN0_RX FTM2_CH1 I2S0_TX_FS FB_OE_b FTM2_QD_ PHB 99 D10 PTB20 ADC2_SE4a ADC2_SE4a PTB20 SPI2_PCS0 FB_AD31/ CMP0_OUT NFC_DATA15 100 D9 PTB21 ADC2_SE5a ADC2_SE5a PTB21 SPI2_SCK FB_AD30/ CMP1_OUT NFC_DATA14 101 C12 PTB22 DISABLED PTB22 SPI2_SOUT FB_AD29/ CMP2_OUT NFC_DATA13 102 C11 PTB23 DISABLED PTB23 SPI2_SIN SPI0_PCS5 FB_AD28/ CMP3_OUT NFC_DATA12 103 B12 PTC0 ADC0_SE14/ TSI0_CH13 ADC0_SE14/ TSI0_CH13 PTC0 SPI0_PCS4 PDB0_EXTRG FB_AD14/ I2S0_TXD1 NFC_DATA11 104 B11 PTC1/ LLWU_P6 ADC0_SE15/ TSI0_CH14 ADC0_SE15/ TSI0_CH14 PTC1/ LLWU_P6 SPI0_PCS3 UART1_RTS_ FTM0_CH0 b FB_AD13/ I2S0_TXD0 NFC_DATA10 105 A12 PTC2 ADC0_SE4b/ CMP1_IN0/ TSI0_CH15 ADC0_SE4b/ CMP1_IN0/ TSI0_CH15 PTC2 SPI0_PCS2 UART1_CTS_ FTM0_CH1 b FB_AD12/ NFC_DATA9 I2S0_TX_FS 106 A11 PTC3/ LLWU_P7 CMP1_IN1 CMP1_IN1 PTC3/ LLWU_P7 SPI0_PCS1 UART1_RX CLKOUT I2S0_TX_ BCLK 107 H8 VSS VSS VSS 108 — VDD VDD VDD FTM0_CH2 ALT7 EzPort K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 82 Freescale Semiconductor, Inc. Pinout 144 144 LQFP MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 109 A9 PTC4/ LLWU_P8 DISABLED PTC4/ LLWU_P8 SPI0_PCS0 UART1_TX FTM0_CH3 FB_AD11/ NFC_DATA8 CMP1_OUT I2S1_TX_ BCLK 110 D8 PTC5/ LLWU_P9 DISABLED PTC5/ LLWU_P9 SPI0_SCK LPTMR0_ ALT2 I2S0_RXD0 FB_AD10/ NFC_DATA7 CMP0_OUT I2S1_TX_FS 111 C8 PTC6/ LLWU_P10 CMP0_IN0 CMP0_IN0 PTC6/ LLWU_P10 SPI0_SOUT PDB0_EXTRG I2S0_RX_ BCLK FB_AD9/ NFC_DATA6 I2S0_MCLK 112 B8 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_SIN USB_SOF_ OUT I2S0_RX_FS FB_AD8/ NFC_DATA5 113 A8 PTC8 ADC1_SE4b/ CMP0_IN2 ADC1_SE4b/ CMP0_IN2 PTC8 FTM3_CH4 I2S0_MCLK FB_AD7/ NFC_DATA4 114 D7 PTC9 ADC1_SE5b/ CMP0_IN3 ADC1_SE5b/ CMP0_IN3 PTC9 FTM3_CH5 I2S0_RX_ BCLK FB_AD6/ NFC_DATA3 FTM2_FLT0 115 C7 PTC10 ADC1_SE6b ADC1_SE6b PTC10 I2C1_SCL FTM3_CH6 I2S0_RX_FS FB_AD5/ NFC_DATA2 I2S1_MCLK 116 B7 PTC11/ LLWU_P11 ADC1_SE7b ADC1_SE7b PTC11/ LLWU_P11 I2C1_SDA FTM3_CH7 I2S0_RXD1 FB_RW_b/ NFC_WE 117 A7 PTC12 DISABLED PTC12 UART4_RTS_ b FB_AD27 118 D6 PTC13 DISABLED PTC13 UART4_CTS_ b FB_AD26 119 C6 PTC14 DISABLED PTC14 UART4_RX FB_AD25 120 B6 PTC15 DISABLED PTC15 UART4_TX FB_AD24 121 — VSS VSS VSS 122 — VDD VDD VDD 123 A6 PTC16 DISABLED PTC16 CAN1_RX UART3_RX ENET0_1588_ FB_CS5_b/ NFC_RB TMR0 FB_TSIZ1/ FB_BE23_16_ b 124 D5 PTC17 DISABLED PTC17 CAN1_TX UART3_TX ENET0_1588_ FB_CS4_b/ NFC_CE0_b TMR1 FB_TSIZ0/ FB_BE31_24_ b 125 C5 PTC18 DISABLED PTC18 UART3_RTS_ ENET0_1588_ FB_TBST_b/ NFC_CE1_b b TMR2 FB_CS2_b/ FB_BE15_8_b 126 B5 PTC19 DISABLED PTC19 UART3_CTS_ ENET0_1588_ FB_CS3_b/ b TMR3 FB_BE7_0_b FB_TA_b 127 A5 PTD0/ LLWU_P12 DISABLED PTD0/ LLWU_P12 SPI0_PCS0 UART2_RTS_ FTM3_CH0 b FB_ALE/ FB_CS1_b/ FB_TS_b I2S1_RXD1 128 D4 PTD1 ADC0_SE5b PTD1 SPI0_SCK UART2_CTS_ FTM3_CH1 b FB_CS0_b I2S1_RXD0 129 C4 PTD2/ LLWU_P13 DISABLED PTD2/ LLWU_P13 SPI0_SOUT UART2_RX FTM3_CH2 FB_AD4 I2S1_RX_FS 130 B4 PTD3 DISABLED PTD3 SPI0_SIN UART2_TX FTM3_CH3 FB_AD3 I2S1_RX_ BCLK 131 A4 PTD4/ LLWU_P14 DISABLED PTD4/ LLWU_P14 SPI0_PCS1 UART0_RTS_ FTM0_CH4 b FB_AD2/ NFC_DATA1 EWM_IN ADC0_SE5b EzPort FTM3_FLT0 K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 83 Pinout 144 144 LQFP MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 132 A3 PTD5 ADC0_SE6b ADC0_SE6b PTD5 SPI0_PCS2 UART0_CTS_ FTM0_CH5 b/ UART0_COL_ b FB_AD1/ NFC_DATA0 EWM_OUT_b 133 A2 PTD6/ LLWU_P15 ADC0_SE7b ADC0_SE7b PTD6/ LLWU_P15 SPI0_PCS3 UART0_RX FTM0_CH6 FB_AD0 FTM0_FLT0 134 M10 VSS VSS VSS 135 F8 VDD VDD VDD 136 A1 PTD7 DISABLED PTD7 CMT_IRO UART0_TX FTM0_CH7 137 C9 PTD8 DISABLED PTD8 I2C0_SCL UART5_RX FB_A16/ NFC_CLE 138 B9 PTD9 DISABLED PTD9 I2C0_SDA UART5_TX FB_A17/ NFC_ALE 139 B3 PTD10 DISABLED PTD10 UART5_RTS_ b FB_A18/ NFC_RE 140 B2 PTD11 DISABLED PTD11 SPI2_PCS0 UART5_CTS_ SDHC0_ b CLKIN FB_A19 141 B1 PTD12 DISABLED PTD12 SPI2_SCK FTM3_FLT0 SDHC0_D4 FB_A20 142 C3 PTD13 DISABLED PTD13 SPI2_SOUT SDHC0_D5 FB_A21 143 C2 PTD14 DISABLED PTD14 SPI2_SIN SDHC0_D6 FB_A22 144 C1 PTD15 DISABLED PTD15 SPI2_PCS1 SDHC0_D7 FB_A23 ALT7 EzPort FTM0_FLT1 8.3 K60 Pinouts The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 84 Freescale Semiconductor, Inc. PTD15 PTD14 PTD13 PTD12 PTD11 PTD10 PTD9 PTD8 PTD7 VDD VSS PTD6/LLWU_P15 PTD5 PTD4/LLWU_P14 PTD3 PTD2/LLWU_P13 PTD1 PTD0/LLWU_P12 PTC19 PTC18 PTC17 PTC16 VDD VSS PTC15 PTC14 PTC13 PTC12 PTC11/LLWU_P11 PTC10 PTC9 PTC8 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 Pinout PTE0 1 108 VDD PTE1/LLWU_P0 2 107 VSS PTE2/LLWU_P1 3 106 PTC3/LLWU_P7 PTE3 4 105 PTC2 VDD 5 104 PTC1/LLWU_P6 VSS 6 103 PTC0 PTE4/LLWU_P2 7 102 PTB23 PTE5 8 101 PTB22 PTE6 9 100 PTB21 PTE7 10 99 PTB20 RESET_b ADC0_SE16/CMP1_IN2/ADC0_SE21 36 73 PTA19 72 74 PTA18 35 71 PTA24 ADC1_SE16/CMP2_IN2/ADC0_SE22 VSS 75 70 34 VDD PTA25 VSSA 69 PTA26 76 PTA17 77 33 68 32 VREFL PTA16 VREFH 67 PTA27 PTA15 78 66 31 PTA14 PTA28 VDDA 65 79 PTA13/LLWU_P4 30 64 PTA29 PGA1_DM/ADC1_DM0/ADC0_DM3 PTA12 80 63 29 PTA11 PTB0/LLWU_P5 PGA1_DP/ADC1_DP0/ADC0_DP3 62 81 PTA10 28 61 PTB1 PGA0_DM/ADC0_DM0/ADC1_DM3 PTA9 82 60 27 PTA8 PTB2 PGA0_DP/ADC0_DP0/ADC1_DP3 59 83 PTA7 26 58 PTB3 PGA3_DM/ADC3_DM0/ADC2_DM3/ADC1_DM1 PTA6 84 57 25 VSS PTB4 PGA3_DP/ADC3_DP0/ADC2_DP3/ADC1_DP1 56 85 VDD 24 55 PTB5 PGA2_DM/ADC2_DM0/ADC3_DM3/ADC0_DM1 PTA5 86 54 23 PTA4/LLWU_P3 PTB6 PGA2_DP/ADC2_DP0/ADC3_DP3/ADC0_DP1 53 87 PTA3 22 52 PTB7 VREGIN PTA2 88 51 21 PTA1 PTB8 VOUT33 50 89 PTA0 20 49 PTB9 USB0_DM PTE28 90 48 19 PTE27 PTB10 USB0_DP 47 91 PTE26 18 46 PTB11 VSS PTE25 92 45 17 PTE24 VSS VSS 44 93 VSS 16 43 VDD VDD VDD 94 42 15 VBAT PTB16 PTE12 41 95 EXTAL32 14 40 PTB17 PTE11 XTAL32 96 39 13 DAC1_OUT/CMP0_IN4/CMP2_IN3/ADC1_SE23 PTB18 PTE10 38 PTB19 97 37 98 12 DAC0_OUT/CMP1_IN3/ADC0_SE23 11 VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18 PTE8 PTE9 Figure 40. K60 144 LQFP Pinout Diagram K60 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. 85 Revision History 1 2 3 4 5 6 7 8 9 10 11 12 A PTD7 PTD6/ LLWU_P15 PTD5 PTD4/ LLWU_P14 PTD0/ LLWU_P12 PTC16 PTC12 PTC8 PTC4/ LLWU_P8 NC PTC3/ LLWU_P7 PTC2 A B PTD12 PTD11 PTD10 PTD3 PTC19 PTC15 PTC11/ LLWU_P11 PTC7 PTD9 NC PTC1/ LLWU_P6 PTC0 B C PTD15 PTD14 PTD13 PTD2/ LLWU_P13 PTC18 PTC14 PTC10 PTC6/ LLWU_P10 PTD8 NC PTB23 PTB22 C D PTE2/ LLWU_P1 PTE1/ LLWU_P0 PTE0 PTD1 PTC17 PTC13 PTC9 PTC5/ LLWU_P9 PTB21 PTB20 PTB19 PTB18 D E PTE6 PTE5 PTE4/ LLWU_P2 PTE3 VDD VDD VDD VDD PTB17 PTB16 PTB11 PTB10 E F PTE10 PTE9 PTE8 PTE7 VDD VSS VSS VDD PTB9 PTB8 PTB7 PTB6 F G VOUT33 VREGIN PTE12 PTE11 VREFH VREFL VSS VSS PTB5 PTB4 PTB3 PTB2 G H USB0_DP USB0_DM VSS PTE28 VDDA VSSA VSS VSS PTB1 PTB0/ LLWU_P5 PTA29 PTA28 H J PGA2_DP/ ADC2_DP0/ ADC3_DP3/ ADC0_DP1 PGA2_DM/ ADC0_SE16/ ADC2_DM0/ CMP1_IN2/ ADC3_DM3/ ADC0_SE21 ADC0_DM1 PTE27 PTA0 PTA1 PTA6 PTA7 PTA13/ LLWU_P4 PTA27 PTA26 PTA25 J K PGA3_DP/ ADC2_DP3/ ADC1_DP1 PGA3_DM/ ADC1_SE16/ ADC3_DM0/ CMP2_IN2/ ADC2_DM3/ ADC0_SE22 ADC1_DM1 PTE26 PTE25 PTA2 PTA3 PTA8 PTA12 PTA16 PTA17 PTA24 K L PGA0_DP/ ADC0_DP0/ ADC1_DP3 PGA0_DM/ ADC0_DM0/ ADC1_DM3 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 RTC_ WAKEUP_B VBAT PTA4/ LLWU_P3 PTA9 PTA11 PTA14 PTA15 RESET_b L PGA1_DP/ M ADC1_DP0/ ADC0_DP3 PGA1_DM/ ADC1_DM0/ ADC0_DM3 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 PTE24 NC EXTAL32 XTAL32 PTA5 PTA10 VSS PTA19 PTA18 M 2 3 4 5 6 7 8 9 10 11 12 1 Figure 41. K60 144 MAPBGA Pinout Diagram 9 Revision History The following table provides a revision history for this document. Table 58. Revision History Rev. No. Date Substantial Changes 3 3/2012 Initial public release 4 10/2012 Replaced TBDs throughout. K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 86 Freescale Semiconductor, Inc. Revision History K60 Sub-Family Data Sheet, Rev. 4, 10/2012. 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