AD ADM1232AAN Microprocessor supervisory circuit Datasheet

a
FEATURES
Superior Upgrade for MAX1232 and Dallas DS1232
Low Power Consumption (500 ␮A max)
Adjustable Precision Voltage Monitor with +4.5 V and
+4.75 V Options
Adjustable STROBE Monitor with 150 ms, 600 ms or
1.2 sec Options
No External Components
Fast (20 ns) Strobe Pulsewidth
APPLICATIONS
Microprocessor Systems
Portable Equipment
Computers
Controllers
Intelligent Instruments
Automotive Systems
Protection Against Damage Caused by ␮P Failure
Microprocessor
Supervisory Circuit
ADM1232A
FUNCTIONAL BLOCK DIAGRAM
VCC
TOLERANCE
RESET
GENERATOR
VREF
RESET
PB RESET
DEBOUNCE
TD
WATCHDOG
TIMEBASE
SELECT
WATCHDOG
TIMER
STROBE
ADM1232A
GND
GENERAL DESCRIPTION
+5V
The ADM1232A is a superior, pin-compatible upgrade for the
MAX1232 and the DS1232LP and DS1232. The ADM1232A
can detect strobe pulsewidths as narrow as 20 ns, making it
compatible with high speed microprocessors. The Analog
Devices ADM1232A is a microprocessor monitoring circuit
that can monitor:
1. Microprocessor Supply Voltage.
2. Whether a Microprocessor has locked up.
3. An External Interrupt.
RESET
5%/10%
TOLERANCE
SELECT
10kV
+5V
ADM1232A
MICROPROCESSOR
ADM1232
RESET
STROBE
STROBE
RESET
GND
TD
I/O
RESET
TOLERANCE
TOLERANCE
The ADM1232A is available in four different packages:
1.
2.
3.
4.
The ADM1232AARM in an 8-lead µSOIC (RM-8).
The ADM1232AAN in an 8-lead PDIP (N-8).
The ADM1232AARW in a 16-lead wide SOIC (R-16).
The ADM1232AARN is an 8-lead narrow SOIC (R-8).
Figure 1. Typical Supply Monitoring Application
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
ADM1232A–SPECIFICATIONS (V
Parameter
Min
TEMPERATURE
–40
POWER SUPPLY
Voltage
Current
4.5
STROBE AND PB RESET INPUTS
Input High Level
Input Low Level
INPUT LEAKAGE CURRENT
(STROBE, TOLERANCE)
TD
CC
= Full Operating Range, TA = TMIN to TMAX unless otherwise noted)
Typ
Max
Units
Test Conditions/Comments
+85
°C
TA = TMIN to TMAX
5.5
50
500
V
µA
µA
VIL , VIH = CMOS Levels
VIL , VIH = TTL Levels
VCC + 0.3
+0.8
V
V
+1.0
1.6
µA
µA
10
–12
mA
mA
When V CC Is at 4.5 V–5.5 V
When V CC Is at 4.5 V–5.5 V
V
While sourcing less than 500 µA, RESET remains
within 0.5 V of V CC on power-down until VCC
drops below 2.0 V. While sinking less than
500 µA, RESET remains within 0.5 V of GND
on power-down until V CC drops below 2.0 V.
5.0
20
200
2.0
–0.3
–1.0
OUTPUT CURRENT
RESET
RESET, RESET
8
–8
OUTPUT VOLTAGE
RESET/RESET
VCC – 0.5 VCC – 0.1
RESET/RESET High Level
RESET/RESET Low Level
0.4
2.4
1 V OPERATION
RESET Output Voltage
RESET Output Voltage
VCC TRIP POINT
5%
10%
V
V
While Sourcing Less than 50 µA
While Sinking Less than 50 µA
4.74
4.49
V
V
TOLERANCE = GND
TOLERANCE = VCC
5
7
pF
pF
TA = +25°C
TA = +25°C
PB RESET Must Be Held Low for a Minimum
of 20 ms to Guarantee a Reset
VCC – 0.1
0.1
4.5
4.25
4.62
4.37
CAPACITANCE
Input (STROBE, TOLERANCE)
Output (RESET, RESET)
V
V
PB RESET
Time
Delay
20
1
4
20
ms
ms
RESET ACTIVE TIME
250
610
1000
ms
20
62.5
250
500
150
600
1200
250
1000
2000
ns
ms
ms
ms
TD = 0 V
TD = Floating
TD = VCC
µS
µS
Guaranteed by Design
Guaranteed by Design
50
µs
1000
ms
After VCC Falls Below the Set Tolerance Voltage
(Figure 5)
After VCC Rises Above the Set Tolerance Voltage
STROBE
Pulsewidth
Timeout Period
VCC
Fall Time
Rise Time
10
0
VCC FAIL DETECT TO RESET OUTPUT DELAY
RESET AND RESET Are Logically Correct
250
610
Specifications subject to change without notice.
–2–
REV. 0
ADM1232A
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
N-8
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW
Derate by 13.5 mW/°C above 25°C
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 100°C/W
R-16
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW
Derate by 12 mW/°C above 25°C
θJA Thermal Impedance (Still Air) . . . . . . . . . . . . . . 73°C/W
RM-8
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW
Derate by 12 mW/°C above 25°C
θJA Thermal Impedance (Still Air) . . . . . . . . . . . . . 206°C/W
R-8
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 µW
Derate by 12 mW/°C above 25°C
θJA Thermal Impedance (Still Air) . . . . . . . . . . . . . 153°C/W
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods of time may affect device reliability.
ORDERING GUIDE
Model
Temperature
Range
Package
Options*
ADM1232AARM
ADM1232AAN
ADM1232AARW
ADM1232AARN
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
RM-8
N-8
R-16
R-8
*N = Plastic DIP; R = Small Outline; RM = µSOIC.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADM1232A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. 0
–3–
WARNING!
ESD SENSITIVE DEVICE
ADM1232A
PIN FUNCTION DESCRIPTIONS
Mnemonic
Function
PB RESET
Push Button Reset Input. This debounced input will ignore pulses of less than 1 ms and is guaranteed to respond to pulses greater than 20 ms.
TD
Time Delay Set allows the user to select the maximum amount of time the ADM1232A will allow the STROBE
input to remain inactive (i.e., STROBE is not receiving any high-to-low transitions), without forcing the
ADM1232A to generate a RESET pulse. (See STROBE specifications, Figure 4 and the note on STROBE
timeout selection.)
TOLERANCE
Tolerance Input. This input will determine how much the supply voltage will be allowed to decrease (as a percentage tolerance) before a RESET is asserted. Connect to VCC for 10% and GND for 5%.
GND
0 V ground reference for all signals.
RESET
Active high logic output. Will be asserted when:
1. VCC decreases below the amount specified by the TOLERANCE input or,
2. PB RESET is forced low or,
3. If there are no high-to-low transitions within the limits set by TD at STROBE or,
4. During power-up.
RESET
Inverse of RESET, with an open drain output.
STROBE
The STROBE input is used to monitor the activity of a microprocessor. If there are no high-to-low transitions within the time specified by TD, a reset will be asserted.
VCC
Power supply input +5 V.
PIN CONFIGURATIONS
R-16
NC 1
PB RESET 2
NC 3
RM-8
16 NC
15 VCC
14 NC
ADM1232A 13
TD 4
STROBE
TOP VIEW
NC 5 (Not to Scale) 12 NC
TOLERANCE 6
NC 7
GND 8
PB RESET 1
TD 2
N-8 and R-8
8 VCC
ADM1232A 7
STROBE
TOP VIEW
TOLERANCE 3 (Not to Scale) 6 RESET
5 RESET
GND 4
PB RESET 1
TD 2
8 VCC
ADM1232A 7 STROBE
TOP VIEW
TOLERANCE 3 (Not to Scale) 6 RESET
GND 4
5 RESET
11 RESET
10 NC
9 RESET
NC = NO CONNECT
–4–
REV. 0
ADM1232A
STROBE Timeout Selection
CIRCUIT INFORMATION
PB RESET
The PB RESET input makes it possible to manually reset a system
using either a standard push-button switch or a logic low
input. An internal debounce circuit provides glitch immunity
when used with a switch, reducing the effects of glitches on the
line. The debounce circuit is guaranteed to cause the ADM1232A
to assert a reset if PB RESET is brought low for more than 20 ms
and is guaranteed to ignore low inputs of less than 1 ms.
VCC
VCC
Table I.
Condition
Min
Typ
Max
Units
TD = 0 V
TD = Floating
TD = VCC
62.5
250
500
150
600
1200
250
1000
2000
ms
ms
ms
TD
ADM1232A
STROBE
PULSEWIDTH
MICROPROCESSOR
ADM1232
PB RESET
STROBE
RESET
STROBE
STROBE
RESET
GND
TD or time delay set is used to set the Strobe Timeout Period.
The Strobe Timeout Period is defined as being the maximum
time between high-to-low transitions (Figure 4) that STROBE
will accept before a reset will be asserted. The Strobe timeout
settings are listed in Table I.
I/O
RESET
TOLERANCE
TOLERANCE
STROBE TIMEOUT PERIOD
Figure 4. STROBE Parameters
Figure 2. Typical Push Button Reset Application
VCC
+5V
PB RESET TIME
PB RESET
DELAY
PB RESET
+4.5V (5% TRIP POINT)
+5V
+4.25V (10% TRIP POINT)
RESET OUTPUT DELAY
WHEN IS VCCFALLING
VIH
RESET OUTPUT DELAY
WHEN IS VCC RISING
RESET
VIL
RESET ACTIVE
TIME
RESET
RESET
Figure 5. Reset Output Delay
RESET
TOLERANCE
Figure 3. PB RESET
The TOLERANCE input is used to determine the level VCC can
vary below 5 V without the ADM1232A asserting a reset. Connecting TOLERANCE to ground will select a –5% tolerance
level and will cause the ADM1232A to generate a reset if VCC
falls below 4.75 V (typical). If TOLERANCE is connected to
VCC a –10% tolerance level is selected and will cause the
ADM1232A to generate a reset if VCC falls below 4.5 V (typical).
Check the parameters for the VCC trip point in the ADM1232A
Specifications for more information.
RESET AND RESET OUTPUTS
While RESET is capable of sourcing and sinking current,
RESET is an open drain MOSFET which sinks current only.
Therefore, it is necessary to pull this output high.
REV. 0
–5–
ADM1232A
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Wide SOIC
(R-16)
0.430 (10.92)
0.348 (8.84)
0.4133 (10.50)
0.3977 (10.00)
8
5
0.280 (7.11)
0.240 (6.10)
1
8
0.4193 (10.65)
0.3937 (10.00)
9
0.2992 (7.60)
0.2914 (7.40)
16
1
0.0118 (0.30)
0.0040 (0.10)
0.210 (5.33)
MAX
SEATING
PLANE
0.015 (0.381)
0.008 (0.204)
0.1968 (5.00)
0.1890 (4.80)
5
0.199 (5.05)
0.187 (4.75)
1
0.195 (4.95)
0.115 (2.93)
0.130
(3.30)
MIN
8-Lead Narrow SOIC
(R-8)
0.122 (3.10)
0.114 (2.90)
8
0.325 (8.25)
0.300 (7.62)
0.0500 (1.27)
0.0157 (0.40)
8-Lead ␮SOIC
(RM-8)
0.122 (3.10)
0.114 (2.90)
0.060 (1.52)
0.015 (0.38)
0.160 (4.06)
0.115 (2.93)
0.022 (0.558) 0.100 0.070 (1.77)
0.014 (0.356) (2.54) 0.045 (1.15)
BSC
0.0291 (0.74)
3 458
0.0098 (0.25)
88
0.0192 (0.49)
08
SEATING 0.0125 (0.32)
0.0138 (0.35) PLANE
0.0091 (0.23)
0.0500
(1.27)
BSC
4
PIN 1
0.1043 (2.65)
0.0926 (2.35)
PIN 1
C3421–8–7/99
8-Lead PDIP
(N-8)
0.2440 (6.20)
0.2284 (5.80)
4
8
5
1
4
PIN 1
PIN 1
0.0256 (0.65) BSC
0.120 (3.05)
0.112 (2.84)
0.018 (0.46)
SEATING 0.008 (0.20)
PLANE
0.043 (1.09)
0.037 (0.94)
0.011 (0.28)
0.003 (0.08)
338
278
0.102 (2.59)
0.094 (2.39)
0.0098 (0.25)
0.0040 (0.10)
0.0500 0.0192 (0.49)
SEATING (1.27) 0.0138 (0.35) 0.0098 (0.25)
PLANE BSC
0.0075 (0.19)
0.028 (0.71)
0.016 (0.41)
0.0196 (0.50)
3 458
0.0099 (0.25)
88
08
0.0500 (1.27)
0.0160 (0.41)
PRINTED IN U.S.A.
0.006 (0.15)
0.002 (0.05)
0.120 (3.05)
0.112 (2.84)
0.1574 (4.00)
0.1497 (3.80)
–6–
REV. 0