54174/DM54174/DM74174, 54175/DM54175/DM74175 Hex/Quad D Flip-Flops with Clear General Description Features These positive-edge triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the quad (175) version features complementary outputs from each flip-flop. Information at the D inputs meeting the setup and hold time requirements is transferred to the Q outputs on the positivegoing edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. Y Y Y Y Y Y Y Y 174 contains six flip-flops with single-rail outputs 175 contains four flip-flops with double-rail outputs Buffered clock and direct clear inputs Individual data input to each flip-flop Applications include: Buffer/storage registers Shift registers Pattern generators Typical clock frequency 40 MHz Typical power dissipation per flip-flop 38 mW Alternate Military/Aerospace device (54174, 54175) is available. Contact a National Semiconductor Sales Office/Distributor for specifications. Connection Diagrams Dual-In-Line Package Dual-In-Line Package TL/F/6557 – 2 TL/F/6557 – 1 Order Number 54175DMQB, 54175FMQB, DM54175J, DM54175W or DM74175N See NS Package Number J16A, N16E or W16A Order Number 54174DMQB, 54174FMQB, DM54174J, DM54174W or DM74174N See NS Package Number J16A, N16E or W16A Function Table (Each Flip-Flop) Inputs Outputs Clear Clock D Q Q² L H H H X X H L X L H L Q0 H L H Q0 u u L H e High Level (steady state) L e Low Level (steady state) X e Don’t Care u e Transition from low to high level Q0 e The level of Q before the indicated steady-state input conditions were established. ² e 175 only C1995 National Semiconductor Corporation TL/F/6557 RRD-B30M105/Printed in U. S. A. 54174/DM54174/DM74174, 54175/DM54175/DM74175 Hex/Quad D Flip-Flops with Clear June 1989 Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 5.5V Operating Free Air Temperature Range b 55§ C to a 125§ C DM54 and 54 DM74 0§ C to a 70§ C Storage Temperature Range b 65§ C to a 150§ C Recommended Operating Conditions Symbol DM54174 Parameter DM74174 Nom Max Min Nom Max 4.5 5 5.5 4.75 5 5.25 VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage IOH High Level Output Current IOL Low Level Output Current fCLK Clock Frequency (Note 4) 0 tW Pulse Width (Note 4) 25 2 V 2 V 0.8 0.8 V b 0.8 b 0.8 mA 16 Clock Low Units Min 30 0 16 mA 30 MHz 25 Clock High 10 10 Clear 20 20 tSU Data Setup Time (Note 4) 20 20 ns tH Data Hold Time (Note 4) 0 0 ns tREL Clear Release Time (Note 4) 30 30 TA Free Air Operating Temperature b 55 125 ns ns 0 70 §C ’174 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions Min Typ (Note 1) Max Units b 1.5 V VI Input Clamp Voltage VCC e Min, II e b12 mA VOH High Level Output Voltage VCC e Min, IOH e Max VIL e Max, VIH e Min VOL Low Level Output Voltage VCC e Min, IOL e Max VIH e Min, VIL e Max II Input Current @ Max Input Voltage VCC e Max, VI e 5.5V IIH High Level Input Current VCC e Max, VI e 2.4V 40 mA IIL Low Level Input Current VCC e Max, VI e 0.4V b 1.6 mA IOS Short Circuit Output Current VCC e Max (Note 2) Supply Current VCC e Max (Note 3) ICC 2.4 V 0.4 V 1 mA DM54 b 20 b 57 DM74 b 18 b 57 45 65 Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time. Note 3: With all outputs open and all DATA and CLEAR inputs at 4.5V, ICC is measured after a momentary ground, then 4.5V applied to the CLOCK input. Note 4: TA e 25§ C and VCC e 5V. 2 mA mA ’174 Switching Characteristics at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load) Symbol Parameter RL e 400X, CL e 15 pF From (Input) To (Output) Min Units Max fMAX Maximum Clock Frequency tPLH Propagation Delay Time Low to High Level Output Clock to Any Q 25 ns tPHL Propagation Delay Time High to Low Level Output Clock to Any Q 25 ns tPHL Propagation Delay Time High to Low Level Output Clear to Any Q 40 ns 30 MHz Recommended Operating Conditions Symbol DM54175 Parameter VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage DM74175 Nom Max Min Nom Max 4.5 5 5.5 4.75 5 5.25 2 2 V V 0.8 0.8 V b 0.8 mA 16 mA 30 MHz IOH High Level Output Current b 0.8 IOL Low Level Output Current 16 fCLK Clock Frequency (Note 1) 0 tW Pulse Width (Note 1) 25 Clock Low Units Min 30 0 25 Clock High 10 10 Clear 20 20 tSU Data Setup Time (Note 1) 20 20 ns tH Data Hold Time (Note 1) 0 0 ns tREL Clear Release Time (Note 1) TA Free Air Operating Temperature 30 ns 30 b 55 125 Note 1: TA e 25§ C and VCC e 5V. 3 0 ns 70 §C ’175 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC e Min, II e b12 mA VOH High Level Output Voltage VCC e Min, IOH e Max VIL e Max, VIH e Min VOL Low Level Output Voltage VCC e Min, IOL e Max VIH e Min, VIL e Max II Input Current @ Max Input Voltage VCC e Max, VI e 5.5V IIH High Level Input Current IIL IOS ICC Min Typ (Note 1) Max Units b 1.5 V 2.4 V 0.4 V 1 mA VCC e Max, VI e 2.4V 40 mA Low Level Input Current VCC e Max, VI e 0.4V b 1.6 mA Short Circuit Output Current VCC e Max (Note 2) Supply Current VCC e Max (Note 3) DM54 b 20 b 57 DM74 b 18 b 57 30 45 mA mA ’175 Switching Characteristics at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load) Symbol Parameter From (Input) To (Output) RL e 400X, CL e 15 pF Min Units Max fMAX Maximum Clock Frequency tPLH Propagation Delay Time Low to High Level Output Clock to Any Q or Q 25 ns tPHL Propagation Delay Time High to Low Level Output Clock to Any Q or Q 25 ns tPLH Propagation Delay Time Low to High Level Output Clear to Any Q 25 ns tPHL Propagation Delay Time High to Low Level Output Clear to Any Q 40 ns 30 MHz Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time. Note 3: With all outputs open and 4.5V applied to all DATA and CLEAR inputs, ICC is measured after a momentary ground then 4.5V applied to the CLOCK. 4 Logic Diagrams 174 175 TL/F/6557 – 4 TL/F/6557 – 3 5 6 Physical Dimensions inches (millimeters) 16-Lead Ceramic Dual-In-Line Package (J) Order Number 54174DMQB, 54175DMQB, DM54174J or DM54175J NS Package Number J16A 16-Lead Molded Dual-In-Line Package (N) Order Number DM74174N or DM74175N NS Package Number N16E 7 54174/DM54174/DM74174, 54175/DM54175/DM74175 Hex/Quad D Flip-Flops with Clear Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flat Package (W) Order Number 54174FMQB, 54175FMQB, DM54174W or DM54175W NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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