TI LMP8603 60v common mode, fixed gain, bidirectional precision current sensing amplifier Datasheet

LMP8602, LMP8602Q, LMP8603, LMP8603Q
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SNOSB36D – JULY 2009 – REVISED MARCH 2013
60V Common Mode, Fixed Gain, Bidirectional Precision Current Sensing Amplifier
Check for Samples: LMP8602, LMP8602Q, LMP8603, LMP8603Q
FEATURES
DESCRIPTION
•
The LMP8602 and LMP8603 are fixed gain precision
amplifiers. The parts will amplify and filter small
differential signals in the presence of high common
mode voltages. The input common mode voltage
range is –22V to +60V when operating from a single
5V supply. With a 3.3V supply, the input common
mode voltage range is from –4V to +27V. The
LMP8602 and LMP8603 are members of the Linear
Monolithic Precision (LMP®) family and are ideal
parts for unidirectional and bidirectional current
sensing applications. All parameter values of the
parts that are shown in the tables are 100% tested
and all bold values are also 100% tested over
temperature.
1
2
•
•
•
•
•
•
•
•
•
Unless Otherwise Noted, Typical Values at TA
= 25°C, VS = 5.0V, Gain = 50x (LMP8602), Gain
= 100x (LMP8603)
TCVos 10μV/°C max
CMRR 90 dB Min
Input Offset Voltage 1 mV Max
CMVR at VS = 3.3V −4V to 27V
CMVR at VS = 5.0V −22V to 60V
Operating Ambient Temperature Range −40°C
to 125°C
Single Supply Bidirectional Operation
All Min / Max Limits 100% Tested
LMP8602Q and LMP8603Q Available in
Automotive AEC-Q100 Grade 1 Qualified
Version
The parts have a precise gain of 50x for the
LMP8602 and 100x for the LMP8603, which are
adequate in most targeted applications to drive an
ADC to its full scale value. The fixed gain is achieved
in two separate stages, a preamplifier with a gain of
10x and an output stage buffer amplifier with a gain
of 5x for the LMP8602 and 10x for the LMP8603. The
connection between the two stages of the signal path
is brought out on two pins to enable the possibility to
create an additional filter network around the output
buffer amplifier. These pins can also be used for
alternative configurations with different gain as
described in the applications section.
APPLICATIONS
•
•
•
•
•
•
•
High Side and Low Side Driver Configuration
Current Sensing
Bidirectional Current Measurement
Current Loop to Voltage Conversion
Automotive Fuel Injection Control
Transmission Control
Power Steering
Battery Management Systems
Typical Applications
D
48V
-
-
+
IC
IL
load
G
+5V
IB
+
+
48V
Inductive
Load
+5V
S
+3.3V
+
D
-
+
Charger
-
G
+
Inductive
Load
-
S
24V
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2013, Texas Instruments Incorporated
LMP8602, LMP8602Q, LMP8603, LMP8603Q
SNOSB36D – JULY 2009 – REVISED MARCH 2013
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DESCRIPTION (CONTINUED)
The mid-rail offset adjustment pin enables the user to use these devices for bidirectional single supply voltage
current sensing. The output signal is bidirectional and mid-rail referenced when this pin is connected to the
positive supply rail. With the offset pin connected to ground, the output signal is unidirectional and groundreferenced.
The LMP8602 and LMP8603 are available in a 8–Pin SOIC package and in a 8–Pin VSSOP package.
The LMP8602Q and LMP8603Q incorporate enhanced manufacturing and support processes for the automotive
market, including defect detection methodologies. Reliability qualification is compliant with the requirements and
temperature grades defined in the AEC Q100 standard.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
Human Body
ESD Tolerance (3)
For input pins only
±4000V
For all other pins
±2000V
Machine Model
200V
Charge Device Model
1000V
Supply Voltage (VS - GND)
6.0V
Continuous Input Voltage (−IN and +IN) (4)
−22V to 60V
−25V to 65V
Transient (400 ms)
Maximum Voltage at A1, A2, OFFSET and OUT Pins
VS +0.3V and
GND -0.3V
−65°C to 150°C
Storage Temperature Range
Junction Temperature (5)
Mounting Temperature
(1)
(2)
(3)
(4)
(5)
2
150°C
Infrared or Convection (20 sec)
235°C
Wave Soldering Lead (10 sec)
260°C
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
the device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be beyond such conditions. All voltages are
measured with respect to the ground pin, unless otherwise specified.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Human Body Model per MIL-STD-883, Method 3015.7. Machine Model, per JESD22-A115-A. Field-Induced Charge-Device Model, per
JESD22-C101-C.
For the VSSOP package, the bare board spacing at the solder pads of the package will be to small for reliable use at higher voltages
(VCM >25V) Therefore it is strongly advised to add a conformal coating on the PCB assembled with the LMP8602 and LMP8603.
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJ(MAX), θJA, and the ambient temperature,
TA. The maximum allowable power dissipation PDMAX = (TJ(MAX) - TA) / θJA or the number given in Absolute Maximum Ratings,
whichever is lower.
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Operating Ratings (1)
Supply Voltage (VS – GND)
3.0V to 5.5V
Offset Voltage (Pin 7 )
0 to VS
Temperature Range (2)
Packaged devices
Package Thermal Resistance (2)
8-Pin SOIC (θJA)
190°C/W
8-Pin VSSOP (θJA)
203°C/W
(1)
(2)
−40°C to +125°C
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
the device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be beyond such conditions. All voltages are
measured with respect to the ground pin, unless otherwise specified.
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJ(MAX), θJA, and the ambient temperature,
TA. The maximum allowable power dissipation PDMAX = (TJ(MAX) - TA) / θJA or the number given in Absolute Maximum Ratings,
whichever is lower.
3.3V Electrical Characteristics (1)
Unless otherwise specified, all limits ensured at TA = 25°C, VS = 3.3V, GND = 0V, −4V ≤ VCM ≤ 27V, and RL = ∞, Offset (Pin
7) is grounded, 10nF between VS and GND. Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min
(2)
Typ
(3)
Max
(2)
Units
mA
Overall Performance (From -IN (pin 1) and +IN (pin 8) to OUT (pin 5) with pins A1 (pin 3) and A2 (pin 4) connected)
IS
Supply Current
AV
Total Gain
1
1.3
LMP8602
49.75
50
50.25
LMP8603
99.5
100
100.5
−2.7
±20
Gain Drift (4)
−40°C ≤ TA ≤ 125°C
SR
Slew Rate (5)
VIN = ±0.165V
BW
Bandwidth
VOS
Input Offset Voltage
VCM = VS / 2
TCVOS
Input Offset Voltage Drift (6)
−40°C ≤ TA ≤ 125°C
en
Input Referred Voltage Noise
PSRR
Power Supply Rejection Ratio
0.7
V/μs
50
60
kHz
Spectral Density, 1 kHz
70
LMP8602
Mid−scale Offset Scaling Accuracy
ppm/°C
0.4
0.1 Hz − 10 Hz, 6 Sigma
DC, 3.0V ≤ VS ≤ 3.6V, VCM = VS/2
V/V
0.15
±1
mV
2
±10
μV/°C
16.4
μVP-P
830
nV/√Hz
86
±0.25
Input Referred
LMP8603
±0.45
Input Referred
dB
±1
%
±0.33
mV
±1.5
%
±0.248
mV
kΩ
Preamplifier (From input pins -IN (pin 1) and +IN (pin 8) to A1 (pin 3))
RCM
Input Impedance Common Mode
−4V ≤ VCM ≤ 27V
250
295
350
RDM
Input Impedance Differential Mode
−4V ≤ VCM ≤ 27V
500
590
700
kΩ
VOS
Input Offset Voltage
VCM = VS / 2
±0.15
±1
mV
DC CMRR DC Common Mode Rejection Ratio
AC CMRR
CMVR
(1)
(2)
(3)
(4)
(5)
(6)
(7)
AC Common Mode Rejection Ratio (7)
−2V ≤ VCM ≤ 24V
86
96
f = 1 kHz
80
94
f = 10 kHz
Input Common Mode Voltage Range
for 80 dB CMRR
dB
dB
85
−4
27
V
The electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise
modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not
ensured.
Datasheet min/max specification limits are ensured by test.
Typical values represent the most likely parameter norms at TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured.
Both the gain of the preamplifier A1V and the gain of the buffer amplifier A2V are measured individually. The over all gain of both
amplifiers AV is also measured to assure the gain of all parts is always within the AV limits.
Slew rate is the average of the rising and falling slew rates.
Offset voltage drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
AC Common Mode Signal is a 5VPP sine-wave (0V to 5V) at the given frequency.
Copyright © 2009–2013, Texas Instruments Incorporated
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3.3V Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits ensured at TA = 25°C, VS = 3.3V, GND = 0V, −4V ≤ VCM ≤ 27V, and RL = ∞, Offset (Pin
7) is grounded, 10nF between VS and GND. Boldface limits apply at the temperature extremes.
Symbol
Parameter
K1
Gain (4)
RF-INT
Output Impedance Filter Resistor
TCRF-INT
Output Impedance Filter Resistor Drift
A1 VOUT
A1 Output Voltage Swing
Conditions
Min
Typ
Max
(2)
Units
9.95
10.0
10.05
V/V
99
100
101
kΩ
±5
±50
ppm/°C
2
10
mV
(2)
RL = ∞
VOL
(3)
VOH
3.2
3.25
V
0V ≤ VCM ≤ VS
−2
−2.5
±0.5
2
2.5
LMP8602
4.975
5
5.025
LMP8603
9.95
10
10.05
Output Buffer (From A2 (pin 4) to OUT ( pin 5 )
VOS
Input Offset Voltage
K2
Gain (4)
IB
Input Bias Current of A2 (8)
A2 VOUT
Output Short-Circuit Current (11)
ISC
(8)
(9)
(10)
(11)
A2 Output Voltage Swing (9) (10)
−40
V/V
fA
±20
VOL,
RL = 100 kΩ
mV
LMP8602
10
40
LMP8603
10
80
VOH,
RL = 100 kΩ
3.28
3.29
Sourcing, VIN = VS, VOUT = GND
-25
-38
-60
Sinking, VIN = GND, VOUT = VS
30
46
65
nA
mV
V
mA
Positive current corresponds to current flowing into the device.
For this test input is driven from A1 stage in uni-directional mode (Offset pin connected to GND).
For VOL, RL is connected to VS and for VOH, RL is connected to GND.
Short-Circuit test is a momentary test. Continuous short circuit operation at elevated ambient temperature can result in exceeding the
maximum allowed junction temperature of 150°C.
5V Electrical Characteristics (1)
Unless otherwise specified, all limits ensured for at TA = 25°C, VS = 5V, GND = 0V, −22V ≤ VCM ≤ 60V, and RL = ∞, Offset
(Pin 7) is grounded, 10nF between VS and GND. Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min
(2)
Typ
(3)
Max
(2)
Units
mA
Overall Performance (From -IN (pin 1) and +IN (pin 8) to OUT (pin 5) with pins A1 (pin 3) and A2 (pin 4) connected)
IS
Supply Current
Total Gain (4)
AV
1.1
1.5
LMP8602
49.75
50
50.25
LMP8603
99.5
100
100.5
−2.8
±20
Gain Drift
−40°C ≤ TA ≤ 125°C
SR
Slew Rate (5)
VIN = ±0.25V
BW
Bandwidth
VOS
Input Offset Voltage
TCVOS
Input Offset Voltage Drift (6)
eN
Input Referred Voltage Noise
(1)
(2)
(3)
(4)
(5)
(6)
4
V/V
ppm/°C
0.6
0.83
V/μs
50
60
kHz
−40°C ≤ TA ≤ 125°C
0.15
±1
mV
2
±10
μV/°C
0.1 Hz − 10 Hz, 6 Sigma
17.5
μVP-P
Spectral Density, 1 kHz
890
nV/√Hz
The electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise
modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not
ensured.
Datasheet min/max specification limits are ensured by test.
Typical values represent the most likely parameter norms at TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured.
Both the gain of the preamplifier A1V and the gain of the buffer amplifier A2V are measured individually. The over all gain of both
amplifiers AV is also measured to assure the gain of all parts is always within the AV limits.
Slew rate is the average of the rising and falling slew rates.
Offset voltage drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
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SNOSB36D – JULY 2009 – REVISED MARCH 2013
5V Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits ensured for at TA = 25°C, VS = 5V, GND = 0V, −22V ≤ VCM ≤ 60V, and RL = ∞, Offset
(Pin 7) is grounded, 10nF between VS and GND. Boldface limits apply at the temperature extremes.
Symbol
PSRR
Parameter
Power Supply Rejection Ratio
Conditions
DC 4.5V ≤ VS ≤ 5.5V
Min
(2)
70
LMP8602
Mid−scale Offset Scaling Accuracy
Typ
(3)
(2)
Units
90
±0.25
Input Referred
LMP8603
Max
±0.45
Input Referred
dB
±1
%
±0.50
mV
±1.5
%
±0.375
mV
Preamplifier (From input pins -IN (pin 1) and +IN (pin 8) to A1 (pin 3))
RCM
Input Impedance Common Mode
RDM
Input Impedance Differential Mode
VOS
Input Offset Voltage
250
295
350
kΩ
−20V ≤ VCM< 0V
165
193
250
kΩ
0V ≤ VCM ≤ 60V
500
590
700
kΩ
−20V ≤ VCM < 0V
300
386
500
kΩ
±0.15
±1
mV
VCM = VS / 2
DC CMRR DC Common Mode Rejection Ratio
AC CMRR AC Common Mode Rejection Ratio (7)
CMVR
Input Common Mode Voltage Range
K1
Gain (4)
RF-INT
Output Impedance Filter Resistor
TCRF-INT
Output Impedance Filter Resistor Drift
A1 VOUT
0V ≤ VCM ≤ 60V
−20V ≤ VCM ≤ 60V
90
105
f = 1 kHz
80
96
f = 10 kHz
A1 Ouput Voltage Swing
dB
83
−22
for 80 dB CMRR
VOL
dB
60
V
9.95
10
10.05
V/V
99
100
101
kΩ
±5
±50
ppm/°C
2
10
mV
RL = ∞
VOH
4.95
4.985
V
0V ≤ VCM ≤ VS
−2
−2.5
±0.5
2
2.5
LMP8602
4.975
5
5.025
LMP8603
9.95
10
10.05
Output Buffer (From A2 (pin 4) to OUT ( pin 5 )
VOS
Input Offset Voltage
K2
Gain (8)
IB
Input Bias Current of A2 (9)
A2 VOUT
ISC
A2 Ouput Voltage Swing
(10) (11)
Output Short-Circuit Current (12)
−40
V/V
fA
±20
VOL,
RL = 100 kΩ
mV
LMP8602
10
40
LMP8603
10
80
VOH,
RL = 100 kΩ
4.98
4.99
Sourcing, VIN = VS, VOUT = GND
–25
–42
–60
Sinking, VIN = GND, VOUT = VS
30
48
65
nA
mV
V
mA
(7)
(8)
AC Common Mode Signal is a 5VPP sine-wave (0V to 5V) at the given frequency.
Both the gain of the preamplifier A1V and the gain of the buffer amplifier A2V are measured individually. The over all gain of both
amplifiers AV is also measured to assure the gain of all parts is always within the AV limits.
(9) Positive current corresponds to current flowing into the device.
(10) For this test input is driven from A1 stage in uni-directional mode (Offset pin connected to GND).
(11) For VOL, RL is connected to VS and for VOH, RL is connected to GND.
(12) Short-Circuit test is a momentary test. Continuous short circuit operation at elevated ambient temperature can result in exceeding the
maximum allowed junction temperature of 150°C.
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BLOCK DIAGRAM
OFFSET
VS
7
6
Level shift
+IN
8
+
Preamplifier
Gain = 10
-IN
Output Buffer
Gain = K2
5
OUT
-
1
100 k:
2
GND
3
4
A1 A2
Figure 1. K2 = 5 for LMP8602, K2 = 10 for LMP8603
Connection Diagram
-IN
1
8
+IN
GND
2
7
OFFSET
A1
3
6
VS
A2
4
5
OUT
Figure 2. 8-Pin SOIC / VSSOP
Top View
PIN DESCRIPTIONS
Pin
Name
Description
2
GND
Power Ground
6
VS
Positive Supply Voltage
1
−IN
Negative Input
8
+IN
Positive Input
3
A1
Preamplifier output
4
A2
Input from the external filter network and / or A1
Offset
7
OFFSET
Output
5
OUT
Power Supply
Inputs
Filter Network
6
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DC Offset for bidirectional signals
Single ended output
Copyright © 2009–2013, Texas Instruments Incorporated
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SNOSB36D – JULY 2009 – REVISED MARCH 2013
Typical Performance Characteristics
Unless otherwise specified, all limits ensured for at TA = 25°C, VS = 5V, GND = 0V, −22V ≤ VCM ≤ 60V, and RL = ∞, Offset
(Pin 7) connected to VS, 10nF between VS and GND.
125°C
85°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
VOS vs. VCM at VS = 5V
VOFFSET (mV)
VOFFSET (mV)
VOS vs. VCM at VS = 3.3V
25°C
-40°C
125°C
85°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
25°C
-40°C
VS = 3.3V
-4
0
4
8
12
16
20
24
VS = 5V
28 30
-20 -10
0
10
VCM (V)
20
30
40
50
60
VCM (V)
Figure 3.
Figure 4.
Input Bias Current Over Temperature (+IN and −IN pins)
at VS = 3.3V
Input Bias Current Over Temperature (+IN and −IN pins)
at VS = 5V
100
200
50
150
25°C
IBIAS (éA)
IBIAS (éA)
75
25
125°C
0
-25
25°C
100
50
125°C
0
-50
-40°C
-50
-10
0
-40°C
-100
10
20
30
-30
-10
10
30
50
70
VCM (V)
VCM (V)
Figure 5.
Figure 6.
Input Bias Current Over Temperature (A2 pin)
at VS = 5V
Input Bias Current Over Temperature (A2 pin)
at VS = 5V
200
100
-40°C
150
100
IBIAS (fA)
IBIAS (pA)
0
50
-100
25°C
125°C
-200
0
-50
0
1
2
3
4
5
-300
0
1
2
3
VCM (V)
VCM (V)
Figure 7.
Figure 8.
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5
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Typical Performance Characteristics (continued)
Unless otherwise specified, all limits ensured for at TA = 25°C, VS = 5V, GND = 0V, −22V ≤ VCM ≤ 60V, and RL = ∞, Offset
(Pin 7) connected to VS, 10nF between VS and GND.
Input Referred Voltage Noise vs. Frequency
PSRR vs. Frequency
1.5
100
80
VS = 5V
PSRR (dB)
VOLTAGE NOISE (PV/ Hz)
VS = 5V
1.2
0.9
0.6
VS = 3.3V
0.3
VS = 3.3V
60
40
20
0
0.1
1
10
100
1k
10k
0
10
100k
100
1k
Figure 10.
Gain vs. Frequency LMP8602
Gain vs. Frequency LMP8603
VS = 3.3V, 5V
VOUT = VS/2
VOUT = VS/2
1k
10k
100k
1M
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 11.
Figure 12.
1M
CMRR vs. Frequency at VS = 3.3V
CMRR vs. Frequency at VS = 5V
25°C
25°C
-40°C
120
-40°C
120
100
100
85°C
CMRR (dB)
CMRR (dB)
50
40
30
20
10
0
-10
-20
-30
VS = 3.3V, 5V
100
125°C
60
40
20
80 125°C
85°C
60
40
20
0
0
VS = 5V
VS = 3.3V
100
1k
10k
FREQUENCY (Hz)
Figure 13.
8
100k
FREQUENCY (Hz)
40
30
20
10
0
-10
-20
-30
-40
80
10k
Figure 9.
GAIN (dB)
GAIN (dB)
FREQUENCY (Hz)
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100k
100
1k
10k
100k
FREQUENCY (Hz)
Figure 14.
Copyright © 2009–2013, Texas Instruments Incorporated
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LMP8602, LMP8602Q, LMP8603, LMP8603Q
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Typical Performance Characteristics (continued)
Unless otherwise specified, all limits ensured for at TA = 25°C, VS = 5V, GND = 0V, −22V ≤ VCM ≤ 60V, and RL = ∞, Offset
(Pin 7) connected to VS, 10nF between VS and GND.
Step Response at VS = 5V
RL = 10kΩ LMP8602
OUTPUT SIGNAL
(1V/DIV)
OUTPUT SIGNAL
(1V/DIV)
INPUT SIGNAL
(50 mV/DIV)
INPUT SIGNAL
(50 mV/DIV)
Step Response at VS = 3.3V
RL = 10kΩ LMP8602
TIME (20 Ps/DIV)
TIME (20 Ps/DIV)
Figure 16.
Settling Time (Falling Edge) at VS = 3.3V
LMP8602
Settling Time (Falling Edge) at VS = 5V
LMP8602
OTPUT SIGNAL
(1V/DIV)
OUTPUT SIGNAL
(1V/DIV)
INPUT SIGNAL
(50 mV/DIV)
INPUT SIGNAL
(50 mV/DIV)
Figure 15.
TIME (5 Ps/DIV)
TIME (5 us/DIV)
Figure 18.
Settling Time (Rising Edge) at VS = 3.3V
LMP8602
Settling Time (Rising Edge) at VS = 5V
LMP8602
OTPUT SIGNAL
(1V/DIV)
OUTPUT SIGNAL
(1V/DIV)
INPUT SIGNAL
(50 mV/DIV)
INPUT SIGNAL
(50 mV/DIV)
Figure 17.
TIME (5 Ps/DIV)
Figure 19.
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TIME (5 us/DIV)
Figure 20.
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Typical Performance Characteristics (continued)
Unless otherwise specified, all limits ensured for at TA = 25°C, VS = 5V, GND = 0V, −22V ≤ VCM ≤ 60V, and RL = ∞, Offset
(Pin 7) connected to VS, 10nF between VS and GND.
Step Response at VS = 3.3V
RL = 10kΩ LMP8603
Step Response at VS = 5V
RL = 10kΩ LMP8603
VIN (20 mV/DIV)
8
7
6
5
6
5
4
3
3
2
1
0
2
1
0
Figure 21.
Figure 22.
Settling Time (Falling Edge) at VS = 3.3V
LMP8603
Settling Time (Falling Edge) at VS = 5V
LMP8603
OUTPUT SIGNAL
(1V/DIV)
OUTPUT SIGNAL
(1V/DIV)
INPUT SIGNAL
(20 mV/DIV)
TIME (20 us/DIV)
INPUT SIGNAL
(20 mV/DIV)
TIME (20 us/DIV)
Figure 23.
Figure 24.
Settling Time (Rising Edge) at VS = 3.3V
LMP8603
Settling Time (Rising Edge) at VS = 5V
LMP8603
OUTPUT SIGNAL
(1V/DIV)
INPUT SIGNAL
(20 mV/DIV)
TIME (5 us/DIV)
INPUT SIGNAL
(20 mV/DIV)
TIME (5 us/DIV)
OUTPUT SIGNAL
(1V/DIV)
10
7
4
VOUT (1V/DIV)
VOUT (1V/DIV)
VIN (20 mV/DIV)
8
TIME (5 us/DIV)
TIME (5 us/DIV)
Figure 25.
Figure 26.
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Typical Performance Characteristics (continued)
Unless otherwise specified, all limits ensured for at TA = 25°C, VS = 5V, GND = 0V, −22V ≤ VCM ≤ 60V, and RL = ∞, Offset
(Pin 7) connected to VS, 10nF between VS and GND.
Positive Swing vs. RLOAD at VS = 3.3V
Positive Swing vs. RLOAD VS = 5V
3.30
5.00
4.98
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
3.28
3.26
3.24
4.96
4.94
4.92
3.22
4.90
3.20
1k
10k
4.88
1
100k
LOAD RESISTANCE (
10k
)
LOAD RESISTANCE (
Figure 27.
100k
)
Figure 28.
Negative Swing vs. RLOAD at VS = 3.3V
Negative Swing vs. RLOAD at VS = 5V
60
90
80
70
OUTPUT VOLTAGE (mV)
OUTPUT VOLTAGE (mV)
50
40
30
20
60
50
40
30
20
10
10
0
1k
10k
LOAD RESISTANCE (
15
10k
)
LOAD RESISTANCE (
100k
)
Figure 29.
Figure 30.
Gain Drift Distribution LMP8602
5000 parts
Gain Drift Distribution LMP8603
5000 parts
VS = 3V3
20
VS = 5V
PERCENTAGE (%)
9
6
3
0
-10 -8
VS = 3.3V
VS = 5V
12
PERCENTAGE (%)
0
1k
100k
15
10
5
0
-6
-4
-2
0
2
4
6
GAIN DRIFT (ppm/°C)
Figure 31.
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8
10
-10 -8
-6
-4 -2 0 2 4
GAIN DRIFT (ppm/°C)
6
8
10
Figure 32.
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Typical Performance Characteristics (continued)
Unless otherwise specified, all limits ensured for at TA = 25°C, VS = 5V, GND = 0V, −22V ≤ VCM ≤ 60V, and RL = ∞, Offset
(Pin 7) connected to VS, 10nF between VS and GND.
Gain error Distribution at VS = 3.3V LMP8602
5000 parts
20
Gain error Distribution at VS = 3.3V LMP8603
5000 parts
20
25°C
VS = 3.3V
PERCENTAGE (%)
PERCENTAGE (%)
VS = 5V
15
125°C
10
-40°C
5
0
15
10
5
0
-0.50
-0.25
0.00
0.25
0.50
-10 -8
-6
GAIN ERROR (%)
10
Gain error Distribution at VS = 5V LMP8602
5000 parts
Gain error Distribution at VS = 5V LMP8603
5000 parts
20
20
25°C
VS = 5V
-40°C
10
VS = 3.3V
125°C
PERCENTAGE (%)
PERCENTAGE (%)
8
Figure 34.
5
0
15
10
5
0
-0.50
-0.25
0.00
0.25
0.50
-10 -8
-6
GAIN ERROR (%)
6
8
10
Figure 36.
CMRR Distribution at VS = 3.3V
5000 parts
CMRR Distribution at VS = 5V
5000 parts
30
-40°C
25°C
PERCENTAGE (%)
25
20
-4 -2 0 2 4
GAIN DRIFT (ppm/°C)
Figure 35.
30
PERCENTAGE (%)
6
Figure 33.
15
125°C
15
10
5
0
25°C
125°C
25
-40°C
20
15
10
5
0
80
90
100
110
120
CMRR (dB)
Figure 37.
12
-4 -2 0 2 4
GAIN DRIFT (ppm/°C)
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130
140
80
90
100
110
120
CMRR (dB)
130
140
Figure 38.
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Typical Performance Characteristics (continued)
Unless otherwise specified, all limits ensured for at TA = 25°C, VS = 5V, GND = 0V, −22V ≤ VCM ≤ 60V, and RL = ∞, Offset
(Pin 7) connected to VS, 10nF between VS and GND.
VOS Distribution at VS = 3.3V
5000 parts
VOS Distribution at VS = 5V
5000 parts
35
30
30
PERCENTAGE (%)
PERCENTAGE (%)
25°C
35
25
20
-40°C
125°C
15
10
5
25
20
-40°C
125°C
15
10
5
0
-1.0
25°C
0
-0.6
-0.2 0 0.2
0.6
1.0
-1.0
-0.6
-0.2 0 0.2
VOS (mV)
VOS (mV)
Figure 39.
Figure 40.
0.6
1.0
TCVOS Distribution
5000 parts
VS = 5V
VS = 3.3V
PERCENTAGE (%)
30
25
20
15
10
5
0
-10 -8
-6
-4
-2
0
2
4
6
8
10
TCVOS (éV/°C)
Figure 41.
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APPLICATION INFORMATION
GENERAL
The LMP8602 and LMP8603 are fixed gain differential voltage precision amplifiers with a gain of 50x for the
LMP8602, and 100x for the LMP8603. The input common mode voltage range is -22V to +60V when operating
from a single 5V supply or -4V to +27V input common mode voltage range when operating from a single 3.3V
supply. The LMP8602 and LMP8603 are members of the LMP family and are ideal parts for unidirectional and
bidirectional current sensing applications. Because of the proprietary chopping level-shift input stage the
LMP8602 and LMP8603 achieve very low offset, very low thermal offset drift, and very high CMRR. The
LMP8602 and LMP8603 will amplify and filter small differential signals in the presence of high common mode
voltages.
The LMP8602/LMP8602Q/LMP8603/LMP8603Q use level shift resistors at the inputs. Because of these
resistors, the LMP8602/LMP8602Q/LMP8603/LMP8603Q can easily withstand very large differential input
voltages that may exist in fault conditions where some other less protected high-performance current sense
amplifiers might sustain permanent damage.
PERFORMANCE GUARANTIES
To guaranty the high performance of the LMP8602/LMP8602Q/LMP8603/LMP8603Q, all minimum and maximum
values shown in the parameter tables of this datasheet are 100% tested where all bold limits are also 100%
tested over temperature.
THEORY OF OPERATION
The schematic shown in Figure 42 gives a schematic representation of the internal operation of the
LMP8602/LMP8603.
The signal on the input pins is typically a small differential voltage across a current sensing shunt resistor. The
input signal may appear at a high common mode voltage. The input signals are accessed through two input
resistors. The proprietary chopping level-shift current circuit pulls or pushes current through the input resistors to
bring the common mode voltage behind these resistors within the supply rails. Subsequently, the signal is gained
up by a factor of 10 (K1) and brought out on the A1 pin through a trimmed 100 kΩ resistor. In the application,
additional gain adjustment or filtering components can be added between the A1 and A2 pins as will be
explained in subsequent sections. The signal on the A2 pin is further amplified by a factor (K2) which equals a
factor of 5 for the LMP8602 and a factor of 10 for the LMP8603. The output signal of the final gain stage is
provided on the OUT pin. The OFFSET pin allows the output signal to be level-shifted to enable bidirectional
current sensing as will be explained below.
OFFSET
VS
7
6
+IN
Level shift
8
+
Preamplifier
Gain = 10
-IN
Output Buffer
Gain = K2
5
OUT
-
1
100 k:
2
GND
3
4
A1 A2
K2 = 5 for LMP8602, K2 = 10 for LMP8603
Figure 42. Theory of Operation
14
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ADDITIONAL SECOND ORDER LOW PASS FILTER
The LMP8602/LMP8602Q/LMP8603/LMP8603Q has a third order Butterworth low-pass characteristic with a
typical bandwidth of 60 kHz integrated in the preamplifier stage of the part. The bandwidth of the output buffer
can be reduced by adding a capacitor on the A1 pin to create a first order low pass filter with a time constant
determined by the 100 kΩ internal resistor and the external filter capacitor.
It is also possible to create an additional second order Sallen-Key low pass filter as shown in Figure 43 by
adding external components R2, C1 and C2. Together with the internal 100 kΩ resistor R1, this circuit creates a
second order low-pass filter characteristic.
OFFSET
7
+IN
8
-IN 1
+
Level
shift
Output Buffer
Gain = K2
Preamplifier
Gain = K1
-
5
OUT
Internal
R1
100 k:
3
4
A1
A2
R2
C1
C2
K1 = 10, K2 = 5 for LMP8602, K2 = 10 for LMP8603
Figure 43. Second Order Low Pass Filter
When the corner frequency of the additional filter is much lower than 60 kHz, the transfer function of the
described amplifier can be written as:
K1 * K2
H(s) =
2
s +s*
1
R1R2C1C2
(1 - K2)
1
1
1
+
+
+
R 1C2 R 2C2
R2C1
R1R2C1C2
where
•
•
K1 equals the gain of the preamplifier
K2 that of the buffer amplifier
(1)
The above equation can be written in the normalized frequency response for a 2nd order low pass filter:
G(jZ) = K1 *
K2
2
jZ
(jZ)
+1
2 +
QZo
Zo
(2)
The Cutt-off frequency ωo in rad/sec (divide by 2π to get the cut-off frequency in Hz) is given by:
Zo =
1
R 1 R 2C 1 C 2
(3)
And the quality factor of the filter is given by:
Q=
R 1R2C1 C2
R1C1 + R2C1 + (1 - K2) * R1C2
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(4)
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For any filter gain K > 1x, the design procedure can be very simple if the two capacitors are chosen to in a
certain ratio.
C2 =
C1
K2
1
(5)
Inserting this in the above equation for Q results in:
R 1R 2
Q=
C1
K2
2
1
(K2
R 1C1 + R 2C 1
1)R1C1
K2
1
(6)
Which results in:
2
R 1R2
Q=
C1
K2 1
C1R2
R1R 2
=
K2
1
R2
(7)
In this case, given the predetermined value of R1 = 100 kΩ (the internal resistor), the quality factor is set solely
by the value of the resistor R2.
R2 can be calculated based on the desired value of Q as the first step of the design procedure with the following
equation:
R2 =
R1
(K - 1) Q2
(8)
For the gain of 5 for the LMP8602 this results in:
R2 =
R1
4Q2
(9)
For the gain of 10 for the LMP8603 this is:
R1
R2 =
2
9Q
(10)
For instance, the value of Q can be set to 0.5√2 to create a Butterworth response, to 1/√3 to create a Bessel
response, or a 0.5 to create a critically damped response. Once the value of R2 has been found, the second and
last step of the design procedure is to calculate the required value of C to give the desired low-pass cut-off
frequency using:
C1 =
(K2
1)Q
R1Z0
(11)
Which for the gain = 5 will give:
C1 =
4Q
R1Z0
(12)
and for the gain = 10:
C1 =
16
9Q
R1Z0
(13)
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For C2 the value is calculated with:
C2 =
C1
K2
1
(14)
Or for a gain = 5:
C2 =
C1
4
(15)
and for a gain = 10:
C2 =
C1
9
(16)
Note that the frequency response achieved using this procedure will only be accurate if the cut-off frequency of
the second order filter is much smaller than the intrinsic 60 kHz low-pass filter. In other words, to have the
frequency response of the LMP8602/LMP8602Q/LMP8603/LMP8603Q circuit chosen such that the internal poles
do not affect the external second order filter.
For a desired Q = 0.707 and a cut off frequency = 3 kHz, this will result for the LMP8602 in rounded values for
R2 = 51 kΩ, C1 = 1.5 nF and C2 = 3.9 nF
And for the LMP8603 this will result in rounded values for R2 = 22 kΩ, C1 = 3.3 nF and C2 = 0.39 nF
GAIN ADJUSTMENT
The gain of the LMP8602 is 50 and the gain of the LMP8603 is 100, however, this gain can be adjusted as the
signal path in between the two internal amplifiers is available on the external pins.
Reduce Gain
Figure 44 shows the configuration that can be used to reduce the gain of the LMP8602 and the LMP8603 in
unidirectional sensing applications.
OFFSET
7
+IN 8
1
+
Level
shift
-IN
Preamplifier
Gain = 10
-
Output Buffer
Gain = K2
5
OUT
Internal
Resistor
100 k:
3
4
A2
A1
Rr
Figure 44. Reduce Gain for Unidirectional Application
Rr creates a resistive divider together with the internal 100 kΩ resistor such that, for the LMP8602, the reduced
gain Gr becomes:
Gr =
50 Rr
Rr + 100 k:
(17)
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For the LMP8603:
Gr =
100 Rr
Rr + 100 k:
(18)
Given a desired value of the reduced gain Gr, using this equation the required value for Rr can be calculated for
the LMP8602 with:
Rr = 100 k: X
Gr
50 - Gr
(19)
and for the LMP8603 with:
Rr = 100 k: x
Gr
100 - Gr
(20)
Figure 45 shows the configuration that can be used to reduce the gain of the LMP8602 and the LMP8603 in
bidirectional sensing applications. The required value for Rr can be calculated with the equations above. The
maximum mid-scale offset scaling accuracy of the LMP8602 is ±1% and the maximum mid-scale offset scaling
accuracy of the LMP8603 is ±1.5%. The pair of resistors selected have to match much better than 1% and 1.5%
to prevent a significant error contribution to the offset voltage.
OFFSET
7
+IN 8
1
-IN
+
Level
shift
Output Buffer
Gain = K2
Preamplifier
Gain = 10
-
5
OUT
Internal
Resistor
100 k:
3
A1
4
A2
VX = OFFSET
2Rr
2Rr
Figure 45. Reduce Gain for Bidirectional Application
Increase Gain
Figure 46 shows the configuration that can be used to increase the gain of the LMP8602/ LMP8602Q/ LMP8603/
LMP8603Q.
Ri creates positive feedback from the output pin to the input of the buffer amplifier. The positive feedback
increases the gain. The increased gain Gi for the LMP8602 becomes:
Gi =
50 Ri
Ri - 400 k:
(21)
and for the LMP8603:
Gi =
100 Ri
Ri - 900 k:
(22)
From this equation, for a desired value of the gain, the required value of Ri can be calculated for the LMP8602
with:
Ri = 400 k: X
18
Gi
Gi - 50
(23)
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and for the LMP8603 with:
Ri = 900 k: x
Gi
Gi - 100
(24)
It should be noted from the equation for the gain Gi that for large gains Ri approaches 100 kΩ x (K2 - 1). In this
case, the denominator in the equation becomes close to zero. In practice, for large gains the denominator will be
determined by tolerances in the values of the external resistor Ri and the internal 100 kΩ resistor, and the K2
gain error. In this case, the gain becomes very inaccurate. If the denominator becomes equal to zero, the system
will even become unstable. It is recommended to limit the application of this technique to gain increases of a
factor 2.5 or smaller.
OFFSET
7
+IN 8
1
+
Level
shift
-IN
Output Buffer
Gain = K2
Preamplifier
Gain = 10
-
5
OUT
Internal
Resistor
100 k:
3
A1
4
A2
Ri
Figure 46. Increase Gain
BIDIRECTIONAL CURRENT SENSING
The signal on the A1 and OUT pins is ground-referenced when the OFFSET pin is connected to ground. This
means that the output signal can only represent positive values of the current through the shunt resistor, so only
currents flowing in one direction can be measured. When the offset pin is tied to the positive supply rail, the
signal on the A1 and OUT pins is referenced to a mid-rail voltage which allows bidirectional current sensing.
When the offset pin is connected to a voltage source, the output signal will be level shifted to that voltage divided
by two. In principle, the output signal can be shifted to any voltage between 0 and VS/2 by applying twice that
voltage from a low impedance source to the OFFSET pin.
With the offset pin connected to the supply pin (VS) the operation of the amplifier will be fully bidirectional and
symmetrical around 0V differential at the input pins. The signal at the output will follow this voltage difference
multiplied by the gain and at an offset voltage at the output of half VS.
Example:
With 5V supply and a gain of 50x for the LMP8602, a differential input signal of +10 mV will result in 3.0V at the
output pin. similarly -10 mV at the input will result in 2.0V at the output pin.
With 5V supply and a gain of 100x for the LMP8603, a differential input signal of +10 mV will result in 3.5V at the
output pin. similarly -10 mV at the input will result in 1.5V at the output pin. (1)
POWER SUPPLY DECOUPLING
In order to decouple the LMP8602/LMP8602Q/LMP8603/LMP8603Q from AC noise on the power supply, it is
recommended to use a 0.1 µF bypass capacitor between the VS and GND pins. This capacitor should be placed
as close as possible to the supply pins. In some cases an additional 10 µF bypass capacitor may further reduce
the supply noise.
(1)
The OFFSET pin has to be driven from a very low-impedance source (<10Ω). This is because the OFFSET pin internally connects
directly to the resistive feedback networks of the two gain stages. When the OFFSET pin is driven from a relatively large impedance
(e.g. a resistive divider between the supply rails) accuracy will decrease.
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LAYOUT CONSIDERATIONS
The two input signals of the LMP8602/LMP8602Q/LMP8603/LMP8603Q are differential signals and should be
handled as a differential pair. For optimum performance these signals should be closely together and of equal
length. Keep all impedances in both traces equal and do not allow any other signal or ground in between the
traces of this signals.
The connection between the preamplifier and the output buffer amplifier is a high impedance signal due to the
100 kΩ series resistor at the output of the preamplifier. Keep the traces at this point as short as possible and
away from interfering signals.
The LMP8602/LMP8602Q/LMP8603/LMP8603Q is available in a 8–Pin SOIC package and in a 8–Pin VSSOP
package. For the VSSOP package, the bare board spacing at the solder pads of the package will be too small for
reliable use at higher voltages (VCM > 25V) In this situation it is strongly advised to add a conformal coating on
the PCB assembled with the LMP8602/LMP8602Q/LMP8603/LMP8603Q in VSSOP package.
DRIVING SWITCHED CAPACITIVE LOADS
Some ADCs load their signal source with a sample and hold capacitor. The capacitor may be discharged prior to
being connected to the signal source. If the LMP8602/LMP8602Q/LMP8603/ LMP8603Q is driving such ADCs
the sudden current that should be delivered when the sampling occurs may disturb the output signal. This effect
was simulated with the circuit shown in Figure 47 where the output is connected to a capacitor that is driven by a
rail to rail square wave.
VS
Output Buffer
0V
Figure 47. Driving Switched Capacitive Load
This circuit simulates the switched connection of a discharged capacitor to the LMP8602/LMP8602Q/LMP8603/
LMP8603Q output. The resulting VOUT disturbance signals are shown in Figure 48 and Figure 49.
VOUT (V)
VS = 3.3V
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
10 pF
20 pF
0
50
100
150
200
250
300
TIME (ns)
Figure 48. Capacitive Load Response at 3.3V
20
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LMP8602, LMP8602Q, LMP8603, LMP8603Q
www.ti.com
SNOSB36D – JULY 2009 – REVISED MARCH 2013
VS = 5V
0.4
0.2
VOUT (V)
0
-0.2
-0.4
-0.6
10 pF
-0.8
20 pF
-1.0
0
50
100
150
200
250
300
TIME (ns)
Figure 49. Capacitive Load Response at 5.0V
These figures can be used to estimate the disturbance that will be caused when driving a switched capacitive
load. To minimize the error signal introduced by the sampling that occurs on the ADC input, an additional RC
filter can be placed in between the LMP8602/LMP8602Q/LMP8603/LMP8603Q and the ADC as illustrated in
Figure 50.
Output Buffer
ADC
Figure 50. Reduce Error When Driving ADCs
The external capacitor absorbs the charge that flows when the ADC sampling capacitor is connected. The
external capacitor should be much larger than the sample and hold capacitor at the input of the ADC and the RC
time constant of the external filter should be such that the speed of the system is not affected.
LOW SIDE CURRENT SENSING APPLICATION WITH LARGE COMMON MODE TRANSIENTS
Figure 51 illustrates a low side current sensing application with a low side driver. The power transistor is pulse
width modulated to control the average current flowing through the inductive load which is connected to a
relatively high battery voltage. The current through the load is measured across a shunt resistor RSENSE in series
with the load. When the power transistor is on, current flows from the battery through the inductive load, the
shunt resistor and the power transistor to ground. In this case, the common mode voltage on the shunt is close
to ground. When the power transistor is off, current flows through the inductive load, through the shunt resistor
and through the freewheeling diode. In this case the common mode voltage on the shunt is at least one diode
voltage drop above the battery voltage. Therefore, in this application the common mode voltage on the shunt is
varying between a large positive voltage and a relatively low voltage. Because the large common mode voltage
range of the LMP8602/LMP8603 and because of the high AC common mode rejection ratio, the
LMP8602/LMP8603 is very well suited for this application.
For this application the following example can be used for the calculation of the output signal:
When using a sense resistor, RSENSE, of 0.01 Ω and a current of 1A, then the output voltage at the input pins of
the LMP8602 is: RSENSE * ILOAD = 0.01 Ω * 1A = 0.01V
With the gain of 50 for the LMP8602 this will give an output of 0.5V. Or in other words, VOUT = 0.5V/A.
For the LMP8603 the calculation is similar, but with a gain of 100, giving an output of 1 V/A.
Copyright © 2009–2013, Texas Instruments Incorporated
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21
LMP8602, LMP8602Q, LMP8603, LMP8603Q
SNOSB36D – JULY 2009 – REVISED MARCH 2013
www.ti.com
OFFSET
7
INDUCTIVE
LOAD
+IN 8
RSENSE
1
5
Output Buffer
Gain = K2
Preamplifier
Gain = 10
-
-IN
+
24V
+
Level
shift
OUT
-
Internal
Resistor
100 k:
3
4
A2
A1
POWER
SWITCH
C1
Figure 51. Low Side Current Sensing Application with Large Common Mode Transients
HIGH SIDE CURRENT SENSING APPLICATION WITH NEGATIVE COMMON MODE TRANSIENTS
Figure 52 illustrates the application of the LMP8602/LMP8603 in a high side sensing application. This application
is similar to the low side sensing discussed above, except in this application the common mode voltage on the
shunt drops below ground when the driver is switched off. Because the common mode voltage range of the
LMP8602/LMP8603 extends below the negative rail, the LMP8602/LMP8603 is also very well suited for this
application.
OFFSET
POWER
SWITCH
+IN
8
+
+
24V
7
-
RSENSE
1
-IN
INDUCTIVE
LOAD
Level
shift
Output Buffer
Gain = K2
Preamplifier
Gain = 10
-
5
OUT
Internal
Resistor
100 k:
3
4
A2
A1
C1
Figure 52. High Side Current Sensing Application with Negative Common Mode Transients
22
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LMP8602, LMP8602Q, LMP8603, LMP8603Q
www.ti.com
SNOSB36D – JULY 2009 – REVISED MARCH 2013
BATTERY CURRENT MONITOR APPLICATION
This application example shows how the LMP8602/LMP8603 can be used to monitor the current flowing in and
out a battery pack. The fact that the LMP8602/LMP8603 can measure small voltages at a high offset voltage
outside the parts own supply range makes this part a very good choice for such applications. If the load current
of the battery is higher then the charging current, the output voltage of the LMP8602/LMP8603 will be above the
“half offset voltage” for a net current flowing out of the battery. When the charging current is higher then the load
current the output will be below this “half offset voltage”.
ICharge
ILoad
LOAD
Charger
VS
OFFSET
ICharge - ILoad
7
+IN 8
RSENSE
1
-IN
+
Level
shift
Output Buffer
Gain = K2
Preamplifier
Gain = 10
-
5
OUT
Internal
Resistor
100 k:
+
3
4
-
A1
A2
C1
Figure 53. Battery Current Monitor Application
ADVANCED BATTERY CHARGER APPLICATION
The above circuit can be used to realize an advanced battery charger that has the capability to monitor the exact
net current that flows in and out the battery as show in Figure 54. The output signal of the
LMP8602/LMP8602Q/LMP8603/LMP8603Q is digitized with the A/D converter and used as an input for the
charge controller. The charge controller can be used to regulate the charger circuit to deliver exactly the current
that is required by the load, avoiding overcharging a fully loaded battery.
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23
LMP8602, LMP8602Q, LMP8603, LMP8603Q
SNOSB36D – JULY 2009 – REVISED MARCH 2013
www.ti.com
ILoad
LOAD
VS
ICharge - ILoad
OFFSET
7
+IN 8
ICharge
RSENSE
1
-IN
Output Buffer
Gain = K2
Preamplifier
Gain = 10
-
5
OUT
A/D
Internal
Resistor
100 k:
+
12V
+
Level
shift
-
3
4
A2
A1
C1
Charge
Controler
Charger
K2 = 5 for LMP8602
K2 = 10 for LMP8603
Figure 54. Advanced Battery Charger Application
24
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Product Folder Links: LMP8602 LMP8602Q LMP8603 LMP8603Q
LMP8602, LMP8602Q, LMP8603, LMP8603Q
www.ti.com
SNOSB36D – JULY 2009 – REVISED MARCH 2013
REVISION HISTORY
Changes from Revision C (March 2013) to Revision D
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 24
Copyright © 2009–2013, Texas Instruments Incorporated
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25
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LMP8602MA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMP86
02MA
LMP8602MAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMP86
02MA
LMP8602MM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AN3A
LMP8602MME/NOPB
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AN3A
LMP8602MMX/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AN3A
LMP8602QMA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMP86
02QMA
LMP8602QMAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMP86
02QMA
LMP8602QMM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AF7A
LMP8602QMME/NOPB
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AF7A
LMP8602QMMX/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AF7A
LMP8603MA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMP86
03MA
LMP8603MAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMP86
03MA
LMP8603MM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AP3A
LMP8603MME/NOPB
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AP3A
LMP8603MMX/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AP3A
LMP8603QMA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMP86
03QMA
LMP8603QMAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMP86
03QMA
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
11-Apr-2013
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LMP8603QMM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AH7A
LMP8603QMME/NOPB
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AH7A
LMP8603QMMX/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AH7A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LMP8602, LMP8602-Q1, LMP8603, LMP8603-Q1 :
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
• Catalog: LMP8602, LMP8603
• Automotive: LMP8602-Q1, LMP8603-Q1
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Nov-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LMP8602MAX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LMP8602MM/NOPB
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMP8602MME/NOPB
VSSOP
DGK
8
250
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMP8602MMX/NOPB
VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMP8602QMAX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LMP8602QMM/NOPB
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMP8602QMME/NOPB
VSSOP
DGK
8
250
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMP8602QMMX/NOPB
VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMP8603MAX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LMP8603MM/NOPB
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMP8603MME/NOPB
VSSOP
DGK
8
250
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMP8603MMX/NOPB
VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMP8603QMAX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LMP8603QMM/NOPB
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMP8603QMME/NOPB
VSSOP
DGK
8
250
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMP8603QMMX/NOPB
VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Nov-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMP8602MAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LMP8602MM/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LMP8602MME/NOPB
VSSOP
DGK
8
250
210.0
185.0
35.0
LMP8602MMX/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
LMP8602QMAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LMP8602QMM/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LMP8602QMME/NOPB
VSSOP
DGK
8
250
210.0
185.0
35.0
LMP8602QMMX/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
LMP8603MAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LMP8603MM/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LMP8603MME/NOPB
VSSOP
DGK
8
250
210.0
185.0
35.0
LMP8603MMX/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
LMP8603QMAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LMP8603QMM/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LMP8603QMME/NOPB
VSSOP
DGK
8
250
210.0
185.0
35.0
LMP8603QMMX/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
Pack Materials-Page 2
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