REJ09B0259-0700
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clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
16
H8/3048 Group, H8/3048 F-ZTAT
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8 Family/H8/300H Series
H8/3048
H8/3047
H8/3045
H8/3044
H8/3048F
Rev. 7.00
Revision Date: Sep 21, 2005
HD6473048,
HD6433048
HD6433047
HD6433045
HD6433044
HD64F3048
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Renesas
Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in
whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must
be exported under a license from the Japanese government and cannot be imported into a country
other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products
contained therein.
Rev. 7.00 Sep 21, 2005 page ii of xxiv
Preface
The H8/3048 Group is a series of high-performance microcontrollers that integrate system
supporting functions together with an H8/300H CPU core.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space.
The on-chip supporting functions include ROM, RAM, a 16-bit integrated timer unit (ITU), a
programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication
interface (SCI), an A/D converter, a D/A converter, I/O ports, a direct memory access controller
(DMAC), a refresh controller, and other facilities. Of the two SCI channels, one has been
expanded to support the ISO/IEC7816-3 smart card interface. Functions have also been added to
reduce power consumption in battery-powered applications: individual modules can be placed in
standby, and the frequency of the system clock supplied to the chip can be divided down under
software control.
The address space is divided into eight areas. The data bus width and access cycle length can be
selected independently in each area, simplifying the connection of different types of memory.
Seven operating modes (modes 1 to 7) are provided, offering a choice of data bus width and
address space size.
With these features, the H8/3048 Group can be used to implement compact, high-performance
systems easily.
In addition to its mask ROM versions, the H8/3048 Group has a ZTAT™*1 version with userprogrammable on-chip PROM and an F-ZTAT™*2 version with on-chip flash memory that can be
programmed on-board. These versions enable users to respond quickly and flexibly to changing
application specifications.
The on-chip emulator (E10T) is installed on the H8/3048F-ONE in the H8/3048 Group
microcomputer. Refer to the H8/3048F-ONE Hardware Manual for details.
This manual describes the H8/3048 Group hardware. For details of the instruction set, refer to the
H8/300H Series Programming Manual.
Notes: 1. ZTAT™ (Zero Turn-Around-Time) is a trademark of Renesas Technology, Corp.
2. F-ZTAT™ (Flexible ZTAT) is a trademark of Renesas Technology, Corp.
Rev. 7.00 Sep 21, 2005 page iii of xxiv
Rev. 7.00 Sep 21, 2005 page iv of xxiv
Comparison of H8/3048 Group Product Specifications
1
There are seven members of the H8/3048 Group; the H8/3048F-ZTAT (H8/3048F* , H8/3048FONE*2), H8/3048ZTAT, H8/3048 mask ROM version, H8/3047 mask ROM version, H8/3045
mask ROM version, and H8/3044 mask ROM version.
The specifications of each model is compared below.
Notes: 1. H8/3048F has dual power supply with flash memory installed.
2. H8/3048F-ONE has single power supply with flash memory and E10T installed.
Refer to the H8/3048F-ONE Hardware Manual (revision 1) for details.
Hardware
Manual
ROM Type
H8/3048 Group
ZTAT
H8/3048F-ONE
Mask ROM
F-ZTAT
Model Type
H8/3048
H8/3048 mask ROM version H8/3048F
H8/3047 mask ROM version
H8/3045 mask ROM version
H8/3044 mask ROM version
H8/3048F-ONE
Model Spec
PROM model
Mask ROM model
Dual power supply,
flash memory is
installed
Single power supply,
flash memory installed,
internal step-down,
high-speed operation
model
Refer to 1.4,
Differences between
H8/3048F and
H8/3048F-ONE.
Refer to 1.4.3,
Differences between
H8/3048F and
H8/3048F-ONE.
HD64F3048
HD64F3048B
Model Type No.
HD6473048
HD6433048
HD6433047
HD6433045
HD6433044
Pin Assignment
Refer to figure 1.2, Pin Arrangement of H8/3048ZTAT, H8/3048
Mask ROM Version, H8/3047 Mask ROM Version, H8/3045 Mask
ROM Version, H8/3044 Mask ROM Version, and H8/3048F
(FP-100B or TFP-100B, Top View), in section 1.
5-V operation models
have a VCL pin and an
external capacitor must
be connected.
Refer to figure 1.3,
H8/3048F-ONE Pin
Arrangement (FP-100B
or TFP-100B, Top
View), in section 1.
RAM Capacity
4 kbytes
H8/3048: 4 kbytes
H8/3047: 4 kbytes
H8/3045: 2 kbytes
H8/3044: 2 kbytes
4 kbytes
4 kbytes
Rev. 7.00 Sep 21, 2005 page v of xxiv
Hardware
Manual
ROM Type
ROM Capacity
Flash Memory
H8/3048 Group
ZTAT
Mask ROM
128 kbytes
H8/3048: 128 kbytes
H8/3047: 96 kbytes
H8/3045: 64 kbytes
H8/3044: 32 kbytes
—
—
H8/3048F-ONE
F-ZTAT
128 kbytes
128 kbytes
Refer to section 19,
ROM (H8/3048F).
Refer to section 18,
Flash Memory
(H8/3048F-ONE Single
Power Supply).
Clock Pulse
Generator
Refer to section 20, Clock Pulse Generator.
Refer to section 19,
Clock Pulse Generator.
Power-Down
State
Refer to section 21, Power-Down State.
Refer to section 20,
Power-Down State.
Clock oscillator settling time: Waiting time of up to 131072 states
Clock oscillator settling
time: Waiting time of up
to 262144 states
Refer to table 22.1, Electrical Characteristics of H8/3048 Group
Products, in section 22.
Refer to table 21.1,
Electrical
Characteristics of
H8/3048 Group
Products, in section 21.
1 to 18 MHz
5 V operation models:
2 to 25 MHz,
3 V operation models:
2 to 25 MHz.
Electrical
Characteristics
(Clock Rate)
1 to 16 MHz
List of Registers Refer to table B.1, Comparison of H8/3048 Group Internal I/O Register Specifications, in
appendix B.
Refer to appendix B.1, Addresses.
Notes on Usage
—
—
—
Refer to section 1.4,
Notes on H8/3048FONE (Single Power
Supply).
On-chip
Emulator (E10T)
—
—
—
On-chip emulator
(E10T)
Rev. 7.00 Sep 21, 2005 page vi of xxiv
Main Revisions for this Edition
Item
Page
Revision (See Manual for Details)
All
All references to Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and
other Hitachi brand names changed to Renesas Technology Corp.
Designation for categories changed from “series” to “group”
13.2.6 Serial Control 461
Register (SCR)
Table amended
Bit 6-Receive
Interrupt Enable
(RIE)
Bit 6: RIE
Description
0
Receive-data-full (RXI) and receive-error (ERI) interrupt requests
are disabled*
(Initial value)
1
Receive-data-full (RXI) and receive-error (ERI) interrupt requests
are enabled
19.5.3 Programming 606
Flowchart and
Sample Program
Flowchart for
Programming One
Byte
Figure 19.9
Programming
Flowchart
Figure amended
Enable watchdog timer*2
Select program mode
(P bit = 1 in FLMCR)
Wait (x) µs
Clear P bit
Disable watchdog timer
Select program-verify mode
(PV bit = 1 in FLMCR)
Wait (tVS1) µs *4
Verify (read memory)*3
OK
Notes: 1. Write the data to be programmed using a
byte transfer instruction.
2. Set the watchdog timer overflow interval
by setting CKS2 and CKS1 to 0 and
CKS0 to 1.
3. Read to verify data from the memory
using a byte transfer instruction.
Programming ends
4. tVS1: 4 µs
z:
5 to 10 µs
N: 6 (set N so that total programming
time does not exceed 1 ms)
5. Programming time x, which is determined
by the initial time × 2n–1 (n = 1 to 6),
increases in proportion to n. Thus, set the
initial time to 15.8 µs or less to make total
programming time 1 ms or less.
No good
Clear PV bit
Clear PV bit
n ≥ N?
Clear erase block register
(clear bit of programmed block to 0)
Clear VPP E bit
Yes
Clear erase block register
(clear bit of block to be
programmed to 0)
Verify ends
No
n+1→n
Double the programming
time (x × 2 → x)*5
End (1-byte data programmed)
Clear VPP E bit
Programming error
Rev. 7.00 Sep 21, 2005 page vii of xxiv
Item
Page
Revision (See Manual for Details)
19.5.6 Erasing
Flowchart and
Sample Program
610
Figure amended
5. tVS1:
z:
tVS2:
N:
Set top address in block
as verify address
Flowchart for
Erasing One Block
Wait initial value setting x = 6.25 ms
6. The erase time x is successively
incremented by the initial set
value × 2n–1 (n = 1, 2, 3, 4). An
initial value of 6.25 ms or less
should be set, and the time for
one erasure should be 50 ms or
less.
Enable watchdog timer*2
Figure 19.10
Erasing Flowchart
Select erase mode
(E bit = 1 in FLMCR)
Wait (x) ms
Clear E bit
4 µs
5 to 10 µs
2 µs
602
Erasing ends
Disable watchdog timer
Select erase-verify mode
(EV bit = 1)
Wait (tVS1) µs*5
Dummy write to verify address*3
(flash memory latches address)
Wait (tVS2) µs*5
Verify (read memory)*4
No
Address + 1 → address
No good
Clear EV bit
OK
Last address?
n ≥ N?
Yes
Clear EV bit
Clear erase block register
(clear bit of erased block to 0)
Yes
Clear erase block register
(clear bit of block to be
erased to 0)
Erase-verify ends
No
n+1→n
n ≥ 5?
No
Rev. 7.00 Sep 21, 2005 page viii of xxiv
Clear VPP E bit
Clear VPP E bit
End of block erase
Erase error
Double the erase time*6
(x × 2 → x)
Yes
Item
Page
Revision (See Manual for Details)
19.5.6 Erasing
Flowchart and
Sample Program
611
Figure amended
Prewrite Flowchart
Figure 19.11
Prewrite Flowchart
Notes: 1. Use a byte transfer instruction.
2. Set the watchdog timer overflow
interval by setting CKS2 = 0,
CKS1 = 0 and CKS0 = 1.
3. In prewrite-verify mode P, E, PV,
and EV are all cleared to 0 and
12 V is applied to VPP. Use a
byte transfer instruction.
4. tVS1: 4 µs
z:
5 to 10 µs
N: 6 (set N so that total
Programming ends
programming time does not
exceed 1 ms)
Write H'00 to flash memory
(flash memory latches
write address and write data)*1
Enable watchdog timer*2
Select program mode
(set P bit to 1 in FLMCR)
Wait (x) µs
Clear P bit
Disable watchdog timer
Wait (tVS1) µs*4
Prewrite verify*3
(read data = H'00?)
No good
n ≥ N?
No
OK
Yes
Clear erase block register
(clear bit of block to be erased to 0)
n+1→n
Double
the programming
time (x × 2 → x)
Clear VPPE bit
Programming error
Last address?
No
Yes
Clear erase block register
(clear bit of block to be erased to 0)
Clear VPP E bit
End of prewrite
Rev. 7.00 Sep 21, 2005 page ix of xxiv
Item
Page
Revision (See Manual for Details)
19.5.6 Erasing
Flowchart and
Sample Program
616
Figure amended
5. tVS1: 4 µs
z:
5 to 10 µs
Wait initial value setting x = 6.25 ms
Flowchart for
Erasing Multiple
Blocks
Enable watchdog timer*2
Select erase mode (E bit = 1 in FLMCR)
Wait (x) ms
Erasing ends
Clear E bit
Figure 19.12
Multiple-Block Erase
Flowchart
Disable watchdog timer
tVS2: 2 µs
N: 602
6. The erase time x is successively
incremented by the initial set value
× 2n–1 (n = 1, 2, 3, 4). An initial
value of 10 ms or less should be
set, and the time for one erasure
should be 50 ms or less.
Select erase-verify mode
(EV bit = 1 in FLMCR)
Wait (tVS1) µs *5
Set top address of block as
verify address
Erase-verify
next block
Dummy write to verify address*3
(flash memory latches address)
Wait (tVS2) µs *5
Verify
(read memory)
Erase-verify next block
No good
OK
Address + 1 → address
No
Last
address in block?
All erased blocks
verified?
Yes
No
Yes
Clear EBR bit of erase-verified block *4
No
All erased blocks
verified?
Yes
Clear EV bit
All blocks erased?
(EBR1 = EBR2 = 0?)
Yes
Clear VPP E bit
End of erase
No
n ≥ 4?
Yes
No
Double the erase time (x × 2 → x)*6
n ≥ N?
No
Yes
Clear erase block registers
(clear bits of blocks to be erased to 0)
Clear VPP E bit
Erase error
Rev. 7.00 Sep 21, 2005 page x of xxiv
n+1→n
Contents
Section 1
1.1
1.2
1.3
1.4
Overview........................................................................................................... 1
Overview........................................................................................................................... 1
Block Diagram .................................................................................................................. 7
Pin Description.................................................................................................................. 8
1.3.1 Pin Arrangement .................................................................................................. 8
1.3.2 Pin Assignments in Each Mode ........................................................................... 10
1.3.3 Pin Functions ....................................................................................................... 15
Differences between H8/3048F and H8/3048F-ONE ....................................................... 20
Section 2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
CPU ....................................................................................................................
Overview...........................................................................................................................
2.1.1 Features ................................................................................................................
2.1.2 Differences from H8/300 CPU ............................................................................
CPU Operating Modes ......................................................................................................
Address Space ...................................................................................................................
Register Configuration ......................................................................................................
2.4.1 Overview..............................................................................................................
2.4.2 General Registers .................................................................................................
2.4.3 Control Registers .................................................................................................
2.4.4 Initial CPU Register Values .................................................................................
Data Formats .....................................................................................................................
2.5.1 General Register Data Formats ............................................................................
2.5.2 Memory Data Formats .........................................................................................
Instruction Set ...................................................................................................................
2.6.1 Instruction Set Overview......................................................................................
2.6.2 Instructions and Addressing Modes .....................................................................
2.6.3 Tables of Instructions Classified by Function......................................................
2.6.4 Basic Instruction Formats ....................................................................................
2.6.5 Notes on Use of Bit Manipulation Instructions....................................................
Addressing Modes and Effective Address Calculation .....................................................
2.7.1 Addressing Modes ...............................................................................................
2.7.2 Effective Address Calculation..............................................................................
Processing States...............................................................................................................
2.8.1 Overview..............................................................................................................
2.8.2 Program Execution State......................................................................................
2.8.3 Exception-Handling State ....................................................................................
2.8.4 Exception-Handling Sequences ...........................................................................
25
25
25
26
27
28
29
29
30
31
32
33
33
35
36
36
37
38
47
48
50
50
52
56
56
57
57
59
Rev. 7.00 Sep 21, 2005 page xi of xxiv
2.9
2.8.5 Bus-Released State...............................................................................................
2.8.6 Reset State............................................................................................................
2.8.7 Power-Down State ...............................................................................................
Basic Operational Timing .................................................................................................
2.9.1 Overview..............................................................................................................
2.9.2 On-Chip Memory Access Timing........................................................................
2.9.3 On-Chip Supporting Module Access Timing.......................................................
2.9.4 Access to External Address Space .......................................................................
Section 3
3.1
3.2
3.3
3.4
3.5
3.6
MCU Operating Modes ................................................................................ 65
Overview...........................................................................................................................
3.1.1 Operating Mode Selection ...................................................................................
3.1.2 Register Configuration.........................................................................................
Mode Control Register (MDCR) ......................................................................................
System Control Register (SYSCR) ...................................................................................
Operating Mode Descriptions ...........................................................................................
3.4.1 Mode 1 .................................................................................................................
3.4.2 Mode 2 .................................................................................................................
3.4.3 Mode 3 .................................................................................................................
3.4.4 Mode 4 .................................................................................................................
3.4.5 Mode 5 .................................................................................................................
3.4.6 Mode 6 .................................................................................................................
3.4.7 Mode 7 .................................................................................................................
Pin Functions in Each Operating Mode ............................................................................
Memory Map in Each Operating Mode ............................................................................
Section 4
4.1
4.2
4.3
4.4
4.5
4.6
60
60
60
61
61
61
62
63
Exception Handling .......................................................................................
Overview...........................................................................................................................
4.1.1 Exception Handling Types and Priority...............................................................
4.1.2 Exception Handling Operation.............................................................................
4.1.3 Exception Vector Table .......................................................................................
Reset .................................................................................................................................
4.2.1 Overview..............................................................................................................
4.2.2 Reset Sequence ....................................................................................................
4.2.3 Interrupts after Reset............................................................................................
Interrupts ...........................................................................................................................
Trap Instruction.................................................................................................................
Stack Status after Exception Handling..............................................................................
Notes on Stack Usage .......................................................................................................
Rev. 7.00 Sep 21, 2005 page xii of xxiv
65
65
66
66
67
69
69
69
69
69
69
70
70
70
71
81
81
81
81
82
84
84
84
87
88
89
89
90
Section 5
5.1
5.2
5.3
5.4
5.5
Interrupt Controller ........................................................................................
Overview...........................................................................................................................
5.1.1 Features ................................................................................................................
5.1.2 Block Diagram .....................................................................................................
5.1.3 Pin Configuration.................................................................................................
5.1.4 Register Configuration.........................................................................................
Register Descriptions ........................................................................................................
5.2.1 System Control Register (SYSCR) ......................................................................
5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB).............................................
5.2.3 IRQ Status Register (ISR)....................................................................................
5.2.4 IRQ Enable Register (IER) ..................................................................................
5.2.5 IRQ Sense Control Register (ISCR) ....................................................................
Interrupt Sources ...............................................................................................................
5.3.1 External Interrupts................................................................................................
5.3.2 Internal Interrupts.................................................................................................
5.3.3 Interrupt Vector Table..........................................................................................
Interrupt Operation............................................................................................................
5.4.1 Interrupt Handling Process...................................................................................
5.4.2 Interrupt Sequence ...............................................................................................
5.4.3 Interrupt Response Time......................................................................................
Usage Notes ......................................................................................................................
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction ......................
5.5.2 Instructions that Inhibit Interrupts........................................................................
5.5.3 Interrupts during EEPMOV Instruction Execution ..............................................
5.5.4 Usage Notes on External Interrupts .....................................................................
5.5.5 Notes on Non-Maskable Interrupts (NMI)...........................................................
Section 6
6.1
6.2
Bus Controller .................................................................................................
Overview...........................................................................................................................
6.1.1 Features ................................................................................................................
6.1.2 Block Diagram .....................................................................................................
6.1.3 Input/Output Pins .................................................................................................
6.1.4 Register Configuration.........................................................................................
Register Descriptions ........................................................................................................
6.2.1 Bus Width Control Register (ABWCR)...............................................................
6.2.2 Access State Control Register (ASTCR) .............................................................
6.2.3 Wait Control Register (WCR)..............................................................................
6.2.4 Wait State Controller Enable Register (WCER) ..................................................
6.2.5 Bus Release Control Register (BRCR) ................................................................
6.2.6 Chip Select Control Register (CSCR)..................................................................
91
91
91
92
93
93
94
94
95
102
103
104
105
105
106
106
110
110
115
116
117
117
118
118
118
120
123
123
123
124
125
126
126
126
127
128
129
130
131
Rev. 7.00 Sep 21, 2005 page xiii of xxiv
6.3
6.4
Operation ..........................................................................................................................
6.3.1 Area Division.......................................................................................................
6.3.2 Chip Select Signals ..............................................................................................
6.3.3 Data Bus...............................................................................................................
6.3.4 Bus Control Signal Timing ..................................................................................
6.3.5 Wait Modes..........................................................................................................
6.3.6 Interconnections with Memory (Example) ..........................................................
6.3.7 Bus Arbiter Operation..........................................................................................
Usage Notes ......................................................................................................................
6.4.1 Connection to Dynamic RAM and Pseudo-Static RAM......................................
6.4.2 Register Write Timing .........................................................................................
6.4.3 BREQ Input Timing.............................................................................................
6.4.4 Transition To Software Standby Mode ................................................................
Section 7
7.1
7.2
7.3
7.4
7.5
Refresh Controller ..........................................................................................
Overview...........................................................................................................................
7.1.1 Features................................................................................................................
7.1.2 Block Diagram.....................................................................................................
7.1.3 Input/Output Pins .................................................................................................
7.1.4 Register Configuration.........................................................................................
Register Descriptions ........................................................................................................
7.2.1 Refresh Control Register (RFSHCR)...................................................................
7.2.2 Refresh Timer Control/Status Register (RTMCSR) ............................................
7.2.3 Refresh Timer Counter (RTCNT)........................................................................
7.2.4 Refresh Time Constant Register (RTCOR) .........................................................
Operation ..........................................................................................................................
7.3.1 Overview..............................................................................................................
7.3.2 DRAM Refresh Control.......................................................................................
7.3.3 Pseudo-Static RAM Refresh Control ...................................................................
7.3.4 Interval Timer ......................................................................................................
Interrupt Source ................................................................................................................
Usage Notes ......................................................................................................................
Section 8
8.1
133
133
134
136
137
145
151
153
156
156
156
158
158
159
159
159
160
161
161
162
162
165
166
167
168
168
170
185
189
195
195
DMA Controller ............................................................................................. 197
Overview...........................................................................................................................
8.1.1 Features................................................................................................................
8.1.2 Block Diagram.....................................................................................................
8.1.3 Functional Overview............................................................................................
8.1.4 Input/Output Pins .................................................................................................
8.1.5 Register Configuration.........................................................................................
Rev. 7.00 Sep 21, 2005 page xiv of xxiv
197
197
198
199
201
201
8.2
8.3
8.4
8.5
8.6
Register Descriptions (Short Address Mode)....................................................................
8.2.1 Memory Address Registers (MAR) .....................................................................
8.2.2 I/O Address Registers (IOAR) .............................................................................
8.2.3 Execute Transfer Count Registers (ETCR) ..........................................................
8.2.4 Data Transfer Control Registers (DTCR) ............................................................
Register Descriptions (Full Address Mode)......................................................................
8.3.1 Memory Address Registers (MAR) .....................................................................
8.3.2 I/O Address Registers (IOAR) .............................................................................
8.3.3 Execute Transfer Count Registers (ETCR) ..........................................................
8.3.4 Data Transfer Control Registers (DTCR) ............................................................
Operation...........................................................................................................................
8.4.1 Overview..............................................................................................................
8.4.2 I/O Mode..............................................................................................................
8.4.3 Idle Mode.............................................................................................................
8.4.4 Repeat Mode ........................................................................................................
8.4.5 Normal Mode .......................................................................................................
8.4.6 Block Transfer Mode ...........................................................................................
8.4.7 DMAC Activation................................................................................................
8.4.8 DMAC Bus Cycle ................................................................................................
8.4.9 DMAC Multiple-Channel Operation ...................................................................
8.4.10 External Bus Requests, Refresh Controller, and DMAC .....................................
8.4.11 NMI Interrupts and DMAC..................................................................................
8.4.12 Aborting a DMA Transfer....................................................................................
8.4.13 Exiting Full Address Mode ..................................................................................
8.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode..........................
Interrupts ...........................................................................................................................
Usage Notes ......................................................................................................................
8.6.1 Note on Word Data Transfer................................................................................
8.6.2 DMAC Self-Access..............................................................................................
8.6.3 Longword Access to Memory Address Registers ................................................
8.6.4 Note on Full Address Mode Setup .......................................................................
8.6.5 Note on Activating DMAC by Internal Interrupts ...............................................
8.6.6 NMI Interrupts and Block Transfer Mode ...........................................................
8.6.7 Memory and I/O Address Register Values ..........................................................
8.6.8 Bus Cycle when Transfer is Aborted ...................................................................
Section 9
9.1
9.2
I/O Ports ............................................................................................................
Overview...........................................................................................................................
Port 1.................................................................................................................................
9.2.1 Overview..............................................................................................................
203
203
204
205
206
209
209
209
210
212
218
218
220
222
225
229
232
237
239
245
246
247
248
249
250
251
252
252
252
252
252
252
254
254
255
257
257
261
261
Rev. 7.00 Sep 21, 2005 page xv of xxiv
9.2.2 Register Descriptions ...........................................................................................
Port 2.................................................................................................................................
9.3.1 Overview..............................................................................................................
9.3.2 Register Descriptions ...........................................................................................
9.4 Port 3.................................................................................................................................
9.4.1 Overview..............................................................................................................
9.4.2 Register Descriptions ...........................................................................................
9.5 Port 4.................................................................................................................................
9.5.1 Overview..............................................................................................................
9.5.2 Register Descriptions ...........................................................................................
9.6 Port 5.................................................................................................................................
9.6.1 Overview..............................................................................................................
9.6.2 Register Descriptions ...........................................................................................
9.7 Port 6.................................................................................................................................
9.7.1 Overview..............................................................................................................
9.7.2 Register Descriptions ...........................................................................................
9.8 Port 7.................................................................................................................................
9.8.1 Overview..............................................................................................................
9.8.2 Register Description.............................................................................................
9.9 Port 8.................................................................................................................................
9.9.1 Overview..............................................................................................................
9.9.2 Register Descriptions ...........................................................................................
9.10 Port 9.................................................................................................................................
9.10.1 Overview..............................................................................................................
9.10.2 Register Descriptions ...........................................................................................
9.11 Port A................................................................................................................................
9.11.1 Overview..............................................................................................................
9.11.2 Register Descriptions ...........................................................................................
9.11.3 Pin Functions .......................................................................................................
9.12 Port B ................................................................................................................................
9.12.1 Overview..............................................................................................................
9.12.2 Register Descriptions ...........................................................................................
9.12.3 Pin Functions .......................................................................................................
9.3
262
264
264
265
268
268
268
270
270
271
274
274
275
278
278
279
282
282
283
284
284
285
289
289
290
294
294
296
298
306
306
308
310
Section 10 16-Bit Integrated Timer Unit (ITU) .......................................................... 315
10.1 Overview...........................................................................................................................
10.1.1 Features................................................................................................................
10.1.2 Block Diagrams ...................................................................................................
10.1.3 Input/Output Pins .................................................................................................
10.1.4 Register Configuration.........................................................................................
Rev. 7.00 Sep 21, 2005 page xvi of xxiv
315
315
318
323
324
10.2 Register Descriptions ........................................................................................................
10.2.1 Timer Start Register (TSTR)................................................................................
10.2.2 Timer Synchro Register (TSNC) .........................................................................
10.2.3 Timer Mode Register (TMDR) ............................................................................
10.2.4 Timer Function Control Register (TFCR)............................................................
10.2.5 Timer Output Master Enable Register (TOER) ...................................................
10.2.6 Timer Output Control Register (TOCR) ..............................................................
10.2.7 Timer Counters (TCNT) ......................................................................................
10.2.8 General Registers (GRA, GRB)...........................................................................
10.2.9 Buffer Registers (BRA, BRB)..............................................................................
10.2.10 Timer Control Registers (TCR) ...........................................................................
10.2.11 Timer I/O Control Register (TIOR) .....................................................................
10.2.12 Timer Status Register (TSR)................................................................................
10.2.13 Timer Interrupt Enable Register (TIER) ..............................................................
10.3 CPU Interface....................................................................................................................
10.3.1 16-Bit Accessible Registers .................................................................................
10.3.2 8-Bit Accessible Registers ...................................................................................
10.4 Operation...........................................................................................................................
10.4.1 Overview..............................................................................................................
10.4.2 Basic Functions....................................................................................................
10.4.3 Synchronization ...................................................................................................
10.4.4 PWM Mode..........................................................................................................
10.4.5 Reset-Synchronized PWM Mode.........................................................................
10.4.6 Complementary PWM Mode ...............................................................................
10.4.7 Phase Counting Mode ..........................................................................................
10.4.8 Buffering ..............................................................................................................
10.4.9 ITU Output Timing ..............................................................................................
10.5 Interrupts ...........................................................................................................................
10.5.1 Setting of Status Flags..........................................................................................
10.5.2 Clearing of Status Flags .......................................................................................
10.5.3 Interrupt Sources and DMA Controller Activation..............................................
10.6 Usage Notes ......................................................................................................................
327
327
328
330
333
335
337
338
339
340
341
343
345
347
349
349
351
352
352
353
362
364
368
371
380
382
389
391
391
393
394
395
Section 11 Programmable Timing Pattern Controller............................................... 411
11.1 Overview...........................................................................................................................
11.1.1 Features ................................................................................................................
11.1.2 Block Diagram .....................................................................................................
11.1.3 TPC Pins ..............................................................................................................
11.1.4 Registers...............................................................................................................
11.2 Register Descriptions ........................................................................................................
411
411
412
413
414
415
Rev. 7.00 Sep 21, 2005 page xvii of xxiv
11.2.1 Port A Data Direction Register (PADDR) ...........................................................
11.2.2 Port A Data Register (PADR)..............................................................................
11.2.3 Port B Data Direction Register (PBDDR) ...........................................................
11.2.4 Port B Data Register (PBDR) ..............................................................................
11.2.5 Next Data Register A (NDRA) ............................................................................
11.2.6 Next Data Register B (NDRB).............................................................................
11.2.7 Next Data Enable Register A (NDERA)..............................................................
11.2.8 Next Data Enable Register B (NDERB) ..............................................................
11.2.9 TPC Output Control Register (TPCR) .................................................................
11.2.10 TPC Output Mode Register (TPMR) ...................................................................
11.3 Operation ..........................................................................................................................
11.3.1 Overview..............................................................................................................
11.3.2 Output Timing......................................................................................................
11.3.3 Normal TPC Output.............................................................................................
11.3.4 Non-Overlapping TPC Output .............................................................................
11.3.5 TPC Output Triggering by Input Capture ............................................................
11.4 Usage Notes ......................................................................................................................
11.4.1 Operation of TPC Output Pins .............................................................................
11.4.2 Note on Non-Overlapping Output........................................................................
415
415
416
416
417
419
421
422
423
425
427
427
428
429
431
433
434
434
434
Section 12 Watchdog Timer ............................................................................................. 437
12.1 Overview...........................................................................................................................
12.1.1 Features................................................................................................................
12.1.2 Block Diagram.....................................................................................................
12.1.3 Pin Configuration.................................................................................................
12.1.4 Register Configuration.........................................................................................
12.2 Register Descriptions ........................................................................................................
12.2.1 Timer Counter (TCNT)........................................................................................
12.2.2 Timer Control/Status Register (TCSR)................................................................
12.2.3 Reset Control/Status Register (RSTCSR) ............................................................
12.2.4 Notes on Register Access.....................................................................................
12.3 Operation ..........................................................................................................................
12.3.1 Watchdog Timer Operation .................................................................................
12.3.2 Interval Timer Operation .....................................................................................
12.3.3 Timing of Setting of Overflow Flag (OVF) .........................................................
12.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) ..................................
12.4 Interrupts ...........................................................................................................................
12.5 Usage Notes ......................................................................................................................
12.6 Notes .................................................................................................................................
Rev. 7.00 Sep 21, 2005 page xviii of xxiv
437
437
438
438
439
439
439
440
442
443
445
445
446
446
447
448
448
449
Section 13 Serial Communication Interface ................................................................
13.1 Overview...........................................................................................................................
13.1.1 Features ................................................................................................................
13.1.2 Block Diagram .....................................................................................................
13.1.3 Input/Output Pins .................................................................................................
13.1.4 Register Configuration.........................................................................................
13.2 Register Descriptions ........................................................................................................
13.2.1 Receive Shift Register (RSR)...............................................................................
13.2.2 Receive Data Register (RDR) ..............................................................................
13.2.3 Transmit Shift Register (TSR) .............................................................................
13.2.4 Transmit Data Register (TDR).............................................................................
13.2.5 Serial Mode Register (SMR)................................................................................
13.2.6 Serial Control Register (SCR)..............................................................................
13.2.7 Serial Status Register (SSR).................................................................................
13.2.8 Bit Rate Register (BRR) ......................................................................................
13.3 Operation...........................................................................................................................
13.3.1 Overview..............................................................................................................
13.3.2 Operation in Asynchronous Mode .......................................................................
13.3.3 Multiprocessor Communication...........................................................................
13.3.4 Synchronous Operation........................................................................................
13.4 SCI Interrupts....................................................................................................................
13.5 Usage Notes ......................................................................................................................
451
451
451
453
454
454
455
455
455
456
456
457
460
464
468
480
480
482
491
498
506
507
Section 14 Smart Card Interface .....................................................................................
14.1 Overview...........................................................................................................................
14.1.1 Features ................................................................................................................
14.1.2 Block Diagram .....................................................................................................
14.1.3 Input/Output Pins .................................................................................................
14.1.4 Register Configuration.........................................................................................
14.2 Register Descriptions ........................................................................................................
14.2.1 Smart Card Mode Register (SCMR) ....................................................................
14.2.2 Serial Status Register (SSR).................................................................................
14.2.3 Serial Mode Register (SMR)................................................................................
14.2.4 Serial Control Register (SCR)..............................................................................
14.3 Operation...........................................................................................................................
14.3.1 Overview..............................................................................................................
14.3.2 Pin Connections ...................................................................................................
14.3.3 Data Format .........................................................................................................
14.3.4 Register Settings ..................................................................................................
14.3.5 Clock....................................................................................................................
509
509
509
510
511
511
512
512
513
515
516
517
517
517
519
520
522
Rev. 7.00 Sep 21, 2005 page xix of xxiv
14.3.6 Transmitting and Receiving Data ........................................................................ 524
14.4 Usage Notes ...................................................................................................................... 531
Section 15 A/D Converter .................................................................................................
15.1 Overview...........................................................................................................................
15.1.1 Features................................................................................................................
15.1.2 Block Diagram.....................................................................................................
15.1.3 Input Pins .............................................................................................................
15.1.4 Register Configuration.........................................................................................
15.2 Register Descriptions ........................................................................................................
15.2.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................
15.2.2 A/D Control/Status Register (ADCSR) ...............................................................
15.2.3 A/D Control Register (ADCR) ............................................................................
15.3 CPU Interface....................................................................................................................
15.4 Operation ..........................................................................................................................
15.4.1 Single Mode (SCAN = 0) ....................................................................................
15.4.2 Scan Mode (SCAN = 1).......................................................................................
15.4.3 Input Sampling and A/D Conversion Time .........................................................
15.4.4 External Trigger Input Timing.............................................................................
15.5 Interrupts ...........................................................................................................................
15.6 Usage Notes ......................................................................................................................
535
535
535
536
537
538
539
539
540
542
543
544
544
546
548
549
550
550
Section 16 D/A Converter .................................................................................................
16.1 Overview...........................................................................................................................
16.1.1 Features................................................................................................................
16.1.2 Block Diagram.....................................................................................................
16.1.3 Input/Output Pins .................................................................................................
16.1.4 Register Configuration.........................................................................................
16.2 Register Descriptions ........................................................................................................
16.2.1 D/A Data Registers 0 and 1 (DADR0/1)..............................................................
16.2.2 D/A Control Register (DACR) ............................................................................
16.2.3 D/A Standby Control Register (DASTCR)..........................................................
16.3 Operation ..........................................................................................................................
16.4 D/A Output Control ..........................................................................................................
16.5 Usage Notes ......................................................................................................................
557
557
557
558
559
559
560
560
560
562
563
564
564
Section 17 RAM ..................................................................................................................
17.1 Overview...........................................................................................................................
17.1.1 Block Diagram.....................................................................................................
17.1.2 Register Configuration.........................................................................................
565
565
566
566
Rev. 7.00 Sep 21, 2005 page xx of xxiv
17.2 System Control Register (SYSCR) ................................................................................... 567
17.3 Operation........................................................................................................................... 568
Section 18 ROM (H8/3048ZTAT and Mask-ROM Versions) ............................... 569
18.1 Overview...........................................................................................................................
18.1.1 Block Diagram .....................................................................................................
18.2 PROM Mode.....................................................................................................................
18.2.1 PROM Mode Setting............................................................................................
18.2.2 Socket Adapter and Memory Map .......................................................................
18.3 PROM Programming ........................................................................................................
18.3.1 Programming and Verification.............................................................................
18.3.2 Programming Precautions ....................................................................................
18.3.3 Reliability of Programmed Data ..........................................................................
18.4 Notes on Ordering Mask ROM Version Chip...................................................................
569
570
571
571
571
573
574
578
579
580
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V)) ....... 583
19.1 Overview........................................................................................................................... 583
19.2 Flash Memory Overview................................................................................................... 584
19.2.1 Flash Memory Operation ..................................................................................... 584
19.2.2 Mode Programming and Flash Memory Address Space...................................... 585
19.2.3 Features ................................................................................................................ 586
19.2.4 Block Diagram ..................................................................................................... 587
19.2.5 Input/Output Pins ................................................................................................. 588
19.2.6 Register Configuration......................................................................................... 588
19.3 Flash Memory Register Descriptions ................................................................................ 589
19.3.1 Flash Memory Control Register........................................................................... 589
19.3.2 Erase Block Register 1......................................................................................... 592
19.3.3 Erase Block Register 2......................................................................................... 593
19.3.4 RAM Control Register (RAMCR) ....................................................................... 595
19.4 On-Board Programming Modes ........................................................................................ 596
19.4.1 Boot Mode ........................................................................................................... 597
19.4.2 User Program Mode ............................................................................................. 602
19.5 Programming and Erasing Flash Memory......................................................................... 604
19.5.1 Program Mode ..................................................................................................... 605
19.5.2 Program-Verify Mode.......................................................................................... 605
19.5.3 Programming Flowchart and Sample Program .................................................... 606
19.5.4 Erase Mode .......................................................................................................... 609
19.5.5 Erase-Verify Mode............................................................................................... 609
19.5.6 Erasing Flowchart and Sample Program.............................................................. 610
19.5.7 Prewrite-Verify Mode .......................................................................................... 624
Rev. 7.00 Sep 21, 2005 page xxi of xxiv
19.6
19.7
19.8
19.9
19.5.8 Protect Modes ......................................................................................................
19.5.9 NMI Input Masking .............................................................................................
Flash Memory Emulation by RAM...................................................................................
Flash Memory PROM Mode.............................................................................................
19.7.1 PROM Mode Setting............................................................................................
19.7.2 Socket Adapter and Memory Map .......................................................................
19.7.3 Operation in PROM Mode...................................................................................
Flash Memory Programming and Erasing Precautions (Dual-Power Supply) ..................
Notes when Converting the F-ZTAT (Dual-Power Supply) Application Software
to the Mask-ROM Versions ..............................................................................................
625
628
629
631
631
632
634
643
651
Section 20 Clock Pulse Generator .................................................................................. 653
20.1 Overview...........................................................................................................................
20.1.1 Block Diagram.....................................................................................................
20.2 Oscillator Circuit...............................................................................................................
20.2.1 Connecting a Crystal Resonator...........................................................................
20.2.2 External Clock Input ............................................................................................
20.3 Duty Adjustment Circuit...................................................................................................
20.4 Prescalers ..........................................................................................................................
20.5 Frequency Divider ............................................................................................................
20.5.1 Register Configuration.........................................................................................
20.5.2 Division Control Register (DIVCR) ....................................................................
20.5.3 Usage Notes .........................................................................................................
653
654
655
655
657
659
659
660
660
660
661
Section 21 Power-Down State ......................................................................................... 663
21.1 Overview........................................................................................................................... 663
21.2 Register Configuration...................................................................................................... 665
21.2.1 System Control Register (SYSCR) ...................................................................... 665
21.2.2 Module Standby Control Register (MSTCR) ...................................................... 667
21.3 Sleep Mode ....................................................................................................................... 669
21.3.1 Transition to Sleep Mode..................................................................................... 669
21.3.2 Exit from Sleep Mode.......................................................................................... 669
21.4 Software Standby Mode.................................................................................................... 669
21.4.1 Transition to Software Standby Mode ................................................................. 669
21.4.2 Exit from Software Standby Mode ...................................................................... 670
21.4.3 Selection of Waiting Time for Exit from Software Standby Mode...................... 670
21.4.4 Sample Application of Software Standby Mode.................................................. 672
21.4.5 Note...................................................................................................................... 672
21.5 Hardware Standby Mode .................................................................................................. 673
21.5.1 Transition to Hardware Standby Mode ................................................................ 673
Rev. 7.00 Sep 21, 2005 page xxii of xxiv
21.5.2 Exit from Hardware Standby Mode .....................................................................
21.5.3 Timing for Hardware Standby Mode ...................................................................
21.6 Module Standby Function .................................................................................................
21.6.1 Module Standby Timing ......................................................................................
21.6.2 Read/Write in Module Standby............................................................................
21.6.3 Usage Notes .........................................................................................................
21.7 System Clock Output Disabling Function.........................................................................
673
673
674
674
674
675
676
Section 22 Electrical Characteristics..............................................................................
22.1 Electrical Characteristics for H8/3048 ZTAT (PROM) and On-Chip Mask ROM
Versions ............................................................................................................................
22.1.1 Absolute Maximum Ratings ................................................................................
22.1.2 DC Characteristics ...............................................................................................
22.1.3 AC Characteristics ...............................................................................................
22.1.4 A/D Conversion Characteristics...........................................................................
22.1.5 D/A Conversion Characteristics...........................................................................
22.2 Electrical Characteristics of H8/3048F (Dual-Power Supply) ..........................................
22.2.1 Absolute Maximum Ratings ................................................................................
22.2.2 DC Characteristics ...............................................................................................
22.2.3 AC Characteristics ...............................................................................................
22.2.4 A/D Conversion Characteristics...........................................................................
22.2.5 D/A Conversion Characteristics...........................................................................
22.2.6 Flash Memory Characteristics..............................................................................
22.3 Operational Timing ...........................................................................................................
22.3.1 Bus Timing...........................................................................................................
22.3.2 Refresh Controller Bus Timing............................................................................
22.3.3 Control Signal Timing .........................................................................................
22.3.4 Clock Timing .......................................................................................................
22.3.5 TPC and I/O Port Timing.....................................................................................
22.3.6 ITU Timing ..........................................................................................................
22.3.7 SCI Input/Output Timing .....................................................................................
22.3.8 DMAC Timing.....................................................................................................
677
Appendix A
A.1
A.2
A.3
679
679
680
686
693
694
695
695
696
703
709
710
711
712
712
716
721
723
723
724
725
726
Instruction Set ............................................................................................. 727
Instruction List .................................................................................................................. 727
Operation Code Map ......................................................................................................... 742
Number of States Required for Execution ........................................................................ 745
Appendix B
B.1
Internal I/O Register ................................................................................. 755
Addresses .......................................................................................................................... 756
Rev. 7.00 Sep 21, 2005 page xxiii of xxiv
B.2
Function ............................................................................................................................ 764
Appendix C
C.1
C.2
C.3
C.4
C.5
C.6
C.7
C.8
C.9
C.10
C.11
I/O Port Block Diagrams .........................................................................
Port 1 Block Diagram .......................................................................................................
Port 2 Block Diagram .......................................................................................................
Port 3 Block Diagram .......................................................................................................
Port 4 Block Diagram .......................................................................................................
Port 5 Block Diagram .......................................................................................................
Port 6 Block Diagrams......................................................................................................
Port 7 Block Diagrams......................................................................................................
Port 8 Block Diagrams......................................................................................................
Port 9 Block Diagrams......................................................................................................
Port A Block Diagrams .....................................................................................................
Port B Block Diagrams .....................................................................................................
844
844
845
846
847
848
849
853
854
857
861
865
Appendix D
D.1
D.2
Pin States...................................................................................................... 869
Port States in Each Mode .................................................................................................. 869
Pin States at Reset ............................................................................................................. 872
Appendix E
Timing of Transition to and Recovery from Hardware Standby
Mode ............................................................................................................. 875
Appendix F
Product Code Lineup ................................................................................ 876
Appendix G
Package Dimensions ................................................................................. 877
Rev. 7.00 Sep 21, 2005 page xxiv of xxiv
Section 1 Overview
Section 1 Overview
1.1
Overview
The H8/3048 Group is a series of microcontrollers (MCUs) that integrate system supporting
functions together with an H8/300H CPU core having an original Renesas Technology
architecture.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space. Its instruction set is upward-compatible at the object-code level with the H8/300 CPU,
enabling easy porting of software from the H8/300 Series.
The on-chip system supporting functions include ROM, RAM, a 16-bit integrated timer unit
(ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial
communication interface (SCI), an A/D converter, a D/A converter, I/O ports, a direct memory
access controller (DMAC), a refresh controller, and other facilities.
The four members of the H8/3048 Group are the H8/3048, the H8/3047, H8/3045, and the
H8/3044. The H8/3048 has 128 kbytes of ROM and 4 kbytes of RAM. The H8/3047 has 96 kbytes
of ROM and 4 kbytes of RAM. The H8/3045 has 64 kbytes of ROM and 2 kbytes of RAM. The
H8/3044 has 32 kbytes of ROM and 2 kbytes of RAM.
Seven MCU operating modes offer a choice of data bus width and address space size. The modes
(modes 1 to 7) include one single-chip mode and six expanded modes.
In addition to the mask ROM versions of the H8/3048 Group, the H8/3048 has a ZTAT™*1
version with user-programmable on-chip PROM and an F-ZTAT™*2 version with on-chip flash
memory that can be programmed on-board. These versions enable users to respond quickly and
flexibly to changing application specifications, growing production volumes, and other conditions.
The F-ZTAT™ version H8/3048F-ONE includes the on-chip emulator E10T.
Table 1.1 summarizes the features of the H8/3048 Group.
Notes: 1. ZTAT (Zero Turn-Around Time) is a trademark of Renesas Technology Corp.
2. F-ZTAT (Flexible ZTAT) is a trademark of Renesas Technology Corp.
Rev. 7.00 Sep 21, 2005 page 1 of 878
REJ09B0259-0700
Section 1 Overview
Table 1.1
Features
Feature
Description
CPU
Upward-compatible with the H8/300 CPU at the object-code level
•
General-register machine
Sixteen 16-bit general registers
(also usable as sixteen 8-bit registers + eight 16-bit registers or eight 32bit registers)
•
High-speed operation (flash memory version)
H8/3048F
Maximum clock rate: 16 MHz
Add/subtract: 125 ns
Multiply/divide: 875 ns
•
High-speed operation (mask ROM and PROM versions)
Maximum clock rate: 18 MHz
Add/subtract: 111 ns
Multiply/divide: 778 ns
•
16-Mbyte address space
•
Instruction features
8/16/32-bit data transfer, arithmetic, and logic instructions
Signed and unsigned multiply instructions (8 bits × 8 bits, 16 bits × 16
bits)
Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16
bits)
Bit accumulator function
Bit manipulation instructions with register-indirect specification of bit
positions
Rev. 7.00 Sep 21, 2005 page 2 of 878
REJ09B0259-0700
Section 1 Overview
Feature
Description
Memory
•
H8/3048, H8/3048F
ROM: 128 kbytes
RAM: 4 kbytes
•
H8/3047
ROM: 96 kbytes
RAM: 4 kbytes
•
H8/3045
ROM: 64 kbytes
RAM: 2 kbytes
•
H8/3044
ROM: 32 kbytes
RAM: 2 kbytes
Interrupt
controller
Bus controller
Refresh
controller
•
Seven external interrupt pins: NMI, IRQ0 to IRQ5
•
30 internal interrupts
•
Three selectable interrupt priority levels
•
Address space can be partitioned into eight areas, with independent bus
specifications in each area
•
Chip select output available for areas 0 to 7
•
8-bit access or 16-bit access selectable for each area
•
Two-state or three-state access selectable for each area
•
Selection of four wait modes
•
Bus arbitration function
•
DRAM refresh
Directly connectable to 16-bit-wide DRAM
CAS-before-RAS refresh
Self-refresh mode selectable
•
Pseudo-static RAM refresh
Self-refresh mode selectable
•
Usable as an interval timer
Rev. 7.00 Sep 21, 2005 page 3 of 878
REJ09B0259-0700
Section 1 Overview
Feature
Description
DMA controller
(DMAC)
•
Short address mode
Maximum four channels available
Selection of I/O mode, idle mode, or repeat mode
Can be activated by compare match/input capture A interrupts from ITU
channels 0 to 3, transmit-data-empty and receive-data-full interrupts from
SCI channel 0, or external requests
•
Full address mode
Maximum two channels available
Selection of normal mode or block transfer mode
Can be activated by compare match/input capture A interrupts from ITU
channels 0 to 3, external requests, or auto-request
16-bit integrated
timer unit (ITU)
Programmable
timing pattern
controller (TPC)
Watchdog timer
(WDT),
1 channel
•
Five 16-bit timer channels, capable of processing up to 12 pulse outputs or
10 pulse inputs
•
16-bit timer counter (channels 0 to 4)
•
Two multiplexed output compare/input capture pins (channels 0 to 4)
•
Operation can be synchronized (channels 0 to 4)
•
PWM mode available (channels 0 to 4)
•
Phase counting mode available (channel 2)
•
Buffering available (channels 3 and 4)
•
Reset-synchronized PWM mode available (channels 3 and 4)
•
Complementary PWM mode available (channels 3 and 4)
•
DMAC can be activated by compare match/input capture A interrupts
(channels 0 to 3)
•
Maximum 16-bit pulse output, using ITU as time base
•
Up to four 4-bit pulse output groups (or one 16-bit group, or two 8-bit groups)
•
Non-overlap mode available
•
Output data can be transferred by DMAC
•
Reset signal can be generated by overflow
•
Reset signal can be output externally
•
Usable as an interval timer
Rev. 7.00 Sep 21, 2005 page 4 of 878
REJ09B0259-0700
Section 1 Overview
Feature
Description
Serial
communication
interface (SCI),
2 channels
•
Selection of asynchronous or synchronous mode
•
Full duplex: can transmit and receive simultaneously
•
On-chip baud-rate generator
•
Smart card interface functions added (SCI0 only)
•
Resolution: 10 bits
•
Eight channels, with selection of single or scan mode
•
Variable analog conversion voltage range
•
Sample-and-hold function
•
A/D conversion can be externally triggered
•
Resolution: 8 bits
A/D converter
D/A converter
I/O ports
Operating
modes
Power-down
state
•
Two channels
•
D/A outputs can be sustained in software standby mode
•
70 input/output pins
•
8 input-only pins
•
Seven MCU operating modes
Mode
Address Space
Address Pins
Initial Bus Width
Max. Bus Width
Mode 1
1 Mbyte
A19 to A0
8 bits
16 bits
Mode 2
1 Mbyte
A19 to A0
16 bits
16 bits
Mode 3
16 Mbytes
A23 to A0
8 bits
16 bits
Mode 4
16 Mbytes
A23 to A0
16 bits
16 bits
Mode 5
1 Mbyte
A19 to A0
8 bits
16 bits
Mode 6
16 Mbytes
A23 to A0
8 bits
16 bits
Mode 7
1 Mbyte
—
—
—
•
On-chip ROM is disabled in modes 1 to 4
•
Sleep mode
•
Software standby mode
•
Hardware standby mode
•
Module standby function
•
Programmable system clock frequency division
Rev. 7.00 Sep 21, 2005 page 5 of 878
REJ09B0259-0700
Section 1 Overview
Feature
Description
Other features
•
Product lineup
Model (5 V)
On-chip clock pulse generator
Model (3 V)
Package
ROM
Flash memory
HD64F3048TF
HD64F3048VTF
100-pin TQFP (TFP-100B)
HD64F3048F
HD64F3048VF
100-pin QFP (FP-100B)
HD6473048TF
HD6473048VTF
100-pin TQFP (TFP-100B)
HD6473048F
HD6473048VF
100-pin QFP (FP-100B)
HD6433048TF
HD6433048VTF
100-pin TQFP (TFP-100B)
HD6433048F
HD6433048VF
100-pin QFP (FP-100B)
HD6433047TF
HD6433047VTF
100-pin TQFP (TFP-100B)
HD6433047F
HD6433047VF
100-pin QFP (FP-100B)
HD6433045TF
HD6433045VTF
100-pin TQFP (TFP-100B)
HD6433045F
HD6433045VF
100-pin QFP (FP-100B)
HD6433044TF
HD6433044VTF
100-pin TQFP (TFP-100B)
HD6433044F
HD6433044VF
100-pin QFP (FP-100B)
Rev. 7.00 Sep 21, 2005 page 6 of 878
REJ09B0259-0700
PROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Section 1 Overview
1.2
Block Diagram
Port 3
P40/D0
P41/D1
P42/D2
P43/D3
P44/D4
P45/D5
P46/D6
P47/D7
P30/D8
P31/D9
P32/D10
P33/D11
P34/D12
P35/D13
P36/D14
P37/D15
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
Figure 1.1 shows an internal block diagram.
Port 4
Address bus
Data bus (upper)
MD1
Data bus (lower)
Port 5
P53/A19
MD2
MD0
P52/A18
P51/A17
P50/A16
EXTAL
P27/A15
Clock pulse
generator
STBY
RES
VPP/RESO *
NMI
DMA controller
(DMAC)
P65/HWR
P24/A12
P23/A11
P22/A10
P21/A9
P20/A8
P17/A7
P16/A6
P15/A5
P61/BREQ
Port 1
P62/BACK
ROM
(mask ROM,
PROM, or flash
memory)
Port 6
P63/AS
P25/A13
Interrupt controller
P66/LWR
P64/RD
P26/A14
H8/300H CPU
Port 2
φ
Bus controller
XTAL
Refresh
controller
P60/WAIT
P14/A4
P13/A3
P12/A2
RAM
P11/A1
P84/CS0
P82/CS2/IRQ2
P81/CS3/IRQ1
Port 8
P83/CS1/IRQ3
P10/A0
Watchdog timer
(WDT)
16-bit integrated
timer unit
(ITU)
P80/RFSH/IRQ0
Serial communication
interface
(SCI) × 2 channels
P95/SCK1/IRQ5
Programmable
timing pattern
controller (TPC)
P94/SCK0/IRQ4
Port 9
A/D converter
D/A converter
P93/RxD1
P92/RxD0
P91/TxD1
P90/TxD0
P70/AN0
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P76/AN6/DA0
P77/AN7/DA1
AVSS
AVCC
VREF
PA0/TP0/TEND0/TCLKA
PA1/TP1/TEND1/TCLKB
Port 7
PA2/TP2/TIOCA0/TCLKC
PA3/TP3/TIOCB0/TCLKD
PA4/TP4/TIOCA1/A23/CS6
PA5/TP5/TIOCB1/A22/CS5
PA6/TP6/TIOCA2/A21/CS4
PA7/TP7/TIOCB2/A20
PB0/TP8/TIOCA3
PB1/TP9/TIOCB3
Port A
PB2/TP10/TIOCA4
PB3/TP11/TIOCB4
PB4/TP12/TOCXA4
PB5/TP13/TOCXB4
PB6/TP14/DREQ0/CS7
PB7/TP15/DREQ1/ADTRG
Port B
Note: * For the mask ROM version, this pin is also used as the RESO (output) terminal. For the flash memory version dual power
supply (VPP = 12 V) and for the PROM version, this pin is also used as the RESO (output)/VPP (input) terminal.
Figure 1.1 Block Diagram
Rev. 7.00 Sep 21, 2005 page 7 of 878
REJ09B0259-0700
Section 1 Overview
1.3
Pin Description
1.3.1
Pin Arrangement
Figure 1.2 shows the pin arrangement of the H8/3048 Group.
The pin arrangement of the H8/3048 Group is shown in figure 1.2. Differences in the H8/3048
Group pin arrangements are shown in table 1.2. Except for the differences shown in table 1.2, the
pin arrangements are the same.
Table 1.2
Package
FP-100B
(TFP-100B)
Comparison of H8/3048 Group Pin Arrangements
Pin
Number
H8/3048
ZTAT
H8/3048
Mask ROM
Version
H8/3047
Mask ROM
Version
H8/3045
Mask ROM
Version
H8/3044
Mask ROM
Version
H8/3048F
1
VCC
VCC
VCC
VCC
VCC
VCC
10
VPP/RESO
RESO
RESO
RESO
RESO
VPP/RESO
Rev. 7.00 Sep 21, 2005 page 8 of 878
REJ09B0259-0700
MD2
MD1
MD0
P66 /LWR
P65 /HWR
P64 /RD
P63 /AS
VCC
XTAL
EXTAL
VSS
NMI
RES
STBY
ø
P62 /BACK
P61 /BREQ
P60 /WAIT
VSS
P53 /A 19
P52 /A 18
P51 /A 17
P50 /A 16
P27 /A 15
P26 /A 14
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Section 1 Overview
D15/P37
PA0/TP0/TEND0/TCLKA
93
33
D14/P36
PA1/TP1/TEND1/TCLKB
94
32
D13/P35
PA2/TP2/TIOCA0/TCLKC
95
31
D12/P34
PA3/TP3/TIOCB0/TCLKD
96
30
D11/P33
PA4/TP4/TIOCA1/A23/CS6
97
29
D10/P32
PA5/TP5/TIOCB1/A22/CS5
98
28
D9/P31
PA6/TP6/TIOCA2/A21/CS4
99
27
D8/P30
100
26
D7/P47
PA7/TP7/TIOCB2/A20
25
34
D6 /P4 6
92
24
VCC
VSS
D5 /P4 5
35
23
91
D4 /P4 4
A0/P10
P84/CS0
22
36
VSS
90
21
A1/P11
P83/CS1/IRQ3
D3 /P4 3
37
20
89
D2 /P4 2
A2/P12
P82/CS2/IRQ2
19
38
D1 /P4 1
(FP-100B, TFP-100B)
18
88
D0 /P4 0
A3/P13
P81/CS3/IRQ1
17
39
IRQ 5/SCK1 /P9 5
Top view
16
87
IRQ 4/SCK0 /P9 4
A4/P14
P80/RFSH/IRQ0
15
40
RxD1 /P9 3
86
14
A5/P15
AVSS
RxD0 /P9 2
41
13
85
TxD1 /P9 1
A6/P16
P77/AN7/DA1
12
42
TxD0 /P9 0
84
11
A7/P17
P76/AN6/DA0
VSS
43
10*
83
VPP/RESO
VSS
P75/AN5
9
44
ADTRG/DREQ 1 /TP15 /PB 7
82
8
A8/P20
P74/AN4
CS7/DREQ 0 /TP14 /PB 6
45
7
81
TOCXB4 /TP13 /PB 5
A9/P21
P73/AN3
6
46
TOCXA4 /TP12 /PB 4
80
5
A10/P22
P72/AN2
TIOCB4 /TP11 /PB 3
A11/P23
47
4
48
79
TIOCA4 /TP10 /PB 2
78
P71/AN1
3
P70/AN0
TIOCB3 /TP 9 /PB 1
A12/P24
2
A13/P25
49
1
50
77
VCC
76
VREF
TIOCA3 /TP 8 /PB 0
AVCC
Note: * For the mask ROM version, this pin is also used as the RESO terminal. For the PROM version and
the flash memory version dual power method, this pin is also used as the RESO/VPP terminal.
For the flash memory version with single power method.
Figure 1.2 Pin Arrangement of H8/3048ZTAT, H8/3048 Mask ROM Version, H8/3047
Mask ROM Version, H8/3045 Mask ROM Version, H8/3044 Mask ROM Version, and
H8/3048F (FP-100B or TFP-100B, Top View)
Rev. 7.00 Sep 21, 2005 page 9 of 878
REJ09B0259-0700
Section 1 Overview
1.3.2
Pin Assignments in Each Mode
Table 1.3 lists the pin assignments in each mode.
Table 1.3
Pin Assignments in Each Mode (FP-100B or TFP-100B)
Pin Name
Pin
No.
PROM Mode
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
EPROM Flash
Remarks
1*
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Mask
ROM
version,
PROM
version
and flash
memory
version
with dual
power
supply.
2
PB0/TP8/ B0/TP8/
TIOCA3 TIOCA3
B0/TP8/
TIOCA3
B0/TP8/
TIOCA3
B0/TP8/
TIOCA3
B0/TP8/
TIOCA3
B0/TP8/
TIOCA3
NC
NC
3
PB1/TP9/ PB1/TP9/ PB1/TP9/ PB1/TP9/ PB1/TP9/ PB1/TP9/ PB1/TP9/ NC
TIOCB3 TIOCB3 TIOCB3 TIOCB3 TIOCB3 TIOCB3 TIOCB3
NC
4
PB2/TP10/ PB2/TP10/ PB2/TP10/ PB2/TP10/ PB2/TP10/ PB2/TP10/ PB2/TP10/ NC
TIOCA4 TIOCA4 TIOCA4 TIOCA4 TIOCA4 TIOCA4 TIOCA4
NC
5
PB3/TP11/ PB3/TP11/ PB3/TP11/ PB3/TP11/ PB3/TP11/ PB3/TP11/ PB3/TP11/ NC
TIOCB4 TIOCB4 TIOCB4 TIOCB4 TIOCB4 TIOCB4 TIOCB4
NC
6
PB4/TP12/ PB4/TP12/ PB4/TP12/ PB4/TP12/ PB4/TP12/ PB4/TP12/ PB4/TP12/ NC
TOCXA4 TOCXA4 TOCXA4 TOCXA4 TOCXA4 TOCXA4 TOCXA4
NC
7
PB5/TP13/ PB5/TP13/ PB5/TP13/ PB5/TP13/ PB5/TP13/ PB5/TP13/ PB5/TP13/ NC
TOCXB4 TOCXB4 TOCXB4 TOCXB4 TOCXB4 TOCXB4 TOCXB4
NC
8
PB6/TP14/ PB6/TP14/ PB6/TP14/ PB6/TP14/ PB6/TP14/ PB6/TP14/ PB6/TP14/ NC
DREQ0/ DREQ0/ DREQ0/ DREQ0/ DREQ0/ DREQ0/ DREQ0
CS7
CS7
CS7
CS7
CS7
CS7
NC
9
PB7/TP15/ PB7/TP15/ PB7/TP15/ PB7/TP15/ PB7/TP15/ PB7/TP15/ PB7/TP15/ NC
DREQ1/ DREQ1/ DREQ1/ DREQ1/ DREQ1/ DREQ1/ DREQ1/
ADTRG ADTRG ADTRG ADTRG ADTRG ADTRG ADTRG
NC
3
Rev. 7.00 Sep 21, 2005 page 10 of 878
REJ09B0259-0700
Section 1 Overview
Pin Name
Pin
No.
PROM Mode
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
EPROM Flash
Remarks
10*
RESO
RESO
RESO
RESO
RESO
RESO
RESO
VPP
VPP
Mask
ROM
version,
PROM
version
and flash
memory
version
with dual
power
supply.
11
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
12
P90/TxD0 P90/TxD0 P90/TxD0 P90/TxD0 P90/TxD0 P90/TxD0 P90/TxD0 NC
NC
13
P91/TxD1 P91/TxD1 P91/TxD1 P91/TxD1 P91/TxD1 P91/TxD1 P91/TxD1 NC
NC
14
P92/RxD0 P92/RxD0 P92/RxD0 P92/RxD0 P92/RxD0 P92/RxD0 P92/RxD0 NC
NC
15
P93/RxD1 P93/RxD1 P93/RxD1 P93/RxD1 P93/RxD1 P93/RxD1 P93/RxD1 NC
NC
16
P94/SCK0 P94/SCK0 P94/SCK0 P94/SCK0 P94/SCK0 P94/SCK0 P94/SCK0 NC
/
/
/
/
/
/
/
IRQ4
IRQ4
IRQ4
IRQ4
IRQ4
IRQ4
IRQ4
NC
17
P95/SCK1 P95/SCK1 P95/SCK1 P95/SCK1 P95/SCK1 P95/SCK1 P95/SCK1 NC
/
/
/
/
/
/
/
IRQ5
IRQ5
IRQ5
IRQ5
IRQ5
IRQ5
IRQ5
NC
18
P40/D0*1
P40/D0*2
P40/D0*1
P40/D0*2
P40/D0*1
P40/D0*1
P40
NC
NC
19
1
P41/D1*
2
P41/D1*
1
P41/D1*
2
P41/D1*
1
P41/D1*
1
P41/D1*
P41
NC
NC
20
P42/D2*1
P42/D2*2
P42/D2*1
P42/D2*2
P42/D2*1
P42/D2*1
P42
NC
NC
21
P43/D3*1
P43/D3*2
P43/D3*1
P43/D3*2
P43/D3*1
P43/D3*1
P43
NC
NC
22
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
23
P44/D4*1
P44/D4*2
P44/D4*1
P44/D4*2
P44/D4*1
P44/D4*1
P44
NC
NC
24
P45/D5*1
P45/D5*2
P45/D5*1
P45/D5*2
P45/D5*1
P45/D5*1
P45
NC
NC
25
1
2
1
2
1
P46/D6*1
P46
NC
NC
1
1
4
P46/D6*
1
P46/D6*
2
P46/D6*
1
P46/D6*
2
P46/D6*
26
P47/D7*
P47/D7*
P47/D7*
P47/D7*
P47/D7*
P47/D7*
P47
NC
NC
27
D8
D8
D8
D8
D8
D8
P30
EO0
I/O0
28
D9
D9
D9
D9
D9
D9
P31
EO1
I/O1
29
D10
D10
D10
D10
D10
D10
P32
EO2
I/O2
30
D11
D11
D11
D11
D11
D11
P33
EO3
I/O3
31
D12
D12
D12
D12
D12
D12
P34
EO4
I/O4
32
D13
D13
D13
D13
D13
D13
P35
EO5
I/O5
33
D14
D14
D14
D14
D14
D14
P36
EO6
I/O6
Rev. 7.00 Sep 21, 2005 page 11 of 878
REJ09B0259-0700
Section 1 Overview
Pin Name
PROM Mode
Pin
No.
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
EPROM Flash
34
D15
D15
D15
D15
D15
D15
P37
EO7
I/O7
35
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
36
A0
A0
A0
A0
P10/A0
P10/A0
P10
EA0
A0
37
A1
A1
A1
A1
P11/A1
P11/A1
P11
EA1
A1
38
A2
A2
A2
A2
P12/A2
P12/A2
P12
EA2
A2
39
A3
A3
A3
A3
P13/A3
P13/A3
P13
EA3
A3
40
A4
A4
A4
A4
P14/A4
P14/A4
P14
EA4
A4
41
A5
A5
A5
A5
P15/A5
P15/A5
P15
EA5
A5
42
A6
A6
A6
A6
P16/A6
P16/A6
P16
EA6
A6
43
A7
A7
A7
A7
P17/A7
P17/A7
P17
EA7
A7
44
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
56
A19
A19
A19
A19
P53/A19
P53/A19
P53
NC
NC
57
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
58
P60/
WAIT
P60/
WAIT
P60/
WAIT
P60/
WAIT
P60/
WAIT
P60/
WAIT
P60
EA15
A15
59
P61/
BREQ
P61/
BREQ
P61/
BREQ
P61/
BREQ
P61/
BREQ
P61/
BREQ
P61
NC
NC
60
P62/
BACK
P62/
BACK
P62/
BACK
P62/
BACK
P62/
BACK
P62/
BACK
P62
NC
NC
61
φ
φ
φ
φ
φ
φ
φ
NC
NC
62
STBY
STBY
STBY
STBY
STBY
STBY
STBY
VSS
VCC
63
RES
RES
RES
RES
RES
RES
RES
NC
RES
64
NMI
NMI
NMI
NMI
NMI
NMI
NMI
EA9
A9
65
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
66
EXTAL
EXTAL
EXTAL
EXTAL
EXTAL
EXTAL
EXTAL
NC
EXTAL
67
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
NC
XTAL
68
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
69
AS
AS
AS
AS
AS
AS
P63
NC
A16
70
RD
RD
RD
RD
RD
RD
P64
NC
NC
71
HWR
HWR
HWR
HWR
HWR
HWR
P65
NC
VCC
72
LWR
LWR
LWR
LWR
LWR
LWR
P66
NC
NC
73
MD0
MD0
MD0
MD0
MD0
MD0
MD0
VSS
VSS
74
MD1
MD1
MD1
MD1
MD1
MD1
MD1
VSS
VSS
75
MD2
MD2
MD2
MD2
MD2
MD2
MD2
VSS
VSS
Rev. 7.00 Sep 21, 2005 page 12 of 878
REJ09B0259-0700
Remarks
Section 1 Overview
Pin Name
PROM Mode
Pin
No.
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
EPROM Flash
76
AVCC
AVCC
AVCC
AVCC
AVCC
AVCC
AVCC
VCC
VCC
77
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VCC
VCC
78
P70/AN0
P70/AN0
P70/AN0
P70/AN0
P70/AN0
P70/AN0
P70/AN0
NC
NC
79
P71/AN1
P71/AN1
P71/AN1
P71/AN1
P71/AN1
P71/AN1
P71/AN1
NC
NC
80
P72/AN2
P72/AN2
P72/AN2
P72/AN2
P72/AN2
P72/AN2
P72/AN2
NC
NC
81
P73/AN3
P73/AN3
P73/AN3
P73/AN3
P73/AN3
P73/AN3
P73/AN3
NC
NC
82
P74/AN4
P74/AN4
P74/AN4
P74/AN4
P74/AN4
P74/AN4
P74/AN4
NC
NC
83
P75/AN5
P75/AN5
P75/AN5
P75/AN5
P75/AN5
P75/AN5
P75/AN5
NC
NC
84
P76/AN6/ P76/AN6/ P76/AN6/ P76/AN6/ P76/AN6/ P76/AN6/ P76/AN6/ NC
DA0
DA0
DA0
DA0
DA0
DA0
DA0
NC
85
P77/AN7/ P77/AN7/ P77/AN7/ P77/AN7/ P77/AN7/ P77/AN7/ P77/AN7/ NC
DA1
DA1
DA1
DA1
DA1
DA1
DA1
NC
86
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
VSS
87
P80/
RFSH/
IRQ0
P80/
RFSH/
IRQ0
P80/
RFSH/
IRQ0
P80/
RFSH/
IRQ0
P80/
RFSH/
IRQ0
P80/
RFSH/
IRQ0
P80/IRQ0 EA16
NC
88
P81/CS3/ P81/CS3/ P81/CS3/ P81/CS3/ P81/CS3/ P81/CS3/ P81/IRQ1 PGM
IRQ1
IRQ1
IRQ1
IRQ1
IRQ1
IRQ1
NC
89
P82/CS2/ P82/CS2/ P82/CS2/ P82/CS2/ P82/CS2/ P82/CS2/ P82/IRQ2 NC
IRQ2
IRQ2
IRQ2
IRQ2
IRQ2
IRQ2
VCC
90
P83/CS1/ P83/CS1/ P83/CS1/ P83/CS1/ P83/CS1/ P83/CS1/ P83/IRQ3 NC
IRQ3
IRQ3
IRQ3
IRQ3
IRQ3
IRQ3
WE
91
P84/CS0
P84/CS0
P84/CS0
P84/CS0
P84/CS0
P84/CS0
P84
NC
NC
92
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
93
PA0/TP0/ PA0/TP0/ PA0/TP0/ PA0/TP0/ PA0/TP0/ PA0/TP0/ PA0/TP0/ NC
TEND0/
TEND0/
TEND0/
TEND0/
TEND0/
TEND0/
TEND0/
TCLKA
TCLKA
TCLKA
TCLKA
TCLKA
TCLKA
TCLKA
NC
94
PA1/TP1/ PA1/TP1/ PA1/TP1/ PA1/TP1/ PA1/TP1/ PA1/TP1/ PA1/TP1/ NC
TEND1/
TEND1/
TEND1/
TEND1/
TEND1/
TEND1/
TEND1/
TCLKB
TCLKB
TCLKB
TCLKB
TCLKB
TCLKB
TCLKB
NC
95
PA2/TP2/ PA2/TP2/ PA2/TP2/ PA2/TP2/ PA2/TP2/ PA2/TP2/ PA2/TP2/ NC
TIOCA0/ TIOCA0/ TIOCA0/ TIOCA0/ TIOCA0/ TIOCA0/ TIOCA0/
TCLKC
TCLKC
TCLKC
TCLKC
TCLKC
TCLKC
TCLKC
NC
96
PA3/TP3/ PA3/TP3/ PA3/TP3/ PA3/TP3/ PA3/TP3/ PA3/TP3/ PA3/TP3/ NC
TIOCB0/ TIOCB0/ TIOCB0/ TIOCB0/ TIOCB0/ TIOCB0/ TIOCB0/
TCLKD
TCLKD
TCLKD
TCLKD
TCLKD
TCLKD
TCLKD
NC
VSS
Remarks
Rev. 7.00 Sep 21, 2005 page 13 of 878
REJ09B0259-0700
Section 1 Overview
Pin Name
Pin
No.
PROM Mode
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
EPROM Flash
97
PA4/TP4/ PA4/TP4/ PA4/TP4/ PA4/TP4/ PA4/TP4/ PA4/TP4/ PA4/TP4/ NC
TIOCA1/ TIOCA1/ TIOCA1/ TIOCA1/ TIOCA1/ TIOCA1/ TIOCA1
CS6
CS6
CS6
CS6
CS6
A23/CS6
NC
98
PA5/TP5/ PA5/TP5/ PA5/TP5/ PA5/TP5/ PA5/TP5/ PA5/TP5/ PA5/TP5/ NC
TIOCB1/ TIOCB1/ TIOCB1/ TIOCB1/ TIOCB1/ TIOCB1/ TIOCB1
CS5
CS5
CS5
CS5
CS5
A22/CS5
NC
99
PA6/TP6/ PA6/TP6/ PA6/TP6/ PA6/TP6/ PA6/TP6/ PA6/TP6/ PA6/TP6/ NC
TIOCA2/ TIOCA2/ TIOCA2/ TIOCA2/ TIOCA2/ TIOCA2/ TIOCA2
CS4
CS4
CS4
CS4
CS4
A21/CS4
NC
100
PA7/TP7/ PA7/TP7/ A20
TIOCB2 TIOCB2
NC
A20
PA7/TP7/ A20
TIOCB2
PA7/TP7/ NC
TIOCB2
Remarks
Notes: 1. In modes 1, 3, 5, and 6 the P40 to P47 functions of pins P40/D0 to P47/D7 are selected
after a reset, but they can be changed by software.
2. In modes 2 and 4 the D0 to D7 functions of pins P40/D0 to P47/D7 are selected after a
reset, but they can be changed by software.
3. For the H8/3048 ZTAT version, H8/3048F version, H8/3048 mask ROM version,
H8/3047 mask ROM version, H8/3045 mask ROM version, and H8/3044 mask ROM
version, this pin is also used as the VCC terminal.
4. For the H8/3048 ZTAT version, H8/3048F version, H8/3048 mask ROM version,
H8/3047 mask ROM version, H8/3045 mask ROM version, and H8/3044 mask ROM
version, this pin is used as the RESO terminal.
Rev. 7.00 Sep 21, 2005 page 14 of 878
REJ09B0259-0700
Section 1 Overview
1.3.3
Pin Functions
Table 1.4 summarizes the pin functions.
Table 1.4
Pin Functions
Type
Symbol
Pin No.
I/O
Name and Function
Power
VCC
1, 35, 68
Input
Power: For connection to the power
supply. Connect all VCC pins to the system
power supply.
VSS
11, 22, 44,
57, 65, 92
Input
Ground: For connection to ground (0 V).
Connect all VSS pins to the 0-V system
power supply.
XTAL
67
Input
For connection to a crystal resonator.
For examples of crystal resonator and
external clock input, see section 20, Clock
Pulse Generator.
EXTAL
66
Input
For connection to a crystal resonator or
input of an external clock signal. For
examples of crystal resonator and external
clock input, see section 20, Clock Pulse
Generator.
φ
61
Output
System clock: Supplies the system clock
to external devices.
Input
Mode 2 to mode 0: For setting the
operating mode, as follows. Inputs at these
pins must not be changed during operation.
Clock
Operating mode MD2 to MD0 75 to 73
control
MD2
MD1
MD0
Operating Mode
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
—
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
Rev. 7.00 Sep 21, 2005 page 15 of 878
REJ09B0259-0700
Section 1 Overview
Type
Symbol
Pin No.
I/O
Name and Function
System control
RES
63
Input
Reset input: When driven low, this pin
resets the chip
RESO
10
Output
Reset output: For the mask ROM version,
outputs a reset signal to external devices
Also used as a power supply for on-board
programming of the flash memory version
with dual power supply.
(RESO/VPP)
STBY
62
Input
Standby: When driven low, this pin forces a
transition to hardware standby mode
BREQ
59
Input
Bus request: Used by an external bus
master to request the bus right
BACK
60
Output
Bus request acknowledge: Indicates that
the bus has been granted to an external bus
master
NMI
64
Input
Nonmaskable interrupt: Requests a
nonmaskable interrupt
IRQ5 to
IRQ0
17, 16,
90 to 87
Input
Interrupt request 5 to 0: Maskable
interrupt request pins
Address bus
A23 to A0
97 to 100,
56 to 45,
43 to 36
Output
Address bus: Outputs address signals
Data bus
D15 to D0
34 to 23,
21 to 18
Input/
output
Data bus: Bidirectional data bus
Bus control
CS7 to CS0
8, 97 to 99,
88 to 91
Output
Chip select: Select signals for areas 7 to 0
AS
69
Output
Address strobe: Goes low to indicate valid
address output on the address bus
RD
70
Output
Read: Goes low to indicate reading from
the external address space
HWR
71
Output
High write: Goes low to indicate writing to
the external address space; indicates valid
data on the upper data bus (D15 to D8).
LWR
72
Output
Low write: Goes low to indicate writing to
the external address space; indicates valid
data on the lower data bus (D7 to D0).
WAIT
58
Input
Wait: Requests insertion of wait states in
bus cycles during access to the external
address space
Interrupts
Rev. 7.00 Sep 21, 2005 page 16 of 878
REJ09B0259-0700
Section 1 Overview
Type
Symbol
Pin No.
I/O
Name and Function
Refresh
controller
RFSH
87
Output
Refresh: Indicates a refresh cycle
CS3
88
Output
Row address strobe RAS:
RAS Row address
strobe signal for DRAM connected to area 3
RD
70
Output
Column address strobe CAS:
CAS Column
address strobe signal for DRAM connected
to area 3; used with 2WE DRAM.
Write enable WE:
WE Write enable signal for
DRAM connected to area 3; used with
2CAS DRAM.
HWR
71
Output
Upper write UW:
UW Write enable signal for
DRAM connected to area 3; used with 2WE
DRAM.
Upper column address strobe UCAS:
UCAS
Column address strobe signal for DRAM
connected to area 3; used with 2CAS
DRAM.
LWR
72
Output
Lower write LW:
LW Write enable signal for
DRAM connected to area 3; used with 2WE
DRAM.
Lower column address strobe LCAS:
LCAS
Column address strobe signal for DRAM
connected to area 3; used with 2CAS
DRAM.
DREQ1,
DREQ0
9, 8
Input
DMA request 1 and 0: DMAC activation
requests
TEND1,
TEND0
94, 93
Output
Transfer end 1 and 0: These signals
indicate that the DMAC has ended a data
transfer
16-bit integrated TCLKD to
timer unit (ITU) TCLKA
96 to 93
Input
Clock input D to A: External clock inputs
TIOCA4 to
TIOCA0
4, 2, 99,
97, 95
Input/
output
Input capture/output compare A4 to A0:
GRA4 to GRA0 output compare or input
capture, or PWM output
TIOCB4 to
TIOCB0
5, 3, 100,
98, 96
Input/
output
Input capture/output compare B4 to B0:
GRB4 to GRB0 output compare or input
capture
TOCXA4
6
Output
Output compare XA4: PWM output
TOCXB4
7
Output
Output compare XB4: PWM output
DMA controller
(DMAC)
Rev. 7.00 Sep 21, 2005 page 17 of 878
REJ09B0259-0700
Section 1 Overview
Type
Pin No.
I/O
Name and Function
Programmable TP15 to TP0
timing pattern
controller (TPC)
9 to 2,
100 to 93
Output
TPC output 15 to 0: Pulse output
Serial
communication
interface (SCI)
13, 12
Output
Transmit data (channels 0 and 1):
SCI data output
RxD1, RxD0 15, 14
Input
Receive data (channels 0 and 1):
SCI data input
SCK1, SCK0 17, 16
Input/
output
Serial clock (channels 0 and 1):
SCI clock input/output
AN7 to AN0
85 to 78
Input
Analog 7 to 0: Analog input pins
ADTRG
9
Input
A/D trigger: External trigger input for
starting A/D conversion
D/A converter
DA1, DA0
85, 84
Output
Analog output: Analog output from the D/A
converter
A/D and D/A
converters
AVCC
76
Input
Power supply pin for the A/D and D/A
converters. Connect to the system power
supply (VCC) when not using the A/D and
D/A converters.
AVSS
86
Input
Ground pin for the A/D and D/A converters.
Connect to system ground (VSS).
VREF
77
Input
Reference voltage input pin for the A/D and
D/A converters. Connect to the system
power supply (VCC) when not using the A/D
and D/A converters.
P17 to P10
43 to 36
Input/
output
Port 1: Eight input/output pins.
The direction of each pin can be selected in
the port 1 data direction register (P1DDR).
P27 to P20
52 to 45
Input/
output
Port 2: Eight input/output pins.
The direction of each pin can be selected in
the port 2 data direction register (P2DDR).
P37 to P30
34 to 27
Input/
output
Port 3: Eight input/output pins.
The direction of each pin can be selected in
the port 3 data direction register (P3DDR).
P47 to P40
26 to 23,
21 to 18
Input/
output
Port 4: Eight input/output pins.
The direction of each pin can be selected in
the port 4 data direction register (P4DDR).
P53 to P50
56 to 53
Input/
output
Port 5: Four input/output pins. The direction
of each pin can be selected in the port 5
data direction register (P5DDR).
A/D converter
I/O ports
Symbol
TxD1, TxD0
Rev. 7.00 Sep 21, 2005 page 18 of 878
REJ09B0259-0700
Section 1 Overview
Type
Symbol
Pin No.
I/O
Name and Function
I/O ports
P66 to P60
72 to 69,
60 to 58
Input/
output
Port 6: Seven input/output pins. The
direction of each pin can be selected in the
port 6 data direction register (P6DDR).
P77 to P70
85 to 78
Input
Port 7: Eight input pins
P84 to P80
91 to 87
Input/
output
Port 8: Five input/output pins. The direction
of each pin can be selected in the port 8
data direction register (P8DDR).
P95 to P90
17 to 12
Input/
output
Port 9: Six input/output pins. The direction
of each pin can be selected in the port 9
data direction register (P9DDR).
PA7 to PA0
100 to 93
Input/
output
Port A: Eight input/output pins. The
direction of each pin can be selected in the
port A data direction register (PADDR).
PB7 to PB0
9 to 2
Input/
output
Port B: Eight input/output pins. The
direction of each pin can be selected in the
port B data direction register (PBDDR).
Rev. 7.00 Sep 21, 2005 page 19 of 878
REJ09B0259-0700
Section 1 Overview
1.4
Differences between H8/3048F and H8/3048F-ONE
Table 1.5 shows the differences between the H8/3048F (dual power supply model) and H8/3048FONE (single power supply model).
Table 1.5
Differences between H8/3048F and H8/3048F-ONE
Item
Pin
specifications
Models with Dual Power Supply:
H8/3048F
Models with Single Power Supply:
H8/3048F-ONE*
Pin 1: VCC
Pin 1: VCL (when a model which
operates at 5 V is used)
Connected to VSS with 0.1 µF externally
applied. Pin 1 becomes VCC when a
model which operates at 3 V is used.
Pin 10: VPP/RESO
Pin 10: FWE
ROM/RAM
128-kbyte flash memory with dual
power supply, RAM: 4 kbytes
128-kbyte flash memory with single
power supply, RAM: 4 kbytes
Units of onboard writing
Writing in 1-byte units
Writing in 128-byte units
Write/erase
voltage
12 V is externally applied from VPP pin
Application of 12 V is not required.
VCC single power supply
VPP pin
functions
Multiplexes with RESO
FWE function only (no RESO function)
RESO = 12 V
FWE = 1
Boot mode
settings
Settings for
user program
mode
MD2
MD1
Mode 5 12 V
0
Mode 6 12 V
1
Mode 7 12 V
1
Cancelled by reset
MD0
1
0
1
RESO = 12 V
Mode 5
Mode 6
Mode 7
MD2
1
1
1
Cancelled by reset
MD2
MD1
0
0
0
1
0
1
Set to mode 1 in mode 5
Set to mode 2 in mode 6
Set to mode 3 in mode 7
Cancelled by reset
Mode 5
Mode 6
Mode 7
MD0
1
0
1
FWE = 1
MD1
0
1
MD0
1
0
1
1
MD2
MD1
1
0
1
1
1
1
Cancelled by reset
Mode 5
Mode 6
Mode 7
MD0
1
0
1
Prewrite
processing
Necessary before erasing
Not necessary
Erasing blocks
More than one block can be erased at
the same time (verifies in block units
and erases only the unerased blocks)
Erases in one block units. More than
one block cannot be erased at the same
time (the erasing flow is different)
Rev. 7.00 Sep 21, 2005 page 20 of 878
REJ09B0259-0700
Section 1 Overview
Item
Models with Dual Power Supply:
H8/3048F
Models with Single Power Supply:
H8/3048F-ONE*
Write
processing
Before writing, sets the block with the
address to be written to EBR1/EBR2
No setting
FLMCR
FLMCR (H'FF40)
FLMCR1 (H'FF40)
VPP VPPE
—
—
EV
PV
E
P
FWE SWE ESU PSU
EV
PV
E
P
—
—
—
—
FLMCR2 (H'FF41)
FLER
EBR
LB6
LB5
—
—
EBR (H'FF42)
EBR1 (H'FF42)
LB7
—
LB4
LB3
LB2
LB1
LB0
EBR2 (H'FF43)
SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0
EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0
Only one block can be selected(setting
for erasing)
More than one block can be selected
(setting for writing/erasing)
RAMCR
RAMCR (H'FF48)
FLER
Division of
flash memory
block
—
—
RAMCR (H'FF47)
— RAMS RAM2 RAM1 RAM0
Division in 16 blocks
16 kbytes × 7: LB0 to LB6
12 kbytes × 1: LB7
512 kbytes × 8: SB0 to SB7
—
—
— RAMS RAM2 RAM1 —
Division in 8 blocks
1 kbyte × 4: EB0 to EB3
28 kbytes × 1: EB4
32 kbytes × 3: EB5 to EB7
Flash memory
Flash memory
LB0 (16 kbytes)
LB1 (16 kbytes)
LB2 (16 kbytes)
LB3 (16 kbytes)
LB4 (16 kbytes)
LB5 (16 kbytes)
LB6 (16 kbytes)
LB7 (12 kbytes)
SB0 (512 bytes)
SB1 (512 bytes)
SB2 (512 bytes)
SB3 (512 bytes)
SB4 (512 bytes)
—
H'00000
H'00000
EB0 (1 kbyte)
EB1 (1 kbyte)
EB2 (1 kbyte)
EB3 (1 kbyte)
EB4 (28 kbytes)
EB5 (32 kbytes)
EB6 (32 kbytes)
EB7 (32 kbytes)
H'1FFFF
SB5 (512 bytes)
SB6 (512 bytes)
SB7 (512 bytes)
H'1FFFF
Rev. 7.00 Sep 21, 2005 page 21 of 878
REJ09B0259-0700
Section 1 Overview
Item
Models with Dual Power Supply:
H8/3048F
Division of RAM
emulation block
On-chip RAM
Flash memory
H'EF10
Models with Single Power Supply:
H8/3048F-ONE*
On-chip RAM
Flash memory
H'00000
H'F000
H'F1FF
H'EF10
H'00000
H'00400
H'F000
H'00800
H'00C00
H'1EFFF
H'1F000
H'F3FF
H'01000
H'1F200
H'1F400
H'FF0F
H'1F600
H'FF0F
H'1F800
H'1FA00
H'1FC00
H'1FE00
H'1FFFF
H'1FFFF
Reset during
operation
The RES signal must be kept low during The RES signal must be kept low during
at least 6 system clock (6φ) cycles.
at least 20 system clock (20φ) cycles.
(RES pulse width tRESW = min. 6.0 tcyc)
(RES pulse width tRESW = min. 20 tcyc)
A/D ADCR
ADCR (H'FFE9)
ADCR (H'FFE9)
Initial value: H'7F
Initial value: H'7E
Only bit 7 can be read or written.
Only bit 7 can be read or written.
Other bits are reserved and always read Bit 0 is reserved and must not be set to
1.
as 1; writing to these bits is invalid.
Other bits are reserved and always read
as 1; writing to these bits is invalid.
WDT RSTCSR
RSTCSR (H'FFAB)
RSTCSR (H'FFAB)
Initial value: H'3F
Initial value: H'3F
Only bits 7 and 6 can be read or written. Only bit 7 can be read or written.
Other bits are reserved and always read Bit 6 is reserved and must not be set to
1.
as 1; writing to these bits is invalid.
Other bits are reserved and always read
as 1; writing to these bits is invalid.
Rev. 7.00 Sep 21, 2005 page 22 of 878
REJ09B0259-0700
Section 1 Overview
Item
Models with Dual Power Supply:
H8/3048F
Clock oscillator Setting of standby timer select
settling time
bits 2 to 0
(SYSCR STS2–
STS2 STS1 STS0
Description
STS0)
0
1
0
0
8,192 states
1
1
0
16,384 states
32,768 states
1
65,536 states
0
0
131,072 states
1
1
—
1,024 states
Illegal setting
Models with Single Power Supply:
H8/3048F-ONE*
Setting of standby timer select
bits 2 to 0
STS2
STS1
STS0
0
0
0
8,192 states
1
1
0
16,384 states
32,768 states
1
65,536 states
0
131,072 states
1
262,144 states
0
1
1,024 states
Illegal setting
1
0
1
Description
Details on flash Refer to section 19, Flash Memory
memory
(H8/3048F, Dual Power Supply).
Refer to section 18, Flash Memory
(H8/3048F-ONE, Single Power Supply)
Electrical
characteristics
(clock rate)
Clock rate: 1 to 16 MHz
Clock rate: 2 to 25 MHz
Refer to section 22, Table 22.1
Electrical Characteristics of H8/3048
Group Products.
Refer to section 21, Table 21.1
Electrical Characteristics of H8/3048
Group Products.
List of registers Refer to appendix B, Table B.1
Comparison of H8/3048 Group Internal
I/O Register Specification
On-chip
emulator
Refer to appendix B, Table B.1
Comparison of H8/3048 Group Internal
I/O Register Specification
Refer to appendix B.1, Addresses
(For H8/3048F, H8/3048ZTAT,
H8/3048 mask-ROM, H8/3047 maskROM, H8/3045 mask-ROM, and
H8/3044 mask-ROM Versions)
Refer to appendix B.1, Addresses
(For H8/3048F-ONE)
—
On-chip emulator (E10T)
Note: * Refer to the “H8/3048F-ONE, H8/3048F-ZTAT™ Hardware Manual” for information about
H8/3048F-ONE.
Rev. 7.00 Sep 21, 2005 page 23 of 878
REJ09B0259-0700
Section 1 Overview
Rev. 7.00 Sep 21, 2005 page 24 of 878
REJ09B0259-0700
Section 2 CPU
Section 2 CPU
2.1
Overview
The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general
registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.
2.1.1
Features
The H8/300H CPU has the following features.
Upward compatibility with H8/300 CPU
Can execute H8/300 Series object programs
General-register architecture
Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers)
Sixty-two basic instructions
8/16/32-bit data transfer and arithmetic and logic instructions
Multiply and divide instructions
Powerful bit-manipulation instructions
Eight addressing modes
Register direct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:16, ERn) or @(d:24, ERn)]
Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
Absolute address [@aa:8, @aa:16, or @aa:24]
Immediate [#xx:8, #xx:16, or #xx:32]
Program-counter relative [@(d:8, PC) or @(d:16, PC)]
Memory indirect [@@aa:8]
16-Mbyte linear address space
High-speed operation
All frequently-used instructions execute in two to four states
Maximum clock frequency:
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Section 2 CPU
18 MHz (H8/3048ZTAT, H8/3048 mask ROM, H8/3047 mask ROM, H8/3045 mask
ROM, H8/3044 mask ROM)
16 MHz (H8/3048F)
8/16/32-bit register-register add/subtract: 111 ns @ 18 MHz/125 ns @ 16 MHz
8 × 8-bit register-register multiply:
778 ns @ 18 MHz/875 ns @ 16 MHz
16 ÷ 8-bit register-register divide:
778 ns @ 18 MHz/875 ns @ 16 MHz
16 × 16-bit register-register multiply:
1,221 ns @ 18 MHz/1,375 ns @ 16 MHz
32 ÷ 16-bit register-register divide:
1,221 ns @ 18 MHz/1,375 ns @ 16 MHz
Two CPU operating modes
Normal mode (not available in the H8/3048 Group)
Advanced mode
Low-power mode
Transition to power-down state by SLEEP instruction
2.1.2
Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8/300H has the following enhancements.
• More general registers
Eight 16-bit registers have been added.
• Expanded address space
Advanced mode supports a maximum 16-Mbyte address space.
Normal mode supports the same 64-kbyte address space as the H8/300 CPU.
(Normal mode is not available in the H8/3048 Group.)
• Enhanced addressing
The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.
• Enhanced instructions
Data transfer, arithmetic, and logic instructions can operate on 32-bit data.
Signed multiply/divide instructions and other instructions have been added.
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2.2
CPU Operating Modes
The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a
maximum 64-kbyte address space. Advanced mode supports up to 16 Mbytes. See figure 2.1.
The H8/3048 Group can be used only in advanced mode. (Information from this point on will
apply to advanced mode unless otherwise stated.)
Normal mode
Maximum 64 kbytes, program
and data areas combined
Advanced mode
Maximum 16 Mbytes, program
and data areas combined
CPU operating modes
Figure 2.1 CPU Operating Modes
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Section 2 CPU
2.3
Address Space
The maximum address space of the H8/300H CPU is 16 Mbytes. The H8/3048 Group has various
operating modes (MCU modes), some providing a 1-Mbyte address space, the others supporting
the full 16 Mbytes.
Figure 2.2 shows the address ranges of the H8/3048 Group. For further details see section 3.6,
Memory Map in Each Operating Mode.
The 1-Mbyte operating modes use 20-bit addressing. The upper 4 bits of effective addresses are
ignored.
H'00000
H'000000
H'FFFFF
H'FFFFFF
a. 1-Mbyte modes
b. 16-Mbyte modes
Figure 2.2 Memory Map
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2.4
Register Configuration
2.4.1
Overview
The H8/300H CPU has the internal registers shown in figure 2.3. There are two types of registers:
general registers and control registers.
Figure 2.3 CPU Internal Registers
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2.4.2
General Registers
The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally
alike and can be used without distinction between data registers and address registers. When a
general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register.
When the general registers are used as 32-bit registers or as address registers, they are designated
by the letters ER (ER0 to ER7).
The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.
The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and
RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit
registers.
Figure 2.4 illustrates the usage of the general registers. The usage of each register can be selected
independently.
• Address registers
• 32-bit registers
• 16-bit registers
• 8-bit registers
E registers
(extended registers)
E0 to E7
RH registers
R0H to R7H
ER registers
ER0 to ER7
R registers
R0 to R7
RL registers
R0L to R7L
Figure 2.4 Usage of General Registers
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Section 2 CPU
General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.5 shows the
stack.
Free area
SP (ER7)
Stack area
Figure 2.5 Stack
2.4.3
Control Registers
The control registers are the 24-bit program counter (PC) and the 8-bit condition code register
(CCR).
Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU
will execute. The length of all CPU instructions is 2 bytes (one word) or a multiple of 2 bytes, so
the least significant PC bit is ignored. When an instruction is fetched, the least significant PC bit is
regarded as 0.
Condition Code Register (CCR): This 8-bit register contains internal CPU status information,
including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and
carry (C) flags.
• Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. NMI is
accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling
sequence.
• Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the
LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt
mask bit. For details see section 5, Interrupt Controller.
• Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or
NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and
cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is
executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise.
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When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if
there is a carry or borrow at bit 27, and cleared to 0 otherwise.
• Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC,
and XORC instructions.
• Bit 3—Negative Flag (N): Indicates the most significant bit (sign bit) of data.
• Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.
• Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at
other times.
• Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:
Add instructions, to indicate a carry
Subtract instructions, to indicate a borrow
Shift and rotate instructions, to store the value shifted out of the end bit
The carry flag is also used as a bit accumulator by bit manipulation instructions.
Some instructions leave flag bits unchanged. Operations can be performed on CCR by the LDC,
STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used by conditional
branch (Bcc) instructions.
For the action of each instruction on the flag bits, see appendix A.1, Instruction List. For the I and
UI bits, see section 5, Interrupt Controller.
2.4.4
Initial CPU Register Values
In reset exception handling, PC is initialized to a value loaded from the vector table, and the I bit
in CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular,
the stack pointer (ER7) is not initialized. The stack pointer must therefore be initialized by an
MOV.L instruction executed immediately after a reset.
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Section 2 CPU
2.5
Data Formats
The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1,
2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as
two digits of 4-bit BCD data.
2.5.1
General Register Data Formats
Figures 2.6 and 2.7 show the data formats in general registers.
Data Type
General
Register
1-bit data
RnH
Data Format
7
0
7 6 5 4 3 2 1 0
Don’t care
7
1-bit data
7
4-bit BCD data
RnH
7 6 5 4 3 2 1 0
Don’t care
RnL
4 3
0
Don’t care
Upper digit Lower digit
7
4-bit BCD data
Byte data
Byte data
Don’t care
RnL
4 3
0
Upper digit Lower digit
7
0
MSB
LSB
Don’t care
RnH
RnL
0
7
0
MSB
LSB
Don’t care
Figure 2.6 General Register Data Formats (1)
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Data Type
General
Register
Word data
Rn
Word data
Data Format
15
0
MSB
LSB
15
0
MSB
LSB
En
31
16 15
0
Longword data ERn
MSB
Legend
ERn: General register
En:
General register E
Rn:
General register R
RnH: General register RH
RnL: General register RL
MSB: Most significant bit
LSB: Least significant bit
Figure 2.7 General Register Data Formats (2)
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LSB
Section 2 CPU
2.5.2
Memory Data Formats
Figure 2.8 shows the data formats on memory. The H8/300H CPU can access word data and
longword data on memory, but word or longword data must begin at an even address. If an attempt
is made to access word or longword data at an odd address, no address error occurs but the least
significant bit of the address is regarded as 0, so the access starts at the preceding address. This
also applies to instruction fetches.
Data Type
Address
Data Format
7
1-bit data
Address L
7
Byte data
Address L
MSB
Word data
Address 2M
MSB
0
6
5
4
Address 2N
2
1
0
LSB
Address 2M + 1
Longword data
3
LSB
MSB
Address 2N + 1
Address 2N + 2
Address 2N + 3
LSB
Figure 2.8 Memory Data Formats
When ER7 (SP) is used as an address register to access the stack, the operand size should be word
size or longword size.
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Section 2 CPU
2.6
Instruction Set
2.6.1
Instruction Set Overview
The H8/300H CPU has 62 types of instructions, which are classified in table 2.1.
Table 2.1
Instruction Classification
Function
Instruction
Types
Data transfer
1
1
2
2
MOV, PUSH* , POP* , MOVTPE* , MOVFPE*
3
Arithmetic operatiozns ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA,
DAS, MULXU, MULXS, DIVXU, DIVXS, CMP, NEG, EXTS,
EXTU
18
Logic operations
AND, OR, XOR, NOT
4
Shift operations
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR
8
Bit manipulation
BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR,
BXOR, BIXOR, BLD, BILD, BST, BIST
14
Branch
Bcc* , JMP, BSR, JSR, RTS
3
5
System control
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP
9
Block data transfer
EEPMOV
1
Total 62 types
Notes: 1. POP.W Rn is identical to MOV.W @SP+, Rn.
PUSH.W Rn is identical to MOV.W Rn, @–SP.
POP.L ERn is identical to MOV.L @SP+, Rn.
PUSH.L ERn is identical to MOV.L Rn, @–SP.
2. Not available in the H8/3048 Group.
3. Bcc is a generic branching instruction.
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2.6.2
Instructions and Addressing Modes
Table 2.2 indicates the instructions available in the H8/300H CPU.
Table 2.2
Instructions and Addressing Modes
@(d:24,ERn)
@ERn+/@–ERn
@aa:8
@aa:16
@aa:24
BWL
BWL
BWL
BWL
B
BWL
BWL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
WL
MOVFPE*,
MOVTPE*
—
—
—
—
—
—
—
B
—
—
—
—
—
Arithmetic
operations
ADD, CMP
BWL
BWL
—
—
—
—
—
—
—
—
—
—
—
WL
BWL
—
—
—
—
—
—
—
—
—
—
—
ADDX, SUBX
B
B
—
—
—
—
—
—
—
—
—
—
—
ADDS, SUBS
—
L
—
—
—
—
—
—
—
—
—
—
—
INC, DEC
—
BWL
—
—
—
—
—
—
—
—
—
—
—
DAA, DAS
—
B
—
—
—
—
—
—
—
—
—
—
—
MULXU, MULXS,
DIVXU, DIVXS
—
BW
—
—
—
—
—
—
—
—
—
—
—
NEG
—
BWL
—
—
—
—
—
—
—
—
—
—
—
EXTU, EXTS
—
WL
—
—
—
—
—
—
—
—
—
—
Logic
operations
—
BWL
BWL
—
—
—
—
—
—
—
—
—
—
—
SUB
AND, OR, XOR
NOT
Shift instructions
—
BWL
—
—
—
—
—
—
—
—
—
—
—
—
BWL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bit manipulation
—
B
B
—
—
—
B
—
—
Branch
Bcc, BSR
—
—
—
—
—
—
—
—
—
JMP, JSR
—
—
—
—
—
—
—
RTS
—
—
—
—
—
—
—
—
TRAPA
—
—
—
—
—
—
—
RTE
—
—
—
—
—
—
—
SLEEP
—
—
—
—
—
—
LDC
B
B
W
W
W
STC
—
B
W
W
W
ANDC, ORC,
XORC
B
—
—
—
—
System
control
NOP
Block data transfer
—
@(d:16,ERn)
BWL
—
MOV
@@aa:8
@ERn
Data
transfer
Instruction
@(d:16,PC)
Rn
BWL
POP, PUSH
Function
@(d:8,PC)
#xx
Addressing Modes
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W
—
W
W
—
—
—
W
—
W
W
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BW
Legend
B:
Byte
W:
Word
L:
Longword
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Section 2 CPU
Note: * Not availabe in the H8/3048 Group.
2.6.3
Tables of Instructions Classified by Function
Tables 2.3 to 2.10 summarize the instructions in each functional category. The operation notation
used in these tables is defined next.
Operation Notation
Rd
General register (destination)*
Rs
General register (source)*
Rn
General register*
ERn
General register (32-bit register or address register)
(EAd)
Destination operand
(EAs)
Source operand
CCR
Condition code register
N
N (negative) flag of CCR
Z
Z (zero) flag of CCR
V
V (overflow) flag of CCR
C
C (carry) flag of CCR
PC
Program counter
SP
Stack pointer
#IMM
Immediate data
disp
Displacement
+
Addition
–
Subtraction
×
Multiplication
÷
Division
∧
AND logical
∨
OR logical
⊕
Exclusive OR logical
→
Move
¬
NOT (logical complement)
:3/:8/:16/:24
3-, 8-, 16-, or 24-bit length
Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to
R7, E0 to E7), and 32-bit data or address registers (ER0 to ER7).
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Section 2 CPU
Table 2.3
Data Transfer Instructions
Instruction
Size*
Function
MOV
B/W/L
(EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general
register and memory, or moves immediate data to a general register.
MOVFPE
B
(EAs) → Rd
Cannot be used in the H8/3048 Group.
MOVTPE
B
Rs → (EAs)
Cannot be used in the H8/3048 Group.
POP
W/L
@SP+ → Rn
Pops a general register from the stack. POP.W Rn is identical to
MOV.W @SP+, Rn. Similarly, POP.L ERn is identical to MOV.L
@SP+, ERn.
PUSH
W/L
Rn → @–SP
Pushes a general register onto the stack. PUSH.W Rn is identical to
MOV.W Rn, @–SP. Similarly, PUSH.L ERn is identical to MOV.L
ERn, @–SP.
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
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Section 2 CPU
Table 2.4
Arithmetic Operation Instructions
Instruction
Size*
Function
ADD, SUB
B/W/L
Rd ± Rs → Rd, Rd ± #IMM → Rd
Performs addition or subtraction on data in two general registers, or
on immediate data and data in a general register. (Immediate byte
data cannot be subtracted from data in a general register. Use the
SUBX or ADD instruction.)
ADDX, SUBX
B
Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry or borrow on data in two
general registers, or on immediate data and data in a general
register.
INC, DEC
B/W/L
Rd ± 1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2. (Byte
operands can be incremented or decremented by 1 only.)
ADDS, SUBS
L
Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit
register.
DAA, DAS
B
Rd decimal adjust → Rd
Decimal-adjusts an addition or subtraction result in a general register
by referring to CCR to produce 4-bit BCD data.
MULXU
B/W
Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers:
either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
MULXS
B/W
Rd × Rs → Rd
Performs signed multiplication on data in two general registers:
either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
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Section 2 CPU
Instruction
Size*
Function
DIVXU
B/W
Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers: either
16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16
bits → 16-bit quotient and 16-bit remainder.
DIVXS
B/W
Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either 16
bits ÷ 8 bits → 8-bit quotient and 8-bit remainder, or 32 bits ÷ 16 bits
→ 16-bit quotient and 16-bit remainder.
CMP
B/W/L
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general
register or with immediate data, and sets CCR according to the
result.
NEG
B/W/L
0 – Rd → Rd
Takes the two’s complement (arithmetic complement) of data in a
general register.
EXTS
W/L
Rd (sign extension) → Rd
Extends byte data in the lower 8 bits of a 16-bit register to word data,
or extends word data in the lower 16 bits of a 32-bit register to
longword data, by extending the sign bit.
EXTU
W/L
Rd (zero extension) → Rd
Extends byte data in the lower 8 bits of a 16-bit register to word data,
or extends word data in the lower 16 bits of a 32-bit register to
longword data, by padding with zeros.
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
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Section 2 CPU
Table 2.5
Logic Operation Instructions
Instruction
Size*
Function
AND
B/W/L
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR
B/W/L
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR
B/W/L
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
NOT
B/W/L
¬ Rd → Rd
Takes the one’s complement of general register contents.
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
Table 2.6
Shift Instructions
Instruction
Size*
Function
SHAL,
SHAR
B/W/L
Rd (shift) → Rd
SHLL,
SHLR
B/W/L
ROTL,
ROTR
B/W/L
ROTXL,
ROTXR
B/W/L
Performs an arithmetic shift on general register contents.
Rd (shift) → Rd
Performs a logical shift on general register contents.
Rd (rotate) → Rd
Rotates general register contents.
Rd (rotate) → Rd
Rotates general register contents through the carry bit.
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
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Section 2 CPU
Table 2.7
Bit Manipulation Instructions
Instruction
Size*
Function
BSET
B
1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory operand to 1.
The bit number is specified by 3-bit immediate data or the lower 3
bits of a general register.
BCLR
B
0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory operand to 0.
The bit number is specified by 3-bit immediate data or the lower 3
bits of a general register.
BNOT
B
¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory operand. The
bit number is specified by 3-bit immediate data or the lower 3 bits of
a general register.
BTST
B
¬ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory operand and
sets or clears the Z flag accordingly. The bit number is specified by
3-bit immediate data or the lower 3 bits of a general register.
BAND
B
C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general register or
memory operand and stores the result in the carry flag.
BIAND
B
C ∧ [¬ (<bit-No.> of <EAd>)] → C
ANDs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
Note: * Size refers to the operand size.
B: Byte
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Section 2 CPU
Instruction
Size*
Function
BOR
B
C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general register or
memory operand and stores the result in the carry flag.
BIOR
B
C ∨ [¬ (<bit-No.> of <EAd>)] → C
ORs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BXOR
B
C ⊕ (<bit-No.> of <EAd>) → C
Exclusive-ORs the carry flag with a specified bit in a general register
or memory operand and stores the result in the carry flag.
BIXOR
B
C ⊕ [¬ (<bit-No.> of <EAd>)] → C
Exclusive-ORs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the result in the carry
flag.
The bit number is specified by 3-bit immediate data.
BLD
B
(<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory operand to
the carry flag.
BILD
B
¬ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general register or
memory operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BST
B
C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general register
or memory operand.
BIST
B
C → ¬ (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in a
general register or memory operand.
The bit number is specified by 3-bit immediate data.
Note: * Size refers to the operand size.
B: Byte
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Table 2.8
Branching Instructions
Instruction
Size
Function
Bcc
—
Branches to a specified address if a specified condition is true. The
branching conditions are listed below.
Mnemonic
Description
Condition
BRA (BT)
Always (true)
Always
BRN (BF)
Never (false)
Never
BHI
High
C∨Z=0
BLS
Low or same
C∨Z=1
Bcc (BHS)
Carry clear (high or same)
C=0
BCS (BLO)
Carry set (low)
C=1
BNE
Not equal
Z=0
BEQ
Equal
Z=1
BVC
Overflow clear
V=0
BVS
Overflow set
V=1
BPL
Plus
N=0
BMI
Minus
N=1
BGE
Greater or equal
N⊕V=0
BLT
Less than
N⊕V=1
BGT
Greater than
Z ∨ (N ⊕ V) = 0
BLE
Less or equal
Z ∨ (N ⊕ V) = 1
JMP
—
Branches unconditionally to a specified address
BSR
—
Branches to a subroutine at a specified address
JSR
—
Branches to a subroutine at a specified address
RTS
—
Returns from a subroutine
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Section 2 CPU
Table 2.9
System Control Instructions
Instruction
Size*
Function
TRAPA
—
Starts trap-instruction exception handling
RTE
—
Returns from an exception-handling routine
SLEEP
—
Causes a transition to the power-down state
LDC
B/W
(EAs) → CCR
Moves the source operand contents to the condition code register.
The condition code register size is one byte, but in transfer from
memory, data is read by word access.
STC
B/W
CCR → (EAd)
Transfers the CCR contents to a destination location. The condition
code register size is one byte, but in transfer to memory, data is
written by word access.
ANDC
B
ORC
B
CCR ∧ #IMM → CCR
Logically ANDs the condition code register with immediate data.
CCR ∨ #IMM → CCR
Logically ORs the condition code register with immediate data.
XORC
B
CCR ⊕ #IMM → CCR
Logically exclusive-ORs the condition code register with immediate
data.
NOP
—
PC + 2 → PC
Only increments the program counter.
Note: * Size refers to the operand size.
B: Byte
W: Word
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Section 2 CPU
Table 2.10 Block Transfer Instruction
Instruction
Size
Function
EEPMOV.B
—
if R4L ≠ 0 then
repeat
until
@ER5+ → @ER6+, R4L – 1 → R4L
R4L = 0
else next;
EEPMOV.W
—
if R4 ≠ 0 then
repeat
until
@ER5+ → @ER6+, R4 – 1 → R4
R4 = 0
else next;
Transfers a data block according to parameters set in general
registers R4L or R4, ER5, and ER6.
R4L or R4: Size of block (bytes)
ER5:
Starting source address
ER6:
Starting destination address
Execution of the next instruction begins as soon as the transfer is
completed.
2.6.4
Basic Instruction Formats
The H8/300H instructions consist of 2-byte (1-word) units. An instruction consists of an operation
field (OP field), a register field (r field), an effective address extension (EA field), and a condition
field (cc).
Operation Field: Indicates the function of the instruction, the addressing mode, and the operation
to be carried out on the operand. The operation field always includes the first 4 bits of the
instruction. Some instructions have two operation fields.
Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers
by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field.
Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute
address, or a displacement. A 24-bit address or displacement is treated as 32-bit data in which the
first 8 bits are 0 (H'00).
Condition Field: Specifies the branching condition of Bcc instructions.
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Section 2 CPU
Figure 2.9 shows examples of instruction formats.
Operation field only
op
NOP, RTS, etc.
Operation field and register fields
op
rn
rm
ADD.B Rn, Rm, etc.
Operation field, register fields, and effective address extension
op
rn
rm
MOV.B @(d:16, Rn), Rm
EA (disp)
Operation field, effective address extension, and condition field
op
cc
EA (disp)
BRA d:8
Figure 2.9 Instruction Formats
2.6.5
Notes on Use of Bit Manipulation Instructions
The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, modify a bit in the
byte, then write the byte back. Care is required when these instructions are used to access registers
with write-only bits, or to access ports.
The BCLR instruction can be used to clear flags in the internal I/O registers. In an interrupthandling routine, for example, if it is known that the flag is set to 1, it is not necessary to read the
flag ahead of time.
Step
Description
1
Read
Read data (byte unit) at the specified address
2
Bit manipulation
Modify the specified bit in the read data
3
Write
Write the modified data (byte unit) to the specified address
In the following example, a BCLR instruction is executed on the data direction register (DDR) of
port 4.
P47 and P46 are set as input pins, and are inputting low-level and high-level signals, respectively.
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Section 2 CPU
P45 to P40 are set as output pins, and are in the low-level output state.
In this example, the BCLR instruction is used to make P40 an input port.
Before Execution of BCLR Instruction
P47
P46
P45
P44
P43
P42
P41
P40
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
DDR
0
0
1
1
1
1
1
1
DR
1
0
0
0
0
0
0
0
Execution of BCLR Instruction
BCLR
; Execute BCLR instruction on DDR
#0, @P4DDR
After Execution of BCLR Instruction
Input/output
P47
P46
P45
P44
P43
P42
P41
P40
Output
Output
Output
Output
Output
Output
Output
Input
DDR
1
1
1
1
1
1
1
0
DR
1
0
0
0
0
0
0
0
Explanation of BCLR Instruction
To execute the BCLR instruction, the CPU begins by reading P4DDR. Since P4DDR is a writeonly register, it is read as H'FF, even though its true value is H'3F.
Next the CPU clears bit 0 of the read data, changing the value to H'FE.
Finally, the CPU writes this value (H'FE) back to DDR to complete the BCLR instruction.
As a result, P40DDR is cleared to 0, making P40 an input pin. In addition, P47DDR and P46DDR
are set to 1, making P47 and P46 output pins.
The BCLR instruction can be used to clear flags in the internal I/O registers to 0. In an interrupthandling routine, for example, if it is known that the flag is set to 1, it is not necessary to read the
flag ahead of time.
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Section 2 CPU
2.7
Addressing Modes and Effective Address Calculation
2.7.1
Addressing Modes
The H8/300H CPU supports the eight addressing modes listed in table 2.11. Each instruction uses
a subset of these addressing modes. Arithmetic and logic instructions can use the register direct
and immediate modes. Data transfer instructions can use all addressing modes except programcounter relative and memory indirect. Bit manipulation instructions use register direct, register
indirect, or absolute (@aa:8) addressing mode to specify an operand, and register direct (BSET,
BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit
number in the operand.
Table 2.11 Addressing Modes
No.
Addressing Mode
Symbol
1
Register direct
Rn
2
Register indirect
@ERn
3
Register indirect with displacement
@(d:16, ERn)/@(d:24, ERn)
4
Register indirect with post-increment
@ERn+
Register indirect with pre-decrement
@–ERn
5
Absolute address
@aa:8/@aa:16/@aa:24
6
Immediate
#xx:8/#xx:16/#xx:32
7
Program-counter relative
@(d:8, PC)/@(d:16, PC)
8
Memory indirect
@@aa:8
1 Register Direct—Rn: The register field of the instruction code specifies an 8-, 16-, or 32-bit
register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers.
R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit
registers.
2 Register Indirect—@ERn: The register field of the instruction code specifies an address
register (ERn), the lower 24 bits of which contain the address of the operand.
3 Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn): A 16-bit or 24-bit
displacement contained in the instruction code is added to the contents of an address register
(ERn) specified by the register field of the instruction, and the lower 24 bits of the sum specify the
address of a memory operand. A 16-bit displacement is sign-extended when added.
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4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn:
• Register indirect with post-increment—@ERn+
The register field of the instruction code specifies an address register (ERn) the lower 24 bits
of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is
added to the address register contents (32 bits) and the sum is stored in the address register.
The value added is 1 for byte access, 2 for word access, or 4 for longword access. For word or
longword access, the register value should be even.
• Register indirect with pre-decrement—@–ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field
in the instruction code, and the lower 24 bits of the result become the address of a memory
operand. The result is also stored in the address register. The value subtracted is 1 for byte
access, 2 for word access, or 4 for longword access. For word or longword access, the resulting
register value should be even.
5 Absolute Address—@aa:8, @aa:16, or @aa:24: The instruction code contains the absolute
address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long
(@aa:16), or 24 bits long (@aa:24). For an 8-bit absolute address, the upper 16 bits are all
assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 8 bits are a sign extension. A
24-bit absolute address can access the entire address space. Table 2.12 indicates the accessible
address ranges.
Table 2.12 Absolute Address Access Ranges
Absolute Address
1-Mbyte Modes
16-Mbyte Modes
8 bits (@aa:8)
H'FFF00 to H'FFFFF
(1048320 to 1048575)
H'FFFF00 to H'FFFFFF
(16776960 to 16777215)
16 bits (@aa:16)
H'00000 to H'07FFF,
H'F8000 to H'FFFFF
(0 to 32767, 1015808 to 1048575)
H'000000 to H'007FFF,
H'FF8000 to H'FFFFFF
(0 to 32767, 16744448 to 16777215)
24 bits (@aa:24)
H'00000 to H'FFFFF
(0 to 1048575)
H'000000 to H'FFFFFF
(0 to 16777215)
6 Immediate—#xx:8, #xx:16, or #xx:32: The instruction code contains 8-bit (#xx:8), 16-bit
(#xx:16), or 32-bit (#xx:32) immediate data as an operand.
The instruction codes of the ADDS, SUBS, INC, and DEC instructions contain immediate data
implicitly. The instruction codes of some bit manipulation instructions contain 3-bit immediate
data specifying a bit number. The TRAPA instruction code contains 2-bit immediate data
specifying a vector address.
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7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and
BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is signextended to 24 bits and added to the 24-bit PC contents to generate a 24-bit branch address. The
PC value to which the displacement is added is the address of the first byte of the next instruction,
so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768
bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an
even number.
8 Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The
instruction code contains an 8-bit absolute address specifying a memory operand. This memory
operand contains a branch address. The memory operand is accessed by longword access. The first
byte of the memory operand is ignored, generating a 24-bit branch address. See figure 2.10. The
upper bits of the 8-bit absolute address are assumed to be 0 (H'0000), so the address range is 0 to
255 (H'000000 to H'0000FF). Note that the first part of this range is also the exception vector area.
For further details see section 5, Interrupt Controller.
Specified by @aa:8
Reserved
Branch address
Figure 2.10 Memory-Indirect Branch Address Specification
When a word-size or longword-size memory operand is specified, or when a branch address is
specified, if the specified memory address is odd, the least significant bit is regarded as 0. The
accessed data or instruction code therefore begins at the preceding address. See section 2.5.2,
Memory Data Formats.
2.7.2
Effective Address Calculation
Table 2.13 explains how an effective address is calculated in each addressing mode. In the
1-Mbyte operating modes the upper 4 bits of the calculated address are ignored in order to
generate a 20-bit effective address.
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Table 2.13 Effective Address Calculation
No.
Addressing Mode and
Instruction Format
1
Register direct (Rn)
op
2
Effective Address
Calculation
Effective Address
Operand is general
register contents
rm rn
Register indirect (@ERn)
31
0
23
0
General register contents
op
3
r
Register indirect with displacement
@(d:16, ERn)/@(d:24, ERn)
31
0
General register contents
op
r
0
23
0
23
0
disp
Sign extension
4.
23
disp
Register indirect with post-increment
or pre-decrement
Register indirect with post-increment
@ERn+
31
0
General register contents
op
r
1, 2, or 4
Register indirect with pre-decrement
@–ERn
31
0
General register contents
op
r
1, 2, or 4
1 for a byte operand, 2 for a word
operand, 4 for a longword operand
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Section 2 CPU
No.
5
Addressing Mode and
Instruction Format
Effective Address
Calculation
Effective Address
Absolute address
@aa:8
@aa:8
op
23
87
0
H'FFFF
abs
@aa:16
op
abs
23 16 15
Sign
extension
0
23
0
@aa:24
op
abs
6
Immediate
#xx:8, #xx:16, or #xx:32
op
7
Operand is immediate
data
IMM
Program-counter relative
@(d:8, PC) or @(d:16, PC)
0
23
PC contents
Sign
extension
op
disp
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disp
23
0
Section 2 CPU
No.
Addressing Mode and
Instruction Format
8
Memory indirect @@aa:8
•
Effective Address
Calculation
Effective Address
Normal mode
op
abs
23
87
0
abs
H'0000
0
15
Memory
contents
•
23
16 15
0
H'00
Advanced mode
op
abs
23
87
H'0000
0
abs
0
31
23
0
Memory contents
Legend:
r, rm, rn: Register field
op:
Operation field
disp:
Displacement
IMM:
Immediate data
abs:
Absolute address
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Section 2 CPU
2.8
Processing States
2.8.1
Overview
The H8/300H CPU has five processing states: the program execution state, exception-handling
state, power-down state, reset state, and bus-released state. The power-down state includes sleep
mode, software standby mode, and hardware standby mode. Figure 2.11 classifies the processing
states. Figure 2.13 indicates the state transitions.
Processing states
Program execution state
The CPU executes program instructions in sequence
Exception-handling state
A transient state in which the CPU executes a hardware sequence
(saving PC and CCR, fetching a vector, etc.) in response to a reset,
interrupt, or other exception
Bus-released state
The external bus has been released in response to a bus request
signal from a bus master other than the CPU
Reset state
The CPU and all on-chip supporting modules are initialized and halted
Power-down state
Sleep mode
The CPU is halted to conserve power
Software standby mode
Hardware standby mode
Figure 2.11 Processing States
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2.8.2
Program Execution State
In this state the CPU executes program instructions in normal sequence.
2.8.3
Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal
program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from
the exception vector table and branches to that address. In interrupt and trap exception handling
the CPU references the stack pointer (ER7) and saves the program counter and condition code
register.
Types of Exception Handling and Their Priority: Exception handling is performed for resets,
interrupts, and trap instructions. Table 2.14 indicates the types of exception handling and their
priority. Trap instruction exceptions are accepted at all times in the program execution state.
Table 2.14 Exception Handling Types and Priority
Priority
Type of
Exception
Detection Timing
Start of Exception Handling
High
Reset
Synchronized with clock
Exception handling starts immediately
when RES changes from low to high
Interrupt
End of instruction
execution or end of
exception handling*
When an interrupt is requested,
exception handling starts at the end of
the current instruction or current
exception-handling sequence
Trap instruction
When TRAPA instruction
is executed
Exception handling starts when a trap
(TRAPA) instruction is executed
↑
Low
Note: * Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or
immediately after reset exception handling.
Figure 2.12 classifies the exception sources. For further details about exception sources, vector
numbers, and vector addresses, see section 4, Exception Handling, and section 5, Interrupt
Controller.
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Section 2 CPU
Reset
External interrupts
Exception
sources
Interrupt
Internal interrupts (from on-chip supporting modules)
Trap instruction
Figure 2.12 Classification of Exception Sources
End of bus release
Bus request
Program execution state
End of bus
release
Bus
request
Exception
SLEEP
instruction
with SSBY = 0
Bus-released state
End of
exception
handling
Exception-handling state
Sleep mode
Interrupt
NMI, IRQ 0 , IRQ 1,
or IRQ 2 interrupt
SLEEP instruction
with SSBY = 1
Software standby mode
RES = 1
Reset state*1
STBY = 1, RES = 0
*2
Hardware standby mode
Power-down state
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs
whenever RES goes low.
2. From any state, a transition to hardware standby mode occurs when STBY goes low.
Figure 2.13 State Transitions
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Section 2 CPU
2.8.4
Exception-Handling Sequences
Reset Exception Handling: Reset exception handling has the highest priority. The reset state is
entered when the RES signal goes low. Reset exception handling starts after that, when RES
changes from low to high. When reset exception handling starts the CPU fetches a start address
from the exception vector table and starts program execution from that address. All interrupts,
including NMI, are disabled during the reset exception-handling sequence and immediately after it
ends.
Interrupt Exception Handling and Trap Instruction Exception Handling: When these
exception-handling sequences begin, the CPU references the stack pointer (ER7) and pushes the
program counter and condition code register on the stack. Next, if the UE bit in the system control
register (SYSCR) is set to 1, the CPU sets the I bit in the condition code register to 1. If the UE bit
is cleared to 0, the CPU sets both the I bit and the UI bit in the condition code register to 1. Then
the CPU fetches a start address from the exception vector table and execution branches to that
address.
Figure 2.14 shows the stack after the exception-handling sequence.
SP–4
SP (ER7)
SP–3
SP+1
SP–2
SP+2
SP–1
SP (ER7)
CCR
PC
SP+3
Stack area
Before exception
handling starts
SP+4
Even
address
Pushed on stack
After exception
handling ends
Legend
CCR: Condition code register
SP:
Stack pointer
Notes: 1. PC is the address of the first instruction executed after the return from the
exception-handling routine.
2. Registers must be saved and restored by word access or longword access,
starting at an even address.
Figure 2.14 Stack Structure after Exception Handling
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2.8.5
Bus-Released State
In this state the bus is released to a bus master other than the CPU, in response to a bus request.
The bus masters other than the CPU are the DMA controller, the refresh controller, and an external
bus master. While the bus is released, the CPU halts except for internal operations. Interrupt
requests are not accepted. For details see section 6.3.7, Bus Arbiter Operation.
2.8.6
Reset State
When the RES input goes low all current processing stops and the CPU enters the reset state. The I
bit in the condition code register is set to 1 by a reset. All interrupts are masked in the reset state.
Reset exception handling starts when the RES signal changes from low to high.
The reset state can also be entered by a watchdog timer overflow. For details see section 12,
Watchdog Timer.
2.8.7
Power-Down State
In the power-down state the CPU stops operating to conserve power. There are three modes: sleep
mode, software standby mode, and hardware standby mode.
Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the
SSBY bit is cleared to 0 in the system control register (SYSCR). CPU operations stop
immediately after execution of the SLEEP instruction, but the contents of CPU registers are
retained.
Software Standby Mode: A transition to software standby mode is made if the SLEEP
instruction is executed while the SSBY bit is set to 1 in SYSCR. The CPU and clock halt and all
on-chip supporting modules stop operating. The on-chip supporting modules are reset, but as long
as a specified voltage is supplied the contents of CPU registers and on-chip RAM are retained.
The I/O ports also remain in their existing states.
Hardware Standby Mode: A transition to hardware standby mode is made when the STBY input
goes low. As in software standby mode, the CPU and all clocks halt and the on-chip supporting
modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are
retained.
For further information see section 21, Power-Down State.
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Section 2 CPU
2.9
Basic Operational Timing
2.9.1
Overview
The H8/300H CPU operates according to the system clock (φ). The interval from one rise of the
system clock to the next rise is referred to as a “state.” A memory cycle or bus cycle consists of
two or three states. The CPU uses different methods to access on-chip memory, the on-chip
supporting modules, and the external address space. Access to the external address space can be
controlled by the bus controller.
2.9.2
On-Chip Memory Access Timing
On-chip memory is accessed in two states. The data bus is 16 bits wide, permitting both byte and
word access. Figure 2.15 shows the on-chip memory access cycle. Figure 2.16 indicates the pin
states.
Bus cycle
T1 state
T2 state
φ
Internal address bus
Address
Internal read signal
Internal data bus
(read access)
Read data
Internal write signal
Internal data bus
(write access)
Write data
Figure 2.15 On-Chip Memory Access Cycle
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Section 2 CPU
T1
T2
φ
Address bus
,
,
Address
,
High
High impedance
D15 to D0
Figure 2.16 Pin States during On-Chip Memory Access
2.9.3
On-Chip Supporting Module Access Timing
The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide,
depending on the register being accessed. Figure 2.17 shows the on-chip supporting module access
timing. Figure 2.18 indicates the pin states.
Bus cycle
T1 state
T2 state
T3 state
φ
Address bus
Read
access
Address
Internal read signal
Internal data bus
Read data
Internal write signal
Write
access
Internal data bus
Write data
Figure 2.17 Access Cycle for On-Chip Supporting Modules
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Section 2 CPU
T1
T2
T3
φ
Address bus
,
,
Address
,
High
High impedance
D15 to D0
Figure 2.18 Pin States during Access to On-Chip Supporting Modules
2.9.4
Access to External Address Space
The external address space is divided into eight areas (areas 0 to 7). Bus-controller settings
determine whether each area is accessed via an 8-bit or 16-bit bus, and whether it is accessed in
two or three states. For details see section 6, Bus Controller.
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Section 2 CPU
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Section 3 MCU Operating Modes
Section 3 MCU Operating Modes
3.1
Overview
3.1.1
Operating Mode Selection
The H8/3048 Group has seven operating modes (modes 1 to 7) that are selected by the mode pins
(MD2 to MD0) as indicated in table 3.1. The input at these pins determines the size of the address
space and the initial bus mode.
Table 3.1
Operating Mode Selection
Mode Pins
Description
Address Space
Initial Bus
Mode*1
On-Chip
ROM
On-Chip
RAM
0
—
—
—
—
0
1
Expanded mode
8 bits
Disabled
Enabled*2
0
1
0
Expanded mode
16 bits
Disabled
Enabled*2
Mode 3
0
1
1
Expanded mode
8 bits
Disabled
Enabled*2
Mode 4
1
0
0
Expanded mode
16 bits
Disabled
Enabled*2
Mode 5
1
0
1
Expanded mode
8 bits
Enabled
Enabled*2
Mode 6
1
1
0
Expanded mode
8 bits
Enabled
Enabled*2
Mode 7
1
1
1
Single-chip advanced
mode
—
Enabled
Enabled
Operating
Mode
MD2
MD1
MD0
—
0
0
Mode 1
0
Mode 2
Notes: 1. In modes 1 to 6, an 8-bit or 16-bit data bus can be selected on a per-area basis by
settings made in the area bus width control register (ABWCR). For details see section
6, Bus Controller.
2. If the RAME bit in SYSCR is cleared to 0, these addresses become external addresses.
For the address space size there are two choices: 1 Mbyte or 16 Mbytes. The external data bus is
either 8 or 16 bits wide depending on ABWCR settings. If 8-bit access is selected for all areas, the
external data bus is 8 bits wide. For details see section 6, Bus Controller.
Modes 1 to 4 are externally expanded modes that enable access to external memory and peripheral
devices and disable access to the on-chip ROM. Modes 1 and 2 support a maximum address space
of 1 Mbyte. Modes 3 and 4 support a maximum address space of 16 Mbytes.
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Section 3 MCU Operating Modes
Modes 5 and 6 are externally expanded modes that enable access to external memory and
peripheral devices and also enable access to the on-chip ROM. Mode 5 supports a maximum
address space of 1 Mbyte. Mode 6 supports a maximum address space of 16 Mbytes.
Mode 7 is a single-chip mode that operates using the on-chip ROM, RAM, and internal I/O
registers, and makes all I/O ports available. Mode 7 supports a 1-Mbyte address space.
The H8/3048 Group can be used only in modes 1 to 7. The inputs at the mode pins must select one
of these seven modes. The inputs at the mode pins must not be changed during operation.
3.1.2
Register Configuration
The H8/3048 Group has a mode control register (MDCR) that indicates the inputs at the mode
pins (MD2 to MD0), and a system control register (SYSCR). Table 3.2 summarizes these registers.
Table 3.2
Registers
Address*
Name
Abbreviation
R/W
Initial Value
H'FFF1
Mode control register
MDCR
R
Undetermined
H'FFF2
System control register
SYSCR
R/W
H'0B
Note: * The lower 16 bits of the address are indicated.
3.2
Mode Control Register (MDCR)
MDCR is an 8-bit read-only register that indicates the current operating mode of the H8/3048
Group.
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
MDS2
MDS1
MDS0
Initial value
1
1
0
0
0
—*
—*
—*
Read/Write
—
—
—
—
—
R
R
R
Reserved bits
Reserved bits
Note: * Determined by pins MD 2 to MD0 .
Bits 7 and 6—Reserved: Read-only bits, always read as 1.
Bits 5 to 3—Reserved: Read-only bits, always read as 0.
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Mode select 2 to 0
Bits indicating the current
operating mode
Section 3 MCU Operating Modes
Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the logic levels at pins
MD2 to MD0 (the current operating mode). MDS2 to MDS0 correspond to MD2 to MD0. MDS2 to
MDS0 are read-only bits. The mode pin (MD2 to MD0) levels are latched into these bits when
MDCR is read.
3.3
System Control Register (SYSCR)
SYSCR is an 8-bit register that controls the operation of the H8/3048 Group.
Bit
7
6
5
4
3
2
1
0
SSBY
STS2
STS1
STS0
UE
NMIEG
—
RAME
Initial value
0
0
0
0
1
0
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
RAM enable
Enables or
disables
on-chip RAM
Reserved bit
NMI edge select
Selects the valid edge
of the NMI input
User bit enable
Selects whether to use the UI bit in CCR
as a user bit or an interrupt mask bit
Standby timer select 2 to 0
These bits select the waiting time at
recovery from software standby mode
Software standby
Enables transition to software standby mode
Bit 7—Software Standby (SSBY): Enables transition to software standby mode. (For further
information about software standby mode see section 21, Power-Down State.)
When software standby mode is exited by an external interrupt, this bit remains set to 1. To clear
this bit, write 0.
Bit 7: SSBY
Description
0
SLEEP instruction causes transition to sleep mode
1
SLEEP instruction causes transition to software standby mode
(Initial value)
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Section 3 MCU Operating Modes
Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU
and on-chip supporting modules wait for the internal clock oscillator to settle when software
standby mode is exited by an external interrupt. When using a crystal oscillator, set these bits so
that the waiting time will be at least 7 ms at the system clock rate. For further information about
waiting time selection, see section 21.4.3, Selection of Waiting Time for Exit from Software
Standby Mode.
Bit 6: STS2
Bit 5: STS1
Bit 4: STS0
Description
0
0
0
Waiting time = 8,192 states
1
Waiting time = 16,384 states
0
Waiting time = 32,768 states
1
Waiting time = 65,536 states
0
Waiting time = 131,072 states
1
Waiting time = 1,024 states
—
Illegal setting
1
1
0
1
(Initial value)
Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in the condition code register as a
user bit or an interrupt mask bit.
Bit 3: UE
Description
0
UI bit in CCR is used as an interrupt mask bit
1
UI bit in CCR is used as a user bit
(Initial value)
Bit 2—NMI Edge Select (NMIEG): Selects the valid edge of the NMI input.
Bit 2: NMIEG
Description
0
An interrupt is requested at the falling edge of NMI
1
An interrupt is requested at the rising edge of NMI
(Initial value)
Bit 1—Reserved: Read-only bit, always read as 1.
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized by the rising edge of the RES signal. It is not initialized in software standby mode.
Bit 0: RAME
Description
0
On-chip RAM is disabled
1
On-chip RAM is enabled
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(Initial value)
Section 3 MCU Operating Modes
3.4
Operating Mode Descriptions
3.4.1
Mode 1
Ports 1, 2, and 5 function as address pins A19 to A0, permitting access to a maximum 1-Mbyte
address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least
one area is designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.
3.4.2
Mode 2
Ports 1, 2, and 5 function as address pins A19 to A0, permitting access to a maximum 1-Mbyte
address space. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. If all
areas are designated for 8-bit access in ABWCR, the bus mode switches to 8 bits.
3.4.3
Mode 3
Ports 1, 2, and 5 and part of port A function as address pins A23 to A0, permitting access to a
maximum 16-Mbyte address space. The initial bus mode after a reset is 8 bits, with 8-bit access to
all areas. If at least one area is designated for 16-bit access in ABWCR, the bus mode switches to
16 bits. A23 to A21 are valid when 0 is written in bits 7 to 5 of the bus release control register
(BRCR). (In this mode A20 is always used for address output.)
3.4.4
Mode 4
Ports 1, 2, and 5 and part of port A function as address pins A23 to A0, permitting access to a
maximum 16-Mbyte address space. The initial bus mode after a reset is 16 bits, with 16-bit access
to all areas. If all areas are designated for 8-bit access in ABWCR, the bus mode switches to 8 bits.
A23 to A21 are valid when 0 is written in bits 7 to 5 of BRCR. (In this mode A20 is always used for
address output.)
3.4.5
Mode 5
Ports 1, 2, and 5 can function as address pins A19 to A0, permitting access to a maximum 1-Mbyte
address space, but following a reset they are input ports. To use ports 1, 2, and 5 as an address bus,
the corresponding bits in their data direction registers (P1DDR, P2DDR, and P5DDR) must be set
to 1. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least one area is
designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.
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Section 3 MCU Operating Modes
3.4.6
Mode 6
Ports 1, 2, and 5 and part of port A function as address pins A23 to A0, permitting access to a
maximum 16-Mbyte address space, but following a reset they are input ports. To use ports 1, 2,
and 5 as an address bus, the corresponding bits in their data direction registers (P1DDR, P2DDR,
and P5DDR) must be set to 1. For A23 to A21 output, clear bits 7 to 5 of BRCR to 0. (In this mode
A20 is always used for address output.)
The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least one area is
designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.
3.4.7
Mode 7
This mode operates using the on-chip ROM, RAM, and internal I/O registers. All I/O ports are
available. Mode 7 supports a 1-Mbyte address space.
3.5
Pin Functions in Each Operating Mode
The pin functions of ports 1 to 5 and port A vary depending on the operating mode. Table 3.3
indicates their functions in each operating mode.
Table 3.3
Port
Port 1
Pin Functions in Each Mode
Mode 1
Mode 2
A7 to A0
Mode 3
A7 to A0
A7 to A0
Mode 4
Mode 5
Mode 6
Mode 7
A7 to A0
P17 to P10*2
P17 to P10*2
P17 to P10
P27 to P20*2
P27 to P20
D15 to D8
P37 to P30
Port 2
A15 to A8
A15 to A8
A15 to A8
A15 to A8
P27 to P20*2
Port 3
D15 to D8
D15 to D8
D15 to D8
D15 to D8
D15 to D8
Port 4
Port 5
Port A
1
P47 to P40*
A19 to A16
PA7 to PA4
1
D7 to D0*
A19 to A16
PA7 to PA4
1
P47 to P40*
1
1
D7 to D0*
P47 to P40*
2
1
P47 to P40
2
P47 to P40*
P53 to P50*
P53 to P50*
P53 to P50
PA7 to PA5* , PA7 to PA5* , PA7 to PA4
A20
A20
PA7 to PA5,
A20*3
PA7 to PA4
A19 to A16
A19 to A16
3
3
Notes: 1. Initial state. The bus mode can be switched by settings in ABWCR. These pins function
as P47 to P40 in 8-bit bus mode, and as D7 to D0 in 16-bit bus mode.
2. Initial state. These pins become address output pins when the corresponding bits in the
data direction registers (P1DDR, P2DDR, P5DDR) are set to 1.
3. Initial state. A20 is always an address output pin. PA7 to PA5 are switched over to A23 to
A21 output by writing 0 in bits 7 to 5 of BRCR.
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Section 3 MCU Operating Modes
3.6
Memory Map in Each Operating Mode
Figure 3.1 shows a memory map of the H8/3048. Figure 3.2 shows a memory map of the H8/3047.
Figure 3.3 shows a memory map of the H8/3044. Figure 3.4 shows a memory map of the H8/3045.
The address space is divided into eight areas.
The initial bus mode differs between modes 1 and 2, and also between modes 3 and 4.
The address locations of the on-chip RAM and internal I/O registers differ between the 1-Mbyte
modes (modes 1, 2, 5, and 7) and 16-Mbyte modes (modes 3, 4, and 6). The address range
specifiable by the CPU in the 8- and 16-bit absolute addressing modes (@aa:8 and @aa:16) also
differs.
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Section 3 MCU Operating Modes
H'07FFF
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000 External address
space
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
H'000000
Vector area
H'0000FF
H'007FFF
16-bit absolute
addresses
H'000FF
Modes 3 and 4
(16-Mbyte expanded modes with
on-chip ROM disabled)
Memory-indirect
branch addresses
Vector area
16-bit absolute
addresses
H'00000
Memory-indirect
branch addresses
Modes 1 and 2
(1-Mbyte expanded modes with
on-chip ROM disabled)
Area 0
Area 0
H'1FFFFF
H'200000
Area 1
Area 1
Area 2
H'3FFFFF
H'400000
Area 3
Area 2
Area 4
H'5FFFFF
H'600000
Area 5
Area 6
H'7FFFFF
H'800000
Area 7
External
address
space
Area 3
Area 4
H'9FFFFF
H'A00000
H'FFF1B
H'FFF1C
H'FFFFF
External
address
space
Internal I/O
registers
Area 5
H'BFFFFF
H'C00000
Area 6
H'DFFFFF
H'E00000
Area 7
H'FF8000
On-chip RAM *
H'FFFF00
H'FFFF0F
H'FFFF10
H'FFFF1B
H'FFFF1C
H'FFFFFF
External
address
space
Internal I/O
registers
8-bit absolute addresses
H'FFEF0F
H'FFEF10
16-bit absolute addresses
On-chip RAM *
H'FFF00
H'FFF0F
H'FFF10
8-bit absolute addresses
H'FEF0F
H'FEF10
16-bit absolute addresses
H'F8000
Note: * External addresses can be accessed by disabling on-chip RAM.
Figure 3.1 H8/3048 Memory Map in Each Operating Mode
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Section 3 MCU Operating Modes
H'0000FF
On-chip ROM
H'007FFF
H'00000
Vector area
H'000FF
On-chip ROM
H'07FFF
16-bit absolute
addresses
Vector area
Mode 7
(single-chip advanced mode)
Memory-indirect
branch addresses
On-chip ROM
H'07FFF
H'000000
16-bit absolute
addresses
H'000FF
Mode 6
(16-Mbyte expanded mode with
on-chip ROM enabled)
Memory-indirect
branch addresses
Vector area
16-bit absolute
addresses
H'00000
Memory-indirect
branch addresses
Mode 5
(1-Mbyte expanded mode with
on-chip ROM enabled)
H'1FFFF
Area 1
Area 2
Area 4
H'7FFFFF
H'800000
Area 7
H'FFFFF
16-bit absolute addresses
Internal I/O
registers
8-bit absolute addresses
H'FFF1B
H'FFF1C
External
address
space
Area 3
H'9FFFFF
H'A00000
Area 4
H'BFFFFF
H'C00000
Area 5
H'FEF10
Area 6
H'FFF00
H'FFF0F
H'F8000
On-chip RAM
H'DFFFFF
H'E00000
Area 7
H'FFF1C
H'FF8000
Internal I/O
registers
H'FFFFF
On-chip RAM *
H'FFFF00
H'FFFF0F
H'FFFF10
H'FFFF1B
H'FFFF1C
External
address
space
Internal I/O
registers
H'FFFFFF
8-bit absolute addresses
H'FFEF0F
H'FFEF10
16-bit absolute addresses
Area 6
Area 2
External
address
space
8-bit absolute addresses
H'5FFFFF
H'600000
Area 5
H'FEF0F
H'FEF10
H'FFF00
H'FFF0F
H'FFF10
Area 1
H'3FFFFF
H'400000
Area 3
H'F8000
On-chip RAM *
Area 0
16-bit absolute addresses
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000 External address
space
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
H'01FFFF
H'020000
H'1FFFFF
H'200000
Area 0
Note: * External addresses can be accessed by disabling on-chip RAM.
Figure 3.1 H8/3048 Memory Map in Each Operating Mode (cont)
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Section 3 MCU Operating Modes
H'07FFF
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000 External address
space
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
H'000000
Vector area
H'0000FF
H'007FFF
16-bit absolute
addresses
H'000FF
Modes 3 and 4
(16-Mbyte expanded modes with
on-chip ROM disabled)
Memory-indirect
branch addresses
Vector area
16-bit absolute
addresses
H'00000
Memory-indirect
branch addresses
Modes 1 and 2
(1-Mbyte expanded modes with
on-chip ROM disabled)
Area 0
Area 0
H'1FFFFF
H'200000
Area 1
Area 1
Area 2
H'3FFFFF
H'400000
Area 3
Area 2
Area 4
H'5FFFFF
H'600000
Area 5
Area 6
H'7FFFFF
H'800000
Area 7
External
address
space
Area 3
Area 4
H'9FFFFF
H'A00000
H'FFF1B
H'FFF1C
H'FFFFF
External
address
space
Internal I/O
registers
Area 5
H'BFFFFF
H'C00000
Area 6
H'DFFFFF
H'E00000
Area 7
H'FF8000
On-chip RAM *
H'FFFF00
H'FFFF0F
H'FFFF10
H'FFFF1B
H'FFFF1C
H'FFFFFF
External
address
space
Internal I/O
registers
8-bit absolute addresses
H'FFEF0F
H'FFEF10
16-bit absolute addresses
On-chip RAM *
H'FFF00
H'FFF0F
H'FFF10
8-bit absolute addresses
H'FEF0F
H'FEF10
16-bit absolute addresses
H'F8000
Note: * External addresses can be accessed by disabling on-chip RAM.
Figure 3.2 H8/3047 Memory Map in Each Operating Mode
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Section 3 MCU Operating Modes
H'007FFF
H'017FFF
H'018000
H'01FFFF
H'020000
H'1FFFFF
H'200000
Area 0
Area 1
H'FFFFF
H'5FFFFF
H'600000
Area 5
Area 6
H'7FFFFF
H'800000
Area 7
16-bit absolute addresses
Internal I/O
registers
H'07FFF
H'17FFF
16-bit absolute
addresses
Area 0
Area 1
Area 4
8-bit absolute addresses
H'FFF1B
H'FFF1C
External
address
space
On-chip ROM
Reserved*1
H'3FFFFF
H'400000
Area 3
H'FEF0F
H'FEF10
H'FFF00
H'FFF0F
H'FFF10
H'000FF
Area 2
H'F8000
On-chip RAM*2
On-chip ROM
Vector area
Area 2
External
address
space
Area 3
H'9FFFFF
H'A00000
Area 4
H'BFFFFF
H'C00000
Area 5
H'DFFFFF
H'E00000
Area 6
H'F8000
H'FEF10
On-chip RAM
H'FFF00
H'FFF0F
Area 7
H'FFF1C
H'FF8000
Internal I/O
registers
H'FFFF00
H'FFFF0F
H'FFFF10
H'FFFF1B
H'FFFF1C
H'FFFFFF
External
address
space
Internal I/O
registers
8-bit absolute addresses
On-chip RAM*2
16-bit absolute addresses
H'FFFFF
H'FFEF0F
H'FFEF10
16-bit absolute addresses
Reserved *1
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000 External address
space
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
H'0000FF
H'00000
Memory-indirect
branch addresses
H'07FFF
H'17FFF
H'18000
Vector area
Mode 7
(single-chip advanced mode)
8-bit absolute addresses
On-chip ROM
H'000000
16-bit absolute
addresses
H'000FF
Mode 6
(16-Mbyte expanded mode with
on-chip ROM enabled)
Memory-indirect
branch addresses
Vector area
16-bit absolute
addresses
H'00000
Memory-indirect
branch addresses
Mode 5
(1-Mbyte expanded mode with
on-chip ROM enabled)
Notes: 1. Do not access the reserved area.
2. External addresses can be accessed by disabling on-chip RAM.
Figure 3.2 H8/3047 Memory Map in Each Operating Mode (cont)
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Section 3 MCU Operating Modes
H'07FFF
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000 External address
space
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
H'000000
Vector area
H'0000FF
H'007FFF
16-bit absolute
addresses
H'000FF
Modes 3 and 4
(16-Mbyte expanded modes with
on-chip ROM disabled)
Memory-indirect
branch addresses
Vector area
16-bit absolute
addresses
H'00000
Memory-indirect
branch addresses
Modes 1 and 2
(1-Mbyte expanded modes with
on-chip ROM disabled)
Area 0
Area 0
H'1FFFFF
H'200000
Area 1
Area 1
Area 2
H'3FFFFF
H'400000
Area 3
Area 2
Area 4
H'5FFFFF
H'600000
Area 5
Area 6
H'7FFFFF
H'800000
Area 7
External
address
space
Area 3
Area 4
External
address
space
Internal I/O
registers
Area 6
H'DFFFFF
H'E00000
Area 7
H'FF8000
H'FFEF10
H'FFF70F
H'FFF710
H'FFFF00
H'FFFF0F
H'FFFF10
H'FFFF1B
H'FFFF1C
H'FFFFFF
Reserved*1
On-chip RAM*2
External
address
space
Internal I/O
registers
16-bit absolute addresses
H'FFFFF
On-chip RAM
Area 5
H'BFFFFF
H'C00000
8-bit absolute addresses
H'FFF1B
H'FFF1C
*2
16-bit absolute addresses
H'FFF00
H'FFF0F
H'FFF10
Reserved*1
8-bit absolute addresses
H'F8000
H'FEF10
H'FF70F
H'FF710
H'9FFFFF
H'A00000
Notes: 1. Do not access the reserved area.
2. External addresses can be accessed by disabling on-chip RAM.
Figure 3.3 H8/3044 Memory Map in Each Operating Mode
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Section 3 MCU Operating Modes
H'0000FF
On-chip ROM
H'007FFF
H'008000
H'00000
Vector area
H'000FF
On-chip ROM
H'07FFF
16-bit absolute
addresses
Vector area
Mode 7
(single-chip advanced mode)
Memory-indirect
branch addresses
On-chip ROM
H'07FFF
H'08000
H'000000
16-bit absolute
addresses
H'000FF
Mode 6
(16-Mbyte expanded mode with
on-chip ROM enabled)
Memory-indirect
branch addresses
Vector area
16-bit absolute
addresses
H'00000
Memory-indirect
branch addresses
Mode 5
(1-Mbyte expanded mode with
on-chip ROM enabled)
Reserved*1
Reserved*1
Area 1
Area 1
H'3FFFFF
H'400000
Area 2
Area 2
Area 3
H'5FFFFF
H'600000
Area 4
Area 5
H'7FFFFF
H'800000
Area 6
External
address
space
Area 3
Area 4
Area 7
H'9FFFFF
H'A00000
External
address
space
Internal I/O
registers
H'FFF00
H'FFF0F
H'DFFFFF
H'E00000
Area 7
H'FFF1C
H'FF8000
H'FFEF10
H'FFF70F
H'FFF710
H'FFFF00
H'FFFF0F
H'FFFF10
H'FFFF1B
H'FFFF1C
H'FFFFFF
Internal I/O
registers
H'FFFFF
Reserved*1
On-chip RAM*2
External
address
space
Internal I/O
registers
8-bit absolute addresses
On-chip RAM
On-chip RAM
Area 6
16-bit absolute addresses
H'FFFFF
*2
H'FF710
H'BFFFFF
H'C00000
8-bit absolute addresses
H'FFF1B
H'FFF1C
Reserved
16-bit absolute addresses
H'FFF00
H'FFF0F
H'FFF10
Area 5
*1
8-bit absolute addresses
H'F8000
H'FEF10
H'FF70F
H'FF710
H'F8000
16-bit absolute addresses
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000 External address
space
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
Area 0
H'01FFFF
H'1FFFFF
H'200000
Area 0
Notes: 1. Do not access the reserved area.
2. External addresses can be accessed by disabling on-chip RAM.
Figure 3.3 H8/3044 Memory Map in Each Operating Mode (cont)
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Section 3 MCU Operating Modes
H'07FFF
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000 External address
space
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
H'000000
Vector area
H'0000FF
H'007FFF
16-bit absolute
addresses
H'000FF
Modes 3 and 4
(16-Mbyte expanded modes with
on-chip ROM disabled)
Memory-indirect
branch addresses
Vector area
16-bit absolute
addresses
H'00000
Memory-indirect
branch addresses
Modes 1 and 2
(1-Mbyte expanded modes with
on-chip ROM disabled)
Area 0
Area 0
H'1FFFFF
H'200000
Area 1
Area 1
Area 2
H'3FFFFF
H'400000
Area 3
Area 2
Area 4
H'5FFFFF
H'600000
Area 5
Area 6
H'7FFFFF
H'800000
Area 7
External
address
space
Area 3
Area 4
Internal I/O
registers
Area 6
H'DFFFFF
H'E00000
Area 7
H'FF8000
H'FFEF10
H'FFF70F
H'FFF710
H'FFFF00
H'FFFF0F
H'FFFF10
H'FFFF1B
H'FFFF1C
H'FFFFFF
Reserved*1
On-chip RAM*2
External
address
space
Internal I/O
registers
16-bit absolute addresses
H'FFFFF
External
address
space
Area 5
H'BFFFFF
H'C00000
8-bit absolute addresses
H'FFF1B
H'FFF1C
On-chip RAM*2
16-bit absolute addresses
H'FFF00
H'FFF0F
H'FFF10
Reserved*1
8-bit absolute addresses
H'F8000
H'FEF10
H'FF70F
H'FF710
H'9FFFFF
H'A00000
Notes: 1. Do not access the reserved area.
2. External addresses can be accessed by disabling on-chip RAM.
Figure 3.4 H8/3045 Memory Map in Each Operating Mode
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Section 3 MCU Operating Modes
H'00FFFF
H'010000
H'01FFFF
H'020000
*1
Area 1
Area 1
Area 2
H'3FFFFF
H'400000
Area 3
Area 2
Area 4
H'5FFFFF
H'600000
Area 5
Area 6
H'7FFFFF
H'800000
Area 7
External
address
space
Area 3
H'F8000
On-chip RAM
H'BFFFFF
H'C00000
H'FFF00
H'FFF0F
Area 6
H'DFFFFF
H'E00000
H'FFF1C
Area 7
Internal I/O
registers
H'FFFFF
H'FF8000
H'FFEF10
H'FFF70F
H'FFF710
H'FFFF1B
H'FFFF1C
H'FFFFFF
Reserved*1
On-chip RAM*2
External
address
space
Internal I/O
registers
16-bit absolute addresses
Internal I/O
registers
H'FF710
Area 5
8-bit absolute addresses
H'FFFFF
External
address
space
16-bit absolute addresses
H'FFF1B
H'FFF1C
On-chip RAM
8-bit absolute addresses
H'FFF00
H'FFF0F
H'FFF10
16-bit absolute
addresses
Area 0
H'1FFFFF
H'200000
H'9FFFFF
H'A00000
*2
On-chip ROM
H'0FFFF
Reserved*1
Area 0
Reserved*1
H'000FF
H'07FFF
Area 4
H'F8000
H'FEF10
H'FF70F
H'FF710
Vector area
Memory-indirect
branch addresses
On-chip ROM
H'00000
16-bit absolute addresses
Reserved
H'0000FF
H'007FFF
H'0FFFF
H'10000
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000 External address
space
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
Vector area
Mode 7
(single-chip advanced mode)
8-bit absolute addresses
On-chip ROM
H'07FFF
H'000000
16-bit absolute
addresses
H'000FF
Mode 6
(16-Mbyte expanded mode with
on-chip ROM enabled)
Memory-indirect
branch addresses
Vector area
16-bit absolute
addresses
H'00000
Memory-indirect
branch addresses
Mode 5
(1-Mbyte expanded mode with
on-chip ROM enabled)
Notes: 1. Do not access the reserved area.
2. External addresses can be accessed by disabling on-chip RAM.
Figure 3.4 H8/3045 Memory Map in Each Operating Mode (cont)
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Section 3 MCU Operating Modes
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Section 4 Exception Handling
Section 4 Exception Handling
4.1
Overview
4.1.1
Exception Handling Types and Priority
As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt.
Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur
simultaneously, they are accepted and processed in priority order. Trap instruction exceptions are
accepted at all times in the program execution state.
Table 4.1
Exception Types and Priority
Priority
Exception Type
Start of Exception Handling
High
Reset
Starts immediately after a low-to-high transition at the
RES pin
Interrupt
Interrupt requests are handled when execution of the
current instruction or handling of the current exception is
completed
Trap instruction (TRAPA)
Started by execution of a trap instruction (TRAPA)
↑
Low
4.1.2
Exception Handling Operation
Exceptions originate from various sources. Trap instructions and interrupts are handled as follows.
1. The program counter (PC) and condition code register (CCR) are pushed onto the stack.
2. The CCR interrupt mask bit is set to 1.
3. A vector address corresponding to the exception source is generated, and program execution
starts from the address indicated in that address.
Note: For a reset exception, steps 2 and 3 above are carried out.
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Section 4 Exception Handling
4.1.3
Exception Vector Table
The exception sources are classified as shown in figure 4.1. Different vectors are assigned to
different exception sources. Table 4.2 lists the exception sources and their vector addresses.
• Reset
External interrupts: NMI, IRQ 0 to IRQ5
Exception
sources
• Interrupts
• Trap instruction
Internal interrupts: 30 interrupts from on-chip
supporting modules
Figure 4.1 Exception Sources
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Section 4 Exception Handling
Table 4.2
Exception Vector Table
Exception Source
Vector Number
Vector Address*1
Reset
0
H'0000 to H'0003
Reserved for system use
1
H'0004 to H'0007
2
H'0008 to H'000B
3
H'000C to H'000F
4
H'0010 to H'0013
5
H'0014 to H'0017
6
H'0018 to H'001B
External interrupt (NMI)
7
H'001C to H'001F
Trap instruction (4 sources)
8
H'0020 to H'0023
9
H'0024 to H'0027
10
H'0028 to H'002B
11
H'002C to H'002F
External interrupt IRQ0
12
H'0030 to H'0033
External interrupt IRQ1
13
H'0034 to H'0037
External interrupt IRQ2
14
H'0038 to H'003B
External interrupt IRQ3
15
H'003C to H'003F
External interrupt IRQ4
16
H'0040 to H'0043
External interrupt IRQ5
17
H'0044 to H'0047
Reserved for system use
18
H'0048 to H'004B
19
H'004C to H'004F
20
to
60
H'0050 to H'0053
to
H'00F0 to H'00F3
Internal interrupts*2
Notes: 1. Lower 16 bits of the address.
2. For the internal interrupt vectors, see section 5.3.3, Interrupt Vector Table.
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Section 4 Exception Handling
4.2
Reset
4.2.1
Overview
A reset is the highest-priority exception. When the RES pin goes low, all processing halts and the
chip enters the reset state. A reset initializes the internal state of the CPU and the registers of the
on-chip supporting modules. Reset exception handling begins when the RES pin changes from
low to high.
The chip can also be reset by overflow of the watchdog timer. For details see section 12,
Watchdog Timer.
4.2.2
Reset Sequence
The chip enters the reset state when the RES pin goes low.
To ensure that the chip is reset, hold the RES pin low for at least 20 ms at power-up. To reset the
chip during operation, hold the RES pin low for at least 10 system clock (φ) cycles. See appendix
D.2, Pin States at Reset, for the states of the pins in the reset state.
When the RES pin goes high after being held low for the necessary time, the chip starts reset
exception handling as follows.
• The internal state of the CPU and the registers of the on-chip supporting modules are
initialized, and the I bit is set to 1 in CCR.
• The contents of the reset vector address (H'0000 to H'0003) are read, and program execution
starts from the address indicated in the vector address.
Figure 4.2 shows the reset sequence in modes 1 and 3. Figure 4.3 shows the reset sequence in
modes 2 and 4. Figure 4.4 shows the reset sequence in modes 5, 6 and 7.
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(2)
(4)
(3)
(6)
(5)
(8)
(7)
Internal
processing
Address of reset vector: (1) = H'00000, (3) = H'00001, (5) = H'00002, (7) = H'00003
Start address (contents of reset vector)
Start address
First instruction of program
High
(1)
Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.
(1), (3), (5), (7)
(2), (4), (6), (8)
(9)
(10)
D15 to D8
HWR , LWR
RD
Address
bus
RES
φ
Vector fetch
(10)
(9)
Prefetch of
first program
instruction
Section 4 Exception Handling
Figure 4.2 Reset Sequence (Modes 1 and 3)
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Section 4 Exception Handling
Internal
processing
Vector fetch
Prefetch of first
program instruction
φ
RES
Address bus
(1)
(3)
(5)
RD
HWR , LWR
D15 to D0
(1), (3)
(2), (4)
(5)
(6)
High
(2)
(4)
(6)
Address of reset vector: (1) = H'000000, (3) = H'000002
Start address (contents of reset vector)
Start address
First instruction of program
Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.
Figure 4.3 Reset Sequence (Modes 2 and 4)
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Section 4 Exception Handling
Internal
processing
Vector fetch
Prefetch of
first program
instruction
φ
RES
Internal
address bus
(1)
(3)
(5)
Internal
read signal
Internal
write signal
Internal
data bus
(16 bits wide)
(1), (3)
(2), (4)
(5)
(6)
(2)
(4)
(6)
Address of reset vector ((1) = H'000000, (2) = H'000002)
Start address (contents of reset vector)
Start address
First instruction of program
Figure 4.4 Reset Sequence (Modes 5, 6, and 7)
4.2.3
Interrupts after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, PC and CCR
will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. The first instruction of the program is
always executed immediately after the reset state ends. This instruction should initialize the stack
pointer (example: MOV.L #xx:32, SP).
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Section 4 Exception Handling
4.3
Interrupts
Interrupt exception handling can be requested by seven external sources (NMI, IRQ0 to IRQ5) and
30 internal sources in the on-chip supporting modules. Figure 4.5 classifies the interrupt sources
and indicates the number of interrupts of each type.
The on-chip supporting modules that can request interrupts are the watchdog timer (WDT), refresh
controller, 16-bit integrated timer unit (ITU), DMA controller (DMAC), serial communication
interface (SCI), and A/D converter. Each interrupt source has a separate vector address.
NMI is the highest-priority interrupt and is always accepted. Interrupts are controlled by the
interrupt controller. The interrupt controller can assign interrupts other than NMI to two priority
levels, and arbitrate between simultaneous interrupts. Interrupt priorities are assigned in interrupt
priority registers A and B (IPRA and IPRB) in the interrupt controller.
For details on interrupts see section 5, Interrupt Controller.
External interrupts
NMI (1)
IRQ 0 to IRQ 5 (6)
Internal interrupts
WDT *1 (1)
Refresh controller *2 (1)
ITU (15)
DMAC (4)
SCI (8)
A/D converter (1)
Interrupts
Notes: Numbers in parentheses are the number of interrupt sources.
1. When the watchdog timer is used as an interval timer, it generates an interrupt
request at every counter overflow.
2. When the refresh controller is used as an interval timer, it generates an interrupt
request at compare match.
Figure 4.5 Interrupt Sources and Number of Interrupts
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Section 4 Exception Handling
4.4
Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is
set to 1 in the system control register (SYSCR), the exception handling sequence sets the I bit to 1
in CCR. If the UE bit is 0, the I and UI bits are both set to 1. The TRAPA instruction fetches a
start address from a vector table entry corresponding to a vector number from 0 to 3, which is
specified in the instruction code.
4.5
Stack Status after Exception Handling
Figure 4.6 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
SP-4
SP-3
SP-2
SP-1
SP (ER7) →
Stack area
SP (ER7) →
SP+1
SP+2
SP+3
SP+4
CCR
PC E
PC H
PC L
Even address
Before exception handling
After exception handling
Pushed on stack
Legend
PCE: Bits 23 to 16 of program counter (PC)
PCH: Bits 15 to 8 of program counter (PC)
PCL: Bits 7 to 0 of program counter (PC)
CCR: Condition code register
SP: Stack pointer
Notes: 1. PC indicates the address of the first instruction that will be executed after return.
2. Registers must be saved in word or longword size at even addresses.
Figure 4.6 Stack after Completion of Exception Handling
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Section 4 Exception Handling
4.6
Notes on Stack Usage
When accessing word data or longword data, the H8/3048 Group regards the lowest address bit as
0. The stack should always be accessed by word access or longword access, and the value of the
stack pointer (SP:ER7) should always be kept even. Use the following instructions to save
registers:
PUSH.W Rn (or MOV.W Rn, @–SP)
PUSH.L ERn (or MOV.L ERn, @–SP)
Use the following instructions to restore registers:
POP.W Rn
POP.L ERn
(or MOV.W @SP+, Rn)
(or MOV.L @SP+, ERn)
Setting SP to an odd value may lead to a malfunction. Figure 4.7 shows an example of what
happens when the SP value is odd.
CCR
SP
R1L
H'FFFEFA
H'FFFEFB
SP
PC
PC
H'FFFEFC
H'FFFEFD
H'FFFEFF
SP
TRAPA instruction executed
SP set to H'FFFEFF
MOV. B R1L, @-ER7
Data saved above SP
CCR contents lost
Legend
CCR: Condition code register
PC: Program counter
R1L: General register R1L
SP: Stack pointer
Note: The diagram illustrates modes 3 and 4.
Figure 4.7 Operation when SP Value is Odd
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Section 5 Interrupt Controller
Section 5 Interrupt Controller
5.1
Overview
5.1.1
Features
The interrupt controller has the following features:
• Interrupt priority registers (IPRs) for setting interrupt priorities
Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis
in interrupt priority registers A and B (IPRA and IPRB).
• Three-level masking by the I and UI bits in the CPU condition code register (CCR)
• Independent vector addresses
All interrupts are independently vectored; the interrupt service routine does not have to
identify the interrupt source.
• Seven external interrupt pins
NMI has the highest priority and is always accepted; either the rising or falling edge can be
selected. For each of IRQ0 to IRQ5, sensing of the falling edge or level sensing can be selected
independently.
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Section 5 Interrupt Controller
5.1.2
Block Diagram
Figure 5.1 shows a block diagram of the interrupt controller.
CPU
ISCR
IER
IPRA, IPRB
NMI
input
IRQ input
section ISR
IRQ input
OVF
TME
.
.
.
.
.
.
.
ADI
ADIE
Priority
decision logic
Interrupt
request
Vector
number
.
.
.
I
UI
Interrupt controller
UE
SYSCR
Legend
ISCR:
IER:
ISR:
IPRA:
IPRB:
SYSCR:
IRQ sense control register
IRQ enable register
IRQ status register
Interrupt priority register A
Interrupt priority register B
System control register
Figure 5.1 Interrupt Controller Block Diagram
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CCR
Section 5 Interrupt Controller
5.1.3
Pin Configuration
Table 5.1 lists the interrupt pins.
Table 5.1
Interrupt Pins
Name
Abbreviation
I/O
Function
Nonmaskable interrupt
NMI
Input
Nonmaskable interrupt, rising edge or
falling edge selectable
External interrupt request
5 to 0
IRQ5 to IRQ0
Input
Maskable interrupts, falling edge or
level sensing selectable
5.1.4
Register Configuration
Table 5.2 lists the registers of the interrupt controller.
Table 5.2
Address*
Interrupt Controller Registers
1
Name
Abbreviation
R/W
Initial Value
H'FFF2
System control register
SYSCR
R/W
H'0B
H'FFF4
IRQ sense control register
ISCR
R/W
H'00
H'FFF5
IRQ enable register
IER
R/W
H'00
H'FFF6
IRQ status register
ISR
2
R/(W)*
H'00
H'FFF8
Interrupt priority register A
IPRA
R/W
H'00
H'FFF9
Interrupt priority register B
IPRB
R/W
H'00
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written, to clear flags.
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Section 5 Interrupt Controller
5.2
Register Descriptions
5.2.1
System Control Register (SYSCR)
SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the
action of the UI bit in CCR, selects the NMI edge, and enables or disables the on-chip RAM.
Only bits 3 and 2 are described here. For the other bits, see section 3.3, System Control Register
(SYSCR).
SYSCR is initialized to H'0B by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit
7
6
5
4
3
2
1
0
SSBY
STS2
STS1
STS0
UE
NMIEG
—
RAME
Initial value
0
0
0
0
1
0
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
RAM enable
Reserved bit
Standby timer
select 2 to 0
Software standby
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NMI edge select
Selects the NMI input edge
User bit enable
Selects whether to use the UI bit in
CCR as a user bit or interrupt mask bit
Section 5 Interrupt Controller
Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an
interrupt mask bit.
Bit 3: UE
Description
0
UI bit in CCR is used as interrupt mask bit
1
UI bit in CCR is used as user bit
(Initial value)
Bit 2—NMI Edge Select (NMIEG): Selects the NMI input edge.
Bit 2: NMIEG
Description
0
Interrupt is requested at falling edge of NMI input
1
Interrupt is requested at rising edge of NMI input
5.2.2
(Initial value)
Interrupt Priority Registers A and B (IPRA, IPRB)
IPRA and IPRB are 8-bit readable/writable registers that control interrupt priority.
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Section 5 Interrupt Controller
Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which
interrupt priority levels can be set.
Bit
7
6
5
4
3
2
1
0
IPRA7
IPRA6
IPRA5
IPRA4
IPRA3
IPRA2
IPRA1
IPRA0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Priority
level A0
Selects the
priority level
of ITU
channel 2
interrupt
requests
Priority level A1
Selects the priority level
of ITU channel 1
interrupt requests
Priority level A2
Selects the priority level of
ITU channel 0 interrupt requests
Priority level A3
Selects the priority level of WDT and
refresh controller interrupt requests
Priority level A4
Selects the priority level of IRQ4 and IRQ 5
interrupt requests
Priority level A5
Selects the priority level of IRQ 2 and IRQ 3 interrupt requests
Priority level A6
Selects the priority level of IRQ1 interrupt requests
Priority level A7
Selects the priority level of IRQ 0 interrupt requests
IPRA is initialized to H'00 by a reset and in hardware standby mode.
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Section 5 Interrupt Controller
Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ0 interrupt requests.
Bit 7: IPRA7
Description
0
IRQ0 interrupt requests have priority level 0 (low priority)
1
IRQ0 interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 6—Priority Level A6 (IPRA6): Selects the priority level of IRQ1 interrupt requests.
Bit 6: IPRA6
Description
0
IRQ1 interrupt requests have priority level 0 (low priority)
1
IRQ1 interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 5—Priority Level A5 (IPRA5): Selects the priority level of IRQ2 and IRQ3 interrupt requests.
Bit 5: IPRA5
Description
0
IRQ2 and IRQ3 interrupt requests have priority level 0 (low priority)
(Initial value)
1
IRQ2 and IRQ3 interrupt requests have priority level 1 (high priority)
Bit 4—Priority Level A4 (IPRA4): Selects the priority level of IRQ4 and IRQ5 interrupt requests.
Bit 4: IPRA4
Description
0
IRQ4 and IRQ5 interrupt requests have priority level 0 (low priority)
(Initial value)
1
IRQ4 and IRQ5 interrupt requests have priority level 1 (high priority)
Bit 3—Priority Level A3 (IPRA3): Selects the priority level of WDT and refresh controller
interrupt requests.
Bit 3: IPRA3
Description
0
WDT and refresh controller interrupt requests have priority level 0 (low priority)
(Initial value)
1
WDT and refresh controller interrupt requests have priority level 1 (high
priority)
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Section 5 Interrupt Controller
Bit 2—Priority Level A2 (IPRA2): Selects the priority level of ITU channel 0 interrupt requests.
Bit 2: IPRA2
Description
0
ITU channel 0 interrupt requests have priority level 0 (low priority) (Initial value)
1
ITU channel 0 interrupt requests have priority level 1 (high priority)
Bit 1—Priority Level A1 (IPRA1): Selects the priority level of ITU channel 1 interrupt requests.
Bit 1: IPRA1
Description
0
ITU channel 1 interrupt requests have priority level 0 (low priority) (Initial value)
1
ITU channel 1 interrupt requests have priority level 1 (high priority)
Bit 0—Priority Level A0 (IPRA0): Selects the priority level of ITU channel 2 interrupt requests.
Bit 0: IPRA0
Description
0
ITU channel 2 interrupt requests have priority level 0 (low priority) (Initial value)
1
ITU channel 2 interrupt requests have priority level 1 (high priority)
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Section 5 Interrupt Controller
Interrupt Priority Register B (IPRB): IPRB is an 8-bit readable/writable register in which
interrupt priority levels can be set.
Bit
7
6
5
4
3
2
1
0
IPRB7
IPRB6
IPRB5
—
IPRB3
IPRB2
IPRB1
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bit
Priority level B1
Selects the priority level
of A/D converter
interrupt request
Priority level B2
Selects the priority level of
SCI channel 1 interrupt requests
Priority level B3
Selects the priority level of SCI
channel 0 interrupt requests
Reserved bit
Priority level B5
Selects the priority level of DMAC
interrupt requests (channels 0 and 1)
Priority level B6
Selects the priority level of ITU channel 4 interrupt requests
Priority level B7
Selects the priority level of ITU channel 3 interrupt requests
IPRB is initialized to H'00 by a reset and in hardware standby mode.
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Section 5 Interrupt Controller
Bit 7—Priority Level B7 (IPRB7): Selects the priority level of ITU channel 3 interrupt requests.
Bit 7: IPRB7
Description
0
ITU channel 3 interrupt requests have priority level 0 (low priority) (Initial value)
1
ITU channel 3 interrupt requests have priority level 1 (high priority)
Bit 6—Priority Level B6 (IPRB6): Selects the priority level of ITU channel 4 interrupt requests.
Bit 6: IPRB6
Description
0
ITU channel 4 interrupt requests have priority level 0 (low priority) (Initial value)
1
ITU channel 4 interrupt requests have priority level 1 (high priority)
Bit 5—Priority Level B5 (IPRB5): Selects the priority level of DMAC interrupt requests
(channels 0 and 1).
Bit 5: IPRB5
Description
0
DMAC interrupt requests (channels 0 and 1) have priority level 0 (low priority)
(Initial value)
1
DMAC interrupt requests (channels 0 and 1) have priority level 1 (high priority)
Bit 4—Reserved: This bit can be written and read, but it does not affect interrupt priority.
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Section 5 Interrupt Controller
Bit 3—Priority Level B3 (IPRB3): Selects the priority level of SCI channel 0 interrupt requests.
Bit 3: IPRB3
Description
0
SCI0 interrupt requests have priority level 0 (low priority)
1
SCI0 interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 2—Priority Level B2 (IPRB2): Selects the priority level of SCI channel 1 interrupt requests.
Bit 2: IPRB2
Description
0
SCI1 interrupt requests have priority level 0 (low priority)
1
SCI1 interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 1—Priority Level B1 (IPRB1): Selects the priority level of A/D converter interrupt requests.
Bit 1: IPRB1
Description
0
A/D converter interrupt requests have priority level 0 (low priority) (Initial value)
1
A/D converter interrupt requests have priority level 1 (high priority)
Bit 0—Reserved: This bit can be written and read, but it does not affect interrupt priority.
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Section 5 Interrupt Controller
5.2.3
IRQ Status Register (ISR)
ISR is an 8-bit readable/writable register that indicates the status of IRQ0 to IRQ5 interrupt
requests.
Bit
7
6
5
4
3
2
1
0
—
—
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
Initial value
0
0
0
0
0
0
0
0
Read/Write
—
—
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
Reserved bits
IRQ 5 to IRQ0 flags
These bits indicate IRQ 5 to IRQ 0
interrupt request status
Note: * Only 0 can be written, to clear flags.
ISR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6—Reserved: Read-only bits, always read as 0.
Bits 5 to 0—IRQ5 to IRQ0 Flags (IRQ5F to IRQ0F): These bits indicate the status of IRQ5 to
IRQ0 interrupt requests.
Bits 5 to 0:
IRQ5F to IRQ0F
Description
0
[Clearing conditions]
(Initial value)
0 is written in IRQnF after reading the IRQnF flag when IRQnF = 1.
IRQnSC = 0, IRQn input is high, and interrupt exception handling is carried out.
IRQnSC = 1 and IRQn interrupt exception handling is carried out.
1
[Setting conditions]
IRQnSC = 0 and IRQn input is low.
IRQnSC = 1 and IRQn input changes from high to low.
Note: n = 5 to 0
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Section 5 Interrupt Controller
5.2.4
IRQ Enable Register (IER)
IER is an 8-bit readable/writable register that enables or disables IRQ0 to IRQ5 interrupt requests.
Bit
7
6
5
4
3
2
1
0
—
—
IRQ5E
IRQ4E
IRQ3E
IRQ2E
IRQ1E
IRQ0E
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bits
IRQ 5 to IRQ0 enable
These bits enable or disable IRQ 5 to IRQ 0 interrupts
IER is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6—Reserved: These bits can be written and read, but they do not enable or disable
interrupts.
Bits 5 to 0—IRQ5 to IRQ0 Enable (IRQ5E to IRQ0E): These bits enable or disable IRQ5 to
IRQ0 interrupts.
Bits 5 to 0:
IRQ5E to IRQ0E
Description
0
IRQ5 to IRQ0 interrupts are disabled
1
IRQ5 to IRQ0 interrupts are enabled
(Initial value)
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Section 5 Interrupt Controller
5.2.5
IRQ Sense Control Register (ISCR)
ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the
inputs at pins IRQ5 to IRQ0.
Bit
7
6
—
—
5
4
3
2
1
0
IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bits
IRQ 5 to IRQ0 sense control
These bits select level sensing or falling-edge
sensing for IRQ 5 to IRQ 0 interrupts
ISCR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6—Reserved: These bits can be written and read, but they do not select level or
falling-edge sensing.
Bits 5 to 0—IRQ5 to IRQ0 Sense Control (IRQ5SC to IRQ0SC): These bits select whether
interrupts IRQ5 to IRQ0 are requested by level sensing of pins IRQ5 to IRQ0, or by falling-edge
sensing.
Bits 5 to 0:
IRQ5SC to IRQ0SC
Description
0
Interrupts are requested when IRQ5 to IRQ0 inputs are low
1
Interrupts are requested by falling-edge input at IRQ5 to IRQ0
Rev. 7.00 Sep 21, 2005 page 104 of 878
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(Initial value)
Section 5 Interrupt Controller
5.3
Interrupt Sources
The interrupt sources include external interrupts (NMI, IRQ0 to IRQ5) and 30 internal interrupts.
5.3.1
External Interrupts
There are seven external interrupts: NMI, and IRQ0 to IRQ5. Of these, NMI, IRQ0, IRQ1, and IRQ2
can be used to exit software standby mode.
NMI: NMI is the highest-priority interrupt and is always accepted, regardless of the states of the
I and UI bits in CCR. The NMIEG bit in SYSCR selects whether an interrupt is requested by the
rising or falling edge of the input at the NMI pin. NMI interrupt exception handling has vector
number 7.
IRQ0 to IRQ5 Interrupts: These interrupts are requested by input signals at pins IRQ0 to IRQ5.
The IRQ0 to IRQ5 interrupts have the following features.
• ISCR settings can select whether an interrupt is requested by the low level of the input at pins
IRQ0 to IRQ5, or by the falling edge.
• IER settings can enable or disable the IRQ0 to IRQ5 interrupts. Interrupt priority levels can be
assigned by four bits in IPRA (IPRA7 to IPRA4).
• The status of IRQ0 to IRQ5 interrupt requests is indicated in ISR. The ISR flags can be cleared
to 0 by software.
Figure 5.2 shows a block diagram of interrupts IRQ0 to IRQ5.
IRQnSC
IRQnE
IRQnF
Edge/level
sense circuit
IRQn input
S
Q
IRQn interrupt
request
R
Clear signal
Note: n = 5 to 0
Figure 5.2 Block Diagram of Interrupts IRQ0 to IRQ5
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Section 5 Interrupt Controller
Figure 5.3 shows the timing of the setting of the interrupt flags (IRQnF).
φ
IRQn
input pin
IRQnF
Note: n = 5 to 0
Figure 5.3 Timing of Setting of IRQnF
Interrupts IRQ0 to IRQ5 have vector numbers 12 to 17. These interrupts are detected regardless of
whether the corresponding pin is set for input or output. When using a pin for external interrupt
input, clear its DDR bit to 0 and do not use the pin for chip select output, refresh output, or SCI
input or output.
5.3.2
Internal Interrupts
Thirty internal interrupts are requested from the on-chip supporting modules.
• Each on-chip supporting module has status flags for indicating interrupt status, and enable bits
for enabling or disabling interrupts.
• Interrupt priority levels can be assigned in IPRA and IPRB.
• ITU and SCI interrupt requests can activate the DMAC, in which case no interrupt request is
sent to the interrupt controller, and the I and UI bits are disregarded.
5.3.3
Interrupt Vector Table
Table 5.3 lists the interrupt sources, their vector addresses, and their default priority order. In the
default priority order, smaller vector numbers have higher priority. The priority of interrupts other
than NMI can be changed in IPRA and IPRB. The priority order after a reset is the default order
shown in table 5.3.
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Section 5 Interrupt Controller
Table 5.3
Interrupt Sources, Vector Addresses, and Priority
Interrupt Source
Origin
Vector
Number
Vector Address*
IPR
Priority
NMI
External pins
7
H'001C to H'001F
—
High
IRQ0
12
H'0030 to H'0033
IPRA7
IRQ1
13
H'0034 to H0037
IPRA6
IRQ2
14
H'0038 to H'003B
IPRA5
IRQ3
15
H'003C to H'003F
IRQ4
16
H'0040 to H'0043
IRQ5
17
H'0044 to H'0047
18
H'0048 to H'004B
19
H'004C to H'004F
Reserved
—
WOVI
(interval timer)
Watchdog
timer
20
H'0050 to H'0053
CMI
(compare match)
Refresh
controller
21
H'0054 to H'0057
Reserved
—
22
H'0058 to H'005B
23
H'005C to H'005F
24
H'0060 to H'0063
25
H'0064 to H'0067
IMIA0
(compare match/
input capture A0)
ITU channel 0
IMIB0
(compare match/
input capture B0)
OVI0 (overflow 0)
26
H'0068 to H'006B
Reserved
—
27
H'006C to H'006F
IMIA1
(compare match/
input capture A1)
ITU channel 1
28
H'0070 to H'0073
IMIB1
(compare match/
input capture B1)
29
H'0074 to H'0077
OVI1 (overflow 1)
30
H'0078 to H'007B
31
H'007C to H'007F
Reserved
—
IPRA4
IPRA3
IPRA2
IPRA1
↑
Low
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Section 5 Interrupt Controller
Interrupt Source
Origin
Vector
Number
Vector Address*
IPR
Priority
IMIA2
(compare match/
input capture A2)
ITU channel 2
32
H'0080 to H'0083
IPRA0
High
IMIB2
(compare match/
input capture B2)
33
H'0084 to H'0087
OVI2 (overflow 2)
34
H'0088 to H'008B
Reserved
—
35
H'008C to H'008F
IMIA3
(compare match/
input capture A3)
ITU channel 3
36
H'0090 to H'0093
37
H'0094 to H'0097
IMIB3
(compare match/
input capture B3)
OVI3 (overflow 3)
38
H'0098 to H'009B
Reserved
—
39
H'009C to H'009F
IMIA4
(compare match/
input capture A4)
ITU channel 4
40
H'00A0 to H'00A3
IMIB4
(compare match/
input capture B4)
41
H'00A4 to H'00A7
OVI4 (overflow 4)
42
H'00A8 to H'00AB
Reserved
—
43
H'00AC to H'00AF
DEND0A
DMAC
44
H'00B0 to H'00B3
DEND0B
45
H'00B4 to H'00B7
DEND1A
46
H'00B8 to H'00BB
DEND1B
47
H'00BC to H'00BF
48
H'00C0 to H'00C3
49
H'00C4 to H'00C7
50
H'00C8 to H'00CB
51
H'00CC to H'00CF
Reserved
—
IPRB7
IPRB6
IPRB5
—
↑
Low
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Section 5 Interrupt Controller
Interrupt Source
Origin
Vector
Number
Vector Address*
IPR
Priority
ERI0
(receive error 0)
SCI channel 0
52
H'00D0 to H'00D3
IPRB3
High
RXI0
(receive data full 0)
53
H'00D4 to H'00D7
TXI0 (transmit data
empty 0)
54
H'00D8 to H'00DB
TEI0
(transmit end 0)
55
H'00DC to H'00DF
56
H'00E0 to H'00E3
IPRB2
RXI1
(receive data full 1)
57
H'00E4 to H'00E7
TXI1 (transmit data
empty 1)
58
H'00E8 to H'00EB
TEI1
(transmit end 1)
59
H'00EC to H'00EF
60
H'00F0 to H'00F3
↑
ERI1
(receive error 1)
ADI (A/D end)
SCI channel 1
A/D
IPRB1
Low
Note: * Lower 16 bits of the address.
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Section 5 Interrupt Controller
5.4
Interrupt Operation
5.4.1
Interrupt Handling Process
The H8/3048 Group handles interrupts differently depending on the setting of the UE bit. When
UE = 1, interrupts are controlled by the I bit. When UE = 0, interrupts are controlled by the I and
UI bits. Table 5.4 indicates how interrupts are handled for all setting combinations of the UE, I,
and UI bits.
NMI interrupts are always accepted except in the reset and hardware standby states. IRQ interrupts
and interrupts from the on-chip supporting modules have their own enable bits. Interrupt requests
are ignored when the enable bits are cleared to 0.
Table 5.4
UE, I, and UI Bit Settings and Interrupt Handling
SYSCR
CCR
UE
I
UI
Description
1
0
—
All interrupts are accepted. Interrupts with priority level 1 have higher
priority.
1
—
No interrupts are accepted except NMI.
0
—
All interrupts are accepted. Interrupts with priority level 1 have higher
priority.
1
0
NMI and interrupts with priority level 1 are accepted.
1
No interrupts are accepted except NMI.
0
UE = 1: Interrupts IRQ0 to IRQ5 and interrupts from the on-chip supporting modules can all be
masked by the I bit in the CPU’s CCR. Interrupts are masked when the I bit is set to 1, and
unmasked when the I bit is cleared to 0. Interrupts with priority level 1 have higher priority. Figure
5.4 is a flowchart showing how interrupts are accepted when UE = 1.
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Section 5 Interrupt Controller
Program execution state
No
Interrupt requested?
Yes
Yes
NMI
No
No
Pending
Priority level 1?
Yes
IRQ 0
No
Yes
IRQ 1
IRQ 0
No
Yes
No
IRQ 1
Yes
No
Yes
ADI
ADI
Yes
Yes
No
I=0
Yes
Save PC and CCR
I ←1
Read vector address
Branch to interrupt
service routine
Figure 5.4 Process Up to Interrupt Acceptance when UE = 1
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Section 5 Interrupt Controller
• If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
• When the interrupt controller receives one or more interrupt requests, it selects the highestpriority request, following the IPR interrupt priority settings, and holds other requests pending.
If two or more interrupts with the same IPR setting are requested simultaneously, the interrupt
controller follows the priority order shown in table 5.3.
• The interrupt controller checks the I bit. If the I bit is cleared to 0, the selected interrupt request
is accepted. If the I bit is set to 1, only NMI is accepted; other interrupt requests are held
pending.
• When an interrupt request is accepted, interrupt exception handling starts after execution of the
current instruction has been completed.
• In interrupt exception handling, PC and CCR are saved to the stack area. The PC value that is
saved indicates the address of the first instruction that will be executed after the return from the
interrupt service routine.
• Next the I bit is set to 1 in CCR, masking all interrupts except NMI.
• The vector address of the accepted interrupt is generated, and the interrupt service routine
starts executing from the address indicated by the contents of the vector address.
UE = 0: The I and UI bits in the CPU’s CCR and the IPR bits enable three-level masking of IRQ0
to IRQ5 interrupts and interrupts from the on-chip supporting modules.
• Interrupt requests with priority level 0 are masked when the I bit is set to 1, and are unmasked
when the I bit is cleared to 0.
• Interrupt requests with priority level 1 are masked when the I and UI bits are both set to 1, and
are unmasked when either the I bit or the UI bit is cleared to 0.
For example, if the interrupt enable bits of all interrupt requests are set to 1, IPRA is set to
H'20, and IPRB is set to H'00 (giving IRQ2 and IRQ3 interrupt requests priority over other
interrupts), interrupts are masked as follows:
a. If I = 0, all interrupts are unmasked (priority order: NMI > IRQ2 > IRQ3 >IRQ0 …).
b. If I = 1 and UI = 0, only NMI, IRQ2, and IRQ3 are unmasked.
c. If I = 1 and UI = 1, all interrupts are masked except NMI.
Figure 5.5 shows the transitions among the above states.
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Section 5 Interrupt Controller
I←0
a. All interrupts are
unmasked
I←0
b. Only NMI, IRQ 2 , and
IRQ 3 are unmasked
I ← 1, UI ← 0
Exception handling,
or I ← 1, UI ← 1
UI ← 0
Exception handling,
or UI ← 1
c. All interrupts are
masked except NMI
Figure 5.5 Interrupt Masking State Transitions (Example)
Figure 5.6 is a flowchart showing how interrupts are accepted when UE = 0.
• If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
• When the interrupt controller receives one or more interrupt requests, it selects the highestpriority request, following the IPR interrupt priority settings, and holds other requests pending.
If two or more interrupts with the same IPR setting are requested simultaneously, the interrupt
controller follows the priority order shown in table 5.3.
• The interrupt controller checks the I bit. If the I bit is cleared to 0, the selected interrupt request
is accepted regardless of its IPR setting, and regardless of the UI bit. If the I bit is set to 1 and
the UI bit is cleared to 0, only NMI and interrupts with priority level 1 are accepted; interrupt
requests with priority level 0 are held pending. If the I bit and UI bit are both set to 1, only
NMI is accepted; all other interrupt requests are held pending.
• When an interrupt request is accepted, interrupt exception handling starts after execution of the
current instruction has been completed.
• In interrupt exception handling, PC and CCR are saved to the stack area. The PC value that is
saved indicates the address of the first instruction that will be executed after the return from the
interrupt service routine.
• The I and UI bits are set to 1 in CCR, masking all interrupts except NMI.
• The vector address of the accepted interrupt is generated, and the interrupt service routine
starts executing from the address indicated by the contents of the vector address.
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Section 5 Interrupt Controller
Program execution state
No
Interrupt requested?
Yes
Yes
NMI
No
No
Pending
Priority level 1?
Yes
IRQ 0
No
IRQ 0
Yes
IRQ 1
No
Yes
No
IRQ 1
Yes
No
Yes
ADI
ADI
Yes
Yes
No
I=0
No
I=0
Yes
Yes
No
UI = 0
Yes
Save PC and CCR
I ← 1, UI ← 1
Read vector address
Branch to interrupt
service routine
Figure 5.6 Process Up to Interrupt Acceptance when UE = 0
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(2)
(1)
(4)
High
(3)
(8)
(7)
(10)
(9)
(12)
(11)
Vector fetch
(14)
(13)
(6), (8)
PC and CCR saved to stack
(9), (11) Vector address
(10), (12) Starting address of interrupt service routine (contents of
vector address)
(13)
Starting address of interrupt service routine; (13) = (10), (12)
(14)
First instruction of interrupt service routine
(6)
(5)
Stack
Note: Mode 2, with program code and stack in external memory area accessed in two states via 16-bit bus.
(1)
Instruction prefetch address (not executed;
return address, same as PC contents)
(2), (4) Instruction code (not executed)
Instruction prefetch address (not executed)
(3)
SP – 2
(5)
SP – 4
(7)
D15 to D0
,
Address
bus
Interrupt
request
signal
φ
Instruction Internal
prefetch
processing
Prefetch of
interrupt
Internal
service routine
processing instruction
5.4.2
Interrupt level
decision and wait
for end of instruction
Interrupt accepted
Section 5 Interrupt Controller
Interrupt Sequence
Figure 5.7 shows the interrupt sequence in mode 2 when the program code and stack are in an
external memory area accessed in two states via a 16-bit bus.
Figure 5.7 Interrupt Sequence (Mode 2, Two-State Access, Stack in External Memory)
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Section 5 Interrupt Controller
5.4.3
Interrupt Response Time
Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until the
first instruction of the interrupt service routine is executed.
Table 5.5
Interrupt Response Time
External Memory
No.
On-Chip
Memory
Item
1
8-Bit Bus
2 States
1
16-Bit Bus
3 States
1
1
1
Interrupt priority
decision
2*
2*
2*
2
Maximum number of
states until end of
current instruction
1 to 23
1 to 27
1 to 31*
3
Saving PC and CCR
to stack
4
8
12*
4
Vector fetch
4
8
12*
3 States
1
2*
2*
1 to 23
1 to 25*
4
4
6*
4
4
6*
4
4
4
4
4
2
4
8
12*
4
6*
3
4
4
4
4
4
19 to 41
31 to 57
43 to 73
19 to 41
25 to 49
5
Instruction prefetch*
6
Internal processing*
Total
2 States
4
Notes: 1. 1 state for internal interrupts.
2. Prefetch after the interrupt is accepted and prefetch of the first instruction in the
interrupt service routine.
3. Internal processing after the interrupt is accepted and internal processing after prefetch.
4. The number of states increases if wait states are inserted in external memory access.
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Section 5 Interrupt Controller
5.5
Usage Notes
5.5.1
Contention between Interrupt and Interrupt-Disabling Instruction
When an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not
disabled until after execution of the instruction is completed. If an interrupt occurs while a BCLR,
MOV, or other instruction is being executed to clear its interrupt enable bit to 0, at the instant
when execution of the instruction ends the interrupt is still enabled, so its interrupt exception
handling is carried out. If a higher-priority interrupt is also requested, however, interrupt exception
handling for the higher-priority interrupt is carried out, and the lower-priority interrupt is ignored.
This also applies to the clearing of an interrupt flag.
Figure 5.8 shows an example in which an IMIEA bit is cleared to 0 in TIER of the ITU.
TIER write cycle by CPU
IMIA exception handling
φ
Internal
address bus
TIER address
Internal
write signal
IMIEA
IMIA
IMFA interrupt
signal
Figure 5.8 Contention between Interrupt and Interrupt-Disabling Instruction
This type of contention will not occur if the interrupt is masked when the interrupt enable bit or
flag is cleared to 0.
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Section 5 Interrupt Controller
5.5.2
Instructions that Inhibit Interrupts
The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after
determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is
currently executing one of these interrupt-inhibiting instructions, however, when the instruction is
completed the CPU always continues by executing the next instruction.
5.5.3
Interrupts during EEPMOV Instruction Execution
The EEPMOV.B and EEPMOV.W instructions differ in their reaction to interrupt requests.
When the EEPMOV.B instruction is executing a transfer, no interrupts are accepted until the
transfer is completed, not even NMI.
When the EEPMOV.W instruction is executing a transfer, interrupt requests other than NMI are
not accepted until the transfer is completed. If NMI is requested, NMI exception handling starts at
a transfer cycle boundary. The PC value saved on the stack is the address of the next instruction.
Programs should be coded as follows to allow for NMI interrupts during EEPMOV.W execution:
L1: EEPMOV.W
MOV.W R4,R4
BNE
5.5.4
L1
Usage Notes on External Interrupts
The IRQnF flag specification calls for the flag to be cleared by writing 0 to it after it has been read
while set to 1. However, it is possible for the IRQnF flag to be cleared by mistake simply by
writing 0 to it, irrespective of whether it has been read while set to 1, with the result that interrupt
exception handling is not executed. This occurs when the following conditions are fulfilled.
• Setting conditions
1. Multiple external interrupts (IRQa, IRQb) are being used.
2. Different clearing methods are being used: clearing by writing 0 for the IRQaF flag, and
clearing by hardware for the IRQbF flag.
3. A bit manipulation instruction is used on the IRQ status register to clear the IRQaF flag, or else
ISR is read as a byte unit, the IRQaF flag bit is cleared, and the values read in the other bits are
written as a byte unit.
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Section 5 Interrupt Controller
• Occurrence conditions
1. When IRQaF = 1, for the IRQaF flag to clear, ISR register read is executed. Thereafter
interrupt processing is carried out and IRQbF flag clears.
2. IRQaF flag clear and IRQbF flag generation compete (IRQaF flag setting).
(The ISR read needed for IRQaF flag clear was at IRQbF = 0 but in the time taken for ISR
write, IRQbF = 1 was reached.)
In all of the setting conditions 1 to 3 and occurrence conditions 1 and 2 are generated, IRQbF
clears in error during ISR write for occurrence condition 2 and interrupt processing is not carried
out. However, if IRQbF flag reaches 0 between occurrence conditions 1 and 2, IRQbF flag does
not clear in error.
IRQaF
Read Write
1
0
Read Write
1
0
Read Write IRQb
1
1
Execution
Read Write
0
0
IRQbF
Clear in error
Occurrence condition 1
Occurrence condition 2
Figure 5.9 IRQnF Flag When Interrupt Processing Is Not Conducted
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Section 5 Interrupt Controller
In this situation, conduct one of the following countermeasures.
Countermeasure 1: When clears IRQaF flag, do not use the bit manipulation instruction, read the
ISR in bytes. Then write a value in bytes which sets IRQnF flag to 0 and other bits to 1.
For example, if a = 0
MOV.B @ISR,R0L
MOV.B #HFE,R0L
MOV.B R0L,@ISR
Countermeasure 2: During IRQb interrupt exception processing, carry out IRQbF flag clear
dummy processing.
For example, if b = 1
IRQB
MOV.B #HFD,R0L
MOV.B R0L,@ISR
·
·
·
5.5.5
Notes on Non-Maskable Interrupts (NMI)
NMI is an exception processing that can be executed by the interrupt controller and CPU when the
chip internal circuits are operating normally under a specified electrical characteristics. If an NMI
is executed when the circuits are not operating normally due to some factors such as software or
abnormal interrupt of input to the pins (runaway execution), the operation will not be guaranteed.
Incorrect NMI Operation Factors: Software
1. When an interrupt exception processing is executed in an H8/300H CPU, it is assumed that the
stack pointer (SP(ER7)) has already been set by software, and that the stack pointer (SP(ER7))
points to the stack area set in a system such as RAM. If the program is in a runaway execution,
the stack pointer may be overflowed and updated illegally. Therefore, normal operation will
not be guaranteed.
2. Requests for NMIs can be accepted on the rising or falling edge of a pin. Acceptance of the
rising or falling edge depends on the setting of the bit NMIEG in the system control register
(SYSCR). It is necessary for the customer to set the bit according to the designated system.
When the program is in a runaway execution, this bit may be rewritten illegally. Therefore, the
system may not operate as expected.
3. This chip has a break function to implement on-board emulation for specific customers. To use
this break function, execute the BRK instruction (H’5770). Note that the BRK instruction is
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Section 5 Interrupt Controller
usually undefined. Therefore, if the CPU accidentally executes the instruction, the chip will
perform exceptional processing and will enter the break mode. In the break mode, interrupts
including the NMI are inhibited and the count of the watch dog timer will be stopped. Then by
executing the RTB (H’56F0) instruction, the break mode will be cancelled, and usual program
execution will resume. When the execution is reset during break mode, the CPU enters the
reset state and the break mode is cancelled. Once the reset has been cancelled, normal program
execution will resume after the reset exception processing has been executed.
Incorrect NMI Operation Factors: Abnormal Interrupts Input to the Chip Pins
If an abnormal interrupt which was not specified in the electrical characteristics is input to a pin
during a chip operation, the chip may be destroyed. In this case, the operation of the chip will not
be guaranteed.
When an abnormal interrupt has been input to a pin, the chip may not be destroyed; however, the
internal circuits of the chip may partially or wholly malfunction, and the CPU may enter an
unimagined undefined state when the CPU was designed. If this occurs, it will be impossible to
control the operation of the chip by external pins other than the external reset and standby pins,
and the operation of the NMI will not be guaranteed. In this case, after some specified signals have
been input to the pins, input an external reset so that the chip can enter the normal program
execution state again.
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Section 5 Interrupt Controller
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Section 6 Bus Controller
Section 6 Bus Controller
6.1
Overview
The H8/3048 Group has an on-chip bus controller that divides the address space into eight areas
and can assign different bus specifications to each. This enables different types of memory to be
connected easily.
A bus arbitration function of the bus controller controls the operation of the DMA controller
(DMAC) and refresh controller. The bus controller can also release the bus to an external device.
6.1.1
Features
Features of the bus controller are listed below.
• Independent settings for address areas 7 to 0
128-kbyte areas in 1-Mbyte modes; 2-Mbyte areas in 16-Mbyte modes.
Chip select signals (CS7 to CS0) can be output for areas 7 to 0.
Areas can be designated for 8-bit or 16-bit access.
Areas can be designated for two-state or three-state access.
• Four wait modes
Programmable wait mode, pin auto-wait mode, and pin wait modes 0 and 1 can be selected.
Zero to three wait states can be inserted automatically.
• Bus arbitration function
A built-in bus arbiter arbitrates the bus right to the CPU, DMAC, refresh controller, or an
external bus master.
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Section 6 Bus Controller
6.1.2
Block Diagram
Figure 6.1 shows a block diagram of the bus controller.
CS7 to CS0
ABWCR
Internal
address bus
ASTCR
Area
decoder
WCER
Chip select
control signals
CSCR
Internal signals
Bus mode control signal
Bus control
circuit
Bus size control signal
Access state control signal
Internal data bus
Wait request signal
Wait-state
controller
WAIT
WCR
Internal signals
CPU bus request signal
DMAC bus request signal
Refresh controller bus request signal
CPU bus acknowledge signal
DMAC bus acknowledge signal
Refresh controller bus acknowledge signal
BRCR
Bus arbiter
BACK
Legend
ABWCR:
ASTCR:
WCER:
WCR:
BRCR:
CSCR:
Bus width control register
Access state control register
Wait state controller enable register
Wait control register
Bus release control register
Chip select control register
BREQ
Figure 6.1 Block Diagram of Bus Controller
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Section 6 Bus Controller
6.1.3
Input/Output Pins
Table 6.1 summarizes the bus controller’s input/output pins.
Table 6.1
Bus Controller Pins
Name
Abbreviation
I/O
Function
Chip select 7 to 0
CS7 to CS0
Output
Strobe signals selecting areas 7 to 0
Address strobe
AS
Output
Strobe signal indicating valid address output
on the address bus
Read
RD
Output
Strobe signal indicating reading from the
external address space
High write
HWR
Output
Strobe signal indicating writing to the
external address space, with valid data on
the upper data bus (D15 to D8)
Low write
LWR
Output
Strobe signal indicating writing to the
external address space, with valid data on
the lower data bus (D7 to D0)
Wait
WAIT
Input
Wait request signal for access to external
three-state-access areas
Bus request
BREQ
Input
Request signal for releasing the bus to an
external device
Bus acknowledge
BACK
Output
Acknowledge signal indicating the bus is
released to an external device
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Section 6 Bus Controller
6.1.4
Register Configuration
Table 6.2 summarizes the bus controller’s registers.
Table 6.2
Bus Controller Registers
Initial Value
Address*
Name
Abbreviation
R/W
Modes
1, 3, 5, 6
Modes
2, 4, 7
H'FFEC
Bus width control register
ABWCR
R/W
H'FF
H'00
H'FFED
Access state control register
ASTCR
R/W
H'FF
H'FF
H'FFEE
Wait control register
WCR
R/W
H'F3
H'F3
H'FFEF
Wait state controller enable
register
WCER
R/W
H'FF
H'FF
H'FFF3
Bus release control register
BRCR
R/W
H'FE
H'FE
H'FF5F
Chip select control register
CSCR
R/W
H'0F
H'0F
Note: * Lower 16 bits of the address.
6.2
Register Descriptions
6.2.1
Bus Width Control Register (ABWCR)
ABWCR is an 8-bit readable/writable register that selects 8-bit or 16-bit access for each area.
Bit
Initial
value
7
6
5
4
3
2
1
0
ABW7
ABW6
ABW5
ABW4
ABW3
ABW2
ABW1
ABW0
Mode 1, 3, 5, 6
1
1
1
1
1
1
1
1
Mode 2, 4, 7
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read/Write
Bits selecting bus width for each area
When ABWCR contains H'FF (selecting 8-bit access for all areas), the chip operates in 8-bit bus
mode: the upper data bus (D15 to D8) is valid, and port 4 is an input/output port. When at least one
bit is cleared to 0 in ABWCR, the chip operates in 16-bit bus mode with a 16-bit data bus (D15 to
D0). In modes 1, 3, 5, and 6 ABWCR is initialized to H'FF by a reset and in hardware standby
mode. In modes 2, 4, and 7 ABWCR is initialized to H'00 by a reset and in hardware standby
mode. ABWCR is not initialized in software standby mode.
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Section 6 Bus Controller
Bits 7 to 0—Areas 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select 8-bit access
or 16-bit access to the corresponding address areas.
Bits 7 to 0:
ABW7 to ABW0
Description
0
Areas 7 to 0 are 16-bit access areas
1
Areas 7 to 0 are 8-bit access areas
ABWCR specifies the bus width of external memory areas. The bus width of on-chip memory and
internal I/O registers is fixed and does not depend on ABWCR settings. These settings are
therefore meaningless in single-chip mode (mode 7).
6.2.2
Access State Control Register (ASTCR)
ASTCR is an 8-bit readable/writable register that selects whether each area is accessed in two
states or three states.
Bit
7
6
5
4
3
2
1
0
AST7
AST6
AST5
AST4
AST3
AST2
AST1
AST0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits selecting number of states for access to each area
ASTCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Areas 7 to 0 Access State Control (AST7 to AST0): These bits select whether the
corresponding area is accessed in two or three states.
Bits 7 to 0:
AST7 to AST0
Description
0
Areas 7 to 0 are accessed in two states
1
Areas 7 to 0 are accessed in three states
(Initial value)
ASTCR specifies the number of states in which external areas are accessed. On-chip memory and
internal I/O registers are accessed in a fixed number of states that does not depend on ASTCR
settings. These settings are therefore meaningless in single-chip mode (mode 7).
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Section 6 Bus Controller
6.2.3
Wait Control Register (WCR)
WCR is an 8-bit readable/writable register that selects the wait mode for the wait-state controller
(WSC) and specifies the number of wait states.
Bit
7
6
5
4
3
2
1
0
—
—
—
—
WMS1
WMS0
WC1
WC0
Initial value
1
1
1
1
0
0
1
1
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
Reserved bits
Wait count 1/0
These bits select the
number of wait states
inserted
Wait mode select 1/0
These bits select the wait mode
WCR is initialized to H'F3 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 4—Reserved: Read-only bits, always read as 1.
Bits 3 and 2—Wait Mode Select 1 and 0 (WMS1/0): These bits select the wait mode.
Bit 3: WMS1
Bit 2: WMS0
Description
0
0
Programmable wait mode
1
No wait states inserted by wait-state controller
0
Pin wait mode 1
1
Pin auto-wait mode
1
(Initial value)
Bits 1 and 0—Wait Count 1 and 0 (WC1/0): These bits select the number of wait states inserted
in access to external three-state-access areas.
Bit 1: WC1
Bit 0: WC0
Description
0
0
No wait states inserted by wait-state controller
1
1 state inserted
0
2 states inserted
1
3 states inserted
1
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(Initial value)
Section 6 Bus Controller
6.2.4
Wait State Controller Enable Register (WCER)
WCER is an 8-bit readable/writable register that enables or disables wait-state control of external
three-state-access areas by the wait-state controller.
Bit
7
6
5
4
3
2
1
0
WCE7
WCE6
WCE5
WCE4
WCE3
WCE2
WCE1
WCE0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Wait-state controller enable 7 to 0
These bits enable or disable wait-state control
WCER is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Wait-State Controller Enable 7 to 0 (WCE7 to WCE0): These bits enable or
disable wait-state control of external three-state-access areas.
Bits 7 to 0:
WCE7 to WCE0
Description
0
Wait-state control disabled (pin wait mode 0)
1
Wait-state control enabled
(Initial value)
Since WCER enables or disables wait-state control of external three-state-access areas, these
settings are meaningless in single-chip mode (mode 7).
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Section 6 Bus Controller
6.2.5
Bus Release Control Register (BRCR)
BRCR is an 8-bit readable/writable register that enables address output on bus lines A23 to A21 and
enables or disables release of the bus to an external device.
Bit
7
6
5
4
3
2
1
0
A23E
A22E
A21E
—
—
—
—
BRLE
Initial value
1
1
1
1
1
1
1
0
Read/ Mode 1, 2, 5, 7
—
—
—
—
—
—
—
R/W
R/W
R/W
R/W
—
—
—
—
R/W
Write
Mode 3, 4, 6
Address 23 to 21 enable
These bits enable PA 6 to
PA 4 to be used for A 23 to
A 21 address output
Reserved bits
Bus release enable
Enables or disables
release of the bus to
an external device
BRCR is initialized to H'FE by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Address 23 Enable (A23E): Enables PA4 to be used as the A23 address output pin.
Writing 0 in this bit enables A23 address output from PA4. In modes other than 3, 4, and 6 this bit
cannot be modified and PA4 has its ordinary input/output functions.
Bit 7: A23E
Description
0
PA4 is the A23 address output pin
1
PA4 is the PA4/TP4/TIOCA1 input/output pin
(Initial value)
Bit 6—Address 22 Enable (A22E): Enables PA5 to be used as the A22 address output pin.
Writing 0 in this bit enables A22 address output from PA5. In modes other than 3, 4, and 6 this bit
cannot be modified and PA5 has its ordinary input/output functions.
Bit 6: A22E
Description
0
PA5 is the A22 address output pin
1
PA5 is the PA5/TP5/TIOCB1 input/output pin
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(Initial value)
Section 6 Bus Controller
Bit 5—Address 21 Enable (A21E): Enables PA6 to be used as the A21 address output pin.
Writing 0 in this bit enables A21 address output from PA6. In modes other than 3, 4, and 6 this bit
cannot be modified and PA6 has its ordinary input/output functions.
Bit 5: A21E
Description
0
PA6 is the A21 address output pin
1
PA6 is the PA6/TP6/TIOCA2 input/output pin
(Initial value)
Bits 4 to 1—Reserved: Read-only bits, always read as 1.
Bit 0—Bus Release Enable (BRLE): Enables or disables release of the bus to an external device.
Bit 0: BRLE
Description
0
The bus cannot be released to an external device; BREQ and BACK can be
used as input/output pins
(Initial value)
1
The bus can be released to an external device
6.2.6
Chip Select Control Register (CSCR)
CSCR is an 8-bit readable/writable register that enables or disables output of chip select signals
(CS7 to CS4).
If a chip select signal (CS7 to CS4) output is selected in this register, the corresponding pin
functions as a chip select signal (CS7 to CS4) output, this function taking priority over other
functions. CSCR cannot be modified in single-chip mode.
Bit
7
6
5
4
3
2
1
0
CS7E
CS6E
CS5E
CS4E
—
—
—
—
Initial value
0
0
0
0
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
—
—
—
—
Chip select 7 to 4 enable
These bits enable or disable
chip select signal output
Reserved bits
CSCR is initialized to H'0F by a reset and in hardware standby mode. It is not initialized in
software standby mode.
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Section 6 Bus Controller
Bits 7 to 4—Chip Select 7 to 4 Enable (CS7E to CS4E): These bits enable or disable output of
the corresponding chip select signal.
Bit n: CSnE
Description
0
Output of chip select signal CSn is disabled
1
Output of chip select signal CSn is enabled
Note: n = 7 to 4
Bits 3 to 0—Reserved: Read-only bits, always read as 1.
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(Initial value)
Section 6 Bus Controller
6.3
Operation
6.3.1
Area Division
The external address space is divided into areas 0 to 7. Each area has a size of 128 kbytes in the
1-Mbyte modes, or 2 Mbytes in the 16-Mbyte modes. Figure 6.2 shows a general view of the
memory map.
H'000000
H'00000
H'1FFFF
H'20000
H'1FFFFF
H'200000
H'3FFFFF
H'400000
H'7FFFFF
H'800000
H'FFFFF
Area 7 (128 kbytes)
Area 7 (2 Mbytes)
Area 4 (2 Mbytes)
H'9FFFFF
H'A00000
Area 5 (128 kbytes)
Area 5 (2 Mbytes)
H'BFFFFF
H'C00000
H'BFFFF
H'C0000
Area 6 (128 kbytes)
Area 6 (2 Mbytes)
H'DFFFFF
H'E00000
Area 3 (2 Mbytes)
H'7FFFFF
H'800000
Area 4 (128 kbytes)
Area 5 (2 Mbytes)
Area 6 (128 kbytes)
Area 2 (2 Mbytes)
Area 3 (128 kbytes)
H'9FFFF
H'A0000
H'BFFFFF
H'C00000
Area 1 (2 Mbytes)
H'5FFFFF
H'600000
H'7FFFF
H'80000
H'9FFFFF
H'A00000
Area 5 (128 kbytes)
H'DFFFF
H'E0000
H'1FFFFF
H'200000
Area 2 (128 kbytes)
Area 4 (2 Mbytes)
Area 4 (128 kbytes)
H'BFFFF
H'C0000
On-chip ROM *1
Area 0 (2 Mbytes)
H'3FFFFF
H'400000
H'5FFFF
H'60000
Area 3 (2 Mbytes)
Area 3 (128 kbytes)
H'9FFFF
H'A0000
H'000000
Area 1 (128 kbytes)
H'3FFFF
H'40000
H'5FFFFF
H'600000
H'7FFFF
H'80000
H'1FFFF
H'20000
Area 2 (2 Mbytes)
Area 2 (128 kbytes)
H'5FFFF
H'60000
On-chip ROM *1
Area 0 (128 kbytes)
Area 1 (2 Mbytes)
Area 1 (128 kbytes)
H'3FFFF
H'40000
H'00000
Area 0 (2 Mbytes)
Area 0 (128 kbytes)
H'DFFFF
H'E0000
Area 7 (128 kbytes)
Area 6 (2 Mbytes)
H'DFFFFF
H'E00000
Area 7 (2 Mbytes)
On-chip RAM * 1 *2
On-chip RAM * 1 *2
On-chip RAM * 1 *2
On-chip RAM * 1 *2
External address space*3
External address space*3
External address space*3
External address space*3
Internal I/O
registers *1
a. 1-Mbyte modes with
on-chip ROM disabled
(modes 1 and 2)
H'FFFFFF
Internal I/O
registers *1
b. 16-Mbyte modes with
on-chip ROM disabled
(modes 3 and 4)
H'FFFFF
Internal I/O
registers *1
H'FFFFFF
c. 1-Mbyte mode with
on-chip ROM enabled
(mode 5)
Internal I/O registers *1
d. 16-Mbyte mode with
on-chip ROM enabled
(mode 6)
Notes: 1. The on-chip ROM, on-chip RAM, and internal I/O registers have a fixed bus width and are accessed in a
fixed number of states.
2. When the RAME bit is cleared to 0 in SYSCR, this area conforms to the specifications of area 7.
3. This external address area conforms to the specifications of area 7.
Figure 6.2 Access Area Map for Modes 1 to 6
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Section 6 Bus Controller
Chip select signals (CS7 to CS0) can be output for areas 7 to 0. The bus specifications for each area
can be selected in ABWCR, ASTCR, WCER, and WCR as shown in table 6.3.
Table 6.3
Bus Specifications
ABWCR
ASTCR
WCER
WCR
ABWn
ASTn
WCEn
WMS1
WMS0
Bus
Width
Access
States Wait Mode
0
0
—
—
—
16
2
Disabled
1
0
—
—
16
3
Pin wait mode 0
1
0
0
16
3
Programmable wait mode
1
16
3
Disabled
0
16
3
Pin wait mode 1
1
16
3
Pin auto-wait mode
—
8
2
Disabled
1
1
Bus Specifications
0
—
—
1
0
—
—
8
3
Pin wait mode 0
1
0
0
8
3
Programmable wait mode
1
8
3
Disabled
0
8
3
Pin wait mode 1
1
8
3
Pin auto-wait mode
1
Note: n = 0 to 7
6.3.2
Chip Select Signals
For each of areas 7 to 0, the H8/3048 Group can output a chip select signal (CS7 to CS0) that goes
low to indicate when the area is selected. Figure 6.3 shows the output timing of a CSn signal (n = 0
to 7).
Output of CS3 to CS0: Output of CS3 to CS0 is enabled or disabled in the data direction register
(DDR) of the corresponding port.
In the expanded modes with on-chip ROM disabled, a reset leaves pin CS0 in the output state and
pins CS3 to CS1 in the input state. To output chip select signals CS3 to CS1, the corresponding
DDR bits must be set to 1. In the expanded modes with on-chip ROM enabled, a reset leaves pins
CS3 to CS0 in the input state. To output chip select signals CS3 to CS0, the corresponding DDR bits
must be set to 1. For details see section 9, I/O Ports.
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Section 6 Bus Controller
Output of CS7 to CS4: Output of CS7 to CS4 is enabled or disabled in the chip select control
register (CSCR). A reset leaves pins CS7 to CS4 in the input state. To output chip select signals
CS7 to CS4, the corresponding CSCR bits must be set to 1. For details see section 9, I/O Ports.
φ
Address
bus
External address in area n
CSn
Figure 6.3 CSn Output Timing (n = 7 to 0)
When the on-chip ROM, on-chip RAM, and internal I/O registers are accessed, CS7 and CS0
remain high. The CSn signals are decoded from the address signals. They can be used as chip
select signals for SRAM and other devices.
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Section 6 Bus Controller
6.3.3
Data Bus
The H8/3048 Group allows either 8-bit access or 16-bit access to be designated for each of areas
7 to 0. An 8-bit-access area uses the upper data bus (D15 to D8). A 16-bit-access area uses both the
upper data bus (D15 to D8) and lower data bus (D7 to D0).
In read access the RD signal applies without distinction to both the upper and lower data bus. In
write access the HWR signal applies to the upper data bus, and the LWR signal applies to the
lower data bus.
Table 6.4 indicates how the two parts of the data bus are used under different access conditions.
Table 6.4
Access Conditions and Data Bus Usage
Access Read/W
Size
rite
Address
Valid
Strobe
Upper Data Bus
(D15 to D8)
Lower Data Bus
(D7 to D0)
8-bit-access
area
—
Valid
Invalid
16-bit-access
area
Byte
Area
Read
—
RD
Write
—
HWR
Read
Even
RD
Odd
Word
Undetermined data
Valid
Invalid
Invalid
Valid
Write
Even
HWR
Valid
Undetermined data
Odd
LWR
Undetermined data
Valid
Read
—
RD
Valid
Valid
Write
—
HWR,
LWR
Valid
Valid
Note: Undetermined data means that unpredictable data is output.
Invalid means that the bus is in the input state and the input is ignored.
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Section 6 Bus Controller
6.3.4
Bus Control Signal Timing
8-Bit, Three-State-Access Areas: Figure 6.4 shows the timing of bus control signals for an 8-bit,
three-state-access area. The upper address bus (D15 to D8) is used to access these areas. The LWR
pin is always high. Wait states can be inserted.
Bus cycle
T1
T2
T3
φ
Address bus
External address in area n
CS n
AS
RD
Read
access
D15 to D8
Valid
D 7 to D 0
Invalid
HWR
Write
access
LWR
High
D15 to D8
Valid
D 7 to D 0
Undetermined data
Note: n = 7 to 0
Figure 6.4 Bus Control Signal Timing for 8-Bit, Three-State-Access Area
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Section 6 Bus Controller
8-Bit, Two-State-Access Areas: Figure 6.5 shows the timing of bus control signals for an 8-bit,
two-state-access area. The upper address bus (D15 to D8) is used to access these areas. The LWR
pin is always high. Wait states cannot be inserted.
Bus cycle
T1
T2
φ
Address bus
External address in area n
CSn
AS
RD
Read
access
D15 to D8
Valid
D 7 to D 0
Invalid
HWR
LWR
High
Write
access
D15 to D8
Valid
D 7 to D 0
Undetermined data
Note: n = 7 to 0
Figure 6.5 Bus Control Signal Timing for 8-Bit, Two-State-Access Area
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Section 6 Bus Controller
16-Bit, Three-State-Access Areas: Figures 6.6 to 6.8 show the timing of bus control signals for a
16-bit, three-state-access area. In these areas, the upper address bus (D15 to D8) is used to access
even addresses and the lower address bus (D7 to D0) is used to access odd addresses. Wait states
can be inserted.
Bus cycle
T1
T2
T3
φ
Address bus
Even external address in area n
CS n
AS
RD
Read
access
D15 to D8
Valid
D 7 to D 0
Invalid
HWR
Write
access
LWR
High
D15 to D8
Valid
D 7 to D 0
Undetermined data
Note: n = 7 to 0
Figure 6.6 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (1)
(Byte Access to Even Address)
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Section 6 Bus Controller
Bus cycle
T1
T2
T3
φ
Address bus
Odd external address in area n
CS n
AS
RD
Read
access
D15 to D8
Invalid
D 7 to D 0
Valid
HWR
Write
access
High
LWR
D15 to D8
Undetermined data
D 7 to D 0
Valid
Note: n = 7 to 0
Figure 6.7 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (2)
(Byte Access to Odd Address)
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Section 6 Bus Controller
Bus cycle
T1
T2
T3
φ
Address bus
External address in area n
CS n
AS
RD
Read
access
D15 to D8
Valid
D 7 to D 0
Valid
HWR
LWR
Write
access
D15 to D8
Valid
D 7 to D 0
Valid
Note: n = 7 to 0
Figure 6.8 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (3)
(Word Access)
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Section 6 Bus Controller
16-Bit, Two-State-Access Areas: Figures 6.9 to 6.11 show the timing of bus control signals for a
16-bit, two-state-access area. In these areas, the upper address bus (D15 to D8) is used to access
even addresses and the lower address bus (D7 to D0) is used to access odd addresses. Wait states
cannot be inserted.
Bus cycle
T1
T2
φ
Address bus
Even external address in area n
CS n
AS
RD
Read
access
D15 to D8
Valid
D 7 to D 0
Invalid
HWR
Write
access
LWR
High
D15 to D8
Valid
D 7 to D 0
Undetermined data
Note: n = 7 to 0
Figure 6.9 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (1)
(Byte Access to Even Address)
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Section 6 Bus Controller
Bus cycle
T1
T2
φ
Address bus
Odd external address in area n
CSn
AS
RD
Read
access
D15 to D8
Invalid
D 7 to D 0
Valid
HWR
Write
access
High
LWR
D15 to D8
Undetermined data
D 7 to D 0
Valid
Note: n = 7 to 0
Figure 6.10 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (2)
(Byte Access to Odd Address)
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Section 6 Bus Controller
Bus cycle
T1
T2
φ
Address bus
External address in area n
CSn
AS
RD
Read
access
D15 to D8
Valid
D 7 to D 0
Valid
HWR
Write
access
LWR
D15 to D8
Valid
D 7 to D 0
Valid
Note: n = 7 to 0
Figure 6.11 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (3)
(Word Access)
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Section 6 Bus Controller
6.3.5
Wait Modes
Four wait modes can be selected as shown in table 6.5.
Table 6.5
Wait Mode Selection
ASTCR
WCER
WCR
ASTn Bit
WCEn Bit
WMS1 Bit WMS0 Bit WSC Control
Wait Mode
0
—
—
—
Disabled
No wait states
1
0
—
—
Disabled
Pin wait mode 0
1
0
0
Enabled
Programmable wait mode
1
Enabled
No wait states
1
0
Enabled
Pin wait mode 1
1
Enabled
Pin auto-wait mode
Note: n = 7 to 0
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Section 6 Bus Controller
Wait Mode in Areas Where Wait-State Controller is Disabled
External three-state access areas in which the wait-state controller is disabled (ASTn = 1, WCEn =
0) operate in pin wait mode 0. The other wait modes are unavailable. The settings of bits WMS1
and WMS0 are ignored in these areas.
Pin Wait Mode 0: Wait states can only be inserted by WAIT pin control. During access to an
external three-state-access area, if the WAIT pin is low at the fall of the system clock (φ) in the T2
state, a wait state (TW) is inserted. If the WAIT pin remains low, wait states continue to be inserted
until the WAIT signal goes high. Figure 6.12 shows the timing.
Inserted by WAIT signal
T1
φ
T2
TW
*
*
TW
T3
*
WAIT pin
Address bus
External address
AS
RD
Read
access
Read data
Data bus
HWR , LWR
Write
access
Data bus
Write data
Note: * Arrows indicate time of sampling of the WAIT pin.
Figure 6.12 Pin Wait Mode 0
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Section 6 Bus Controller
Wait Modes in Areas Where Wait-State Controller is Enabled
External three-state access areas in which the wait-state controller is enabled (ASTn = 1, WCEn =
1) can operate in pin wait mode 1, pin auto-wait mode, or programmable wait mode, as selected by
bits WMS1 and WMS0. Bits WMS1 and WMS0 apply to all areas, so all areas in which the waitstate controller is enabled operate in the same wait mode.
Pin Wait Mode 1: In all accesses to external three-state-access areas, the number of wait states
(TW) selected by bits WC1 and WC0 are inserted. If the WAIT pin is low at the fall of the system
clock (φ) in the last of these wait states, an additional wait state is inserted. If the WAIT pin
remains low, wait states continue to be inserted until the WAIT signal goes high.
Pin wait mode 1 is useful for inserting four or more wait states, or for inserting different numbers
of wait states for different external devices.
If the wait count is 0, this mode operates in the same way as pin wait mode 0.
Figure 6.13 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1) and one additional
wait state is inserted by WAIT input.
T1
Inserted by
wait count
Inserted by
WAIT signal
TW
TW
T2
φ
*
T3
*
WAIT pin
Address bus
External address
AS
Read
access
RD
Read data
Data bus
HWR, LWR
Write
access
Data bus
Write data
Note: * Arrows indicate time of sampling of the WAIT pin.
Figure 6.13 Pin Wait Mode 1
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Section 6 Bus Controller
Pin Auto-Wait Mode: If the WAIT pin is low, the number of wait states (TW) selected by bits
WC1 and WC0 are inserted.
In pin auto-wait mode, if the WAIT pin is low at the fall of the system clock (φ) in the T2 state, the
number of wait states (TW) selected by bits WC1 and WC0 are inserted. No additional wait states
are inserted even if the WAIT pin remains low. Pin auto-wait mode can be used for an easy
interface to low-speed memory, simply by routing the chip select signal to the WAIT pin.
Figure 6.14 shows the timing when the wait count is 1.
T1
φ
T2
T3
*
T1
T2
TW
T3
*
WAIT
Address bus
External address
External address
AS
RD
Read
access
Read data
Read data
Data bus
HWR , LWR
Write
access
Data bus
Write data
Note: * Arrows indicate time of sampling of the WAIT pin.
Figure 6.14 Pin Auto-Wait Mode
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Write data
Section 6 Bus Controller
Programmable Wait Mode: The number of wait states (TW) selected by bits WC1 and WC0 are
inserted in all accesses to external three-state-access areas. Figure 6.15 shows the timing when the
wait count is 1 (WC1 = 0, WC0 = 1).
T1
T2
TW
T3
φ
Address bus
External address
AS
RD
Read
access
Read data
Data bus
HWR, LWR
Write
access
Data bus
Write data
Figure 6.15 Programmable Wait Mode
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Section 6 Bus Controller
Example of Wait State Control Settings: A reset initializes ASTCR and WCER to H'FF and
WCR to H'F3, selecting programmable wait mode and three wait states for all areas. Software can
select other wait modes for individual areas by modifying the ASTCR, WCER, and WCR settings.
Figure 6.16 shows an example of wait mode settings.
Area 0
Area 1
3-state-access area,
programmable wait mode
(3 states inserted)
3-state-access area,
programmable wait mode
(3 states inserted)
Area 2
3-state-access area,
pin wait mode 0
Area 3
3-state-access area,
pin wait mode 0
Area 4
2-state-access area,
no wait states inserted
Area 5
2-state-access area,
no wait states inserted
Area 6
2-state-access area,
no wait states inserted
Area 7
2-state-access area,
no wait states inserted
Bit:
ASTCR H'0F:
7
0
6
0
5
0
4
0
3
1
2
1
1
1
0
1
WCER H'33:
0
0
1
1
0
0
1
1
WCR H'F3:
—
—
—
—
0
0
1
1
Note: Wait states cannot be inserted in areas designated for two-state access by ASTCR.
Figure 6.16 Wait Mode Settings (Example)
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Section 6 Bus Controller
6.3.6
Interconnections with Memory (Example)
For each area, the bus controller can select two- or three-state access and an 8- or 16-bit data bus
width. In three-state-access areas, wait states can be inserted in a variety of modes, simplifying the
connection of both high-speed and low-speed devices.
Figure 6.18 shows an example of interconnections between the H8/3048 Group and memory.
Figure 6.17 shows a memory map for this example.
A 256-kword × 16-bit EPROM is connected to area 0. This device is accessed in three states via a
16-bit bus.
Two 32-kword × 8-bit SRAM devices (SRAM1 and SRAM2) are connected to area 1. These
devices are accessed in two states via a 16-bit bus.
One 32-kword × 8-bit SRAM (SRAM3) is connected to area 2. This device is accessed via an 8-bit
bus, using three-state access with an additional wait state inserted in pin auto-wait mode.
H'000000
EPROM
H'07FFFF
Area 0
16-bit, three-state-access area
Not used
H'1FFFFF
H'200000
SRAM 1, 2
Area 1
16-bit, two-state-access area
H'20FFFF
H'210000
Not used
H'3FFFFF
H'400000
SRAM 3
H'407FFF
Area 2
8-bit, three-state-access area
(one auto-wait state)
Not used
H'5FFFFF
On-chip RAM
H'FFFFFF
Internal I/O registers
Figure 6.17 Memory Map (Example)
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Section 6 Bus Controller
EPROM
A19 to A 1
A 18 to A 0
I/O 15 to I/O8
H8/3048 Group
I/O 7 to I/O 0
CS 0
CE
OE
CS 1
CS 2
SRAM1 (even addresses)
A15 to A 1
A14 to A 0
I/O 7 to I/O 0
WAIT
CS
RD
OE
WE
HWR
LWR
SRAM2 (odd addresses)
A15 to A 1
A 14 to A 0
A 23 to A 0
I/O 7 to I/O 0
CS
OE
WE
D15 to D 8
D 7 to D 0
SRAM3
A14 to A 0
A 14 to A 0
I/O 7 to I/O 0
CS
OE
WE
Figure 6.18 Interconnections with Memory (Example)
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Section 6 Bus Controller
6.3.7
Bus Arbiter Operation
The bus controller has a built-in bus arbiter that arbitrates between different bus masters. There are
four bus masters: the CPU, DMA controller (DMAC), refresh controller, and an external bus
master. When a bus master has the bus right it can carry out read, write, or refresh access. Each
bus master uses a bus request signal to request the bus right. At fixed times the bus arbiter
determines priority and uses a bus acknowledge signal to grant the bus to a bus master, which can
then operate using the bus.
The bus arbiter checks whether the bus request signal from a bus master is active or inactive, and
returns an acknowledge signal to the bus master if the bus request signal is active. When two or
more bus masters request the bus, the highest-priority bus master receives an acknowledge signal.
The bus master that receives an acknowledge signal can continue to use the bus until the
acknowledge signal is deactivated.
The bus master priority order is:
(High)
External bus master > refresh controller > DMAC > CPU
(Low)
The bus arbiter samples the bus request signals and determines priority at all times, but it does not
always grant the bus immediately, even when it receives a bus request from a bus master with
higher priority than the current bus master. Each bus master has certain times at which it can
release the bus to a higher-priority bus master.
CPU: The CPU is the lowest-priority bus master. If the DMAC, refresh controller, or an external
bus master requests the bus while the CPU has the bus right, the bus arbiter transfers the bus right
to the bus master that requested it. The bus right is transferred at the following times:
• The bus right is transferred at the boundary of a bus cycle. If word data is accessed by two
consecutive byte accesses, however, the bus right is not transferred between the two byte
accesses.
• If another bus master requests the bus while the CPU is performing internal operations, such as
executing a multiply or divide instruction, the bus right is transferred immediately. The CPU
continues its internal operations.
• If another bus master requests the bus while the CPU is in sleep mode, the bus right is
transferred immediately.
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Section 6 Bus Controller
DMAC: When the DMAC receives an activation request, it requests the bus right from the bus
arbiter. If the DMAC is bus master and the refresh controller or an external bus master requests the
bus, the bus arbiter transfers the bus right from the DMAC to the bus master that requested the
bus. The bus right is transferred at the following times.
The bus right is transferred when the DMAC finishes transferring 1 byte or 1 word. A DMAC
transfer cycle consists of a read cycle and a write cycle. The bus right is not transferred between
the read cycle and the write cycle.
There is a priority order among the DMAC channels. For details see section 8.4.9, DMAC
Multiple-Channel Operation.
Refresh Controller: When a refresh cycle is requested, the refresh controller requests the bus
right from the bus arbiter. When the refresh cycle is completed, the refresh controller releases the
bus. For details see section 7, Refresh Controller.
External Bus Master: When the BRLE bit is set to 1 in BRCR, the bus can be released to an
external bus master. The external bus master has highest priority, and requests the bus right from
the bus arbiter by driving the BREQ signal low. Once the external bus master gets the bus, it keeps
the bus right until the BREQ signal goes high. While the bus is released to an external bus master,
the H8/3048 Group holds the address bus and data bus control signals (AS, RD, HWR, and LWR)
in the high-impedance state, holds the chip select signals high (CSn: n = 7 to 0), and holds the
BACK pin in the low output state.
The bus arbiter samples the BREQ pin at the rise of the system clock (φ). If BREQ is low, the bus
is released to the external bus master at the appropriate opportunity. The BREQ signal should be
held low until the BACK signal goes low.
When the BREQ pin is high in two consecutive samples, the BACK signal is driven high to end
the bus-release cycle.
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Section 6 Bus Controller
Figure 6.19 shows the timing when the bus right is requested by an external bus master during a
read cycle in a two-state-access area. There is a minimum interval of two states from when the
BREQ signal goes low until the bus is released.
CPU cycles
T1
External bus released
CPU cycles
T2
φ
High-impedance
Address
bus
Address
High level
CSn
High-impedance
Data bus
AS , RD
High-impedance
High
High-impedance
HWR , LWR
BREQ
BACK
Minimum 2 cycles
1
2
3
4
5
6
n = 7 to 0
1
2
3
4, 5
6
Low BREQ signal is sampled at rise of T1 state.
BACK signal goes low at end of CPU read cycle, releasing bus right to external bus master.
BREQ pin continues to be sampled while bus is released to external bus master.
High BREQ signal is sampled twice consecutively.
BREQ signal goes high, ending bus-release cycle.
Figure 6.19 External-Bus-Released State (Two-State-Access Area, During Read Cycle)
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Section 6 Bus Controller
6.4
Usage Notes
6.4.1
Connection to Dynamic RAM and Pseudo-Static RAM
A different bus control signal timing applies when dynamic RAM or pseudo-static RAM is
connected to area 3. For details see section 7, Refresh Controller.
6.4.2
Register Write Timing
ABWCR, ASTCR, and WCER Write Timing: Data written to ABWCR, ASTCR, or WCER
takes effect starting from the next bus cycle. Figure 6.20 shows the timing when an instruction
fetched from area 0 changes area 0 from three-state access to two-state access.
T1
T2
T3
T1
T2
T3
T1
T2
φ
Address
bus
ASTCR address
3-state access to area 0
Figure 6.20 ASTCR Write Timing
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2-state access
to area 0
Section 6 Bus Controller
DDR Write Timing: Data written to a data direction register (DDR) to change a CSn pin from
CSn output to generic input, or vice versa, takes effect starting from the T3 state of the DDR write
cycle. Figure 6.21 shows the timing when the CS1 pin is changed from generic input to CS1 output.
T1
T2
T3
φ
Address
bus
CS1
P8DDR address
High impedance
Figure 6.21 DDR Write Timing
BRCR Write Timing: Data written to switch between A23, A22, or A21 output and generic input or
output takes effect starting from the T3 state of the BRCR write cycle. Figure 6.22 shows the
timing when a pin is changed from generic input to A23, A22, or A21 output.
T1
T2
T3
φ
Address
bus
A 23 to A 21
BRCR address
High impedance
Figure 6.22 BRCR Write Timing
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Section 6 Bus Controller
BREQ Input Timing
6.4.3
After driving the BREQ pin low, hold it low until BACK goes low. If BREQ returns to the high
level before BACK goes low, the bus arbiter may operate incorrectly.
To terminate the external-bus-released state, hold the BREQ signal high for at least three states. If
BREQ is high for too short an interval, the bus arbiter may operate incorrectly.
6.4.4
Transition To Software Standby Mode
If contention occurs between a transition to software standby mode and a bus request from an
external bus master, the bus may be released for one state just before the transition to software
standby mode (see figure 6.23). When using software standby mode, clear the BRLE bit to 0 in
BRCR before executing the SLEEP instruction.
Bus-released state
Software standby mode
φ
BREQ
BACK
Address bus
Strobe
Figure 6.23 Contention between Bus-Released State and Software Standby Mode
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Section 7 Refresh Controller
Section 7 Refresh Controller
7.1
Overview
The H8/3048 Group has an on-chip refresh controller that enables direct connection of 16-bit-wide
DRAM or pseudo-static RAM (PSRAM).
DRAM or pseudo-static RAM can be directly connected to area 3 of the external address space.
A maximum 128 kbytes can be connected in modes 1, 2, and 5 (1-Mbyte modes). A maximum
2 Mbytes can be connected in modes 3, 4, and 6 (16-Mbyte modes).
Systems that do not need to refresh DRAM or pseudo-static RAM can use the refresh controller as
an 8-bit interval timer.
When the refresh controller is not used, it can be independently halted to conserve power. For
details see section 21.6, Module Standby Function.
7.1.1
Features
The refresh controller can be used for one of three functions: DRAM refresh control, pseudo-static
RAM refresh control, or 8-bit interval timing. Features of the refresh controller are listed below.
Features as a DRAM Refresh Controller
• Enables direct connection of 16-bit-wide DRAM
• Selection of 2CAS or 2WE mode
• Selection of 8-bit or 9-bit column address multiplexing for DRAM address input
Examples:
1-Mbit DRAM: 8-bit row address × 8-bit column address
4-Mbit DRAM: 9-bit row address × 9-bit column address
4-Mbit DRAM: 10-bit row address × 8-bit column address
• CAS-before-RAS refresh control
• Software-selectable refresh interval
• Software-selectable self-refresh mode
• Wait states can be inserted
Features as a Pseudo-Static RAM Refresh Controller
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Section 7 Refresh Controller
• RFSH signal output for refresh control
• Software-selectable refresh interval
• Software-selectable self-refresh mode
• Wait states can be inserted
Features as an Interval Timer
• Refresh timer counter (RTCNT) can be used as an 8-bit up-counter
• Selection of seven counter clock sources: φ/2, φ/8, φ/32, φ/128, φ/512, φ/2048, φ/4096
• Interrupts can be generated by compare match between RTCNT and the refresh time constant
register (RTCOR)
7.1.2
Block Diagram
Figure 7.1 shows a block diagram of the refresh controller.
φ/2, φ/8, φ/32,
φ/128, φ/512,
φ/2048, φ/4096
Refresh signal
Clock selector
Control logic
CMI interrupt
Module data bus
Legend
RTCNT:
RTCOR:
RTMCSR:
RFSHCR:
Refresh timer counter
Refresh time constant register
Refresh timer control/status register
Refresh control register
Figure 7.1 Block Diagram of Refresh Controller
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Internal data bus
Bus interface
RFSHCR
RTMCSR
RTCOR
RTCNT
Comparator
Section 7 Refresh Controller
7.1.3
Input/Output Pins
Table 7.1 summarizes the refresh controller’s input/output pins.
Table 7.1
Refresh Controller Pins
Signal
Pin
Name
Abbr.
I/O
Function
RFSH
Refresh
RFSH
Output
Goes low during refresh cycles;
used to refresh DRAM and PSRAM
HWR
Upper write/upper column
address strobe
UW/UCAS
Output
Connects to the UW pin of 2WE
DRAM or UCAS pin of 2CAS DRAM
LWR
Lower write/lower column
address strobe
LW/LCAS
Output
Connects to the LW pin of 2WE
DRAM or LCAS pin of 2CAS DRAM
RD
Column address strobe/
write enable
CAS/WE
Output
Connects to the CAS pin of 2WE
DRAM or WE pin of 2CAS DRAM
CS3
Row address strobe
RAS
Output
Connects to the RAS pin of DRAM
7.1.4
Register Configuration
Table 7.2 summarizes the refresh controller’s registers.
Table 7.2
Refresh Controller Registers
Address*
Name
Abbreviation
R/W
Initial Value
H'FFAC
Refresh control register
RFSHCR
R/W
H'02
H'FFAD
Refresh timer control/status register
RTMCSR
R/W
H'07
H'FFAE
Refresh timer counter
RTCNT
R/W
H'00
H'FFAF
Refresh time constant register
RTCOR
R/W
H'FF
Note: * Lower 16 bits of the address.
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Section 7 Refresh Controller
7.2
Register Descriptions
7.2.1
Refresh Control Register (RFSHCR)
RFSHCR is an 8-bit readable/writable register that selects the operating mode of the refresh
controller.
Bit
7
6
5
4
3
SRFMD PSRAME DRAME CAS/WE M9/M8
2
1
0
RFSHE
—
RCYCE
Initial value
0
0
0
0
0
0
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
Refresh cycle
enable
Enables or
disables
insertion of
refresh cycles
Reserved bit
Refresh pin enable
Enables refresh signal output
from the refresh pin
Address multiplex mode select
Selects the number of column address bits
Strobe mode select
Selects 2CAS or 2WE strobing of DRAM
PSRAM enable and DRAM enable
These bits enable or disable connection of pseudo-static RAM and DRAM
Self-refresh mode
Selects self-refresh mode
RFSHCR is initialized to H'02 by a reset and in hardware standby mode.
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Section 7 Refresh Controller
Bit 7—Self-Refresh Mode (SRFMD): Specifies DRAM or pseudo-static RAM self-refresh
during software standby mode. When PSRAME = 1 and DRAME = 0, after the SRFMD bit is set
to 1, pseudo-static RAM can be self-refreshed when the H8/3048 Group enters software standby
mode. When PSRAME = 0 and DRAME = 1, after the SRFMD bit is set to 1, DRAM can be selfrefreshed when the H8/3048 Group enters software standby mode. In either case, the normal
access state resumes on exit from software standby mode.
Bit 7: SRFMD
Description
0
DRAM or PSRAM self-refresh is disabled in software standby mode
(Initial value)
1
DRAM or PSRAM self-refresh is enabled in software standby mode
Bit 6—PSRAM Enable (PSRAME) and
Bit 5—DRAM Enable (DRAME): These bits enable or disable connection of pseudo-static RAM
and DRAM to area 3 of the external address space.
When DRAM or pseudo-static RAM is connected, the bus cycle and refresh cycle of area 3 consist
of three states, regardless of the setting in the access state control register (ASTCR). If AST3 = 0
in ASTCR, wait states cannot be inserted.
When the PSRAME or DRAME bit is set to 1, bits 0, 2, 3, and 4 in RFSHCR and registers
RTMCSR, RTCNT, and RTCOR are write-disabled, except that the CMF flag in RTMCSR can be
cleared by writing 0.
Bit 6: PSRAME
Bit 5: DRAME
Description
0
0
Can be used as an interval timer
1
DRAM can be directly connected
0
PSRAM can be directly connected
1
Illegal setting
(Initial value)
(DRAM and PSRAM cannot be directly connected)
1
Bit 4—Strobe Mode Select (CAS/WE
WE):
WE Selects 2CAS or 2WE mode. The setting of this bit is
valid when PSRAME = 0 and DRAME = 1. This bit is write-disabled when the PSRAME or
DRAME bit is set to 1.
Bit 4: CAS/WE
WE
Description
0
2WE mode
1
2CAS mode
(Initial value)
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Section 7 Refresh Controller
Bit 3—Address Multiplex Mode Select (M9/M8
M8):
M8 Selects 8-bit or 9-bit column addressing.
The setting of this bit is valid when PSRAME = 0 and DRAME = 1. This bit is write-disabled
when the PSRAME or DRAME bit is set to 1.
Bit 3: M9/M8
M8
Description
0
8-bit column address mode
1
9-bit column address mode
(Initial value)
Bit 2—Refresh Pin Enable (RFSHE): Enables or disables refresh signal output from the RFSH
pin. This bit is write-disabled when the PSRAME or DRAME bit is set to 1.
Bit 2: RFSHE
Description
0
Refresh signal output at the RFSH pin is disabled (the RFSH pin can be used
as a generic input/output port)
(Initial value)
1
Refresh signal output at the RFSH pin is enabled
Bit 1—Reserved: Read-only bit, always read as 1.
Bit 0—Refresh Cycle Enable (RCYCE): Enables or disables insertion of refresh cycles.
The setting of this bit is valid when PSRAME = 1 or DRAME = 1. When PSRAME = 0 and
DRAME = 0, refresh cycles are not inserted regardless of the setting of this bit.
Bit 0: RCYCE
Description
0
Refresh cycles are disabled
1
Refresh cycles are enabled for area 3
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(Initial value)
Section 7 Refresh Controller
7.2.2
Refresh Timer Control/Status Register (RTMCSR)
RTMCSR is an 8-bit readable/writable register that selects the clock source for RTCNT. It also
enables or disables interrupt requests when the refresh controller is used as an interval timer.
Bit
7
6
5
4
3
2
1
0
CMF
CMIE
CKS2
CKS1
CKS0
—
—
—
Initial value
0
0
0
0
0
1
1
1
Read/Write
R/(W)*
R/W
R/W
R/W
R/W
—
—
—
Clock select 2 to 0
These bits select an
internal clock source
for input to RTCNT
Reserved bits
Compare match interrupt enable
Enables or disables the CMI interrupt requested by CMF
Compare match flag
Status flag indicating that RTCNT has matched RTCOR
Note: * Only 0 can be written, to clear the flag.
Bits 7 and 6 are initialized by a reset and in standby mode. Bits 5 to 3 are initialized by a reset and
in hardware standby mode, but retain their previous values on transition to software standby mode.
Bit 7—Compare Match Flag (CMF): This status flag indicates that the RTCNT and RTCOR
values have matched.
Bit 7: CMF
Description
0
[Clearing condition]
Cleared by reading CMF when CMF = 1, then writing 0 in CMF
1
[Setting condition]
When RTCNT = RTCOR
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Section 7 Refresh Controller
Bit 6—Compare Match Interrupt Enable (CMIE): Enables or disables the CMI interrupt
requested when the CMF flag is set to 1 in RTMCSR. The CMIE bit is always cleared to 0 when
PSRAME = 1 or DRAME = 1.
Bit 6: CMIE
Description
0
The CMI interrupt requested by CMF is disabled
1
The CMI interrupt requested by CMF is enabled
(Initial value)
Bits 5 to 3—Clock Select 2 to 0 (CKS2 to CKS0): These bits select an internal clock source for
input to RTCNT. When used for refresh control, the refresh controller outputs a refresh request at
periodic intervals determined by compare match between RTCNT and RTCOR. When used as an
interval timer, the refresh controller generates CMI interrupts at periodic intervals determined by
compare match. These bits are write-disabled when the PSRAME bit or DRAME bit is set to 1.
Bit 5: CKS2
Bit 4: CKS1
Bit 3: CKS0
Description
0
0
0
Clock input is disabled
1
φ/2 clock source
0
φ/8 clock source
1
φ/32 clock source
1
1
0
1
0
φ/128 clock source
1
φ/512 clock source
0
φ/2048 clock source
1
φ/4096 clock source
(Initial value)
Bits 2 to 0—Reserved: Read-only bits, always read as 1.
7.2.3
Refresh Timer Counter (RTCNT)
RTCNT is an 8-bit readable/writable up-counter.
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RTCNT is an up-counter that is incremented by an internal clock selected by bits CKS2 to CKS0
in RTMCSR. When RTCNT matches RTCOR (compare match), the CMF flag is set to 1 and
RTCNT is cleared to H'00.
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Section 7 Refresh Controller
RTCNT is write-disabled when the PSRAME bit or DRAME bit is set to 1. RTCNT is initialized
to H'00 by a reset and in standby mode.
7.2.4
Refresh Time Constant Register (RTCOR)
RTCOR is an 8-bit readable/writable register that determines the interval at which RTCNT is
compare matched.
Bit
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RTCOR and RTCNT are constantly compared. When their values match, the CMF flag is set to 1
in RTMCSR, and RTCNT is simultaneously cleared to H'00.
RTCOR is write-disabled when the PSRAME bit or DRAME bit is set to 1. RTCOR is initialized
to H'FF by a reset and in hardware standby mode. In software standby mode it retains its previous
value.
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Section 7 Refresh Controller
7.3
Operation
7.3.1
Overview
One of three functions can be selected for the H8/3048 Group refresh controller: interfacing to
DRAM connected to area 3, interfacing to pseudo-static RAM connected to area 3, or interval
timing. Table 7.3 summarizes the register settings when these three functions are used.
Table 7.3
Refresh Controller Settings
Usage
Register Settings
DRAM Interface
PSRAM Interface
Interval Timer
RFSHCR
SRFMD
Selects self-refresh
mode
Selects self-refresh
mode
Cleared to 0
PSRAME
Cleared to 0
Set to 1
Cleared to 0
DRAME
Set to 1
Cleared to 0
Cleared to 0
CAS/WE
Selects 2CAS or
2WE mode
—
—
M9/M8
Selects column
addressing mode
—
—
RFSHE
Selects RFSH signal
output
Selects RFSH signal
output
Cleared to 0
RCYCE
Selects insertion of
refresh cycles
Selects insertion of
refresh cycles
—
Refresh interval
setting
Refresh interval
setting
Interrupt interval
setting
CMF
Set to 1 when
RTCNT = RTCOR
Set to 1 when
RTCNT = RTCOR
Set to 1 when
RTCNT = RTCOR
CMIE
Cleared to 0
Cleared to 0
Enables or disables
interrupt requests
P8DDR
P81DDR
Set to 1 (CS3 output)
Set to 1 (CS3 output)
Set to 0 or 1
ABWCR
ABW3
Cleared to 0
—
—
RTCOR
RTMCSR
CKS2 to
CKS0
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Section 7 Refresh Controller
DRAM Interface: To set up area 3 for connection to 16-bit-wide DRAM, initialize RTCOR,
RTMCSR, and RFSHCR in that order, clearing bit PSRAME to 0 and setting bit DRAME to 1.
Set bit P81DDR to 1 in the port 8 data direction register (P8DDR) to enable CS3 output. In
ABWCR, make area 3 a 16-bit-access area.
Pseudo-Static RAM Interface: To set up area 3 for connection to pseudo-static RAM, initialize
RTCOR, RTMCSR, and RFSHCR in that order, setting bit PSRAME to 1 and clearing bit
DRAME to 0. Set bit P81DDR to 1 in P8DDR to enable CS3 output.
Interval Timer: When PSRAME = 0 and DRAME = 0, the refresh controller operates as an
interval timer. After setting RTCOR, select an input clock in RTMCSR and set the CMIE bit to 1.
CMI interrupts will be requested at compare match intervals determined by RTCOR and bits
CKS2 to CKS0 in RTMCSR.
When setting RTCOR, RTMCSR, and RFSHCR, make sure that PSRAME = 0 and DRAME = 0.
Writing is disabled when either of these bits is set to 1.
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Section 7 Refresh Controller
7.3.2
DRAM Refresh Control
Refresh Request Interval and Refresh Cycle Execution: The refresh request interval is
determined by the settings of RTCOR and bits CKS2 to CKS0 in RTMCSR. Figure 7.2 illustrates
the refresh request interval.
RTCOR
RTCNT
H'00
Refresh request
Figure 7.2 Refresh Request Interval (RCYCE = 1)
Refresh requests are generated at regular intervals as shown in figure 7.2, but the refresh cycle is
not actually executed until the refresh controller gets the bus right.
Table 7.4 summarizes the relationship among area 3 settings, DRAM read/write cycles, and
refresh cycles.
Table 7.4
Area 3 Settings, DRAM Access Cycles, and Refresh Cycles
Read/Write Cycle by CPU
or DMAC
Refresh Cycle
2-state-access area
(AST3 = 0)
3 states
3 states
Wait states cannot be inserted
Wait states cannot be inserted
3-state-access area
(AST3 = 1)
3 states
3 states
Wait states can be inserted
Wait states can be inserted
Area 3 Settings
To insert refresh cycles, set the RCYCE bit to 1 in RFSHCR. Figure 7.3 shows the state transitions
for execution of refresh cycles.
When the first refresh request occurs after exit from the reset state or standby mode, the refresh
controller does not execute a refresh cycle, but goes into the refresh request pending state. Note
this point when using a DRAM that requires a refresh cycle for initialization.
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Section 7 Refresh Controller
When a refresh request occurs in the refresh request pending state, the refresh controller acquires
the bus right, then executes a refresh cycle. If another refresh request occurs during execution of
the refresh cycle, it is ignored.
Exit from reset or standby mode
Refresh request
Refresh request pending state
End of refresh
cycle*
Refresh request
Refresh
request *
Requesting bus right
Bus granted
Refresh
request *
Executing refresh cycle
Note: * A refresh request is ignored if it occurs while the refresh controller is requesting the
bus right or executing a refresh cycle.
Figure 7.3 State Transitions for Refresh Cycle Execution
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Section 7 Refresh Controller
Address Multiplexing: Address multiplexing depends on the setting of the M9/M8 bit in
RFSHCR, as described in table 7.5. Figure 7.4 shows the address output timing. Address output is
multiplexed only in area 3.
Table 7.5
Address Multiplexing
Address Pins
A23 to
A9
A10
Address signals during row
address output
A23 to
A10
Address signals
during column
address output
M9/M8 = 0
M9/M8 = 1
A8
A7
A6
A5
A4
A3
A2
A1
A0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
A23 to
A10
A9
A9
A16
A15
A14
A13
A12
A11
A10
A0
A23 to
A10
A18
A17
A16
A15
A14
A13
A12
A11
A10
A0
T1
T2
T3
φ
A 23 to A 9, A 0
A 23 to A 9 , A 0
Address
bus
A 8 to A 1
A 8 to A1
A 16 to A 9
Row address
Column address
a. M9/ M8 = 0
T1
T2
T3
φ
A 23 to A10 , A 0
A 23 to A10 , A 0
Address
bus
A 9 to A 1
A 9 to A1
A 18 to A 10
Row address
Column address
b. M9/ M8 = 1
Figure 7.4 Multiplexed Address Output (Example without Wait States)
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Section 7 Refresh Controller
2CAS
CAS and 2WE
WE Modes: The CAS/WE bit in RFSHCR can select two control modes for 16-bitwide DRAM: one using UCAS and LCAS; the other using UW and LW. These DRAM pins
correspond to H8/3048 Group pins as shown in table 7.6.
Table 7.6
DRAM Pins and H8/3048 Group Pins
DRAM Pin
H8/3048 Group Pin
CAS/WE
WE = 0 (2WE
WE Mode)
CAS/WE
WE = 1 (2CAS
CAS Mode)
HWR
UW
UCAS
LWR
LW
LCAS
RD
CAS
WE
CS3
RAS
RAS
Figure 7.5 (1) shows the interface timing for 2WE DRAM. Figure 7.5 (2) shows the interface
timing for 2CAS DRAM.
Read cycle
Write cycle*
Refresh cycle
φ
Address
bus
Row
Column
Row
Column
Area 3 top address
CS 3
(RAS )
RD
(CAS )
HWR
(UW )
LWR
(LW )
RFSH
AS
Note: * 16-bit access
Figure 7.5(1) DRAM Control Signal Output Timing (2WE
WE Mode)
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Section 7 Refresh Controller
Read cycle
Write cycle*
Refresh cycle
φ
Address
bus
Row
Column
Row
Column
Area 3 top address
CS3
(RAS)
HWR
(UCAS)
HWR
(UW)
LWR
(LW)
RFSH
AS
Note: * 16-bit access
Figure 7.5(2) DRAM Control Signal Output Timing (2CAS
CAS Mode)
Refresh Cycle Priority Order: When there are simultaneous bus requests, the priority order is:
(High)
External bus master > refresh controller > DMA controller > CPU
(Low)
For details see section 6.3.7, Bus Arbiter Operation.
Wait State Insertion: When bit AST3 is set to 1 in ASTCR, bus controller settings can cause wait
states to be inserted into bus cycles and refresh cycles. For details see section 6.3.5, Wait Modes.
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Section 7 Refresh Controller
Self-Refresh Mode: Some DRAM devices have a self-refresh function. After the SRFMD bit is
set to 1 in RFSHCR, when a transition to software standby mode occurs, the CAS and RAS
outputs go low in that order so that the DRAM self-refresh function can be used. On exit from
software standby mode, the CAS and RAS outputs both go high.
Table 7.7 shows the pin states in software standby mode. Figure 7.6 shows the signal output
timing.
Table 7.7
Pin States in Software Standby Mode (1) (PSRAME = 0, DRAME = 1)
Software Standby Mode
SRFMD = 0
SRFMD = 1 (self-refresh mode)
Signal
CAS/WE
WE = 0
CAS/WE
WE = 1
CAS/WE
WE = 0
CAS/WE
WE = 1
HWR
High-impedance
High-impedance
High
Low
LWR
High-impedance
High-impedance
High
Low
RD
High-impedance
High-impedance
Low
High
CS3
High
High
Low
Low
RFSH
High
High
Low
Low
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Section 7 Refresh Controller
Software
standby mode
Oscillator
settling time
φ
High-impedance
Address
bus
CS 3 (RAS)
RD (CAS)
HWR (UW)
High
LWR (LW)
High
RFSH
a. 2 WE mode (SRFMD = 1)
Software
standby mode
Oscillator
settling time
φ
Address
bus
High-impedance
CS 3 (RAS)
HWR
(UCAS)
LWR
(LCAS)
RD (WE)
RFSH
b. 2 CAS mode (SRFMD = 1)
Figure 7.6 Signal Output Timing in Self-Refresh Mode (PSRAME = 0, DRAME = 1)
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Section 7 Refresh Controller
Operation in Power-Down State: The refresh controller operates in sleep mode. It does not
operate in hardware standby mode. In software standby mode RTCNT is initialized, but RFSHCR,
RTMCSR bits 5 to 3, and RTCOR retain their settings prior to the transition to software standby
mode.
Example 1: Connection to 2WE
WE 1-Mbit DRAM (1-Mbyte Mode): Figure 7.7 shows typical
interconnections to a 2WE 1-Mbit DRAM, and the corresponding address map. Figure 7.8 shows a
setup procedure to be followed by a program for this example. After power-up the DRAM must be
refreshed to initialize its internal state. Initialization takes a certain length of time, which can be
measured by using an interrupt from another timer module, or by counting the number of times
RTMCSR bit 7 (CMF) is set. Note that no refresh cycle is executed for the first refresh request
after exit from the reset state or standby mode (the first time the CMF flag is set; see figure 7.3).
When using this example, check the DRAM device characteristics carefully and use a procedure
that fits them.
2 WE 1-Mbit DRAM with
× 16-bit organization
H8/3048 Group
A7
A6
A5
A4
A3
A2
A1
A0
A8
A7
A6
A5
A4
A3
A2
A1
CS 3
RD
HWR
LWR
RAS
CAS
UW
LW
OE
D15 to D 0
I/O 15 to I/O 0
a. Interconnections (example)
H'60000
DRAM area
Area 3 (1-Mbyte mode)
H'7FFFF
b. Address map
Figure 7.7 Interconnections and Address Map for 2WE
WE 1-Mbit DRAM (Example)
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Section 7 Refresh Controller
Set area 3 for 16-bit access
Set P81 DDR to 1 for
3
output
Set RTCOR
Set bits CKS2 to CKS0 in RTMCSR
Write H'23 in RFSHCR
Wait for DRAM to be initialized
DRAM can be accessed
Figure 7.8 Setup Procedure for 2WE
WE 1-Mbit DRAM (1-Mbyte Mode)
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Section 7 Refresh Controller
Example 2: Connection to 2WE
WE 4-Mbit DRAM (16-Mbyte Mode): Figure 7.9 shows typical
interconnections to a single 2WE 4-Mbit DRAM, and the corresponding address map. Figure 7.10
shows a setup procedure to be followed by a program for this example.
The DRAM in this example has 10-bit row addresses and 8-bit column addresses. Its address area
is H'600000 to H'67FFFF.
2 WE 4-Mbit DRAM with 10-bit
row address, 8-bit column address,
and × 16-bit organization
H8/3048 Group
A18
A17
A9
A8
A8
A7
A6
A5
A4
A3
A2
A1
A7
A6
A5
A4
A3
A2
A1
A0
CS 3
RD
HWR
LWR
RAS
CAS
UW
LW
OE
D15 to D 0
I/O 15 to I/O 0
a. Interconnections (example)
H'600000
DRAM area
H'67FFFF
H'680000
Area 3 (16-Mbyte mode)
Not used
H'7FFFFF
b. Address map
Figure 7.9 Interconnections and Address Map for 2WE
WE 4-Mbit DRAM (Example)
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Section 7 Refresh Controller
Set area 3 for 16-bit access
Set P81 DDR to 1 for CS3 output
Set RTCOR
Set bits CKS2 to CKS0 in RTMCSR
Write H'23 in RFSHCR
Wait for DRAM to be initialized
DRAM can be accessed
Figure 7.10 Setup Procedure for 2WE
WE 4-Mbit DRAM with 10-Bit Row Address and 8-Bit
Column Address (16-Mbyte Mode)
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Section 7 Refresh Controller
Example 3: Connection to 2CAS
CAS 4-Mbit DRAM (16-Mbyte Mode): Figure 7.11 shows typical
interconnections to a single 2CAS 4-Mbit DRAM, and the corresponding address map.
Figure 7.12 shows a setup procedure to be followed by a program for this example.
The DRAM in this example has 9-bit row addresses and 9-bit column addresses. Its address area is
H'600000 to H'67FFFF.
2 CAS 4-Mbit DRAM with 9-bit
row address, 9-bit column address,
and × 16-bit organization
A9
A8
A7
A6
A5
A4
A3
A2
A1
H8/3048 Group
A8
A7
A6
A5
A4
A3
A2
A1
A0
CS 3
HWR
LWR
RD
RAS
UCAS
LCAS
WE
OE
D15 to D 0
I/O 15 to I/O 0
a. Interconnections (example)
H'600000
DRAM area
H'67FFFF
H'680000
Not used
Area 3 (16-Mbyte mode)
H'7FFFFF
b. Address map
Figure 7.11 Interconnections and Address Map for 2CAS
CAS 4-Mbit DRAM (Example)
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Section 7 Refresh Controller
Set area 3 for 16-bit access
Set P81 DDR to 1 for CS3 output
Set RTCOR
Set bits CKS2 to CKS0 in RTMCSR
Write H'3B in RFSHCR
Wait for DRAM to be initialized
DRAM can be accessed
Figure 7.12 Setup Procedure for 2CAS
CAS 4-Mbit DRAM with 9-Bit Row Address and 9-Bit
Column Address (16-Mbyte Mode)
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Section 7 Refresh Controller
Example 4: Connection to Multiple 4-Mbit DRAM Chips (16-Mbyte Mode): Figure 7.13
shows an example of interconnections to two 2CAS 4-Mbit DRAM chips, and the corresponding
address map. Up to four DRAM chips can be connected to area 3 by decoding upper address bits
A19 and A20.
Figure 7.14 shows a setup procedure to be followed by a program for this example. The DRAM in
this example has 9-bit row addresses and 9-bit column addresses. Both chips must be refreshed
simultaneously, so the RFSH pin must be used.
2 CAS 4-Mbit DRAM with 9-bit
row address, 9-bit column
address, and × 16-bit organization
A 8 to A 0
H8/3048 Group
RAS
A19
A 9 to A 1
UCAS
No. 1
LCAS
WE
OE
I/O15 to I/O 0
A 8 to A 0
CS 3
RAS
HWR
UCAS
LWR
RD
LCAS
WE
RFSH
No. 2
OE
D15 to D 0
I/O15 to I/O 0
a. Interconnections (example)
H'600000
H'67FFFF
H'680000
H'6FFFFF
H'700000
No. 1
DRAM area
No. 2
DRAM area
Area 3 (16-Mbyte mode)
Not used
H'7FFFFF
b. Address map
Figure 7.13 Interconnections and Address Map for Multiple 2CAS
CAS 4-Mbit DRAM Chips
(Example)
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Section 7 Refresh Controller
Set area 3 for 16-bit access
Set P81 DDR to 1 for CS 3 output
Set RTCOR
Set bits CKS2 to CKS0 in RTMCSR
Write H'3F in RFSHCR
Wait for DRAM to be initialized
DRAM can be accessed
Figure 7.14 Setup Procedure for Multiple 2CAS
CAS 4-Mbit DRAM Chips with 9-Bit Row
Address and 9-Bit Column Address (16-Mbyte Mode)
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Section 7 Refresh Controller
7.3.3
Pseudo-Static RAM Refresh Control
Refresh Request Interval and Refresh Cycle Execution: The refresh request interval is
determined as in a DRAM interface, by the settings of RTCOR and bits CKS2 to CKS0 in
RTMCSR. The numbers of states required for pseudo-static RAM read/write cycles and refresh
cycles are the same as for DRAM (see table 7.4). The state transitions are as shown in figure 7.3.
Pseudo-Static RAM Control Signals: Figure 7.15 shows the control signals for pseudo-static
RAM read, write, and refresh cycles.
Read cycle
Write cycle *
Refresh cycle
φ
Address
bus
Area 3 top address
CS 3
RD
HWR
LWR
RFSH
AS
Note: * 16-bit access
Figure 7.15 Pseudo-Static RAM Control Signal Output Timing
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Section 7 Refresh Controller
Refresh Cycle Priority Order: When there are simultaneous bus requests, the priority order is:
(High)
External bus master > refresh controller > DMA controller > CPU
(Low)
For details see section 6.3.7, Bus Arbiter Operation.
Wait State Insertion: When bit AST3 is set to 1 in ASTCR, the wait state controller (WSC) can
insert wait states into bus cycles and refresh cycles. For details see section 6.3.5, Wait Modes.
Self-Refresh Mode: Some pseudo-static RAM devices have a self-refresh function. After the
SRFMD bit is set to 1 in RFSHCR, when a transition to software standby mode occurs, the
H8/3048 Group’ CS3 output goes high and its RFSH output goes low so that the pseudo-static
RAM self-refresh function can be used. On exit from software standby mode, the RFSH output
goes high.
Table 7.8 shows the pin states in software standby mode. Figure 7.16 shows the signal output
timing.
Table 7.8
Pin States in Software Standby Mode (2) (PSRAME = 1, DRAME = 0)
Software Standby Mode
Signal
SRFMD = 0
SRFMD = 1 (Self-Refresh Mode)
CS3
High
High
RD
High-impedance
High-impedance
HWR
High-impedance
High-impedance
LWR
High-impedance
High-impedance
RFSH
High
Low
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Section 7 Refresh Controller
Software standby mode
Oscillator
settling time
φ
High-impedance
Address
bus
CS3
High
High-impedance
RD
High-impedance
HWR
High-impedance
LWR
RFSH
Figure 7.16 Signal Output Timing in Self-Refresh Mode (PSRAME = 1, DRAME = 0)
Operation in Power-Down State: The refresh controller operates in sleep mode. It does not
operate in hardware standby mode. In software standby mode RTCNT is initialized, but RFSHCR,
RTMCSR bits 5 to 3, and RTCOR retain their settings prior to the transition to software standby
mode.
Example: Pseudo-static RAM may have separate OE and RFSH pins, or these may be combined
into a single OE/RFSH pin. Figure 7.17 shows an example of a circuit for generating an OE/RFSH
signal. Check the device characteristics carefully, and design a circuit that fits them. Figure 7.18
shows a setup procedure to be followed by a program.
H8/3048 Group
PSRAM
RD
OE/RFSH
RFSH
Figure 7.17 Interconnection to Pseudo-Static RAM with OE/RFSH
OE RFSH Signal (Example)
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Section 7 Refresh Controller
Set P81 DDR to 1 for CS 3 output
Set RTCOR
Set bits CKS2 to CKS0 in RTMCSR
Write H'47 in RFSHCR
Wait for PSRAM to be initialized
PSRAM can be accessed
Figure 7.18 Setup Procedure for Pseudo-Static RAM
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Section 7 Refresh Controller
7.3.4
Interval Timer
To use the refresh controller as an interval timer, clear the PSRAME and DRAME both to 0. After
setting RTCOR, select a clock source with bits CKS2 to CKS0 in RTMCSR, and set the CMIE bit
to 1.
Timing of Setting of Compare Match Flag and Clearing by Compare Match: The CMF flag
in RTCSR is set to 1 by a compare match signal output when the RTCOR and RTCNT values
match. The compare match signal is generated in the last state in which the values match (when
RTCNT is updated from the matching value to a new value). Accordingly, when RTCNT and
RTCOR match, the compare match signal is not generated until the next counter clock pulse.
Figure 7.19 shows the timing.
φ
RTCNT
RTCOR
N
H'00
N
Compare
match signal
CMF flag
Figure 7.19 Timing of Setting of CMF Flag
Operation in Power-Down State: The interval timer function operates in sleep mode. It does not
operate in hardware standby mode. In software standby mode RTCNT and RTMCSR bits 7 and 6
are initialized, but RTMCSR bits 5 to 3 and RTCOR retain their settings prior to the transition to
software standby mode.
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Section 7 Refresh Controller
Contention between RTCNT Write and Counter Clear: If a counter clear signal occurs in the
T3 state of an RTCNT write cycle, clearing of the counter takes priority and the write is not
performed. See figure 7.20.
RTCNT write cycle by CPU
T2
T1
T3
φ
Address bus
RTCNT address
Internal
write signal
Counter
clear signal
RTCNT
N
H'00
Figure 7.20 Contention between RTCNT Write and Clear
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Section 7 Refresh Controller
Contention between RTCNT Write and Increment: If an increment pulse occurs in the T3 state
of an RTCNT write cycle, writing takes priority and RTCNT is not incremented. See figure 7.21.
RTCNT write cycle by CPU
T1
T2
T3
φ
Address bus
RTCNT address
Internal
write signal
RTCNT
input clock
RTCNT
N
M
Counter write data
Figure 7.21 Contention between RTCNT Write and Increment
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Section 7 Refresh Controller
Contention between RTCOR Write and Compare Match: If a compare match occurs in the T3
state of an RTCOR write cycle, writing takes priority and the compare match signal is inhibited.
See figure 7.22.
RTCOR write cycle by CPU
T1
T2
T3
φ
Address bus
RTCNT address
Internal
write signal
RTCNT
N
N+1
RTCOR
N
M
RTCOR write data
Compare
match signal
Inhibited
Figure 7.22 Contention between RTCOR Write and Compare Match
RTCNT Operation at Internal Clock Source Switchover: Switching internal clock sources may
cause RTCNT to increment, depending on the switchover timing. Table 7.9 shows the relation
between the time of the switchover (by writing to bits CKS2 to CKS0) and the operation of
RTCNT.
The RTCNT input clock is generated from the internal clock source by detecting the falling edge
of the internal clock. If a switchover is made from a high clock source to a low clock source, as in
case No. 3 in table 7.9, the switchover will be regarded as a falling edge, an RTCNT clock pulse
will be generated, and RTCNT will be incremented.
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Section 7 Refresh Controller
Table 7.9
Internal Clock Switchover and RTCNT Operation
No.
CKS2 to CKS0
Write Timing
1
Low → low switchover*
RTCNT Operation
1
Old clock
source
New clock
source
RTCNT
clock
RTCNT
N
N+1
CKS bits rewritten
2
Low → high switchover*
2
Old clock
source
New clock
source
RTCNT
clock
RTCNT
N
N+1
N+2
CKS bits rewritten
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Section 7 Refresh Controller
No.
CKS2 to CKS0
Write Timing
3
High → low
RTCNT Operation
switchover*3
Old clock
source
New clock
source
*4
RTCNT
clock
RTCNT
N
N+1
N+2
CKS bits rewritten
4
High → high switchover*4
Old clock
source
New clock
source
RTCNT
clock
RTCNT
N
N+1
N+2
CKS bits rewritten
Notes: 1. Including switchovers from a low clock source to the halted state, and from the halted
state to a low clock source.
2. Including switchover from the halted state to a high clock source.
3. Including switchover from a high clock source to the halted state.
4. The switchover is regarded as a falling edge, causing RTCNT to increment.
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Section 7 Refresh Controller
7.4
Interrupt Source
Compare match interrupts (CMI) can be generated when the refresh controller is used as an
interval timer. Compare match interrupt requests are masked/unmasked with the CMIE bit of
RTMCSR.
7.5
Usage Notes
When using the DRAM or pseudo-static RAM refresh function, note the following points:
• With the refresh controller, if directly connected DRAM or PSRAM is disconnected*, the
P80/RFSH/IRQ0 pin and the P81/CS3/IRQ1 pin may both become low-level outputs
simultaneously.
Note: * When the DRAM enable bit (DRAME) or PSRAM enable bit (PSRAME) in the refresh
control register (RFSHCR) is cleared to 0 after being set to 1.
Address bus
Area 3 start address
P80/RFSH/IRQ0
P81/CS3/IRQ1
Figure 7.23 Operation when DRAM/PSRAM Connection is Switched
• Refresh cycles are not executed while the bus is released, during software standby mode, and
when a bus cycle is greatly prolonged by insertion of wait states. When these conditions occur,
other means of refreshing are required.
• If refresh requests occur while the bus is released, the first request is held and one refresh cycle
is executed after the bus-released state ends. Figure 7.24 shows the bus cycles in this case.
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Section 7 Refresh Controller
Bus-released state
Refresh cycle
CPU cycle
Refresh cycle
φ
RFSH
Refresh
request
BACK
Figure 7.24 Refresh Cycles when Bus is Released
• If a bus cycle is prolonged by insertion of wait states, the first refresh request is held, as in the
bus-released state.
• If there is contention with a bus request from an external bus master when making a transition
to software standby mode, a one-state bus-released state may occur immediately before the
transition to software standby mode (see figure 7.25).
When using software standby mode, clear the BRLE bit to 0 in BRCR before executing the
SLEEP instruction.
When making a transition to self-refresh mode, the strobe waveform output may not be
guaranteed due to the same kind of contention. This, too, can be prevented by clearing the
BRLE bit to 0 in BRCR.
External bus
released state
Software standby mode
φ
BREQ
BACK
Address bus
Strobe
Figure 7.25 Contention between Bus-Released State and Software Standby Mode
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Section 8 DMA Controller
Section 8 DMA Controller
8.1
Overview
The H8/3048 Group has an on-chip DMA controller (DMAC) that can transfer data on up to four
channels.
When the DMA controller is not used, it can be independently halted to conserve power. For
details see section 21.6, Module Standby Function.
8.1.1
Features
DMAC features are listed below.
• Selection of short address mode or full address mode
Short address mode
8-bit source address and 24-bit destination address, or vice versa
Maximum four channels available
Selection of I/O mode, idle mode, or repeat mode
Full address mode
24-bit source and destination addresses
Maximum two channels available
Selection of normal mode or block transfer mode
• Directly addressable 16-Mbyte address space
• Selection of byte or word transfer
• Activation by internal interrupts, external requests, or auto-request (depending on transfer
mode)
16-bit integrated timer unit (ITU) compare match/input capture interrupts (four)
Serial communication interface (SCI channel 0) transmit-data-empty/receive-data-full
interrupts
External requests
Auto-request
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Section 8 DMA Controller
8.1.2
Block Diagram
Figure 8.1 shows a DMAC block diagram.
Internal address bus
Address buffer
IMIA0
IMIA1
IMIA2
IMIA3
TXI0
RXI0
DREQ0
DREQ1
TEND0
TEND1
Arithmetic-logic unit
MAR0A
Channel
0A
Control logic
Channel
0
MAR0B
Channel
0B
DTCR0A
Interrupt DEND0A
signals
DEND0B
DEND1A
DEND1B
ETCR0B
Channel
1A
DTCR1A
MAR1B
Internal data bus
Legend
DTCR: Data transfer control register
MAR: Memory address register
IOAR: I/O address register
ETCR: Execute transfer count register
Figure 8.1 Block Diagram of DMAC
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IOAR1A
ETCR1A
Channel
1
Channel
1B
Data buffer
IOAR0B
MAR1A
DTCR0B
DTCR1B
IOAR0A
ETCR0A
IOAR1B
ETCR1B
Module data bus
Internal
interrupts
Section 8 DMA Controller
8.1.3
Functional Overview
Table 8.1 gives an overview of the DMAC functions.
Table 8.1
DMAC Functional Overview
Address
Reg. Length
Transfer Mode
Activation
Source
Destination
Short
address
mode
•
Compare match/
input capture A
interrupts from ITU
channels 0 to 3
24
8
•
Transmit-data-empty
interrupt from SCI
channel 0
•
Receive-data-full
interrupt from SCI
channel 0
8
24
•
External request
24
8
I/O mode
•
Transfers one byte or one word
per request
•
Increments or decrements the
memory address by 1 or 2
•
Executes 1 to 65,536 transfers
Idle mode
•
Transfers one byte or one word
per request
•
Holds the memory address fixed
•
Executes 1 to 65,536 transfers
Repeat mode
•
Transfers one byte or one word per
request
•
Increments or decrements the
memory address by 1 or 2
•
Executes a specified number (1 to
255) of transfers, then returns to
the initial state and continues
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Section 8 DMA Controller
Address
Reg. Length
Transfer Mode
Activation
Source
Destination
Full
address
mode
Normal mode
•
Auto-request
24
24
•
•
External request
•
Compare match/
input capture A
interrupts from ITU
channels 0 to 3
24
24
•
External request
Auto-request
Retains the transfer request
internally
Executes a specified number
(1 to 65,536) of transfers
continuously
Selection of burst mode or
cycle-steal mode
•
External request
Transfers one byte or one
word per request
Executes 1 to 65,536 transfers
Block transfer
•
Transfers one block of a specified
size per request
•
Executes 1 to 65,536 transfers
•
Allows either the source or
destination to be a fixed block
area
•
Block size can be 1 to 255 bytes
or words
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Section 8 DMA Controller
8.1.4
Input/Output Pins
Table 8.2 lists the DMAC pins.
Table 8.2
DMAC Pins
Channel
Name
Abbreviation
Input/
Output
Function
0
DMA request 0
DREQ0
Input
External request for DMAC channel 0
Transfer end 0
TEND0
Output
Transfer end on DMAC channel 0
DMA request 1
DREQ1
Input
External request for DMAC channel 1
Transfer end 1
TEND1
Output
Transfer end on DMAC channel 1
1
Note: External requests cannot be made to channel A in short address mode.
8.1.5
Register Configuration
Table 8.3 lists the DMAC registers.
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Section 8 DMA Controller
Table 8.3
DMAC Registers
Channel
Address* Name
Abbreviation
R/W
Initial Value
0
H'FF20
Memory address register 0AR
MAR0AR
R/W
Undetermined
H'FF21
Memory address register 0AE
MAR0AE
R/W
Undetermined
H'FF22
Memory address register 0AH
MAR0AH
R/W
Undetermined
H'FF23
Memory address register 0AL
MAR0AL
R/W
Undetermined
H'FF26
I/O address register 0A
IOAR0A
R/W
Undetermined
H'FF24
Execute transfer count register 0AH ETCR0AH
R/W
Undetermined
H'FF25
Execute transfer count register 0AL ETCR0AL
R/W
Undetermined
1
H'FF27
Data transfer control register 0A
DTCR0A
R/W
H'00
H'FF28
Memory address register 0BR
MAR0BR
R/W
Undetermined
H'FF29
Memory address register 0BE
MAR0BE
R/W
Undetermined
H'FF2A
Memory address register 0BH
MAR0BH
R/W
Undetermined
H'FF2B
Memory address register 0BL
MAR0BL
R/W
Undetermined
H'FF2E
I/O address register 0B
IOAR0B
R/W
Undetermined
H'FF2C
Execute transfer count register 0BH ETCR0BH
R/W
Undetermined
H'FF2D
Execute transfer count register 0BL ETCR0BL
R/W
Undetermined
H'FF2F
Data transfer control register 0B
DTCR0B
R/W
H'00
H'FF30
Memory address register 1AR
MAR1AR
R/W
Undetermined
H'FF31
Memory address register 1AE
MAR1AE
R/W
Undetermined
H'FF32
Memory address register 1AH
MAR1AH
R/W
Undetermined
H'FF33
Memory address register 1AL
MAR1AL
R/W
Undetermined
H'FF36
I/O address register 1A
IOAR1A
R/W
Undetermined
H'FF34
Execute transfer count register 1AH ETCR1AH
R/W
Undetermined
H'FF35
Execute transfer count register 1AL ETCR1AL
R/W
Undetermined
H'FF37
Data transfer control register 1A
DTCR1A
R/W
H'00
H'FF38
Memory address register 1BR
MAR1BR
R/W
Undetermined
H'FF39
Memory address register 1BE
MAR1BE
R/W
Undetermined
H'FF3A
Memory address register 1BH
MAR1BH
R/W
Undetermined
H'FF3B
Memory address register 1BL
MAR1BL
R/W
Undetermined
H'FF3E
I/O address register 1B
IOAR1B
R/W
Undetermined
H'FF3C
Execute transfer count register 1BH ETCR1BH
R/W
Undetermined
H'FF3D
Execute transfer count register 1BL ETCR1BL
R/W
Undetermined
H'FF3F
Data transfer control register 1B
R/W
H'00
Note: * The lower 16 bits of the address are indicated.
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DTCR1B
Section 8 DMA Controller
8.2
Register Descriptions (Short Address Mode)
In short address mode, transfers can be carried out independently on channels A and B. Short
address mode is selected by bits DTS2A and DTS1A in data transfer control register A (DTCRA)
as indicated in table 8.4.
Table 8.4
Selection of Short and Full Address Modes
Channel
Bit 2:
DTS2A
Bit 1:
DTS1A
0
1
1
1
Other than above
DMAC channels 0A and 0B operate as two independent
channels in short address mode
1
DMAC channel 1 operates as one channel in full address
mode
1
Other than above
8.2.1
Description
DMAC channel 0 operates as one channel in full address
mode
DMAC channels 1A and 1B operate as two independent
channels in short address mode
Memory Address Registers (MAR)
A memory address register (MAR) is a 32-bit readable/writable register that specifies a source or
destination address. The transfer direction is determined automatically from the activation source.
An MAR consists of four 8-bit registers designated MARR, MARE, MARH, and MARL. All bits
of MARR are reserved: they cannot be modified and are always read as 1.
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Initial value
1
Read/Write
— — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
1
1
1
1
MARR
1
1
1
8
7
6
5
4
3
2
1
0
Undetermined
MARE
MARH
MARL
Source or destination address
An MAR functions as a source or destination address register depending on how the DMAC is
activated: as a destination address register if activation is by a receive-data-full interrupt from the
serial communication interface (SCI) (channel 0), and as a source address register otherwise.
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Section 8 DMA Controller
The MAR value is incremented or decremented each time one byte or word is transferred,
automatically updating the source or destination memory address. For details, see section 8.2.4,
Data Transfer Control Registers (DTCR).
The MARs are not initialized by a reset or in standby mode.
8.2.2
I/O Address Registers (IOAR)
An I/O address register (IOAR) is an 8-bit readable/writable register that specifies a source or
destination address. The IOAR value is the lower 8 bits of the address. The upper 16 address bits
are all 1 (H'FFFF).
Bit
7
6
5
3
2
1
0
R/W
R/W
R/W
Undetermined
Initial value
Read/Write
4
R/W
R/W
R/W
R/W
R/W
Source or destination address
An IOAR functions as a source or destination address register depending on how the DMAC is
activated: as a source address register if activation is by a receive-data-full interrupt from the SCI
(channel 0), and as a destination address register otherwise.
The IOAR value is held fixed. It is not incremented or decremented when a transfer is executed.
The IOARs are not initialized by a reset or in standby mode.
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Section 8 DMA Controller
8.2.3
Execute Transfer Count Registers (ETCR)
An execute transfer count register (ETCR) is a 16-bit readable/writable register that specifies the
number of transfers to be executed. These registers function in one way in I/O mode and idle
mode, and another way in repeat mode.
• I/O mode and idle mode
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
Undetermined
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Transfer counter
In I/O mode and idle mode, ETCR functions as a 16-bit counter. The count is decremented by
1 each time one transfer is executed. The transfer ends when the count reaches H'0000.
• Repeat mode
Bit
7
6
5
Initial value
Read/Write
4
3
2
1
0
R/W
R/W
R/W
2
1
0
R/W
R/W
R/W
Undetermined
R/W
R/W
R/W
R/W
R/W
ETCRH
Transfer counter
Bit
7
6
5
R/W
R/W
R/W
Initial value
Read/Write
4
3
Undetermined
R/W
R/W
ETCRL
Initial count
In repeat mode, ETCRH functions as an 8-bit transfer counter and ETCRL holds the initial
transfer count. ETCRH is decremented by 1 each time one transfer is executed. When ETCRH
reaches H'00, the value in ETCRL is reloaded into ETCRH and the same operation is repeated.
The ETCRs are not initialized by a reset or in standby mode.
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Section 8 DMA Controller
8.2.4
Data Transfer Control Registers (DTCR)
A data transfer control register (DTCR) is an 8-bit readable/writable register that controls the
operation of one DMAC channel.
Bit
7
6
5
4
3
2
1
0
DTE
DTSZ
DTID
RPE
DTIE
DTS2
DTS1
DTS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data transfer enable
Enables or disables
data transfer
Data transfer select
These bits select the data
transfer activation source
Data transfer size
Selects byte or
word size
Data transfer interrupt enable
Enables or disables the CPU interrupt
at the end of the transfer
Data transfer
increment/decrement
Selects whether to
increment or decrement
the memory address
register
Repeat enable
Selects repeat
mode
The DTCRs are initialized to H'00 by a reset and in standby mode.
Bit 7—Data Transfer Enable (DTE): Enables or disables data transfer on a channel. When the
DTE bit is set to 1, the channel waits for a transfer to be requested, and executes the transfer when
activated as specified by bits DTS2 to DTS0. When DTE is 0, the channel is disabled and does not
accept transfer requests. DTE is set to 1 by reading the register when DTE is 0, then writing 1.
Bit 7: DTE
Description
0
Data transfer is disabled. In I/O mode or idle mode, DTE is cleared to 0 when
the specified number of transfers have been completed.
(Initial value)
1
Data transfer is enabled
If DTIE is set to 1, a CPU interrupt is requested when DTE is cleared to 0.
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Section 8 DMA Controller
Bit 6—Data Transfer Size (DTSZ): Selects the data size of each transfer.
Bit 6: DTSZ
Description
0
Byte-size transfer
1
Word-size transfer
(Initial value)
Bit 5—Data Transfer Increment/Decrement (DTID): Selects whether to increment or
decrement the memory address register (MAR) after a data transfer in I/O mode or repeat mode.
Bit 5: DTID
Description
0
MAR is incremented after each data transfer
1
•
If DTSZ = 0, MAR is incremented by 1 after each transfer
•
If DTSZ = 1, MAR is incremented by 2 after each transfer
MAR is decremented after each data transfer
•
If DTSZ = 0, MAR is decremented by 1 after each transfer
•
If DTSZ = 1, MAR is decremented by 2 after each transfer
MAR is not incremented or decremented in idle mode.
Bit 4—Repeat Enable (RPE): Selects whether to transfer data in I/O mode, idle mode, or repeat
mode.
Bit 4: RPE
Bit 3: DTIE
Description
0
0
I/O mode
(Initial value)
1
1
0
Repeat mode
1
Idle mode
Operations in these modes are described in sections 8.4.2, I/O Mode, 8.4.3, Idle Mode, and 8.4.4,
Repeat Mode.
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Section 8 DMA Controller
Bit 3—Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND)
requested when the DTE bit is cleared to 0.
Bit 3: DTIE
Description
0
The DEND interrupt requested by DTE is disabled
1
The DEND interrupt requested by DTE is enabled
(Initial value)
Bits 2 to 0—Data Transfer Select (DTS2, DTS1, DTS0): These bits select the data transfer
activation source. Some of the selectable sources differ between channels A and B.*
Note: * Refer to section 8.3.4, Data Transfer Control Registers (DTCR).
Bit 2: DTS2
Bit 1: DTS1
Bit 0: DTS0
Description
0
0
0
Compare match/input capture A interrupt from ITU
channel 0
(Initial value)
1
Compare match/input capture A interrupt from ITU
channel 1
0
Compare match/input capture A interrupt from ITU
channel 2
1
Compare match/input capture A interrupt from ITU
channel 3
0
Transmit-data-empty interrupt from SCI channel 0
1
Receive-data-full interrupt from SCI channel 0
0
Falling edge of DREQ input (channel B)
1
1
0
1
Transfer in full address mode (channel A)
1
Low level of DREQ input (channel B)
Transfer in full address mode (channel A)
The same internal interrupt can be selected as an activation source for two or more channels at
once. In that case the channels are activated in a priority order, highest-priority channel first. For
the priority order, see section 8.4.9, DMAC Multiple-Channel Operation.
When a channel is enabled (DTE = 1), its selected DMAC activation source cannot generate a
CPU interrupt.
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Section 8 DMA Controller
8.3
Register Descriptions (Full Address Mode)
In full address mode the A and B channels operate together. Full address mode is selected as
indicated in table 8.4.
8.3.1
Memory Address Registers (MAR)
A memory address register (MAR) is a 32-bit readable/writable register. MARA functions as the
source address register of the transfer, and MARB as the destination address register.
An MAR consists of four 8-bit registers designated MARR, MARE, MARH, and MARL. All bits
of MARR are reserved: they cannot be modified and are always read as 1.
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Initial value
1
Read/Write
— — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
1
1
1
1
MARR
1
1
1
8
7
6
5
4
3
2
1
0
Undetermined
MARE
MARH
MARL
Source or destination address
The MAR value is incremented or decremented each time one byte or word is transferred,
automatically updating the source or destination memory address. For details, see section 8.3.4,
Data Transfer Control Registers (DTCR).
The MARs are not initialized by a reset or in standby mode.
8.3.2
I/O Address Registers (IOAR)
The I/O address registers (IOARs) are not used in full address mode.
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Section 8 DMA Controller
8.3.3
Execute Transfer Count Registers (ETCR)
An execute transfer count register (ETCR) is a 16-bit readable/writable register that specifies the
number of transfers to be executed. The functions of these registers differ between normal mode
and block transfer mode.
• Normal mode
ETCRA
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
Undetermined
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Transfer counter
ETCRB: Is not used in normal mode.
In normal mode ETCRA functions as a 16-bit transfer counter. The count is decremented by 1
each time one transfer is executed. The transfer ends when the count reaches H'0000. ETCRB
is not used.
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Section 8 DMA Controller
• Block transfer mode
ETCRA
Bit
7
6
5
4
Initial value
Read/Write
3
2
1
0
R/W
R/W
R/W
2
1
0
R/W
R/W
R/W
Undetermined
R/W
R/W
R/W
R/W
R/W
ETCRAH
Block size counter
Bit
7
6
5
4
Initial value
Read/Write
3
Undetermined
R/W
R/W
R/W
R/W
R/W
ETCRAL
Initial block size
ETCRB
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
Undetermined
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Block transfer counter
In block transfer mode, ETCRAH functions as an 8-bit block size counter. ETCRAL holds the
initial block size. ETCRAH is decremented by 1 each time one byte or word is transferred.
When the count reaches H'00, ETCRAH is reloaded from ETCRAL. Blocks consisting of an
arbitrary number of bytes or words can be transferred repeatedly by setting the same initial
block size value in ETCRAH and ETCRAL.
In block transfer mode ETCRB functions as a 16-bit block transfer counter. ETCRB is
decremented by 1 each time one block is transferred. The transfer ends when the count reaches
H'0000.
The ETCRs are not initialized by a reset or in standby mode.
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Section 8 DMA Controller
8.3.4
Data Transfer Control Registers (DTCR)
The data transfer control registers (DTCRs) are 8-bit readable/writable registers that control the
operation of the DMAC channels. A channel operates in full address mode when bits DTS2A and
DTS1A are both set to 1 in DTCRA. DTCRA and DTCRB have different functions in full address
mode.
DTCRA
Bit
7
6
5
4
3
2
1
0
DTE
DTSZ
SAID
SAIDE
DTIE
DTS2A
DTS1A
DTS0A
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data transfer enable
Enables or disables
data transfer
Data transfer size
Selects byte or
word size
Data transfer
interrupt enable
Enables or disables the
CPU interrupt at the end
of the transfer
Source address
increment/decrement
Source address increment/
decrement enable
These bits select whether
the source address register
(MARA) is incremented,
decremented, or held fixed
during the data transfer
DTCRA is initialized to H'00 by a reset and in standby mode.
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Data transfer
select 0A
Selects block
transfer mode
Data transfer select
2A and 1A
These bits must both be
set to 1
Section 8 DMA Controller
Bit 7—Data Transfer Enable (DTE): Together with the DTME bit in DTCRB, this bit enables
or disables data transfer on the channel. When the DTME and DTE bits are both set to 1, the
channel is enabled. If auto-request is specified, data transfer begins immediately. Otherwise, the
channel waits for transfers to be requested. When the specified number of transfers have been
completed, the DTE bit is automatically cleared to 0. When DTE is 0, the channel is disabled and
does not accept transfer requests. DTE is set to 1 by reading the register when DTE is 0, then
writing 1.
Bit 7: DTE
Description
0
Data transfer is disabled (DTE is cleared to 0 when the specified number of
transfers have been completed)
(Initial value)
1
Data transfer is enabled
If DTIE is set to 1, a CPU interrupt is requested when DTE is cleared to 0.
Bit 6—Data Transfer Size (DTSZ): Selects the data size of each transfer.
Bit 6: DTSZ
Description
0
Byte-size transfer
1
Word-size transfer
(Initial value)
Bit 5—Source Address Increment/Decrement (SAID) and
Bit 4—Source Address Increment/Decrement Enable (SAIDE): These bits select whether the
source address register (MARA) is incremented, decremented, or held fixed during the data
transfer.
Bit 5: SAID
Bit 4: SAIDE
Description
0
0
MARA is held fixed
1
MARA is incremented after each data transfer
1
(Initial value)
•
If DTSZ = 0, MARA is incremented by 1 after each transfer
•
If DTSZ = 1, MARA is incremented by 2 after each transfer
0
MARA is held fixed
1
MARA is decremented after each data transfer
•
If DTSZ = 0, MARA is decremented by 1 after each
transfer
•
If DTSZ = 1, MARA is decremented by 2 after each
transfer
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Section 8 DMA Controller
Bit 3—Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND)
requested when the DTE bit is cleared to 0.
Bit 3: DTIE
Description
0
The DEND interrupt requested by DTE is disabled
1
The DEND interrupt requested by DTE is enabled
(Initial value)
Bits 2 and 1—Data Transfer Select 2A and 1A (DTS2A, DTS1A): A channel operates in full
address mode when DTS2A and DTS1A are both set to 1.
Bit 0—Data Transfer Select 0A (DTS0A): Selects normal mode or block transfer mode.
Bit 0: DTS0A
Description
0
Normal mode
1
Block transfer mode
(Initial value)
Operations in these modes are described in sections 8.4.5, Normal Mode, and 8.4.6, Block
Transfer Mode.
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Section 8 DMA Controller
DTCRB
Bit
7
6
5
4
3
2
1
0
DTME
—
DAID
DAIDE
TMS
DTS2B
DTS1B
DTS0B
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data transfer master enable
Enables or disables data
transfer, together with
the DTE bit, and is cleared
to 0 by an interrupt
Reserved bit
Transfer mode select
Selects whether the
block area is the source
or destination in block
transfer mode
Destination address
increment/decrement
Destination address
increment/decrement enable
These bits select whether
the destination address
register (MARB) is incremented,
decremented, or held fixed
during the data transfer
Data transfer select
2B to 0B
These bits select the data
transfer activation source
DTCRB is initialized to H'00 by a reset and in standby mode.
Bit 7—Data Transfer Master Enable (DTME): Together with the DTE bit in DTCRA, this bit
enables or disables data transfer. When the DTME and DTE bits are both set to 1, the channel is
enabled. When an NMI interrupt occurs DTME is cleared to 0, suspending the transfer so that the
CPU can use the bus. The suspended transfer resumes when DTME is set to 1 again. For further
information on operation in block transfer mode, see section 8.6.6, NMI Interrupts and Block
Transfer Mode.
DTME is set to 1 by reading the register while DTME = 0, then writing 1.
Bit 7: DTME
Description
0
Data transfer is disabled (DTME is cleared to 0 when an NMI interrupt occurs)
(Initial value)
1
Data transfer is enabled
Bit 6—Reserved: Although reserved, this bit can be written and read.
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Section 8 DMA Controller
Bit 5—Destination Address Increment/Decrement (DAID) and
Bit 4—Destination Address Increment/Decrement Enable (DAIDE): These bits select whether
the destination address register (MARB) is incremented, decremented, or held fixed during the
data transfer.
Bit 5: DAID
Bit 4: DAIDE
Description
0
0
MARB is held fixed
1
MARB is incremented after each data transfer
1
(Initial value)
•
If DTSZ = 0, MARB is incremented by 1 after each
data transfer
•
If DTSZ = 1, MARB is incremented by 2 after each
data transfe
0
MARB is held fixed
1
MARB is decremented after each data transfer
•
If DTSZ = 0, MARB is decremented by 1 after each
data transfer
•
If DTSZ = 1, MARB is decremented by 2 after each
data transfer
Bit 3—Transfer Mode Select (TMS): Selects whether the source or destination is the block area
in block transfer mode.
Bit 3: TMS
Description
0
Destination is the block area in block transfer mode
1
Source is the block area in block transfer mode
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(Initial value)
Section 8 DMA Controller
Bits 2 to 0—Data Transfer Select 2B to 0B (DTS2B, DTS1B, DTS0B): These bits select the
data transfer activation source. The selectable activation sources differ between normal mode and
block transfer mode.
• Normal mode
Bit 2:
DTS2B
Bit 1:
DTS1B
Bit 0:
DTS0B
Description
0
0
0
Auto-request (burst mode)
1
Cannot be used
1
0
Auto-request (cycle-steal mode)
1
Cannot be used
0
Cannot be used
1
Cannot be used
0
Falling edge of DREQ
1
Low level input at DREQ
1
0
1
(Initial value)
• Block transfer mode
Bit 2:
DTS2B
Bit 1:
DTS1B
Bit 0:
DTS0B
0
0
0
Compare match/input capture A interrupt from ITU
channel 0
(Initial value)
1
Compare match/input capture A interrupt from ITU
channel 1
0
Compare match/input capture A interrupt from ITU
channel 2
1
Compare match/input capture A interrupt from ITU
channel 3
0
0
Cannot be used
1
Cannot be used
1
0
Falling edge of DREQ
1
Cannot be used
1
1
Description
The same internal interrupt can be selected to activate two or more channels. The channels are
activated in a priority order, highest priority first. For the priority order, see section 8.4.9, DMAC
Multiple-Channel Operation.
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Section 8 DMA Controller
8.4
Operation
8.4.1
Overview
Table 8.5 summarizes the DMAC modes.
Table 8.5
DMAC Modes
Transfer Mode
Short address
mode
I/O mode
Idle mode
Repeat mode
Activation
Notes
Compare match/input
capture A interrupt from
ITU channels 0 to 3
•
Up to four channels can
operate independently
•
Only the B channels
support external requests
•
A and B channels are
paired; up to two channels
are available
Transmit-data-empty and
receive-data-full interrupts
from SCI channel 0
External request
Full address
mode
Normal mode
Auto-request
External request
Block transfer
mode
Compare match/input
capture A interrupt from ITU •
channels 0 to 3
External request
Burst mode or cycle-steal
mode can be selected for
auto-requests
A summary of operations in these modes follows.
I/O Mode: One byte or word is transferred per request. A designated number of these transfers are
executed. A CPU interrupt can be requested at completion of the designated number of transfers.
One 24-bit address and one 8-bit address are specified. The transfer direction is determined
automatically from the activation source.
Idle Mode: One byte or word is transferred per request. A designated number of these transfers
are executed. A CPU interrupt can be requested at completion of the designated number of
transfers. One 24-bit address and one 8-bit address are specified. The addresses are held fixed. The
transfer direction is determined automatically from the activation source.
Repeat Mode: One byte or word is transferred per request. A designated number of these transfers
are executed. When the designated number of transfers are completed, the initial address and
counter value are restored and operation continues. No CPU interrupt is requested. One 24-bit
address and one 8-bit address are specified. The transfer direction is determined automatically
from the activation source.
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Section 8 DMA Controller
Normal Mode
• Auto-request
The DMAC is activated by register setup alone, and continues executing transfers until the
designated number of transfers have been completed. A CPU interrupt can be requested at
completion of the transfers. Both addresses are 24-bit addresses.
Cycle-steal mode
The bus is released to another bus master after each byte or word is transferred.
Burst mode
Unless requested by a higher-priority bus master, the bus is not released until the
designated number of transfers have been completed.
• External request
One byte or word is transferred per request. A designated number of these transfers are
executed. A CPU interrupt can be requested at completion of the designated number of
transfers. Both addresses are 24-bit addresses.
Block Transfer Mode: One block of a specified size is transferred per request. A designated
number of block transfers are executed. At the end of each block transfer, one address is restored
to its initial value. When the designated number of blocks have been transferred, a CPU interrupt
can be requested. Both addresses are 24-bit addresses.
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Section 8 DMA Controller
8.4.2
I/O Mode
I/O mode can be selected independently for each channel.
One byte or word is transferred at each transfer request in I/O mode. A designated number of these
transfers are executed. One address is specified in the memory address register (MAR), the other
in the I/O address register (IOAR). The direction of transfer is determined automatically from the
activation source. The transfer is from the address specified in IOAR to the address specified in
MAR if activated by an SCI channel 0 receive-data-full interrupt, and from the address specified
in MAR to the address specified in IOAR otherwise.
Table 8.6 indicates the register functions in I/O mode.
Table 8.6
Register Functions in I/O Mode
Function
Activated by
SCI 0 ReceiveData-Full
Other
Interrupt
Activation
Register
23
7
All 1s
Destination
address
register
Source
address
register
Destination or
source address
Incremented or
decremented
once per
transfer
0
Source
address
register
Destination
address
register
Source or
destination
address
Held fixed
Transfer
counter
Transfer
counter
Number of
transfers
Decremented
once per
transfer until
H'0000 is
reached and
transfer ends
IOAR
15
0
ETCR
Operation
0
MAR
23
Initial Setting
Legend
MAR: Memory address register
IOAR: I/O address register
ETCR: Execute transfer count register
MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or
destination address, which is incremented or decremented as each byte or word is transferred.
IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all 1s. IOAR is not
incremented or decremented.
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Section 8 DMA Controller
Figure 8.2 illustrates how I/O mode operates.
Transfer
Address T
IOAR
1 byte or word is
transferred per request
Address B
Legend
L = initial setting of MAR
N = initial setting of ETCR
Address T = L
Address B = L + (–1) DTID • (2 DTSZ • N – 1)
Figure 8.2 Operation in I/O Mode
The transfer count is specified as a 16-bit value in ETCR. The ETCR value is decremented by 1 at
each transfer. When the ETCR value reaches H'0000, the DTE bit is cleared and the transfer ends.
If the DTIE bit is set to 1, a CPU interrupt is requested at this time. The maximum transfer count
is 65,536, obtained by setting ETCR to H'0000.
Transfers can be requested (activated) by compare match/input capture A interrupts from ITU
channels 0 to 3, transmit-data-empty and receive-data-full interrupts from SCI channel 0, and
external request signals.
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Section 8 DMA Controller
For the detailed settings see section 8.2.4, Data Transfer Control Registers (DTCR).
Figure 8.3 shows a sample setup procedure for I/O mode.
I/O mode setup
Set source and
destination addresses
1
Set transfer count
2
Read DTCR
3
Set DTCR
4
1. Set the source and destination addresses
in MAR and IOAR. The transfer direction is
determined automatically from the activation
source.
2. Set the transfer count in ETCR.
3. Read DTCR while the DTE bit is cleared to 0.
4. Set the DTCR bits as follows.
• Select the DMAC activation source with bits
DTS2 to DTS0.
• Set or clear the DTIE bit to enable or disable
the CPU interrupt at the end of the transfer.
• Clear the RPE bit to 0 to select I/O mode.
• Select MAR increment or decrement with the
DTID bit.
• Select byte size or word size with the DTSZ bit.
• Set the DTE bit to 1 to enable the transfer.
I/O mode
Figure 8.3 I/O Mode Setup Procedure (Example)
8.4.3
Idle Mode
Idle mode can be selected independently for each channel.
One byte or word is transferred at each transfer request in idle mode. A designated number of
these transfers are executed. One address is specified in the memory address register (MAR), the
other in the I/O address register (IOAR). The direction of transfer is determined automatically
from the activation source. The transfer is from the address specified in IOAR to the address
specified in MAR if activated by an SCI channel 0 receive-data-full interrupt, and from the
address specified in MAR to the address specified in IOAR otherwise.
Table 8.7 indicates the register functions in idle mode.
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Section 8 DMA Controller
Table 8.7
Register Functions in Idle Mode
Function
Activated by
SCI 0 ReceiveData-Full
Other
Interrupt
Activation
Register
23
7
All 1s
Destination
address
register
Source
address
register
Destination or
source address
Held fixed
0
Source
address
register
Destination
address
register
Source or
destination
address
Held fixed
Transfer
counter
Transfer
counter
Number of
transfers
Decremented
once per
transfer until
H'0000 is
reached and
transfer ends
IOAR
15
0
ETCR
Operation
0
MAR
23
Initial Setting
Legend
MAR: Memory address register
IOAR: I/O address register
ETCR: Execute transfer count register
MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or
destination address. IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all
1s. MAR and IOAR are not incremented or decremented.
Figure 8.4 illustrates how idle mode operates.
MAR
Transfer
IOAR
1 byte or word is
transferred per request
Figure 8.4 Operation in Idle Mode
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Section 8 DMA Controller
The transfer count is specified as a 16-bit value in ETCR. The ETCR value is decremented by 1 at
each transfer. When the ETCR value reaches H'0000, the DTE bit is cleared, the transfer ends, and
a CPU interrupt is requested. The maximum transfer count is 65,536, obtained by setting ETCR to
H'0000.
Transfers can be requested (activated) by compare match/input capture A interrupts from ITU
channels 0 to 3, transmit-data-empty and receive-data-full interrupts from SCI channel 0, and
external request signals.
For the detailed settings see section 8.2.4, Data Transfer Control Registers (DTCR).
Figure 8.5 shows a sample setup procedure for idle mode.
Idle mode setup
Set source and
destination addresses
1
Set transfer count
2
Read DTCR
3
Set DTCR
4
1. Set the source and destination addresses
in MAR and IOAR. The transfer direction is determined automatically from the activation source.
2. Set the transfer count in ETCR.
3. Read DTCR while the DTE bit is cleared to 0.
4. Set the DTCR bits as follows.
• Select the DMAC activation source with bits
DTS2 to DTS0.
• Set the DTIE and RPE bits to 1 to select idle mode.
• Select byte size or word size with the DTSZ bit.
• Set the DTE bit to 1 to enable the transfer.
Idle mode
Figure 8.5 Idle Mode Setup Procedure (Example)
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Section 8 DMA Controller
8.4.4
Repeat Mode
Repeat mode is useful for cyclically transferring a bit pattern from a table to the programmable
timing pattern controller (TPC) in synchronization, for example, with ITU compare match. Repeat
mode can be selected for each channel independently.
One byte or word is transferred per request in repeat mode, as in I/O mode. A designated number
of these transfers are executed. One address is specified in the memory address register (MAR),
the other in the I/O address register (IOAR). At the end of the designated number of transfers,
MAR and ETCR are restored to their original values and operation continues. The direction of
transfer is determined automatically from the activation source. The transfer is from the address
specified in IOAR to the address specified in MAR if activated by an SCI channel 0 receive-datafull interrupt, and from the address specified in MAR to the address specified in IOAR otherwise.
Table 8.8 indicates the register functions in repeat mode.
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Table 8.8
Register Functions in Repeat Mode
Function
Register
23
0
Activated by
SCI 0 ReceiveData-Full
Interrupt
Other
Activation
Destination
address
register
Initial Setting
Operation
Source
address
register
Destination or
source address
Incremented or
decremented at
each transfer
until H'0000,
then restored to
initial value
Source
address
register
Destination
address
register
Source or
destination
address
Held fixed
Transfer
counter
Transfer
counter
Number of
transfers
Decremented
once per
transfer until
H'0000 is
reached, then
reloaded from
ETCRL
Initial transfer
count
Initial transfer Number of
count
transfers
MAR
7
23
All 1s
0
IOAR
7
0
ETCRH
7
0
ETCRL
Held fixed
Legend
MAR: Memory address register
IOAR: I/O address register
ETCR: Execute transfer count register
In repeat mode ETCRH is used as the transfer counter while ETCRL holds the initial transfer
count. ETCRH is decremented by 1 at each transfer until it reaches H'00, then is reloaded from
ETCRL. MAR is also restored to its initial value, which is calculated from the DTSZ and DTID
bits in DTCR. Specifically, MAR is restored as follows:
MAR ← MAR – (–1)DTID · 2DTSZ · ETCRL
ETCRH and ETCRL should be initially set to the same value.
In repeat mode transfers continue until the CPU clears the DTE bit to 0. After DTE is cleared to 0,
if the CPU sets DTE to 1 again, transfers resume from the state at which DTE was cleared. No
CPU interrupt is requested.
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As in I/O mode, MAR and IOAR specify the source and destination addresses. MAR specifies a
24-bit source or destination address. IOAR specifies the lower 8 bits of a fixed address. The upper
16 bits are all 1s. IOAR is not incremented or decremented.
Figure 8.6 illustrates how repeat mode operates.
Address T
Transfer
IOAR
1 byte or word is
transferred per request
Address B
Legend
L = initial setting of MAR
N = initial setting of ETCRH and ETCRL
Address T = L
Address B = L + (–1) DTID • (2 DTSZ • N – 1)
Figure 8.6 Operation in Repeat Mode
The transfer count is specified as an 8-bit value in ETCRH and ETCRL. The maximum transfer
count is 255, obtained by setting both ETCRH and ETCRL to H'FF.
Transfers can be requested (activated) by compare match/input capture A interrupts from ITU
channels 0 to 3, transmit-data-empty and receive-data-full interrupts from SCI channel 0, and
external request signals.
For the detailed settings see section 8.2.4, Data Transfer Control Registers (DTCR).
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Figure 8.7 shows a sample setup procedure for repeat mode.
Repeat mode
Set source and
destination addresses
1
Set transfer count
2
Read DTCR
3
Set DTCR
4
1. Set the source and destination addresses in MAR
and IOAR. The transfer direction is determined
automatically from the activation source.
2. Set the transfer count in both ETCRH and ETCRL.
3. Read DTCR while the DTE bit is cleared to 0.
4. Set the DTCR bits as follows.
• Select the DMAC activation source with bits
DTS2 to DTS0.
• Clear the DTIE bit to 0 and set the RPE bit to 1
to select repeat mode.
• Select MAR increment or decrement with the
DTID bit.
• Select byte size or word size with the DTSZ bit.
• Set the DTE bit to 1 to enable the transfer.
Repeat mode
Figure 8.7 Repeat Mode Setup Procedure (Example)
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Section 8 DMA Controller
8.4.5
Normal Mode
In normal mode the A and B channels are combined. One byte or word is transferred per request.
A designated number of these transfers are executed. Addresses are specified in MARA and
MARB. Table 8.9 indicates the register functions in I/O mode.
Table 8.9
Register Functions in Normal Mode
Register
23
Function
Initial Setting
Operation
0
Source address
register
Source address
Incremented or
decremented once per
transfer, or held fixed
0
Destination
address register
Destination
address
Incremented or
decremented once per
transfer, or held fixed
0
Transfer counter
Number of
transfers
Decremented once per
transfer
MARA
23
MARB
15
ETCRA
Legend
MARA: Memory address register A
MARB: Memory address register B
ETCRA: Execute transfer count register A
The source and destination addresses are both 24-bit addresses. MARA specifies the source
address. MARB specifies the destination address. MARA and MARB can be independently
incremented, decremented, or held fixed as data is transferred.
The transfer count is specified as a 16-bit value in ETCRA. The ETCRA value is decremented by
1 at each transfer. When the ETCRA value reaches H'0000, the DTE bit is cleared and the transfer
ends. If the DTIE bit is set, a CPU interrupt is requested at this time. The maximum transfer count
is 65,536, obtained by setting ETCRA to H'0000.
Figure 8.8 illustrates how normal mode operates.
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Section 8 DMA Controller
Transfer
Address TA
Address BA
Address T B
Address B B
Legend
L A = initial setting of MARA
L B = initial setting of MARB
N = initial setting of ETCRA
TA = LA
BA = L A + SAIDE • (–1)SAID • (2 DTSZ • N – 1)
TB = LB
BB = L B + DAIDE • (–1)DAID • (2 DTSZ • N – 1)
Figure 8.8 Operation in Normal Mode
Transfers can be requested (activated) by an external request or auto-request. An auto-requested
transfer is activated by the register settings alone. The designated number of transfers are executed
automatically. Either cycle-steal or burst mode can be selected. In cycle-steal mode the DMAC
releases the bus temporarily after each transfer. In burst mode the DMAC keeps the bus until the
transfers are completed, unless there is a bus request from a higher-priority bus master.
For the detailed settings see section 8.3.4, Data Transfer Control Registers (DTCR).
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Figure 8.9 shows a sample setup procedure for normal mode.
Normal mode
Set initial source address
1
Set initial destination address
2
1.
2.
3.
4.
5.
Set transfer count
3
Set DTCRB (1)
4
Set DTCRA (1)
5
Read DTCRB
6
Set DTCRB (2)
7
Read DTCRA
8
Set DTCRA (2)
9
6.
7.
8.
9.
Set the initial source address in MARA.
Set the initial destination address in MARB.
Set the transfer count in ETCRA.
Set the DTCRB bits as follows.
• Clear the DTME bit to 0.
• Set the DAID and DAIDE bits to select whether
MARB is incremented, decremented, or held fixed.
• Select the DMAC activation source with bits
DTS2B to DTS0B.
Set the DTCRA bits as follows.
• Clear the DTE bit to 0.
• Select byte or word size with the DTSZ bit.
• Set the SAID and SAIDE bits to select whether
MARA is incremented, decremented, or held fixed.
• Set or clear the DTIE bit to enable or disable the
CPU interrupt at the end of the transfer.
• Clear the DTS0A bit to 0 and set the DTS2A
and DTS1A bits to 1 to select normal mode.
Read DTCRB with DTME cleared to 0.
Set the DTME bit to 1 in DTCRB.
Read DTCRA with DTE cleared to 0.
Set the DTE bit to 1 in DTCRA to enable the transfer.
Normal mode
Note: Carry out settings 1 to 9 with the DEND interrupt masked in the CPU.
If an NMI interrupt occurs during the setup procedure, it may clear the DTME bit to 0, in
which case the transfer will not start.
Figure 8.9 Normal Mode Setup Procedure (Example)
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Section 8 DMA Controller
8.4.6
Block Transfer Mode
In block transfer mode the A and B channels are combined. One block of a specified size is
transferred per request. A designated number of block transfers are executed. Addresses are
specified in MARA and MARB. The block area address can be either held fixed or cycled.
Table 8.10 indicates the register functions in block transfer mode.
Table 8.10 Register Functions in Block Transfer Mode
Register
23
Function
Initial Setting
Operation
0
Source address
register
Source address
Incremented or
decremented once per
transfer, or held fixed
0
Destination
address register
Destination
address
Incremented or
decremented once per
transfer, or held fixed
0
Block size
counter
Block size
Decremented once per
transfer until H'00 is
reached, then reloaded
from ETCRAL
Initial block size
Block size
Held fixed
Block transfer
counter
Number of block
transfers
Decremented once per
block transfer until H'0000
is reached and the
transfer ends
MARA
23
MARB
7
ETCRAH
7
0
ETCRAL
15
0
ETCRB
Legend
MARA:
MARB:
ETCRA:
ETCRB:
Memory address register A
Memory address register B
Execute transfer count register A
Execute transfer count register B
The source and destination addresses are both 24-bit addresses. MARA specifies the source
address. MARB specifies the destination address. MARA and MARB can be independently
incremented, decremented, or held fixed as data is transferred. One of these registers operates as a
block area register: even if it is incremented or decremented, it is restored to its initial value at the
end of each block transfer. The TMS bit in DTCRB selects whether the block area is the source or
destination.
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If M (1 to 255) is the size of the block transferred at each request and N (1 to 65,536) is the
number of blocks to be transferred, then ETCRAH and ETCRAL should initially be set to M and
ETCRB should initially be set to N.
Figure 8.10 illustrates how block transfer mode operates. In this figure, bit TMS is cleared to 0,
meaning the block area is the destination.
TA
Address T B
Transfer
Block 1
Block area
BA
Address B B
Block 2
M bytes or words are
transferred per request
Block N
Legend
L A = initial setting of MARA
L B = initial setting of MARB
M = initial setting of ETCRAH and ETCRAL
N = initial setting of ETCRB
T A = LA
B A = L A + SAIDE • (–1) SAID • (2 DTSZ • M – 1)
T B = LB
B B = L B + DAIDE • (–1)DAID • (2 DTSZ • M – 1)
Figure 8.10 Operation in Block Transfer Mode
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When activated by a transfer request, the DMAC executes a burst transfer. During the transfer
MARA and MARB are updated according to the DTCR settings, and ETCRAH is decremented.
When ETCRAH reaches H'00, it is reloaded from ETCRAL to restore the initial value. The
memory address register of the block area is also restored to its initial value, and ETCRB is
decremented. If ETCRB is not H'0000, the DMAC then waits for the next transfer request.
ETCRAH and ETCRAL should be initially set to the same value.
The above operation is repeated until ETCRB reaches H'0000, at which point the DTE bit is
cleared to 0 and the transfer ends. If the DTIE bit is set to 1, a CPU interrupt is requested at this
time.
Figure 8.11 shows examples of a block transfer with byte data size when the block area is the
destination. In (a) the block area address is cycled. In (b) the block area address is held fixed.
Transfers can be requested (activated) by compare match/input capture A interrupts from ITU
channels 0 to 3, and by external request signals.
For the detailed settings see section 8.3.4, Data Transfer Control Registers (DTCR).
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Start
(DTE = DTME = 1)
Transfer requested?
Start
(DTE = DTME = 1)
No
Transfer requested?
Yes
No
Yes
Get bus
Get bus
Read from MARA address
Read from MARA address
MARA = MARA + 1
MARA = MARA + 1
Write to MARB address
Write to MARB address
MARB = MARB + 1
ETCRAH = ETCRAH – 1
ETCRAH = ETCRAH – 1
No
ETCRAH = H'00
No
ETCRAH = H'00
Yes
Yes
Release bus
Release bus
ETCRAH = ETCRAL
MARB = MARB – ETCRAL
ETCRAH = ETCRAL
ETCRB = ETCRB – 1
ETCRB = ETCRB – 1
ETCRB = H'0000
No
ETCRB = H'0000
Yes
No
Yes
Clear DTE to 0 and end transfer
Clear DTE to 0 and end transfer
a. DTSZ = TMS = 0
SAID = DAID = 0
SAIDE = DAIDE = 1
b. DTSZ = TMS = 0
SAID = 0
SAIDE = 1
DAIDE = 0
Figure 8.11 Block Transfer Mode Flowcharts (Examples)
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Figure 8.12 shows a sample setup procedure for block transfer mode.
Block transfer mode
Set source address
1
Set destination address
2
Set block transfer count
3
Set block size
4
Set DTCRB (1)
5
Set DTCRA (1)
6
Read DTCRB
7
Set DTCRB (2)
8
Read DTCRA
9
Set DTCRA (2)
10
Set the source address in MARA.
Set the destination address in MARB.
Set the block transfer count in ETCRB.
Set the block size (number of bytes or words)
in both ETCRAH and ETCRAL.
5. Set the DTCRB bits as follows.
• Clear the DTME bit to 0.
• Set the DAID and DAIDE bits to select whether
MARB is incremented, decremented, or held fixed.
• Set or clear the TMS bit to make the block area
the source or destination.
• Select the DMAC activation source with bits
DTS2B to DTS0B.
6. Set the DTCRA bits as follows.
• Clear the DTE to 0.
• Select byte size or word size with the DTSZ bit.
• Set the SAID and SAIDE bits to select whether
MARA is incremented, decremented, or held fixed.
• Set or clear the DTIE bit to enable or disable the
CPU interrupt at the end of the transfer.
• Set bits DTS2A to DTS0A all to 1 to select
block transfer mode.
7. Read DTCRB with DTME cleared to 0.
8. Set the DTME bit to 1 in DTCRB.
9. Read DTCRA with DTE cleared to 0.
10. Set the DTE bit to 1 in DTCRA to enable
the transfer.
1.
2.
3.
4.
Block transfer mode
Note: Carry out settings 1 to 10 with the DEND interrupt masked in the CPU.
If an NMI interrupt occurs during the setup procedure, it may clear the DTME bit to 0, in
which case the transfer will not start.
Figure 8.12 Block Transfer Mode Setup Procedure (Example)
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Section 8 DMA Controller
8.4.7
DMAC Activation
The DMAC can be activated by an internal interrupt, external request, or auto-request. The
available activation sources differ depending on the transfer mode and channel as indicated in
table 8.11.
Table 8.11 DMAC Activation Sources
Short Address Mode
Channels
0A and 1A
Channels
0B and 1B
Normal
Block
IMIA0
Yes
Yes
No
Yes
IMIA1
Yes
Yes
No
Yes
IMIA2
Yes
Yes
No
Yes
IMIA3
Yes
Yes
No
Yes
TXI0
Yes
Yes
No
No
RXI0
Yes
Yes
No
No
Falling edge of
DREQ
No
Yes
Yes
Yes
Low input at
DREQ
No
Yes
Yes
No
No
No
Yes
No
Activation Source
Internal
interrupts
External
requests
Auto-request
Full Address Mode
Activation by Internal Interrupts: When an interrupt request is selected as a DMAC activation
source and the DTE bit is set to 1, that interrupt request is not sent to the CPU. It is not possible
for an interrupt request to activate the DMAC and simultaneously generate a CPU interrupt.
When the DMAC is activated by an interrupt request, the interrupt request flag is cleared
automatically. If the same interrupt is selected to activate two or more channels, the interrupt
request flag is cleared when the highest-priority channel is activated, but the transfer request is
held pending on the other channels in the DMAC, which are activated in their priority order.
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Activation by External Request: If an external request (DREQ pin) is selected as an activation
source, the DREQ pin becomes an input pin and the corresponding TEND pin becomes an output
pin, regardless of the port data direction register (DDR) settings. The DREQ input can be levelsensitive or edge-sensitive.
In short address mode and normal mode, an external request operates as follows. If edge sensing is
selected, one byte or word is transferred each time a high-to-low transition of the DREQ input is
detected. If the next edge is input before the transfer is completed, the next transfer may not be
executed. If level sensing is selected, the transfer continues while DREQ is low, until the transfer
is completed. The bus is released temporarily after each byte or word has been transferred,
however. If the DREQ input goes high during a transfer, the transfer is suspended after the current
byte or word has been transferred. When DREQ goes low, the request is held internally until one
byte or word has been transferred. The TEND signal goes low during the last write cycle.
In block transfer mode, an external request operates as follows. Only edge-sensitive transfer
requests are possible in block transfer mode. Each time a high-to-low transition of the DREQ
input is detected, a block of the specified size is transferred. The TEND signal goes low during the
last write cycle in each block.
Activation by Auto-Request: The transfer starts as soon as enabled by register setup, and
continues until completed. Cycle-steal mode or burst mode can be selected.
In cycle-steal mode the DMAC releases the bus temporarily after transferring each byte or word.
Normally, DMAC cycles alternate with CPU cycles.
In burst mode the DMAC keeps the bus until the transfer is completed, unless there is a higherpriority bus request. If there is a higher-priority bus request, the bus is released after the current
byte or word has been transferred.
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Section 8 DMA Controller
8.4.8
DMAC Bus Cycle
Figure 8.13 shows an example of the timing of the basic DMAC bus cycle. This example shows a
word-size transfer from a 16-bit two-state access area to an 8-bit three-state access area. When the
DMAC gets the bus from the CPU, after one dead cycle (Td), it reads from the source address and
writes to the destination address. During these read and write operations the bus is not released
even if there is another bus request. DMAC cycles comply with bus controller settings in the same
way as CPU cycles.
CPU cycle
T1
T2
T1
DMAC cycle (word transfer)
T2
Td
T1
T2
T1
T2
T3
T1
T2
CPU cycle
T3
T1
T2
T1
T2
φ
Source
address
Destination address
Address
bus
RD
HWR
LWR
Figure 8.13 DMA Transfer Bus Timing (Example)
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Figure 8.14 shows the timing when the DMAC is activated by low input at a DREQ pin. This
example shows a word-size transfer from a 16-bit two-state access area to another 16-bit two-state
access area. The DMAC continues the transfer while the DREQ pin is held low.
CPU cycle
T1
T2
T3
DMAC cycle
Td
T1
T2
T1
DMAC cycle
(last transfer cycle)
CPU cycle
T2
T1
T2
Td
T1
T2
T1
T2
CPU cycle
T1
φ
DREQ
Source Destination
address address
Source Destination
address address
Address
bus
RD
HWR , LWR
TEND
Figure 8.14 Bus Timing of DMA Transfer Requested by Low DREQ Input
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Section 8 DMA Controller
Figure 8.15 shows an auto-requested burst-mode transfer. This example shows a transfer of three
words from a 16-bit two-state access area to another 16-bit two-state access area.
CPU cycle
T1
T2
DMAC cycle
Td
T1
T2
T1
T2
T1
T2
T1
CPU cycle
T2
T1
T2
T1
T2
T1
T2
φ
Source
address
Destination
address
Address
bus
RD
HWR ,
LWR
Figure 8.15 Bus Timing of Burst Mode DMA Transfer
When the DMAC is activated from a DREQ pin there is a minimum interval of four states from
when the transfer is requested until the DMAC starts operating. The DREQ pin is not sampled
during the time between the transfer request and the start of the transfer. In short address mode and
normal mode, the pin is next sampled at the end of the read cycle. In block transfer mode, the pin
is next sampled at the end of one block transfer.
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Figure 8.16 shows the timing when the DMAC is activated by the falling edge of DREQ in normal
mode.
CPU cycle
T2
T1
T2
T1
CPU
cycle
DMAC cycle
T2
Td
T1
T2
T1
T2
T1
T2
DMAC cycle
Td
T1
T2
DREQ
Address
bus
RD
HWR, LWR
Minimum 4 states
Next sampling point
Figure 8.16 Timing of DMAC Activation by Falling Edge of DREQ in Normal Mode
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Section 8 DMA Controller
Figure 8.17 shows the timing when the DMAC is activated by level-sensitive low DREQ input in
normal mode.
CPU cycle
T2
T1
T2
T1
DMAC cycle
T2
Td
T1
T2
T1
CPU cycle
T2
T1
T2
T1
T2
T1
φ
DREQ
Address
bus
RD
HWR , LWR
Minimum 4 states
Next sampling point
Figure 8.17 Timing of DMAC Activation by Low DREQ Level in Normal Mode
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Section 8 DMA Controller
Figure 8.18 shows the timing when the DMAC is activated by the falling edge of DREQ in block
transfer mode.
End of 1 block transfer
DMAC cycle
T1
T2
T1
T2
T1
CPU cycle
T2
T1
T2
T1
T2
T1
T2
DMAC cycle
Td
T1
T2
φ
DREQ
Address
bus
RD
HWR , LWR
TEND
Next sampling
Minimum 4 states
Figure 8.18 Timing of DMAC Activation by Falling Edge of DREQ in Block Transfer Mode
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Section 8 DMA Controller
8.4.9
DMAC Multiple-Channel Operation
The DMAC channel priority order is: channel 0 > channel 1 and channel A > channel B.
Table 8.12 shows the complete priority order.
Table 8.12 Channel Priority Order
Short Address Mode
Full Address Mode
Priority
Channel 0A
Channel 0
High
Channel 0B
Channel 1A
Channel 1B
Channel 1
↑
Low
If transfers are requested on two or more channels simultaneously, or if a transfer on one channel
is requested during a transfer on another channel, the DMAC operates as follows.
1. When a transfer is requested, the DMAC requests the bus right. When it gets the bus right, it
starts a transfer on the highest-priority channel at that time.
2. Once a transfer starts on one channel, requests to other channels are held pending until that
channel releases the bus.
3. After each transfer in short address mode, and each externally-requested or cycle-steal transfer
in normal mode, the DMAC releases the bus and returns to step 1. After releasing the bus, if
there is a transfer request for another channel, the DMAC requests the bus again.
4. After completion of a burst-mode transfer, or after transfer of one block in block transfer
mode, the DMAC releases the bus and returns to step 1. If there is a transfer request for a
higher-priority channel or a bus request from a higher-priority bus master, however, the
DMAC releases the bus after completing the transfer of the current byte or word. After
releasing the bus, if there is a transfer request for another channel, the DMAC requests the bus
again.
Figure 8.19 shows the timing when channel 0A is set up for I/O mode and channel 1 for burst
mode, and a transfer request for channel 0A is received while channel 1 is active.
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Section 8 DMA Controller
DMAC cycle
(channel 1)
T1
T2
CPU
cycle
T1
T2
DMAC cycle
(channel 0A)
Td
T1
T2
T1
CPU
cycle
T2
T1
T2
DMAC cycle
(channel 1)
Td
T1
T2
T1
T2
φ
Address
bus
RD
HWR ,
LWR
Figure 8.19 Timing of Multiple-Channel Operations
8.4.10
External Bus Requests, Refresh Controller, and DMAC
During a DMA transfer, if the bus right is requested by an external bus request signal (BREQ) or
by the refresh controller, the DMAC releases the bus after completing the transfer of the current
byte or word. If there is a transfer request at this point, the DMAC requests the bus right again.
Figure 8.20 shows an example of the timing of insertion of a refresh cycle during a burst transfer
on channel 0.
Refresh
cycle
DMAC cycle (channel 0)
T1
T2
T1
T2
T1
T2
T1
T2
T1
T2
DMAC cycle (channel 0)
Td
T1
T2
T1
φ
Address
bus
RD
HWR , LWR
Figure 8.20 Bus Timing of Refresh Controller and DMAC
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T2
T1
T2
Section 8 DMA Controller
8.4.11
NMI Interrupts and DMAC
NMI interrupts do not affect DMAC operations in short address mode.
If an NMI interrupt occurs during a transfer in full address mode, the DMAC suspends operations.
In full address mode, a channel is enabled when its DTE and DTME bits are both set to 1. NMI
input clears the DTME bit to 0. After transferring the current byte or word, the DMAC releases the
bus to the CPU. In normal mode, the suspended transfer resumes when the CPU sets the DTME
bit to 1 again. Check that the DTE bit is set to 1 and the DTME bit is cleared to 0 before setting
the DTME bit to 1.
Figure 8.21 shows the procedure for resuming a DMA transfer in normal mode on channel 0 after
the transfer was halted by NMI input.
Resuming DMA transfer
in normal mode
1. Check that DTE = 1 and DTME = 0.
2. Read DTCRB while DTME = 0,
then write 1 in the DTME bit.
1
DTE = 1
DTME = 0
No
Yes
Set DTME to 1
DMA transfer continues
2
End
Figure 8.21 Procedure for Resuming a DMA Transfer Halted by NMI (Example)
For information about NMI interrupts in block transfer mode, see section 8.6.6, NMI Interrupts
and Block Transfer Mode.
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Section 8 DMA Controller
8.4.12
Aborting a DMA Transfer
When the DTE bit in an active channel is cleared to 0, the DMAC halts after transferring the
current byte or word. The DMAC starts again when the DTE bit is set to 1. In full address mode,
the DTME bit can be used for the same purpose. Figure 8.22 shows the procedure for aborting a
DMA transfer by software.
DMA transfer abort
Set DTCR
1. Clear the DTE bit to 0 in DTCR.
To avoid generating an interrupt when
aborting a DMA transfer, clear the DTIE
bit to 0 simultaneously.
1
DMA transfer aborted
Figure 8.22 Procedure for Aborting a DMA Transfer
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Section 8 DMA Controller
8.4.13
Exiting Full Address Mode
Figure 8.23 shows the procedure for exiting full address mode and initializing the pair of channels.
To set the channels up in another mode after exiting full address mode, follow the setup procedure
for the relevant mode.
Exiting full address mode
Halt the channel
1
Initialize DTCRB
2
Initialize DTCRA
3
1. Clear the DTE bit to 0 in DTCRA, or wait
for the transfer to end and the DTE bit
to be cleared to 0.
2. Clear all DTCRB bits to 0.
3. Clear all DTCRA bits to 0.
Initialized and halted
Figure 8.23 Procedure for Exiting Full Address Mode (Example)
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Section 8 DMA Controller
8.4.14
DMAC States in Reset State, Standby Modes, and Sleep Mode
When the chip is reset or enters hardware or software standby mode, the DMAC is initialized and
halts. DMAC operations continue in sleep mode. Figure 8.24 shows the timing of a cycle-steal
transfer in sleep mode.
Sleep mode
CPU cycle
T2
DMAC cycle
Td
T1
T2
T1
DMAC cycle
T2
Td
T1
T2
T1
T2
φ
Address bus
RD
HWR , LWR
Figure 8.24 Timing of Cycle-Steal Transfer in Sleep Mode
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Td
Section 8 DMA Controller
8.5
Interrupts
The DMAC generates only DMA-end interrupts. Table 8.13 lists the interrupts and their priority.
Table 8.13 DMAC Interrupts
Description
Interrupt
Short Address Mode
Full Address Mode
Interrupt
Priority
DEND0A
End of transfer on channel 0A
End of transfer on channel 0
High
DEND0B
End of transfer on channel 0B
—
DEND1A
End of transfer on channel 1A
End of transfer on channel 1
DEND1B
End of transfer on channel 1B
—
↑
Low
Each interrupt is enabled or disabled by the DTIE bit in the corresponding data transfer control
register (DTCR). Separate interrupt signals are sent to the interrupt controller.
The interrupt priority order among channels is channel 0 > channel 1 and channel A > channel B.
Figure 8.25 shows the DMA-end interrupt logic. An interrupt is requested whenever DTE = 0 and
DTIE = 1.
DTE
DMA-end interrupt
DTIE
Figure 8.25 DMA-End Interrupt Logic
The DMA-end interrupt for the B channels (DENDB) is unavailable in full address mode. The
DTME bit does not affect interrupt operations.
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Section 8 DMA Controller
8.6
Usage Notes
8.6.1
Note on Word Data Transfer
Word data cannot be accessed starting at an odd address. When word-size transfer is selected, set
even values in the memory and I/O address registers (MAR and IOAR).
8.6.2
DMAC Self-Access
The DMAC itself cannot be accessed during a DMAC cycle. DMAC registers cannot be specified
as source or destination addresses.
8.6.3
Longword Access to Memory Address Registers
A memory address register can be accessed as longword data at the MARR address.
Example
MOV.L
MOV.L
#LBL, ER0
ER0, @MARR
Four byte accesses are performed. Note that the CPU may release the bus between the second byte
(MARE) and third byte (MARH).
Memory address registers should be written and read only when the DMAC is halted.
8.6.4
Note on Full Address Mode Setup
Full address mode is controlled by two registers: DTCRA and DTCRB. Care must be taken to
prevent the B channel from operating in short address mode during the register setup. The enable
bits (DTE and DTME) should not be set to 1 until the end of the setup procedure.
8.6.5
Note on Activating DMAC by Internal Interrupts
When using an internal interrupt to activate the DMAC, make sure that the interrupt selected as
the activating source does not occur during the interval after it has been selected but before the
DMAC has been enabled. The on-chip supporting module that will generate the interrupt should
not be activated until the DMAC has been enabled. If the DMAC must be enabled while the onchip supporting module is active, follow the procedure in figure 8.26.
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Section 8 DMA Controller
Enabling of DMAC
Yes
Interrupt handling by CPU
Selected interrupt
requested?
1
No
Clear selected interrupt’s
enable bit to 0
2
Enable DMAC
3
Set selected interrupt’s
enable bit to 1
4
1. While the DTE bit is cleared to 0,
interrupt requests are sent to the
CPU.
2. Clear the interrupt enable bit to 0
in the interrupt-generating on-chip
supporting module.
3. Enable the DMAC.
4. Enable the DMAC-activating
interrupt.
DMAC operates
Figure 8.26 Procedure for Enabling DMAC while On-Chip Supporting Module is
Operating (Example)
If the DTE bit is set to 1 but the DTME bit is cleared to 0, the DMAC is halted and the selected
activating source cannot generate a CPU interrupt. If the DMAC is halted by an NMI interrupt, for
example, the selected activating source cannot generate CPU interrupts. To terminate DMAC
operations in this state, clear the DTE bit to 0 to allow CPU interrupts to be requested. To continue
DMAC operations, carry out steps 2 and 4 in figure 8.26 before and after setting the DTME bit to
1.
When an ITU interrupt activates the DMAC, make sure the next interrupt does not occur before
the DMA transfer ends. If one ITU interrupt activates two or more channels, make sure the next
interrupt does not occur before the DMA transfers end on all the activated channels. If the next
interrupt occurs before a transfer ends, the channel or channels for which that interrupt was
selected may fail to accept further activation requests.
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Section 8 DMA Controller
8.6.6
NMI Interrupts and Block Transfer Mode
If an NMI interrupt occurs in block transfer mode, the DMAC operates as follows.
• When the NMI interrupt occurs, the DMAC finishes transferring the current byte or word, then
clears the DTME bit to 0 and halts. The halt may occur in the middle of a block.
It is possible to find whether a transfer was halted in the middle of a block by checking the
block size counter. If the block size counter does not have its initial value, the transfer was
halted in the middle of a block.
• If the transfer is halted in the middle of a block, the activating interrupt flag is cleared to 0. The
activation request is not held pending.
• While the DTE bit is set to 1 and the DTME bit is cleared to 0, the DMAC is halted and does
not accept activating interrupt requests. If an activating interrupt occurs in this state, the
DMAC does not operate and does not hold the transfer request pending internally. Neither is a
CPU interrupt requested.
For this reason, before setting the DTME bit to 1, first clear the enable bit of the activating
interrupt to 0. Then, after setting the DTME bit to 1, set the interrupt enable bit to 1 again. See
section 8.6.5, Note on Activating DMAC by Internal Interrupts.
• When the DTME bit is set to 1, the DMAC waits for the next transfer request. If it was halted
in the middle of a block transfer, the rest of the block is transferred when the next transfer
request occurs. Otherwise, the next block is transferred when the next transfer request occurs.
8.6.7
Memory and I/O Address Register Values
Table 8.14 indicates the address ranges that can be specified in the memory and I/O address
registers (MAR and IOAR).
Table 8.14 Address Ranges Specifiable in MAR and IOAR
1-Mbyte Mode
16-Mbyte Mode
MAR
H'00000 to H'FFFFF
(0 to 1048575)
H'000000 to H'FFFFFF
(0 to 16777215)
IOAR
H'FFF00 to H'FFFFF
(1048320 to 1048575)
H'FFFF00 to H'FFFFFF
(16776960 to 16777215)
MAR bits 23 to 20 are ignored in 1-Mbyte mode.
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Section 8 DMA Controller
8.6.8
Bus Cycle when Transfer is Aborted
When a transfer is aborted by clearing the DTE bit or suspended by an NMI that clears the DTME
bit, if this halts a channel for which the DMAC has a transfer request pending internally, a dead
cycle may occur. This dead cycle does not update the halted channel’s address register or counter
value. Figure 8.27 shows an example in which an auto-requested transfer in cycle-steal mode on
channel 0 is aborted by clearing the DTE bit in channel 0.
CPU cycle
T1
T2
DMAC cycle
Td
T1
T2
T1
DMAC
cycle
CPU cycle
T2
T1
T2
T3
Td
Td
CPU cycle
T1
T2
φ
Address bus
RD
HWR, LWR
DTE bit is
cleared
Figure 8.27 Bus Timing at Abort of DMA Transfer in Cycle-Steal Mode
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Section 8 DMA Controller
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Section 9 I/O Ports
Section 9 I/O Ports
9.1
Overview
The H8/3048 Group has 10 input/output ports (ports 1, 2, 3, 4, 5, 6, 8, 9, A, and B) and one input
port (port 7). Table 9.1 summarizes the port functions. The pins in each port are multiplexed as
shown in table 9.1.
Each port has a data direction register (DDR) for selecting input or output, and a data register
(DR) for storing output data. In addition to these registers, ports 2, 4, and 5 have an input pull-up
MOS control register (PCR) for switching input pull-up MOS transistors on and off.
Ports 1 to 6 and port 8 can drive one TTL load and a 90-pF capacitive load. Ports 9, A, and B can
drive one TTL load and a 30-pF capacitive load. Ports 1 to 6 and 8 to B can drive a darlington
pair. Ports 1, 2, 5, and B can drive LEDs (with 10-mA current sink). Pins P82 to P80, PA7 to PA0,
and PB3 to PB0 have Schmitt-trigger input circuits.
For block diagrams of the ports see appendix C, I/O Port Block Diagrams.
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Section 9 I/O Ports
Table 9.1
Port
Port Functions
Description
Pins
Port 1 • 8-bit I/O port P17 to P10/
A7 to A0
• Can drive
LEDs
Mode 1
Mode 2
Mode 3
Mode 4
Address output pins (A7 to A0)
Mode 5
Mode 6
Mode 7
Address output (A7 Generic
to A0) and generic input/
output
input
DDR = 0: generic
input
DDR = 1: address
output
Port 2 • 8-bit I/O port P27 to P20/
• Input pull-up A15 to A8
Address output pins (A15 to A8)
MOS
Address output (A15 Generic
to A8) and generic input/
input
output
DDR = 0: generic
input
• Can drive
LEDs
DDR = 1: address
output
Port 3 • 8-bit I/O port P37 to P30/
D15 to D8
Data input/output (D15 to D8)
Generic
input/
output
Port 4 • 8-bit I/O port P47 to P40/
• Input pull-up D7 to D0
Data input/output (D7 to D0) and 8-bit generic input/output
Generic
input/
output
MOS
8-bit bus mode: generic input/output
16-bit bus mode: data input/output
Port 5 • 4-bit I/O port P53 to P50/
• Input pull-up A19 to A16
Address output (A19 to A16)
MOS
Address output (A19 Generic
to A16) and 4-bit
input/
generic input
output
DDR = 0: generic
input
• Can drive
LEDs
DDR = 1: address
output
Port 6 • 7-bit I/O port P66/LWR,
P65/HWR,
P64/RD,
P63/AS
P62/BACK,
P61/BREQ,
P60/WAIT
Port 7 • 8-bit I/O port P77/AN7/DA1,
P76/AN6/DA0
P75 to P70/
AN5 to AN0
Bus control signal output (LWR, HWR, RD, AS)
Generic
input/
output
Bus control signal input/output (BACK, BREQ, WAIT) and 3bit generic input/output
Analog input (AN7, AN6) to A/D converter, analog output (DA1, DA0) from
D/A converter, and generic input
Analog input (AN5 to AN0) to A/D converter, and generic input
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Section 9 I/O Ports
Port
Description
Pins
Port 8 • 5-bit I/O port P84/CS0
• P82 to P80
have Schmitt
inputs
P83/CS1/IRQ3,
P82/CS2/IRQ2,
P81/CS3/IRQ1
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
Generic
input/
output
DDR = 0: generic input
DDR = 1 (after reset): CS0 output
IRQ3 to IRQ1 input, CS1 to CS3 output, and generic input
DDR = 0 (after reset): generic input
DDR = 1: CS1 to CS3 output
P80/RFSH/IRQ0 IRQ0 input, RFSH output, and generic input/output
IRQ3 to
IRQ0
input and
generic
input/
output
Port 9 • 6-bit I/O port P95/SCK1/IRQ5, Input and output (SCK1, SCK0, RxD1, RxD0, TxD1, TxD0) for serial
P94/SCK0/IRQ4, communication interfaces 1 and 0 (SCI1/0), IRQ5 and IRQ4 input, and 6P93/RxD1,
bit generic input/output
P92/RxD0,
P91/TxD1,
P90/TxD0
Port A • 8-bit I/O port PA7/TP7/
TIOCB2/A20
• Schmitt
inputs
Output (TP7) from Address output
(A20)
programmable
timing pattern
controller (TPC),
input or output
(TIOCB2) for 16-bit
integrated timer unit
(ITU), and generic
input/output
TPC output (TP6 to
PA6/TP6/
TIOCA2/A21/CS4 TP4), ITU input and
output (TIOCA2,
PA5/TP5/
TIOCB1/A22/CS5 TIOCB1, TIOCA1),
CS4 to CS6 output,
PA4/TP4/
TIOCA1/A23/CS6 and generic input/
output
TPC output (TP6 to
TP4), ITU input and
output (TIOCA2,
TIOCB1, TIOCA1),
address output (A23
to A21), CS4 to CS6
output, and generic
input/output
Address
TPC
output
output
(A20)
(TP7),
ITU input
or output
(TIOCB2),
and
generic
input/
output
TPC
output
(TP6 to
TP4), ITU
input and
output
(TIOCA2,
TIOCB1,
TIOCA1),
CS4 to
CS6
output,
and
generic
input/
output
TPC
output
(TP6 to
TP4), ITU
input and
output
(TIOCA2,
TIOCB1,
TIOCA1),
address
output
(A23 to
A21), CS4
to CS6
output,
and
generic
input/out
put
TPC
output
(TP7),
ITU input
or output
(TIOCB2),
and
generic
input/
output
TPC
output
(TP6 to
TP4), ITU
input and
output
(TIOCA2,
TIOCB1,
TIOCA1),
and
generic
input/
output
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Section 9 I/O Ports
Port
Description
Pins
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
Port A • 8-bit I/O port PA3/TP3/
TPC output (TP3 to TP0), output (TEND1, TEND0) from DMA controller
TIOCB0/
(DMAC), ITU input and output (TCLKD, TCLKC, TCLKB, TCLKA,
• Schmitt
TIOCB0, TIOCA0), and generic input/output
TCLKD,
inputs
PA2/TP2/
TIOCA0/
TCLKC,
PA1/TP1/
TEND1/TCLKB,
PA0/TP0/
TEND0/TCLKA
Port B • 8-bit I/O port PB7/TP15/
TPC output (TP15), DMAC input (DREQ1), trigger input (ADTRG) to A/D
DREQ1/ADTR converter, and generic input/output
• Can drive
G
LEDs
• PB3 to PB0 PB6/TP14/
have Schmitt DREQ0/CS7
inputs
PB5/TP13/
TOCXB4,
PB4/TP12/
TOCXA4,
PB3/TP11/
TIOCB4,
PB2/TP10/
TIOCA4,
PB1/TP9/
TIOCB3,
PB0/TP8/
TIOCA3
TPC output (TP14), DMAC input (DREQ0), CS7 output, and
generic input/output
TPC
output
(TP14),
DMAC
input
(DREQ0),
and
generic
input/
output
TPC output (TP13 to TP8), ITU input and output (TOCXB4, TOCXA4,
TIOCB4, TIOCA4, TIOCB3, TIOCA3), and generic input/output
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Section 9 I/O Ports
9.2
Port 1
9.2.1
Overview
Port 1 is an 8-bit input/output port with the pin configuration shown in figure 9.1. The pin
functions differ between the expanded modes with on-chip ROM disabled, expanded modes with
on-chip ROM enabled, and single-chip mode. In modes 1 to 4 (expanded modes with on-chip
ROM disabled), they are address bus output pins (A7 to A0).
In modes 5 and 6 (expanded modes with on-chip ROM enabled), settings in the port 1 data
direction register (P1DDR) can designate pins for address bus output (A7 to A0) or generic input.
In mode 7 (single-chip mode), port 1 is a generic input/output port.
When DRAM is connected to area 3, A7 to A0 output row and column addresses in read and write
cycles. For details see section 7, Refresh Controller.
Pins in port 1 can drive one TTL load and a 90-pF capacitive load. They can also drive a
darlington transistor pair.
Port 1 pins
Port 1
Modes 1 to 4
Modes 5 and 6
Mode 7
P17 /A 7
A 7 (output)
P17 (input)/A 7 (output)
P17 (input/output)
P16 /A 6
A 6 (output)
P16 (input)/A 6 (output)
P16 (input/output)
P15 /A 5
A 5 (output)
P15 (input)/A 5 (output)
P15 (input/output)
P14 /A 4
A 4 (output)
P14 (input)/A 4 (output)
P14 (input/output)
P13 /A 3
A 3 (output)
P13 (input)/A 3 (output)
P13 (input/output)
P12 /A 2
A 2 (output)
P12 (input)/A 2 (output)
P12 (input/output)
P11 /A 1
A 1 (output)
P11 (input)/A 1 (output)
P11 (input/output)
P10 /A 0
A 0 (output)
P10 (input)/A 0 (output)
P10 (input/output)
Figure 9.1 Port 1 Pin Configuration
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Section 9 I/O Ports
9.2.2
Register Descriptions
Table 9.2 summarizes the registers of port 1.
Table 9.2
Port 1 Registers
Initial Value
Address*
Name
Abbreviation
R/W
Modes 1 to 4
Modes 5 to 7
H'FFC0
Port 1 data direction
register
P1DDR
W
H'FF
H'00
H'FFC2
Port 1 data register
P1DR
R/W
H'00
H'00
Note: * Lower 16 bits of the address.
Port 1 Data Direction Register (P1DDR)
P1DDR is an 8-bit write-only register that can select input or output for each pin in port 1.
Bit
7
6
5
4
3
2
1
0
P1 7 DDR P1 6 DDR P1 5 DDR P1 4 DDR P1 3 DDR P1 2 DDR P1 1 DDR P1 0 DDR
Modes Initial value
1 to 4 Read/Write
Modes Initial value
5 to 7 Read/Write
1
1
1
1
1
1
1
1
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Port 1 data direction 7 to 0
These bits select input or
output for port 1 pins
Modes 1 to 4 (Expanded Modes with On-Chip ROM Disabled): P1DDR values are fixed at 1
and cannot be modified. Port 1 functions as an address bus.
Modes 5 and 6 (Expanded Modes with On-Chip ROM Enabled): A pin in port 1 becomes an
address output pin if the corresponding P1DDR bit is set to 1, and a generic input pin if this bit is
cleared to 0.
Mode 7 (Single-Chip Mode): Port 1 functions as an input/output port. A pin in port 1 becomes an
output pin if the corresponding P1DDR bit is set to 1, and an input pin if this bit is cleared to 0.
In modes 5 to 7, P1DDR is a write-only register. Its value cannot be read. All bits return 1 when
read.
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Section 9 I/O Ports
P1DDR is initialized to H'FF in modes 1 to 4 and H'00 in modes 5 to 7 by a reset and in hardware
standby mode. In software standby mode it retains its previous setting. If a P1DDR bit is set to 1,
the corresponding pin maintains its output state in software standby mode.
Port 1 Data Register (P1DR)
P1DR is an 8-bit readable/writable register that stores port 1 output data. While port 1 acts as an
output port, the value of this register is output. When this register is read, the pin logic level of a
pin is read for bits for which the P1DDR setting is 0, and the P1DR value is read for bits for which
the P1DDR setting is 1.
Bit
7
6
5
4
3
2
1
0
P17
P16
P15
P14
P13
P12
P11
P10
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 1 data 7 to 0
These bits store data for port 1 pins
P1DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
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Section 9 I/O Ports
9.3
Port 2
9.3.1
Overview
Port 2 is an 8-bit input/output port with the pin configuration shown in figure 9.2. The pin
functions differ according to the operating mode.
In modes 1 to 4 (expanded modes with on-chip ROM disabled), port 2 consists of address bus
output pins (A15 to A8). In modes 5 and 6 (expanded modes with on-chip ROM enabled), settings
in the port 2 data direction register (P2DDR) can designate pins for address bus output (A15 to A8)
or generic input. In mode 7 (single-chip mode), port 2 is a generic input/output port.
When DRAM is connected to area 3, A9 and A8 output row and column addresses in read and
write cycles. For details see section 7, Refresh Controller.
Port 2 has software-programmable built-in pull-up MOS. Pins in port 2 can drive one TTL load
and a 90-pF capacitive load. They can also drive a darlington transistor pair.
Port 2
Port 2 pins
Modes 1 to 4
Modes 5 and 6
Mode 7
P27 /A 15
A15 (output)
P27 (input)/A15 (output)
P27 (input/output)
P26 /A 14
A14 (output)
P26 (input)/A14 (output)
P26 (input/output)
P25 /A 13
A13 (output)
P25 (input)/A13 (output)
P25 (input/output)
P24 /A 12
A12 (output)
P24 (input)/A12 (output)
P24 (input/output)
P23 /A 11
A11 (output)
P23 (input)/A11 (output)
P23 (input/output)
P22 /A 10
A10 (output)
P22 (input)/A10 (output)
P22 (input/output)
P21 /A 9
A9 (output)
P21 (input)/A9 (output)
P21 (input/output)
P20 /A 8
A8 (output)
P20 (input)/A8 (output)
P20 (input/output)
Figure 9.2 Port 2 Pin Configuration
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Section 9 I/O Ports
9.3.2
Register Descriptions
Table 9.3 summarizes the registers of port 2.
Table 9.3
Port 2 Registers
Initial Value
Address*
Name
Abbreviation
R/W
Modes 1 to 4
Modes 5 to 7
H'FFC1
Port 2 data direction
register
P2DDR
W
H'FF
H'00
H'FFC3
Port 2 data register
P2DR
R/W
H'00
H'00
H'FFD8
Port 2 input pull-up MOS
control register
P2PCR
R/W
H'00
H'00
Note: * Lower 16 bits of the address.
Port 2 Data Direction Register (P2DDR)
P2DDR is an 8-bit write-only register that can select input or output for each pin in port 2.
Bit
7
6
5
4
3
2
1
0
P2 7 DDR P2 6 DDR P2 5 DDR P2 4 DDR P2 3 DDR P2 2 DDR P2 1 DDR P2 0 DDR
Modes Initial value
1 to 4 Read/Write
1
1
1
1
1
1
1
1
—
—
—
—
—
—
—
—
Modes Initial value
5 to 7 Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Port 2 data direction 7 to 0
These bits select input or
output for port 2 pins
Modes 1 to 4 (Expanded Modes with On-Chip ROM Disabled): P2DDR values are fixed at 1
and cannot be modified. Port 2 functions as an address bus.
Modes 5 and 6 (Expanded Modes with On-Chip ROM Enabled): Following a reset, port 2 is
an input port. A pin in port 2 becomes an address output pin if the corresponding P2DDR bit is set
to 1, and a generic input port if this bit is cleared to 0.
Mode 7 (Single-Chip Mode): Port 2 functions as an input/output port. A pin in port 2 becomes an
output port if the corresponding P2DDR bit is set to 1, and an input port if this bit is cleared to 0.
In modes 1 to 4, P2DDR always returns 1 when read. No value can be written to.
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Section 9 I/O Ports
In modes 5 to 7, P2DDR is a write-only register. Its value cannot be read. All bits return 1 when
read.
P2DDR is initialized to H'FF in modes 1 to 4 and H'00 in modes 5 to 7 by a reset and in hardware
standby mode. In software standby mode it retains its previous setting. If a P2DDR bit is set to 1,
the corresponding pin maintains its output state in software standby mode.
Port 2 Data Register (P2DR)
P2DR is an 8-bit readable/writable register that stores output data for pins P27 to P20. While port 2
acts as an output port, the value of this register is output. When a bit in P2DDR is set to 1, if port 2
is read the value of the corresponding P2DR bit is returned. When a bit in P2DDR is cleared to 0,
if port 2 is read the corresponding pin level is read.
Bit
7
6
5
4
3
2
1
0
P2 7
P2 6
P2 5
P2 4
P2 3
P2 2
P2 1
P2 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 2 data 7 to 0
These bits store data for port 2 pins
P2DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Port 2 Input Pull-Up MOS Control Register (P2PCR)
P2PCR is an 8-bit readable/writable register that controls the MOS input pull-up transistors in port
2.
Bit
7
6
5
4
3
2
1
0
P2 7 PCR P2 6 PCR P2 5 PCR P2 4 PCR P2 3 PCR P2 2 PCR P2 1 PCR P2 0 PCR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 2 input pull-up MOS control 7 to 0
These bits control input pull-up
transistors built into port 2
In modes 5 to 7, when a P2DDR bit is cleared to 0 (selecting generic input), if the corresponding
bit from P27PCR to P20PCR is set to 1, the input pull-up MOS is turned on.
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Section 9 I/O Ports
P2PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Table 9.4 summarizes the states of the input pull-up transistors.
Table 9.4
Input Pull-Up MOS States (Port 2)
Mode
Reset
Hardware
Standby Mode
Software
Standby Mode
Other Modes
1
Off
Off
Off
Off
Off
Off
On/off
On/off
2
3
4
5
6
7
Legend
Off:
The input pull-up MOS is always off.
On/off: The input pull-up MOS is on if P2PCR = 1 and P2DDR = 0. Otherwise, it is off.
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Section 9 I/O Ports
9.4
Port 3
9.4.1
Overview
Port 3 is an 8-bit input/output port with the pin configuration shown in figure 9.3. Port 3 is a data
bus in modes 1 to 6 (expanded modes) and a generic input/output port in mode 7 (single-chip
mode).
Pins in port 3 can drive one TTL load and a 90-pF capacitive load. They can also drive a
darlington transistor pair.
Port 3
Port 3 pins
Modes 1 to 6
Mode 7
P37 /D15
D15 (input/output)
P37 (input/output)
P36 /D14
D14 (input/output)
P36 (input/output)
P35 /D13
D13 (input/output)
P35 (input/output)
P34 /D12
D12 (input/output)
P34 (input/output)
P33 /D11
D11 (input/output)
P33 (input/output)
P32 /D10
D10 (input/output)
P32 (input/output)
P31 /D9
D9 (input/output)
P31 (input/output)
P30 /D8
D8 (input/output)
P30 (input/output)
Figure 9.3 Port 3 Pin Configuration
9.4.2
Register Descriptions
Table 9.5 summarizes the registers of port 3.
Table 9.5
Port 3 Registers
Address*
Name
Abbreviation
R/W
Initial Value
H'FFC4
Port 3 data direction register
P3DDR
W
H'00
H'FFC6
Port 3 data register
P3DR
R/W
H'00
Note: * Lower 16 bits of the address.
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Section 9 I/O Ports
Port 3 Data Direction Register (P3DDR)
P3DDR is an 8-bit write-only register that can select input or output for each pin in port 3.
Bit
7
6
5
4
3
2
1
0
P3 7 DDR P3 6 DDR P3 5 DDR P3 4 DDR P3 3 DDR P3 2 DDR P3 1 DDR P3 0 DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 3 data direction 7 to 0
These bits select input or output for port 3 pins
Modes 1 to 6 (Expanded Modes): Port 3 functions as a data bus. P3DDR is ignored.
Mode 7 (Single-Chip Mode): Port 3 functions as an input/output port. A pin in port 3 becomes an
output port if the corresponding P3DDR bit is set to 1, and an input port if this bit is cleared to 0.
P3DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P3DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting. If a P3DDR bit is set to 1, the corresponding pin maintains its output
state in software standby mode.
Port 3 Data Register (P3DR)
P3DR is an 8-bit readable/writable register that stores output data for pins P37 to P30. While port 3
acts as an output port, the value of this register is output. When a bit in P3DDR is set to 1, if port 3
is read the value of the corresponding P3DR bit is returned. When a bit in P3DDR is cleared to 0,
if port 3 is read the corresponding pin level is read.
Bit
7
6
5
4
3
2
1
0
P3 7
P3 6
P3 5
P3 4
P3 3
P3 2
P3 1
P3 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 3 data 7 to 0
These bits store data for port 3 pins
P3DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
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Section 9 I/O Ports
9.5
Port 4
9.5.1
Overview
Port 4 is an 8-bit input/output port with the pin configuration shown in figure 9.4. The pin
functions differ according to the operating mode.
In modes 1 to 6 (expanded modes), when the bus width control register (ABWCR) designates
areas 0 to 7 all as 8-bit-access areas, the chip operates in 8-bit bus mode and port 4 is a generic
input/output port. When at least one of areas 0 to 7 is designated as a 16-bit-access area, the chip
operates in 16-bit bus mode and port 4 becomes part of the data bus. In mode 7 (single-chip
mode), port 4 is a generic input/output port.
Port 4 has software-programmable built-in pull-up MOS.
Pins in port 4 can drive one TTL load and a 90-pF capacitive load. They can also drive a
darlington transistor pair.
Port 4
Port 4 pins
Modes 1 to 6
Mode 7
P47 /D7
P47 (input/output)/D7 (input/output)
P47 (input/output)
P46 /D6
P46 (input/output)/D6 (input/output)
P46 (input/output)
P45 /D5
P45 (input/output)/D5 (input/output)
P45 (input/output)
P44 /D4
P44 (input/output)/D4 (input/output)
P44 (input/output)
P43 /D3
P43 (input/output)/D3 (input/output)
P43 (input/output)
P42 /D2
P42 (input/output)/D2 (input/output)
P42 (input/output)
P41 /D1
P41 (input/output)/D1 (input/output)
P41 (input/output)
P40 /D0
P40 (input/output)/D0 (input/output)
P40 (input/output)
Figure 9.4 Port 4 Pin Configuration
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Section 9 I/O Ports
9.5.2
Register Descriptions
Table 9.6 summarizes the registers of port 4.
Table 9.6
Port 4 Registers
Address*
Name
Abbreviation
R/W
Initial Value
H'FFC5
Port 4 data direction register
P4DDR
W
H'00
H'FFC7
Port 4 data register
P4DR
R/W
H'00
H'FFDA
Port 4 input pull-up MOS control
register
P4PCR
R/W
H'00
Note: * Lower 16 bits of the address.
Port 4 Data Direction Register (P4DDR)
P4DDR is an 8-bit write-only register that can select input or output for each pin in port 4.
Bit
7
6
5
4
3
2
1
0
P4 7 DDR P4 6 DDR P4 5 DDR P4 4 DDR P4 3 DDR P4 2 DDR P4 1 DDR P4 0 DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 4 data direction 7 to 0
These bits select input or output for port 4 pins
Modes 1 to 6 (Expanded Modes): When all areas are designated as 8-bit-access areas using the
bus width control register (ABWCR) of the bus controller, selecting 8-bit bus mode, port 4
functions as a generic input/output port. A pin in port 4 becomes an output port if the
corresponding P4DDR bit is set to 1, and an input port if this bit is cleared to 0.
When at least one area is designated as a 16-bit-access area, selecting 16-bit bus mode, port 4
functions as part of the data bus regardless of the value in P4DDR.
Mode 7 (Single-Chip Mode): Port 4 functions as an input/output port. A pin in port 4 becomes an
output port if the corresponding P4DDR bit is set to 1, and an input port if this bit is cleared to 0.
P4DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P4DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting.
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Section 9 I/O Ports
ABWCR and P4DDR are not initialized in software standby mode. When port 4 functions as a
generic input/output port, if a P4DDR bit is set to 1, the corresponding pin maintains its output
state in software standby mode.
Port 4 Data Register (P4DR)
P4DR is an 8-bit readable/writable register that stores output data for pins P47 to P40. While port 4
acts as an output port, the value of this register is output. When a bit in P4DDR is set to 1, if port 4
is read the value of the corresponding P4DR bit is returned. When a bit in P4DDR is cleared to 0,
if port 4 is read the corresponding pin level is read.
Bit
7
6
5
4
3
2
1
0
P4 7
P4 6
P4 5
P4 4
P4 3
P4 2
P4 1
P4 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 4 data 7 to 0
These bits store data for port 4 pins
P4DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Port 4 Input Pull-Up MOS Control Register (P4PCR)
P4PCR is an 8-bit readable/writable register that controls the MOS input pull-up transistors in port
4.
Bit
7
6
5
4
3
2
1
0
P4 7 PCR P4 6 PCR P4 5 PCR P4 4 PCR P4 3 PCR P4 2 PCR P4 1 PCR P4 0 PCR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 4 input pull-up MOS control 7 to 0
These bits control input pull-up MOS transistors built into port 4
In mode 7 (single-chip mode), and in 8-bit bus mode in modes 1 to 6 (expanded modes), when a
P4DDR bit is cleared to 0 (selecting generic input), if the corresponding P4PCR bit is set to 1, the
input pull-up MOS transistor is turned on.
P4PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
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Section 9 I/O Ports
Table 9.7 summarizes the states of the input pull-ups MOS in the 8-bit and 16-bit bus modes.
Table 9.7
Input Pull-Up MOS Transistor States (Port 4)
Mode
1 to 6
8-bit bus mode
16-bit bus mode
7
Reset
Hardware
Standby Mode
Software
Standby Mode
Other Modes
Off
Off
On/off
On/off
Off
Off
On/off
On/off
Legend
Off:
The input pull-up MOS transistor is always off.
On/off: The input pull-up MOS transistor is on if P4PCR = 1 and P4DDR = 0. Otherwise, it is off.
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Section 9 I/O Ports
9.6
Port 5
9.6.1
Overview
Port 5 is a 4-bit input/output port with the pin configuration shown in figure 9.5. The pin functions
differ depending on the operating mode.
In modes 1 to 4 (expanded modes with on-chip ROM disabled), port 5 consists of address output
pins (A19 to A16). In modes 5 and 6 (expanded modes with on-chip ROM enabled), settings in the
port 5 data direction register (P5DDR) designate pins for address bus output (A19 to A16) or
generic input. In mode 7 (single-chip mode), port 5 is a generic input/output port.
Port 5 has software-programmable built-in pull-up MOS transistors.
Pins in port 5 can drive one TTL load and a 90-pF capacitive load. They can also drive an LED or
a darlington transistor pair.
Port 5
Port 5
pins
Modes 1 to 4
Modes 5 and 6
Mode 7
P53 /A 19
A19 (output)
P5 3 (input)/A19 (output)
P5 3 (input/output)
P52 /A 18
A18 (output)
P5 2 (input)/A18 (output)
P5 2 (input/output)
P51 /A 17
A17 (output)
P5 1 (input)/A17 (output)
P5 1 (input/output)
P50 /A 16
A16 (output)
P5 0 (input)/A16 (output)
P5 0 (input/output)
Figure 9.5 Port 5 Pin Configuration
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Section 9 I/O Ports
9.6.2
Register Descriptions
Table 9.8 summarizes the registers of port 5.
Table 9.8
Port 5 Registers
Initial Value
Address*
Name
Abbreviation
R/W
Modes 1 to 4
Modes 5 to 7
H'FFC8
Port 5 data direction
register
P5DDR
W
H'FF
H'F0
H'FFCA
Port 5 data register
P5DR
R/W
H'F0
H'F0
H'FFDB
Port 5 input pull-up MOS
control register
P5PCR
R/W
H'F0
H'F0
Note: * Lower 16 bits of the address.
Port 5 Data Direction Register (P5DDR)
P5DDR is an 8-bit write-only register that can select input or output for each pin in port 5.
Bits 7 to 4 are reserved. They cannot be modified and are always read as 1.
Bit
Modes Initial value
1 to 4 Read/Write
Modes Initial value
5 to 7 Read/Write
7
6
5
4
—
—
—
—
1
1
1
1
1
1
1
1
—
—
—
—
—
—
—
—
1
1
1
1
0
0
0
0
—
—
—
—
W
W
W
W
Reserved bits
3
2
1
0
P5 3 DDR P5 2 DDR P5 1 DDR P5 0 DDR
Port 5 data direction 3 to 0
These bits select input or
output for port 5 pins
Modes 1 to 4 (Expanded Modes with On-Chip ROM Disabled): P5DDR values are fixed at 1
and cannot be modified. Port 5 functions as an address bus.
Modes 5 and 6 (Expanded Modes with On-Chip ROM Enabled): Following a reset, port 5 is
an input port. A pin in port 5 becomes an address output pin if the corresponding P5DDR bit is set
to 1, and an input port if this bit is cleared to 0.
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Section 9 I/O Ports
Mode 7 (Single-Chip Mode): Port 5 functions as an input/output port. A pin in port 5 becomes an
output port if the corresponding P5DDR bit is set to 1, and an input port if this bit is cleared to 0.
In modes 1 to 4, P5DDR always returns 1 when read. No value can be written to.
In modes 5 to 7, P5DDR is a write-only register. Its value cannot be read. All bits return 1 when
read.
P5DDR is initialized to H'FF in modes 1 to 4 and H'F0 in modes 5 to 7 by a reset and in hardware
standby mode. In software standby mode it retains its previous setting, so if a P5DDR bit is set to
1 while port 5 acts as an I/O port, the corresponding pin maintains its output state in software
standby mode.
Port 5 Data Register (P5DR)
P5DR is an 8-bit readable/writable register that stores output data for pins P53 to P50. While port 5
acts as an output port, the value of this register is output. When a bit in P5DDR is set to 1, if port 5
is read the value of the corresponding P5DR bit is returned. When a bit in P5DDR is cleared to 0,
if port 5 is read the corresponding pin level is read.
Bits 7 to 4 are reserved. They cannot be modified and are always read as 1.
Bit
7
6
5
4
3
2
1
0
—
—
—
—
P5 3
P5 2
P5 1
P5 0
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
Reserved bits
Port 5 data 3 to 0
These bits store data
for port 5 pins
P5DR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
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Section 9 I/O Ports
Port 5 Input Pull-Up MOS Control Register (P5PCR)
Bit
7
6
5
4
—
—
—
—
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
Reserved bits
2
3
1
0
P5 3 PCR P5 2 PCR P5 1 PCR P5 0 PCR
Port 5 input pull-up MOS control 3 to 0
These bits control input pull-up MOS
transistors built into port 5
P5PCR is an 8-bit readable/writable register that controls the MOS input pull-up MOS transistors
in port 5.
Bits 7 to 4 are reserved. They cannot be modified and are always read as 1.
In modes 5 to 7, when a P5DDR bit is cleared to 0 (selecting generic input), if the corresponding
bit from P53PCR to P50PCR is set to 1, the input pull-up MOS transistor is turned on.
P5PCR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting.
Table 9.9 summarizes the states of the input pull-ups MOS in each mode.
Table 9.9
Input Pull-Up MOS Transistor States (Port 5)
Mode
Reset
Hardware
Standby Mode
Software
Standby Mode
Other Modes
1
Off
Off
Off
Off
Off
Off
On/off
On/off
2
3
4
5
6
7
Legend
Off:
The input pull-up MOS transistor is always off.
On/off: The input pull-up MOS transistor is on if P5PCR = 1 and P5DDR = 0. Otherwise, it is off.
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Section 9 I/O Ports
9.7
Port 6
9.7.1
Overview
Port 6 is a 7-bit input/output port that is also used for input and output of bus control signals
(LWR, HWR, RD, AS, BACK, BREQ, and WAIT). When DRAM is connected to area 3, LWR,
HWR, and RD also function as LW, UW, and CAS, or LCAS, UCAS, and WE, respectively. For
details see section 7, Refresh Controller.
Figure 9.6 shows the pin configuration of port 6. In modes 1 to 6 (expanded modes) the pin
functions are LWR, HWR, RD, AS, P62/BACK, P61/BREQ, and P60/WAIT. See table 9.11 for the
method of selecting the pin states. In mode 7 (single-chip mode) port 6 is a generic input/output
port.
Pins in port 6 can drive one TTL load and a 30-pF capacitive load. They can also drive a
darlington transistor pair.
Port 6 pins
Port 6
Mode 7
(single-chip mode)
Modes 1 to 6
(expanded modes)
P6 6 / LWR
LWR (output)
P6 6 (input/output)
P6 5 / HWR
HWR (output)
P6 5 (input/output)
P6 4 / RD
RD
(output)
P6 4 (input/output)
P6 3 / AS
AS
(output)
P6 3 (input/output)
P6 2 / BACK
P6 2 (input/output)/ BACK (output)
P6 2 (input/output)
P6 1 / BREQ
P6 1 (input/output)/ BREQ (input)
P6 1 (input/output)
P6 0 / WAIT
P6 0 (input/output)/ WAIT (input)
P6 0 (input/output)
Figure 9.6 Port 6 Pin Configuration
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Section 9 I/O Ports
9.7.2
Register Descriptions
Table 9.10 summarizes the registers of port 6.
Table 9.10 Port 6 Registers
Initial Value
Address*
Name
Abbreviation
R/W
Mode 1 to 5
Mode 6, 7
H'FFC9
Port 6 data direction
register
P6DDR
W
H'F8
H'80
H'FFCB
Port 6 data register
P6DR
R/W
H'80
H'80
Note: * Lower 16 bits of the address.
Port 6 Data Direction Register (P6DDR)
P6DDR is an 8-bit write-only register that can select input or output for each pin in port 6. Bit 7 is
reserved. It cannot be modified and is always read as 1.
Bit
7
—
6
5
4
3
2
1
0
P6 6 DDR P6 5 DDR P6 4 DDR P6 3 DDR P6 2 DDR P6 1 DDR P6 0 DDR
Initial value
1
0
0
0
0
0
0
0
Read/Write
—
W
W
W
W
W
W
W
Reserved bit
Port 6 data direction 6 to 0
These bits select input or output for port 6 pins
Modes 1 to 6 (Expanded Modes): Ports P66 to P63 function as bus control output pins (LWR,
HWR, RD, AS), regardless of the settings of P66DDR to P63DDR. Ports P62 to P60 function as the
bus control pins (BACK, BREQ, WAIT) or I/O ports. For selecting the pin function, see table
9.11. When ports P62 to P60 function as I/O ports and if P6DDR is set to 1, the corresponding pin
of port 6 functions as an output port. If P6DDR is cleared to 0, the corresponding pin functions as
an input port.
Mode 7 (Single-Chip Mode): Port 6 is a generic input/output port. A pin in port 6 becomes an
output port if the corresponding P6DDR bit is set to 1, and an input port if this bit is cleared to 0.
P6DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P6DDR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting. If a P6DDR bit is set to 1 while port 6 acts as an I/O port, the
corresponding pin maintains its output state in software standby mode.
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Section 9 I/O Ports
Port 6 Data Register (P6DR)
Bit
7
6
5
4
3
2
1
0
—
P6 6
P6 5
P6 4
P6 3
P6 2
P6 1
P6 0
Initial value
1
0
0
0
0
0
0
0
Read/Write
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bit
Port 6 data 6 to 0
These bits store data for port 6 pins
P6DR is an 8-bit readable/writable register that stores output data for pins P66 to P60. When this
register is read, bits 6 to 0 each returns the logic level of the pin, when the corresponding bit of
P6DDR is 0. When the corresponding bit of P6DDR is 1, bits 6 to 0 return the P6DR value.
Bit 7 is reserved, cannot be modified, and always read as 1.
P6DR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Table 9.11 Port 6 Pin Functions in Modes 1 to 6
Pin
Pin Functions and Selection Method
P66/LWR
Functions as follows regardless of P66DDR
P66DDR
0
P65/HWR
Functions as follows regardless of P65DDR
P65DDR
0
1
HWR output
Pin function
P64/RD
1
LWR output
Pin function
Functions as follows regardless of P64DDR
P64DDR
0
RD output
Pin function
P63/AS
1
Functions as follows regardless of P63DDR
P63DDR
Pin function
Rev. 7.00 Sep 21, 2005 page 280 of 878
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0
1
AS output
Section 9 I/O Ports
Pin
Pin Functions and Selection Method
P62/BACK
Bit BRLE in BRCR and bit P62DDR select the pin function as follows
BRLE
0
P62DDR
Pin function
P61/BREQ
0
1
—
P62 input
P62 output
BACK output
Bit BRLE in BRCR and bit P61DDR select the pin function as follows
BRLE
0
P61DDR
Pin function
P60/WAIT
1
1
0
1
—
P61 input
P61 output
BREQ input
Bits WCE7 to WCE0 in WCER, bit WMS1 in WCR, and bit P60DDR select the
pin function as follows
WCER
All 1s
WMS1
P60DDR
Pin function
0
0
1
P60 input
P60 output
Not all 1s
1
—
0*
0*
WAIT input
Note: * Do not set bit P60DDR to 1.
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Section 9 I/O Ports
9.8
Port 7
9.8.1
Overview
Port 7 is an 8-bit input port that is also used for analog input to the A/D converter and analog
output from the D/A converter. The pin functions are the same in all operating modes. Figure 9.7
shows the pin configuration of port 7.
For the analog input pins of the A/D converter, see section 15, A/D Converter.
For the analog input pins of the D/A converter, see section 16, D/A Converter.
Port 7 pins
P77 (input)/AN 7 (input)/DA 1 (output)
P76 (input)/AN 6 (input)/DA 0 (output)
P75 (input)/AN 5 (input)
Port 7
P74 (input)/AN 4 (input)
P73 (input)/AN 3 (input)
P72 (input)/AN 2 (input)
P71 (input)/AN 1 (input)
P70 (input)/AN 0 (input)
Figure 9.7 Port 7 Pin Configuration
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Section 9 I/O Ports
9.8.2
Register Description
Table 9.12 summarizes the port 7 register. Port 7 is an input-only port, so it has no data direction
register.
Table 9.12 Port 7 Data Register
Address*
Name
Abbreviation
R/W
Initial Value
H'FFCE
Port 7 data register
P7DR
R
Undetermined
Note: * Lower 16 bits of the address.
Port 7 Data Register (P7DR)
Bit
7
6
5
4
3
2
1
0
P77
P76
P75
P74
P73
P72
P71
P70
Initial value
—*
—*
—*
—*
—*
—*
—*
—*
Read/Write
R
R
R
R
R
R
R
R
Note: * Determined by pins P7 7 to P70 .
When P7DR is read, the logic level of the pin is always read. No data can be written to.
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Section 9 I/O Ports
9.9
Port 8
9.9.1
Overview
Port 8 is a 5-bit input/output port that is also used for CS3 to CS0 output, RFSH output, and IRQ3
to IRQ0 input. Figure 9.8 shows the pin configuration of port 8.
In modes 1 to 6 (expanded modes), port 8 can provide CS3 to CS0 output, RFSH output, and IRQ3
to IRQ0 input. See table 9.14 for the selection of pin functions in expanded modes.
In mode 7 (single-chip mode), port 8 can provide IRQ3 to IRQ0 input. See table 9.15 for the
selection of pin functions in single-chip mode.
The IRQ3 to IRQ0 functions are selected by IER settings, regardless of whether the pin is used for
input or output. For details see section 5, Interrupt Controller.
Pins in port 8 can drive one TTL load and a 90-pF capacitive load. They can also drive a
darlington transistor pair.
Pins P82 to P80 have Schmitt-trigger inputs.
Port 8
Port 8 pins
Pin functions in modes 1 to 6
(expanded modes)
P84 / CS 0
P84 (input)/ CS 0 (output)
P83 / CS 1 / IRQ 3
P83 (input)/ CS 1 (output)/ IRQ 3 (input)
P82 / CS 2 / IRQ 2
P82 (input)/ CS 2 (output)/ IRQ 2 (input)
P81 / CS 3 / IRQ 1
P81 (input)/ CS 3 (output)/ IRQ 1 (input)
P80 / RFSH /IRQ 0
P80 (input/output)/ RFSH (output)/ IRQ 0 (input)
Pin functions in mode 7
(single-chip mode)
P84 /(input/output)
P83 /(input/output)/ IRQ 3 (input)
P82 /(input/output)/ IRQ 2 (input)
P81 /(input/output)/ IRQ 1 (input)
P80 /(input/output)/ IRQ 0 (input)
Figure 9.8 Port 8 Pin Configuration
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Section 9 I/O Ports
9.9.2
Register Descriptions
Table 9.13 summarizes the registers of port 8.
Table 9.13 Port 8 Registers
Initial Value
Address*
Name
Abbreviation
R/W
Mode 1 to 4
Mode 5 to 7
H'FFCD
Port 8 data direction
register
P8DDR
W
H'F0
H'E0
H'FFCF
Port 8 data register
P8DR
R/W
H'E0
H'E0
Note: * Lower 16 bits of the address.
Port 8 Data Direction Register (P8DDR)
P8DDR is an 8-bit write-only register that can select input or output for each pin in port 8.
Bits 7 to 5 are reserved. They cannot be modified and are always read as 1.
Bit
Modes Initial value
1 to 4 Read/Write
Modes Initial value
5 to 7 Read/Write
7
6
5
—
—
—
1
1
1
1
0
0
0
0
—
—
—
W
W
W
W
W
1
1
1
0
0
0
0
0
—
—
—
W
W
W
W
W
Reserved bits
4
3
2
1
0
P8 4 DDR P8 3 DDR P8 2 DDR P8 1 DDR P8 0 DDR
Port 8 data direction 4 to 0
These bits select input or
output for port 8 pins
Modes 1 to 6 (Expanded Modes): When bits in P8DDR bit are set to 1, P84 to P81 become CS0 to
CS3 output pins. When bits in P8DDR are cleared to 0, the corresponding pins become input ports.
In modes 1 to 4 (expanded modes with on-chip ROM disabled), following a reset only CS0 is
output. The other three pins are input ports. In modes 5 and 6 (expanded modes with on-chip
ROM enabled), following a reset all four pins are input ports.
When the refresh controller is enabled, P80 is used unconditionally for RFSH output. When the
refresh controller is disabled, P80 becomes a generic input/output port according to the P8DDR
setting. For details see table 9.15.
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Section 9 I/O Ports
Mode 7 (Single-Chip Mode): Port 8 is a generic input/output port. A pin in port 8 becomes an
output port if the corresponding P8DDR bit is set to 1, and an input port if this bit is cleared to 0.
P8DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P8DDR is initialized to H'F0 in modes 1 to 4 and H'E0 in modes 5 to 7 by a reset and in hardware
standby mode. In software standby mode it retains its previous setting, so if a P8DDR bit is set to
1 while port 8 acts as an I/O port, the corresponding pin maintains its output state in software
standby mode.
Port 8 Data Register (P8DR)
P8DR is an 8-bit readable/writable register that stores output data for pins P84 to P80. While port 8
acts as an output port, the value of this register is output. When a bit in P8DDR is set to 1, if port 8
is read the value of the corresponding P8DR bit is returned. When a bit in P8DDR is cleared to 0,
if port 8 is read the corresponding pin level is read.
Bits 7 to 5 are reserved. They cannot be modified and always are read as 1.
Bit
7
6
5
4
3
2
1
0
—
—
—
P8 4
P8 3
P8 2
P8 1
P8 0
Initial value
1
1
1
0
0
0
0
0
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
Reserved bits
Port 8 data 4 to 0
These bits store data
for port 8 pins
P8DR is initialized to H'E0 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
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Section 9 I/O Ports
Table 9.14 Port 8 Pin Functions in Modes 1 to 6
Pin
Pin Functions and Selection Method
P84/CS0
Bit P84DDR selects the pin function as follows
P84DDR
Pin function
P83/CS1/IRQ3
0
1
P84 input
CS0 output
Bit P83DDR selects the pin function as follows
P83DDR
Pin function
0
1
P83 input
CS1 output
IRQ3 input
P82/CS2/IRQ2
Bit P82DDR selects the pin function as follows
P82DDR
Pin function
0
1
P82 input
CS2 output
IRQ2 input
P81/CS3/IRQ1
Bit P81DDR selects the pin function as follows
P81DDR
Pin function
0
1
P81 input
CS3 output
IRQ1 input
P80/RFSH/IRQ0
Bit RFSHE in RFSHCR and bit P80DDR select the pin function as follows
RFSHE
P80DDR
Pin function
0
1
0
1
—
P80 input
P80 output
RFSH output
IRQ0 input
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Section 9 I/O Ports
Table 9.15 Port 8 Pin Functions in Mode 7
Pin
Pin Functions and Selection Method
P84
Bit P84DDR selects the pin function as follows
P84DDR
Pin function
P83/IRQ3
0
1
P84 input
P84 output
Bit P83DDR selects the pin function as follows
P83DDR
Pin function
0
1
P83 input
P83 output
IRQ3 input
P82/IRQ2
Bit P82DDR selects the pin function as follows
P82DDR
Pin function
0
1
P82 input
P82 output
IRQ2 input
P81/IRQ1
Bit P81DDR selects the pin function as follows
P81DDR
Pin function
0
1
P81 input
P81 output
IRQ1 input
P80/IRQ0
Bit P80DDR select the pin function as follows
P80DDR
Pin function
0
1
P80 input
P80 output
IRQ0 input
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Section 9 I/O Ports
9.10
Port 9
9.10.1
Overview
Port 9 is a 6-bit input/output port that is also used for input and output (TxD0, TxD1, RxD0, RxD1,
SCK0, SCK1) by serial communication interface channels 0 and 1 (SCI0 and SCI1), and for IRQ5
and IRQ4 input. See table 9.17 for the selection of pin functions.
The IRQ5 and IRQ4 functions are selected by IER settings, regardless of whether the pin is used
for input or output. For details see section 5, Interrupt Controller.
Port 9 has the same set of pin functions in all operating modes. Figure 9.9 shows the pin
configuration of port 9.
Pins in port 9 can drive one TTL load and a 30-pF capacitive load. They can also drive a
darlington transistor pair.
Port 9 pins
P95 (input/output)/SCK 1 (input/output)/IRQ 5 (input)
P94 (input/output)/SCK 0 (input/output)/IRQ 4 (input)
Port 9
P93 (input/output)/RxD1 (input)
P92 (input/output)/RxD0 (input)
P91 (input/output)/TxD1 (output)
P90 (input/output)/TxD0 (output)
Figure 9.9 Port 9 Pin Configuration
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Section 9 I/O Ports
9.10.2
Register Descriptions
Table 9.16 summarizes the registers of port 9.
Table 9.16 Port 9 Registers
Address*
Name
Abbreviation
R/W
Initial Value
H'FFD0
Port 9 data direction register
P9DDR
W
H'C0
H'FFD2
Port 9 data register
P9DR
R/W
H'C0
Note: * Lower 16 bits of the address.
Port 9 Data Direction Register (P9DDR)
P9DDR is an 8-bit write-only register that can select input or output for each pin in port 9.
Bits 7 and 6 are reserved. They cannot be modified and are always read as 1.
Bit
7
6
5
4
3
2
1
0
PA 7
PA 6
PA 5
PA 4
PA 3
PA 2
PA 1
PA 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port A data 7 to 0
These bits store data for port A pins
While port 9 acts as an I/O port, a pin in port 9 becomes an output port if the corresponding
P9DDR bit is set to 1, and an input port if this bit is cleared to 0. For selecting the pin function, see
table 9.17.
P9DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P9DDR is initialized to H'C0 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting. If a P9DDR bit is set to 1 while port 9 acts as an I/O port, the
corresponding pin maintains its output state in software standby mode.
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Section 9 I/O Ports
Port 9 Data Register (P9DR)
P9DR is an 8-bit readable/writable register that stores output data for pins P95 to P90. While port 9
acts as an output port, the value of this register is output. When a bit in P9DDR is set to 1, if port 9
is read the value of the corresponding P9DR bit is returned. When a bit in P9DDR is cleared to 0,
if port 9 is read the corresponding pin level is read.
Bit
7
6
5
4
3
2
1
0
—
—
P9 5
P9 4
P9 3
P9 2
P9 1
P9 0
Initial value
1
1
0
0
0
0
0
0
Read/Write
—
—
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bits
Port 9 data 5 to 0
These bits store data
for port 9 pins
Bits 7 and 6 are reserved. They cannot be modified and are always read as 1.
P9DR is initialized to H'C0 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
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Section 9 I/O Ports
Table 9.17 Port 9 Pin Functions
Pin
Pin Functions and Selection Method
P95/SCK1/IRQ5
Bit C/A in SMR of SCI1, bits CKE0 and CKE1 in SCR of SCI1, and bit P95DDR
select the pin function as follows
CKE1
0
C/A
0
CKE0
0
P95DDR
Pin function
1
1
—
1
—
—
0
1
—
—
—
P95
input
P95
output
SCK1
output
SCK1
output
SCK1
input
IRQ5 input
P94/SCK0/IRQ4
Bit C/A in SMR of SCI0, bits CKE0 and CKE1 in SCR of SCI0, and bit P94DDR
select the pin function as follows
CKE1
0
C/A
0
CKE0
0
P94DDR
Pin function
1
1
—
1
—
—
0
1
—
—
—
P94
input
P94
output
SCK0
output
SCK0
output
SCK0
input
IRQ4 input
P93/RxD1
Bit RE in SCR of SCI1 and bit P93DDR select the pin function as follows
RE
0
P93DDR
Pin function
P92/RxD0
1
0
1
—
P93 input
P93 output
RxD1 input
Bit RE in SCR of SCI0, bit SMIF in SCMR, and bit P92DDR select the pin
function as follows
SMIF
0
RE
0
1
—
0
1
—
—
P92 input
P92 output
RxD0 input
RxD0 input
P92DDR
Pin function
1
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Section 9 I/O Ports
Pin
Pin Functions and Selection Method
P91/TxD1
Bit TE in SCR of SCI1 and bit P91DDR select the pin function as follows
TE
0
P91DDR
Pin function
P90/TxD0
1
0
1
—
P91 input
P91 output
TxD1 output
Bit TE in SCR of SCI0, bit SMIF in SCMR, and bit P90DDR select the pin
function as follows
SMIF
0
TE
P90DDR
Pin function
0
1
1
—
0
1
—
—
P90 input
P90 output
TxD0 output
TxD0 output*
Note: * Functions as the TxD0 output pin, but there are two states: one in which
the pin is driven, and another in which the pin is at high-impedance.
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Section 9 I/O Ports
9.11
Port A
9.11.1
Overview
Port A is an 8-bit input/output port that is also used for output (TP7 to TP0) from the
programmable timing pattern controller (TPC), input and output (TIOCB2, TIOCA2, TIOCB1,
TIOCA1, TIOCB0, TIOCA0, TCLKD, TCLKC, TCLKB, TCLKA) by the 16-bit integrated timer
unit (ITU), output (TEND1, TEND0) from the DMA controller (DMAC), CS4 to CS6 output, and
address output (A23 to A20). A reset or hardware standby leaves port A as an input port, except that
in modes 3, 4, and 6, one pin is always used for A20 output. For selecting the pin function, see
table 9.19. Usage of pins for TPC, ITU, and DMAC input and output is described in the sections
on those modules. For output of address bits A23 to A21 in modes 3, 4, and 6, see section 6.2.5, Bus
Release Control Register (BRCR). For output of CS4 to CS6 in modes 1 to 6, see section 6.3.2,
Chip Select Signals. Pins not assigned to any of these functions are available for generic
input/output. Figure 9.10 shows the pin configuration of port A.
Pins in port A can drive one TTL load and a 30-pF capacitive load. They can also drive a
darlington transistor pair. Port A has Schmitt-trigger inputs.
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Section 9 I/O Ports
Port A pins
PA 7/TP7 /TIOCB2 /A 20
PA 6/TP6 /TIOCA2 /A21/CS4
PA 5/TP5 /TIOCB1 /A22/CS5
PA 4/TP4 /TIOCA1 /A23/CS6
Port A
PA 3/TP3 /TIOCB 0 /TCLKD
PA 2/TP2 /TIOCA 0 /TCLKC
PA 1/TP1 /TEND1 /TCLKB
PA 0/TP0 /TEND0 /TCLKA
Pin functions in modes 1, 2, and 5
PA 7 (input/output)/TP7 (output)/TIOCB 2 (input/output)
PA 6 (input/output)/TP6 (output)/TIOCA 2 (input/output)/CS4 (output)
PA 5 (input/output)/TP5 (output)/TIOCB 1 (input/output)/CS5(output)
PA 4 (input/output)/TP4 (output)/TIOCA 1 (input/output)/CS6(output)
PA 3 (input/output)/TP3 (output)/TIOCB 0 (input/output)/TCLKD (input)
PA 2 (input/output)/TP2 (output)/TIOCA 0 (input/output)/TCLKC (input)
PA 1 (input/output)/TP1 (output)/TEND 1 (output)/TCLKB (input)
PA 0 (input/output)/TP0 (output)/TEND 0 (output)/TCLKA (input)
Pin functions in modes 3, 4, and 6
A20 (output)
PA 6 (input/output)/TP6 (output)/TIOCA 2 (input/output)/A 21 (output)/CS4 (output)
PA 5 (input/output)/TP5 (output)/TIOCB 1 (input/output)/A 22 (output)/CS5 (output)
PA 4 (input/output)/TP4 (output)/TIOCA 1 (input/output)/A 23 (output)/CS6 (output)
PA 3 (input/output)/TP3 (output)/TIOCB 0 (input/output)/TCLKD (input)
PA 2 (input/output)/TP2 (output)/TIOCA 0 (input/output)/TCLKC (input)
PA 1 (input/output)/TP1 (output)/TEND 1 (output)/TCLKB (input)
PA 0 (input/output)/TP0 (output)/TEND 0 (output)/TCLKA (input)
Pin functions in mode 7
PA7 (input/output)/TP7 (output)/TIOCB2 (input/output)
PA6 (input/output)/TP6 (output)/TIOCA2 (input/output)
PA5 (input/output)/TP5 (output)/TIOCB1 (input/output)
PA4 (input/output)/TP4 (output)/TIOCA1 (input/output)
PA3 (input/output)/TP3 (output)/TIOCB0 (input/output)/TCLKD (input)
PA2 (input/output)/TP2 (output)/TIOCA0 (input/output)/TCLKC (input)
PA1 (input/output)/TP1 (output)/TEND1 (output)/TCLKB (input)
PA0 (input/output)/TP0 (output)/TEND0 (output)/TCLKA (input)
Figure 9.10 Port A Pin Configuration
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Section 9 I/O Ports
9.11.2
Register Descriptions
Table 9.18 summarizes the registers of port A.
Table 9.18 Port A Registers
Initial Value
Address*
Name
Abbreviation
R/W
Modes
1, 2, 5, and 7
Modes
3, 4, and 6
H'FFD1
Port A data direction
register
PADDR
W
H'00
H'80
H'FFD3
Port A data register
PADR
R/W
H'00
H'00
Note: * Lower 16 bits of the address.
Port A Data Direction Register (PADDR)
PADDR is an 8-bit write-only register that can select input or output for each pin in port A. When
pins are used for TPC output, the corresponding PADDR bits must also be set.
Bit
7
6
5
4
3
2
1
0
PA7 DDR PA6 DDR PA5 DDR PA4 DDR PA3 DDR PA2 DDR PA1 DDR PA0 DDR
Modes
3, 4,
and 6
Modes
1, 2, 5,
and 7
Initial value
1
0
0
0
0
0
0
0
Read/Write —
W
W
W
W
W
W
W
Initial value
0
0
0
0
0
0
0
0
Read/Write W
W
W
W
W
W
W
W
Port A data direction 7 to 0
These bits select input or output for port A pins
While port A acts as an I/O port, a pin in port A becomes an output pin if the corresponding
PADDR bit is set to 1, and an input pin if this bit is cleared to 0. In modes 3, 4, and 6, PA7DDR is
fixed at 1 and PA7 functions as an address output pin.
PADDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PADDR is initialized to H'00 by a reset and in hardware standby mode in modes 1, 2, 5, and 7.
It is initialized to H'80 by a reset and in hardware standby mode in modes 3, 4, and 6. In software
standby mode it retains its previous setting. If a PADDR bit is set to 1, the corresponding pin
maintains its output state in software standby mode.
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Section 9 I/O Ports
Port A Data Register (PADR)
PADR is an 8-bit readable/writable register that stores output data for pins PA7 to PA0. While port
A acts as an output port, the value of this register is output. When a bit in PADDR is set to 1, if
port A is read the value of the corresponding PADR bit is returned. When a bit in PADDR is
cleared to 0, if port A is read the corresponding pin level is read.
Bit
7
6
5
4
3
2
1
0
PA 7
PA 6
PA 5
PA 4
PA 3
PA 2
PA 1
PA 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port A data 7 to 0
These bits store data for port A pins
PADR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
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Section 9 I/O Ports
9.11.3
Pin Functions
Table 9.19 describes the selection of pin functions.
Table 9.19 Port A Pin Functions
Pin
Pin Functions and Selection Method
The mode setting, ITU channel 2 settings (bit PWM2 in TMDR and bits IOB2 to IOB0 in
PA7/TP7/
TIOCB2/A20 TIOR2), bit NDER7 in NDERA, and bit PA7DDR in PADDR select the pin function as
follows
Mode
1, 2, 5, 7
3, 4, 6
ITU
channel 2
settings
(1) in table
below
PA7DDR
—
0
1
1
—
NDER7
—
—
0
1
—
TIOCB2
output
PA7 input
PA7 output
TP7 output
A20 output
Pin function
(2) in table below
—
TIOCB2 input*
Note: * TIOCB2 input when IOB2 = 1 and PWM2 = 0.
ITU
channel 2
settings
(2)
IOB2
(1)
(2)
0
1
IOB1
0
0
1
—
IOB0
0
1
—
—
Rev. 7.00 Sep 21, 2005 page 298 of 878
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Section 9 I/O Ports
Pin
Pin Functions and Selection Method
PA6/TP6/
TIOCA2/
A21/CS4
The mode setting, bit A21E in BRCR, bit CS4E in CSCR, ITU channel 2 settings (bit
PWM2 in TMDR and bits IOA2 to IOA0 in TIOR2), bit NDER6 in NDERA, and bit
PA6DDR in PADDR select the pin function as follows
Mode
1, 2, 5
3, 4, 6
CS4E
0
1
A21E
—
—
0
1
(2) in table
table
below
—
0
—
—
—
—
(1) in
(2) in table
channel 2
table
below
settings
below
PA6DDR
—
0
1
1
—
—
0
1
1
—
—
—
0
1
1
NDER6
—
—
0
1
—
—
—
0
1
—
—
—
—
0
1
function
(1) in
1
ITU
Pin
—
7
below
(1) in
(2) in table
table
below
below
PA6
TP6
CS4 TIOCA2 PA6
PA6
TP6
A21
CS4 TIOCA2 PA6
PA6
TP6
output input out-
out-
out-
output input out-
out-
out-
out-
output input out-
out-
put
put
put
put
put
put
put
put
put
TIOCA2 PA6
TIOCA2 input*
TIOCA2 input*
TIOCA2 input*
Note: * TIOCA2 input when IOA2 = 1.
ITU
channel 2
(2)
(1)
(2)
(1)
settings
PWM2
0
IOA2
1
0
1
—
IOA1
0
0
1
—
—
IOA0
0
1
—
—
—
Rev. 7.00 Sep 21, 2005 page 299 of 878
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Section 9 I/O Ports
Pin
Pin Functions and Selection Method
PA5/TP5/
The mode setting, bit A22E in BRCR, bit CS5E in CSCR, ITU channel 1 settings (bit
PWM1 in TMDR and bits IOB2 to IOB0 in TIOR1), bit NDER5 in NDERA, and bit
PA5DDR in PADDR select the pin function as follows
TIOCB1/
A22/CS5
Mode
1, 2, 5
3, 4, 6
CS5E
0
1
A22E
—
—
0
1
(2) in table
table
below
—
0
—
—
—
—
(1) in
(2) in table
channel 1
table
below
settings
below
PA5DDR
—
0
1
1
—
—
0
1
1
—
—
—
0
1
1
NDER5
—
—
0
1
—
—
—
0
1
—
—
—
—
0
1
function
(1) in
1
ITU
Pin
—
7
below
(1) in
(2) in table
table
below
below
PA5
TP5
CS5 TIOCB1 PA5
PA5
TP5
A22
CS5 TIOCB1 PA5
PA5
TP5
output input out-
out-
out-
output input out-
out-
out-
out-
output input out-
out-
put
put
put
put
put
put
put
put
put
TIOCB1 PA5
TIOCB1 input*
TIOCB1 input*
TIOCB1 input*
Note: * TIOCB1 input when IOB2 = 1 and PWM1 = 0.
ITU
channel 1
(2)
(1)
(2)
settings
IOB2
0
1
IOB1
0
0
1
—
IOB0
0
1
—
—
Rev. 7.00 Sep 21, 2005 page 300 of 878
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Section 9 I/O Ports
Pin
Pin Functions and Selection Method
PA4/TP4/
TIOCA1/
A23/CS6
The mode setting, bit A23E in BRCR, bit CS6E in CSCR, ITU channel 1 settings (bit
PWM1 in TMDR and bits IOA2 to IOA0 in TIOR1), bit NDER4 in NDERA, and bit
PA4DDR in PADDR select the pin function as follows
Mode
1, 2, 5
3, 4, 6
CS6E
0
1
A23E
—
—
ITU
(1) in
(2) in table
channel 2
table
below
settings
below
—
7
0
1
(1) in
(2) in table
table
below
1
—
0
—
—
—
—
below
(1) in
(2) in table
table
below
below
PA4DDR
—
0
1
1
—
—
0
1
1
—
—
—
0
1
1
NDER4
—
—
0
1
—
—
—
0
1
—
—
—
—
0
1
Pin
function
PA4
TP4
CS6 TIOCA1 PA4
PA4
TP4
A23
CS6 TIOCA1 PA4
PA4
TP4
output input out-
out-
out-
output input out-
out-
out-
out-
output input out-
out-
put
put
put
put
put
put
put
put
put
TIOCA1 PA4
TIOCA1 input*
TIOCA1 input*
TIOCA1 input*
Note: * TIOCA1 input when IOA2 = 1.
ITU
channel 1
(2)
(1)
(2)
(1)
settings
PWM1
0
IOA2
1
0
1
—
IOA1
0
0
1
—
—
IOA0
0
1
—
—
—
Rev. 7.00 Sep 21, 2005 page 301 of 878
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Section 9 I/O Ports
Pin
Pin Functions and Selection Method
PA3/TP3/
TIOCB0/
TCLKD
ITU channel 0 settings (bit PWM0 in TMDR and bits IOB2 to IOB0 in TIOR0), bits
TPSC2 to TPSC0 in TCR4 to TCR0, bit NDER3 in NDERA, and bit PA3DDR in PADDR
select the pin function as follows
ITU channel 0
settings
PA3DDR
NDER3
Pin function
(1) in table
below
—
(2) in table
below
0
1
1
—
—
0
1
TIOCB0 output
PA3 input
PA3 output
TP3 output
1
TIOCB0 input*
2
TCLKD input*
Notes: 1. TIOCB0 input when IOB2 = 1 and PWM0 = 0.
2. TCLKD input when TPSC2 = TPSC1 = TPSC0 = 1 in any of TCR4 to TCR0.
ITU channel 0
settings
(2)
IOB2
(1)
(2)
0
1
IOB1
0
0
1
—
IOB0
0
1
—
—
Rev. 7.00 Sep 21, 2005 page 302 of 878
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Section 9 I/O Ports
Pin
Pin Functions and Selection Method
PA2/TP2/
TIOCA0/
TCLKC
ITU channel 0 settings (bit PWM0 in TMDR and bits IOA2 to IOA0 in TIOR0), bits
TPSC2 to TPSC0 in TCR4 to TCR0, bit NDER2 in NDERA, and bit PA2DDR in PADDR
select the pin function as follows
ITU channel 0
settings
(1) in table
below
PA2DDR
—
NDER2
Pin function
(2) in table
below
0
1
1
—
—
0
1
IOCA0 output
PA2 input
PA2 output
TP2 output
1
TIOCA0 input*
2
TCLKC input*
Notes: 1. TIOCA0 input when IOA2 = 1.
2. TCLKC input when TPSC2 = TPSC1 = 1 and TPSC0 = 0 in any of TCR4 to
TCR0.
ITU channel 0
settings
(2)
(1)
PWM0
(2)
0
IOA2
(1)
1
1
—
IOA1
0
0
0
1
—
—
IOA0
0
1
—
—
—
Rev. 7.00 Sep 21, 2005 page 303 of 878
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Section 9 I/O Ports
Pin
Pin Functions and Selection Method
PA1/TP1/
TCLKB/
TEND1
DMAC channel 1 settings (bits DTS2/1/0A and DTS2/1/0B in DTCR1A and DTCR1B),
bit NDER1 in NDERA, and bit PA1DDR in PADDR select the pin function as follows
DMAC
channel 1
settings
(1) in table
below
PA1DDR
—
NDER1
Pin function
(2) in table
below
0
1
1
—
—
0
1
TEND1 output
PA1 input
PA1 output
TP1 output
TCLKB input*
Note: * TCLKB input when MDF = 1 in TMDR, or when TPSC2 = 1, TPSC1 = 0, and
TPSC0 = 1 in any of TCR4 to TCR0.
DMAC
channel 1
settings
(2)
(1)
DTS2A,
DTS1A
Not both 1
DTS0A
—
(2)
(1)
(2)
(1)
Both 1
0
0
1
1
1
DTS2B
0
1
1
0
1
0
1
1
DTS1B
—
0
1
—
—
—
0
1
Rev. 7.00 Sep 21, 2005 page 304 of 878
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Section 9 I/O Ports
Pin
Pin Functions and Selection Method
PA0/TP0/
TCLKA/
TEND0
DMAC channel 0 settings (bits DTS2/1/0A and DTS2/1/0B in DTCR0A and DTCR0B),
bit NDER0 in NDERA, and bit PA0DDR in PADDR select the pin function as follows
DMAC
channel 0
settings
(1) in table
below
PA0DDR
—
NDER0
Pin function
(2) in table
below
0
1
1
—
—
0
1
TEND0 output
PA0 input
PA0 output
TP0 output
TCLKA input*
Note: * TCLKA input when MDF = 1 in TMDR, or when TPSC2 = 1 and TPSC1 = 0 in
any of TCR4 to TCR0.
DMAC
channel 0
settings
(2)
(1)
DTS2A,
DTS1A
Not both 1
DTS0A
—
(2)
(1)
(2)
(1)
Both 1
0
0
1
1
1
DTS2B
0
1
1
0
1
0
1
1
DTS1B
—
0
1
—
—
—
0
1
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Section 9 I/O Ports
9.12
Port B
9.12.1
Overview
Port B is an 8-bit input/output port that is also used for output (TP15 to TP8) from the
programmable timing pattern controller (TPC), input/output (TIOCB4, TIOCB3, TIOCA4,
TIOCA3) and output (TOCXB4, TOCXA4) by the 16-bit integrated timer unit (ITU), input
(DREQ1, DREQ0) to the DMA controller (DMAC), ADTRG input to the A/D converter, and CS7
output. A reset or hardware standby leaves port B as an input port. For selecting the pin function,
see table 9.21. Usage of pins for TPC, ITU, DMAC, and A/D converter input and output is
described in the sections on those modules. For output of CS7 in modes 1 to 6, see section 6.3.2,
Chip Select Signals. Pins not assigned to any of these functions are available for generic
input/output. Figure 9.11 shows the pin configuration of port B.
Pins in port B can drive one TTL load and a 30-pF capacitive load. They can also drive an LED or
darlington transistor pair. Pins PB3 to PB0 have Schmitt-trigger inputs.
Rev. 7.00 Sep 21, 2005 page 306 of 878
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Section 9 I/O Ports
Port B pins
PB7/TP15/DREQ1/ADTRG
PB6/TP14/DREQ0/CS7
PB5/TP13/TOCXB4
PB4/TP12/TOCXA4
Port B
PB3/TP11/TIOCB4
PB2/TP10/TIOCA4
PB1/TP9/TIOCB3
PB0/TP8/TIOCA3
Pin functions in modes 1 to 6
PB7 (input/output)/TP15 (output)/DREQ1 (input)/ADTRG (input)
PB6 (input/output)/TP14 (output)/DREQ0 (input)/CS7 (output)
PB5 (input/output)/TP13 (output)/TOCXB4 (output)
PB4 (input/output)/TP12 (output)/TOCXA4 (output)
PB3 (input/output)/TP11 (output)/TIOCB4 (input/output)
PB2 (input/output)/TP10 (output)/TIOCA4 (input/output)
PB1 (input/output)/TP9 (output)/TIOCB3 (input/output)
PB0 (input/output)/TP8 (output)/TIOCA3 (input/output)
Pin functions in mode 7
PB7 (input/output)/TP15 (output)/DREQ1 (input)/ADTRG (input)
PB6 (input/output)/TP14 (output)/DREQ0 (input)
PB5 (input/output)/TP13 (output)/TOCXB4 (output)
PB4 (input/output)/TP12 (output)/TOCXA4 (output)
PB3 (input/output)/TP11 (output)/TIOCB4 (input/output)
PB2 (input/output)/TP10 (output)/TIOCA4 (input/output)
PB1 (input/output)/TP9 (output)/TIOCB3 (input/output)
PB0 (input/output)/TP8 (output)/TIOCA3 (input/output)
Figure 9.11 Port B Pin Configuration
Rev. 7.00 Sep 21, 2005 page 307 of 878
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Section 9 I/O Ports
9.12.2
Register Descriptions
Table 9.20 summarizes the registers of port B.
Table 9.20 Port B Registers
Address*
Name
Abbreviation
R/W
Initial Value
H'FFD4
Port B data direction register
PBDDR
W
H'00
H'FFD6
Port B data register
PBDR
R/W
H'00
Note: * Lower 16 bits of the address.
Port B Data Direction Register (PBDDR)
PBDDR is an 8-bit write-only register that can select input or output for each pin in port B. When
pins are used for TPC output, the corresponding PBDDR bits must also be set.
Bit
7
6
5
4
3
2
1
0
PB7 DDR PB6 DDR PB5 DDR PB4 DDR PB3 DDR PB2 DDR PB1 DDR PB0 DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port B data direction 7 to 0
These bits select input or output for port B pins
While port B acts as an I/O port, a pin in port B becomes an output pin if the corresponding
PBDDR bit is set to 1, and an input pin if this bit is cleared to 0.
PBDDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PBDDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting. If a PBDDR bit is set to 1 while port B acts as an I/O port, the
corresponding pin maintains its output state in software standby mode.
Rev. 7.00 Sep 21, 2005 page 308 of 878
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Section 9 I/O Ports
Port B Data Register (PBDR)
PBDR is an 8-bit readable/writable register that stores output data for pins PB7 to PB0. While port
B acts as an output port, the value of this register is output. When a bit in PBDDR is set to 1, if
port B is read the value of the corresponding PBDR bit is returned. When a bit in PBDDR is
cleared to 0, if port B is read the corresponding pin level is read.
Bit
7
6
5
4
3
2
1
0
PB 7
PB 6
PB 5
PB 4
PB 3
PB 2
PB 1
PB 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port B data 7 to 0
These bits store data for port B pins
PBDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Rev. 7.00 Sep 21, 2005 page 309 of 878
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Section 9 I/O Ports
9.12.3
Pin Functions
Table 9.21 describes the selection of pin functions.
Table 9.21 Port B Pin Functions
Pin
Pin Functions and Selection Method
PB7/TP15/
DREQ1/
ADTRG
DMAC channel 1 settings (bits DTS2/1/0A and DTS2/1/0B in DTCR1A and DTCR1B),
bit TRGE in ADCR, bit NDER15 in NDERB, and bit PB7DDR in PBDDR select the pin
function as follows
PB7DDR
0
1
1
NDER15
—
0
1
PB7 input
PB7 output
Pin function
TP15 output
1
DREQ1 input*
2
ADTRG input*
Notes: 1. DREQ1 input under DMAC channel 1 settings (1) in the table below.
2. ADTRG input when TRGE = 1.
DMAC
channel
1 settings
(2)
DTS2A, DTS1A
Not both 1
DTS0A
(1)
(2)
(1)
(2)
(1)
Both 1
—
0
0
1
1
1
DTS2B
0
1
1
0
1
0
1
1
DTS1B
—
0
1
—
—
—
0
1
Rev. 7.00 Sep 21, 2005 page 310 of 878
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Section 9 I/O Ports
Pin
Pin Functions and Selection Method
PB6/TP14/
DREQ0/
CS7
Bit CS7E in CSCR, DMAC channel 0 settings (bits DTS2/1/0A and DTS2/1/0B in
DTCR0A and DTCR0B), bit NDER14 in NDERB, and bit PB6DDR in PBDDR select the
pin function as follows
PB6DDR
0
1
1
—
CS7E
0
0
0
1
NDER14
—
0
1
—
PB6 input
PB6 output
TP14 output
—
Pin function
DREQ0 input*
CS7 output
Note: * DREQ0 input under DMAC channel 0 settings (1) in the table below.
DMAC
channel 0
settings
(2)
DTS2A, DTS1A
Not both 1
DTS0A
PB5/TP13/
TOCXB4
(1)
(1)
(2)
(1)
Both 1
—
0
0
1
1
1
DTS2B
0
1
1
0
1
0
1
1
DTS1B
—
0
1
—
—
—
0
1
ITU channel 4 settings (bit CMD1 in TFCR and bit EXB4 in TOER), bit NDER13 in
NDERB, and bit PB5DDR in PBDDR select the pin function as follows
EXB4, CMD1
Not both 1
Both 1
PB5DDR
0
1
1
—
NDER13
—
0
1
—
PB5 input
PB5 output
TP13 output
TOCXB4 output
Pin function
PB4/TP12/
TOCXA4
(2)
ITU channel 4 settings (bit CMD1 in TFCR and bit EXA4 in TOER), bit NDER12 in
NDERB, and bit PB4DDR in PBDDR select the pin function as follows
EXA4, CMD1
Not both 1
Both 1
PB4DDR
0
1
1
—
NDER12
—
0
1
—
PB4 input
PB4 output
TP12 output
TOCXA4 output
Pin function
Rev. 7.00 Sep 21, 2005 page 311 of 878
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Section 9 I/O Ports
Pin
Pin Functions and Selection Method
PB3/TP11/
TIOCB4
ITU channel 4 settings (bit PWM4 in TMDR, bit CMD1 in TFCR, bit EB4 in TOER, and
bits IOB2 to IOB0 in TIOR4), bit NDER11 in NDERB, and bit PB3DDR in PBDDR
select the pin function as follows
ITU channel 4
settings
(1) in table
below
(2) in table
below
PB3DDR
—
0
1
1
NDER11
—
—
0
1
TIOCB4 output
PB3 input
PB3 output
TP11 output
Pin function
TIOCB4 input*
Note: * TIOCB4 input when CMD1 = PWM4 = 0 and IOB2 = 1.
ITU channel 4
settings
PB2/TP10/
TIOCA4
(2)
(2)
(1)
(2)
(1)
EB4
0
CMD1
—
1
IOB2
—
0
0
0
1
—
IOB1
—
0
0
1
—
—
IOB0
—
0
1
—
—
—
0
1
ITU channel 4 settings (bit CMD1 in TFCR, bit EA4 in TOER, bit PWM4 in TMDR, and
bits IOA2 to IOA0 in TIOR4), bit NDER10 in NDERB, and bit PB2DDR in PBDDR
select the pin function as follows
ITU channel 4
settings
(1) in table
below
(2) in table
below
PB2DDR
—
0
1
1
NDER10
—
—
0
1
TIOCA4 output
PB2 input
PB2 output
TP10 output
Pin function
TIOCA4 input*
Note: * TIOCA4 input when CMD1 = PWM4 = 0 and IOA2 = 1.
ITU channel 4
settings
(2)
(2)
(1)
EA4
0
CMD1
—
PWM4
—
IOA2
—
0
0
IOA1
—
0
IOA0
—
0
Rev. 7.00 Sep 21, 2005 page 312 of 878
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(2)
(1)
1
0
1
0
1
—
0
1
—
—
0
1
—
—
—
1
—
—
—
—
Section 9 I/O Ports
Pin
Pin Functions and Selection Method
PB1/TP9/
TIOCB3
ITU channel 3 settings (bit PWM3 in TMDR, bit CMD1 in TFCR, bit EB3 in TOER, and
bits IOB2 to IOB0 in TIOR3), bit NDER9 in NDERB, and bit PB1DDR in PBDDR select
the pin function as follows
ITU channel 3
settings
(1) in table
below
(2) in table
below
PB1DDR
—
0
1
1
NDER9
—
—
0
1
TIOCB3 output
PB1 input
PB1 output
TP9 output
Pin function
TIOCB3 input*
Note: * TIOCB3 input when CMD1 = PWM3 = 0 and IOB2 = 1.
ITU channel 3
settings
PB0/TP8/
TIOCA3
(2)
(2)
(1)
(2)
(1)
EB3
0
CMD1
—
1
IOB2
—
0
0
0
1
—
IOB1
—
0
0
1
—
—
IOB0
—
0
1
—
—
—
0
1
ITU channel 3 settings (bit CMD1 in TFCR, bit EA3 in TOER, bit PWM3 in TMDR, and
bits IOA2 to IOA0 in TIOR3), bit NDER8 in NDERB, and bit PB0DDR in PBDDR select
the pin function as follows
ITU channel 3
settings
(1) in table
below
(2) in table
below
PB0DDR
—
0
1
1
NDER8
—
—
0
1
TIOCA3 output
PB0 input
PB0 output
TP8 output
Pin function
TIOCA3 input*
Note: * TIOCA3 input when CMD1 = PWM3 = 0 and IOA2 = 1.
ITU channel 3
settings
(2)
(2)
(1)
EA3
0
CMD1
—
PWM3
—
IOA2
—
0
0
IOA1
—
0
IOA0
—
0
(2)
(1)
1
0
1
0
1
—
0
1
—
—
0
1
—
—
—
1
—
—
—
—
Rev. 7.00 Sep 21, 2005 page 313 of 878
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Section 9 I/O Ports
Rev. 7.00 Sep 21, 2005 page 314 of 878
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Section 10 16-Bit Integrated Timer Unit (ITU)
Section 10 16-Bit Integrated Timer Unit (ITU)
10.1
Overview
The H8/3048 Group has a built-in 16-bit integrated timer unit (ITU) with five 16-bit timer
channels.
When the ITU is not used, it can be independently halted to conserve power. For details see
section 21.6, Module Standby Function.
10.1.1
Features
ITU features are listed below.
• Capability to process up to 12 pulse outputs or 10 pulse inputs
• Ten general registers (GRs, two per channel) with independently-assignable output compare or
input capture functions
• Selection of eight counter clock sources for each channel:
Internal clocks: φ, φ/2, φ/4, φ/8
External clocks: TCLKA, TCLKB, TCLKC, TCLKD
• Five operating modes selectable in all channels:
Waveform output by compare match
Selection of 0 output, 1 output, or toggle output (only 0 or 1 output in channel 2)
Input capture function
Rising edge, falling edge, or both edges (selectable)
Counter clearing function
Counters can be cleared by compare match or input capture
Synchronization
Two or more timer counters (TCNTs) can be preset simultaneously, or cleared
simultaneously by compare match or input capture. Counter synchronization enables
synchronous register input and output.
PWM mode
PWM output can be provided with an arbitrary duty cycle. With synchronization, up to
five-phase PWM output is possible
• Phase counting mode selectable in channel 2
Two-phase encoder output can be counted automatically.
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Section 10 16-Bit Integrated Timer Unit (ITU)
• Three additional modes selectable in channels 3 and 4
Reset-synchronized PWM mode
If channels 3 and 4 are combined, three-phase PWM output is possible with three pairs of
complementary waveforms.
Complementary PWM mode
If channels 3 and 4 are combined, three-phase PWM output is possible with three pairs of
non-overlapping complementary waveforms.
Buffering
Input capture registers can be double-buffered. Output compare registers can be updated
automatically.
• High-speed access via internal 16-bit bus
The 16-bit timer counters, general registers, and buffer registers can be accessed at high speed
via a 16-bit bus.
• Fifteen interrupt sources
Each channel has two compare match/input capture interrupts and an overflow interrupt. All
interrupts can be requested independently.
• Activation of DMA controller (DMAC)
Four of the compare match/input capture interrupts from channels 0 to 3 can start the DMAC.
• Output triggering of programmable timing pattern controller (TPC)
Compare match/input capture signals from channels 0 to 3 can be used as TPC output triggers.
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Section 10 16-Bit Integrated Timer Unit (ITU)
Table 10.1 summarizes the ITU functions.
Table 10.1 ITU Functions
Item
Channel 0
Clock sources
Internal clocks: φ, φ/2, φ/4, φ/8
Channel 1
Channel 2
Channel 3
Channel 4
External clocks: TCLKA, TCLKB, TCLKC, TCLKD, selectable independently
General registers
(output compare/input
capture registers)
GRA0, GRB0
GRA1, GRB1
GRA2, GRB2
GRA3, GRB3
GRA4, GRB4
Buffer registers
—
—
—
BRA3, BRB3
BRA4, BRB4
Input/output pins
TIOCA0,
TIOCB0
TIOCA1,
TIOCB1
TIOCA2,
TIOCB2
TIOCA3,
TIOCB3
TIOCA4,
TIOCB4
Output pins
—
—
—
—
TOCXA4,
TOCXB4
Counter clearing function
GRA0/GRB0
GRA1/GRB1
GRA2/GRB2
GRA3/GRB3
GRA4/GRB4
compare match compare match compare match compare match compare match
or input capture or input capture or input capture or input capture or input capture
Compare match 0
output
1
O
O
O
O
O
O
O
O
O
O
O
O
—
O
O
Input capture function
O
O
O
O
O
Synchronization
O
O
O
O
O
PWM mode
O
O
O
O
O
Reset-synchronized
PWM mode
—
—
—
O
O
Complementary PWM
mode
—
—
—
O
O
Phase counting mode
—
—
O
—
—
Buffering
—
—
—
O
O
DMAC activation
GRA0 compare GRA1 compare GRA2 compare GRA3 compare —
match or input match or input match or input match or input
capture
capture
capture
capture
Toggle
Interrupt sources
Three sources
Three sources
Three sources
•
Compare
match/input
capture A0
•
Compare
match/input
capture A1
•
Compare
•
Compare
match/input match/input
capture A2
capture A3
•
Compare
match/input
capture A4
•
Compare
match/input
capture B0
•
Compare
match/input
capture B1
•
Compare
•
Compare
match/input match/input
capture B2
capture B3
•
Compare
match/input
capture B4
•
Overflow •
Overflow •
Overflow
Three sources
•
Three sources
Overflow •
Overflow
Legend
O: Available
—: Not available
Rev. 7.00 Sep 21, 2005 page 317 of 878
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Section 10 16-Bit Integrated Timer Unit (ITU)
10.1.2
Block Diagrams
ITU Block Diagram (Overall): Figure 10.1 is a block diagram of the ITU.
TCLKA to TCLKD
IMIA0 to IMIA4
IMIB0 to IMIB4
OVI0 to OVI4
Clock selector
φ, φ/2, φ/4, φ/8
Control logic
TOCXA4, TOCXB4
TIOCA0 to TIOCA4
TIOCB0 to TIOCB4
TSTR
TSNC
TMDR
TFCR
Module data bus
Legend
TOER:
TOCR:
TSTR:
TSNC:
TMDR:
TFCR:
Timer output master enable register (8 bits)
Timer output control register (8 bits)
Timer start register (8 bits)
Timer synchro register (8 bits)
Timer mode register (8 bits)
Timer function control register (8 bits)
Figure 10.1 ITU Block Diagram (Overall)
Rev. 7.00 Sep 21, 2005 page 318 of 878
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Internal data bus
TOCR
Bus interface
16-bit timer channel 0
16-bit timer channel 1
16-bit timer channel 2
16-bit timer channel 3
16-bit timer channel 4
TOER
Section 10 16-Bit Integrated Timer Unit (ITU)
Block Diagram of Channels 0 and 1: ITU channels 0 and 1 are functionally identical. Both have
the structure shown in figure 10.2.
TCLKA to TCLKD
φ, φ/2, φ/4, φ/8
TIOCA0
TIOCB0
Clock selector
Control logic
IMIA0
IMIB0
OVI0
TSR
TIER
TIOR
TCR
GRB
GRA
TCNT
Comparator
Module data bus
Legend
TCNT:
GRA, GRB:
TCR:
TIOR:
TIER:
TSR:
Timer counter (16 bits)
General registers A and B (input capture/output compare registers) (16 bits × 2)
Timer control register (8 bits)
Timer I/O control register (8 bits)
Timer interrupt enable register (8 bits)
Timer status register (8 bits)
Figure 10.2 Block Diagram of Channels 0 and 1 (for Channel 0)
Rev. 7.00 Sep 21, 2005 page 319 of 878
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Section 10 16-Bit Integrated Timer Unit (ITU)
Block Diagram of Channel 2: Figure 10.3 is a block diagram of channel 2. This is the channel
that provides only 0 output and 1 output.
TCLKA to TCLKD
φ, φ/2, φ/4, φ/8
TIOCA2
TIOCB2
Clock selector
Control logic
IMIA2
IMIB2
OVI2
TSR2
TIER2
TIOR2
TCR2
GRB2
GRA2
TCNT2
Comparator
Module data bus
Legend
Timer counter 2 (16 bits)
TCNT2:
GRA2, GRB2: General registers A2 and B2 (input capture/output compare registers)
(16 bits × 2)
Timer control register 2 (8 bits)
TCR2:
Timer I/O control register 2 (8 bits)
TIOR2:
Timer interrupt enable register 2 (8 bits)
TIER2:
Timer status register 2 (8 bits)
TSR2:
Figure 10.3 Block Diagram of Channel 2
Rev. 7.00 Sep 21, 2005 page 320 of 878
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Section 10 16-Bit Integrated Timer Unit (ITU)
Block Diagrams of Channels 3 and 4: Figure 10.4 is a block diagram of channel 3. Figure 10.5 is
a block diagram of channel 4.
TCLKA to
TCLKD
φ, φ/2,
φ/4, φ/8
TIOCA3
TIOCB3
Clock selector
Control logic
IMIA3
IMIB3
OVI3
TSR3
TIER3
TIOR3
TCR3
GRB3
BRB3
GRA3
BRA3
TCNT3
Comparator
Module data bus
Legend
Timer counter 3 (16 bits)
TCNT3:
GRA3, GRB3: General registers A3 and B3 (input capture/output compare registers)
(16 bits × 2)
BRA3, BRB3: Buffer registers A3 and B3 (input capture/output compare buffer registers)
(16 bits × 2)
Timer control register 3 (8 bits)
TCR3:
TIOR3:
Timer I/O control register 3 (8 bits)
TIER3:
Timer interrupt enable register 3 (8 bits)
TSR3:
Timer status register 3 (8 bits)
Figure 10.4 Block Diagram of Channel 3
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Section 10 16-Bit Integrated Timer Unit (ITU)
TCLKA to
TCLKD
φ, φ/2,
φ/4, φ/8
TOCXA4
TOCXB4
TIOCA4
TIOCB4
IMIA4
IMIB4
OVI4
Clock selector
Control logic
TSR4
TIER4
TIOR4
TCR4
GRB4
BRB4
GRA4
BRA4
TCNT4
Comparator
Module data bus
Legend
Timer counter 4 (16 bits)
TCNT4:
GRA4, GRB4: General registers A4 and B4 (input capture/output compare registers)
(16 bits × 2)
BRA4, BRB4: Buffer registers A4 and B4 (input capture/output compare buffer registers)
(16 bits × 2)
Timer control register 4 (8 bits)
TCR4:
TIOR4:
Timer I/O control register 4 (8 bits)
TIER4:
Timer interrupt enable register 4 (8 bits)
TSR4:
Timer status register 4 (8 bits)
Figure 10.5 Block Diagram of Channel 4
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Section 10 16-Bit Integrated Timer Unit (ITU)
10.1.3
Input/Output Pins
Table 10.2 summarizes the ITU pins.
Table 10.2 ITU Pins
Abbreviation
Input/
Output
Common Clock input A
TCLKA
Input
External clock A input pin
(phase-A input pin in phase counting mode)
Clock input B
TCLKB
Input
External clock B input pin
(phase-B input pin in phase counting mode)
Clock input C
TCLKC
Input
External clock C input pin
Clock input D
TCLKD
Input
External clock D input pin
Input capture/output
compare A0
TIOCA0
Input/
output
GRA0 output compare or input capture pin
PWM output pin in PWM mode
Input capture/output
compare B0
TIOCB0
Input/
output
GRB0 output compare or input capture pin
Input capture/output
compare A1
TIOCA1
Input/
output
GRA1 output compare or input capture pin
PWM output pin in PWM mode
Input capture/output
compare B1
TIOCB1
Input/
output
GRB1 output compare or input capture pin
Input capture/output
compare A2
TIOCA2
Input/
output
GRA2 output compare or input capture pin
PWM output pin in PWM mode
Input capture/output
compare B2
TIOCB2
Input/
output
GRB2 output compare or input capture pin
Input capture/output
compare A3
TIOCA3
Input/
output
Input capture/output
compare B3
TIOCB3
Input/
output
GRA3 output compare or input capture pin
PWM output pin in PWM mode,
t compare
PWM or dinput capture
t pin
GRB3l output
Input capture/output
compare A4
TIOCA4
Input/
output
Input capture/output
compare B4
TIOCB4
Input/
output
Channel
0
1
2
3
4
Name
Output compare XA4 TOCXA4
Output
Output compare XB4 TOCXB4
Output
Function
PWM output pin in complementary PWM
d output tcompare
h or
i input
d PWM
GRA4
captured pin
PWM output pin in PWM mode,
t compare
PWM or dinput capture
t pin
GRB4l output
PWM output pin in complementary PWM
d output pin
t in complementary
h i d PWM PWM
d
PWM
mode or reset-synchronized PWM mode
PWM output pin in complementary PWM
mode or reset-synchronized PWM mode
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Section 10 16-Bit Integrated Timer Unit (ITU)
10.1.4
Register Configuration
Table 10.3 summarizes the ITU registers.
Table 10.3 ITU Registers
Name
Abbreviation
R/W
Initial
Value
H'FF60
Timer start register
TSTR
R/W
H'E0
H'FF61
Timer synchro register
TSNC
R/W
H'E0
H'FF62
Timer mode register
TMDR
R/W
H'80
H'FF63
Timer function control register
TFCR
R/W
H'C0
H'FF90
Timer output master enable register
TOER
R/W
H'FF
H'FF91
Timer output control register
TOCR
R/W
H'FF
H'FF64
Timer control register 0
TCR0
R/W
H'80
H'FF65
Timer I/O control register 0
TIOR0
R/W
H'88
H'FF66
Timer interrupt enable register 0
TIER0
R/W
Channel
Address*
Common
0
1
1
H'F8
2
H'FF67
Timer status register 0
TSR0
R/(W)*
H'F8
H'FF68
Timer counter 0 (high)
TCNT0H
R/W
H'00
H'FF69
Timer counter 0 (low)
TCNT0L
R/W
H'00
H'FF6A
General register A0 (high)
GRA0H
R/W
H'FF
H'FF6B
General register A0 (low)
GRA0L
R/W
H'FF
H'FF6C
General register B0 (high)
GRB0H
R/W
H'FF
H'FF6D
General register B0 (low)
GRB0L
R/W
H'FF
H'FF6E
Timer control register 1
TCR1
R/W
H'80
H'FF6F
Timer I/O control register 1
TIOR1
R/W
H'88
H'FF70
Timer interrupt enable register 1
TIER1
R/W
H'F8
2
H'FF71
Timer status register 1
TSR1
R/(W)*
H'F8
H'FF72
Timer counter 1 (high)
TCNT1H
R/W
H'00
H'FF73
Timer counter 1 (low)
TCNT1L
R/W
H'00
H'FF74
General register A1 (high)
GRA1H
R/W
H'FF
H'FF75
General register A1 (low)
GRA1L
R/W
H'FF
H'FF76
General register B1 (high)
GRB1H
R/W
H'FF
H'FF77
General register B1 (low)
GRB1L
R/W
H'FF
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Section 10 16-Bit Integrated Timer Unit (ITU)
Name
Abbreviation
R/W
Initial
Value
Timer control register 2
TCR2
R/W
H'80
H'FF79
Timer I/O control register 2
TIOR2
R/W
H'88
H'FF7A
Timer interrupt enable register 2
TIER2
R/W
Channel
Address*
2
H'FF78
3
1
H'F8
2
H'FF7B
Timer status register 2
TSR2
R/(W)*
H'F8
H'FF7C
Timer counter 2 (high)
TCNT2H
R/W
H'00
H'FF7D
Timer counter 2 (low)
TCNT2L
R/W
H'00
H'FF7E
General register A2 (high)
GRA2H
R/W
H'FF
H'FF7F
General register A2 (low)
GRA2L
R/W
H'FF
H'FF80
General register B2 (high)
GRB2H
R/W
H'FF
H'FF81
General register B2 (low)
GRB2L
R/W
H'FF
H'FF82
Timer control register 3
TCR3
R/W
H'80
H'FF83
Timer I/O control register 3
TIOR3
R/W
H'88
H'FF84
Timer interrupt enable register 3
TIER3
R/W
H'F8
2
H'FF85
Timer status register 3
TSR3
R/(W)*
H'F8
H'FF86
Timer counter 3 (high)
TCNT3H
R/W
H'00
H'FF87
Timer counter 3 (low)
TCNT3L
R/W
H'00
H'FF88
General register A3 (high)
GRA3H
R/W
H'FF
H'FF89
General register A3 (low)
GRA3L
R/W
H'FF
H'FF8A
General register B3 (high)
GRB3H
R/W
H'FF
H'FF8B
General register B3 (low)
GRB3L
R/W
H'FF
H'FF8C
Buffer register A3 (high)
BRA3H
R/W
H'FF
H'FF8D
Buffer register A3 (low)
BRA3L
R/W
H'FF
H'FF8E
Buffer register B3 (high)
BRB3H
R/W
H'FF
H'FF8F
Buffer register B3 (low)
BRB3L
R/W
H'FF
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Section 10 16-Bit Integrated Timer Unit (ITU)
Name
Abbreviation
R/W
Initial
Value
Timer control register 4
TCR4
R/W
H'80
H'FF93
Timer I/O control register 4
TIOR4
R/W
H'88
H'FF94
Timer interrupt enable register 4
TIER4
R/W
Channel
Address*
4
H'FF92
1
H'F8
2
H'FF95
Timer status register 4
TSR4
R/(W)*
H'F8
H'FF96
Timer counter 4 (high)
TCNT4H
R/W
H'00
H'FF97
Timer counter 4 (low)
TCNT4L
R/W
H'00
H'FF98
General register A4 (high)
GRA4H
R/W
H'FF
H'FF99
General register A4 (low)
GRA4L
R/W
H'FF
H'FF9A
General register B4 (high)
GRB4H
R/W
H'FF
H'FF9B
General register B4 (low)
GRB4L
R/W
H'FF
H'FF9C
Buffer register A4 (high)
BRA4H
R/W
H'FF
H'FF9D
Buffer register A4 (low)
BRA4L
R/W
H'FF
H'FF9E
Buffer register B4 (high)
BRB4H
R/W
H'FF
H'FF9F
Buffer register B4 (low)
BRB4L
R/W
H'FF
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written, to clear flags.
Rev. 7.00 Sep 21, 2005 page 326 of 878
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Section 10 16-Bit Integrated Timer Unit (ITU)
10.2
Register Descriptions
10.2.1
Timer Start Register (TSTR)
TSTR is an 8-bit readable/writable register that starts and stops the timer counter (TCNT) in
channels 0 to 4.
Bit
7
6
5
4
3
2
1
0
—
—
—
STR4
STR3
STR2
STR1
STR0
Initial value
1
1
1
0
0
0
0
0
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
Reserved bits
Counter start 4 to 0
These bits start and
stop TCNT4 to TCNT0
TSTR is initialized to H'E0 by a reset and in standby mode.
Bits 7 to 5—Reserved: Read-only bits, always read as 1.
Bit 4—Counter Start 4 (STR4): Starts and stops timer counter 4 (TCNT4).
Bit 4: STR4
Description
0
TCNT4 is halted
1
TCNT4 is counting
(Initial value)
Bit 3—Counter Start 3 (STR3): Starts and stops timer counter 3 (TCNT3).
Bit 3: STR3
Description
0
TCNT3 is halted
1
TCNT3 is counting
(Initial value)
Bit 2—Counter Start 2 (STR2): Starts and stops timer counter 2 (TCNT2).
Bit 2: STR2
Description
0
TCNT2 is halted
1
TCNT2 is counting
(Initial value)
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Section 10 16-Bit Integrated Timer Unit (ITU)
Bit 1—Counter Start 1 (STR1): Starts and stops timer counter 1 (TCNT1).
Bit 1: STR1
Description
0
TCNT1 is halted
1
TCNT1 is counting
(Initial value)
Bit 0—Counter Start 0 (STR0): Starts and stops timer counter 0 (TCNT0).
Bit 0: STR0
Description
0
TCNT0 is halted
1
TCNT0 is counting
10.2.2
(Initial value)
Timer Synchro Register (TSNC)
TSNC is an 8-bit readable/writable register that selects whether channels 0 to 4 operate
independently or synchronously. Channels are synchronized by setting the corresponding bits to 1.
Bit
7
6
5
4
3
2
1
0
—
—
—
SYNC4
SYNC3
SYNC2
SYNC1
SYNC0
Initial value
1
1
1
0
0
0
0
0
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
Reserved bits
Timer sync 4 to 0
These bits synchronize
channels 4 to 0
TSNC is initialized to H'E0 by a reset and in standby mode.
Bits 7 to 5—Reserved: Read-only bits, always read as 1.
Bit 4—Timer Sync 4 (SYNC4): Selects whether channel 4 operates independently or
synchronously.
Bit 4: SYNC4
Description
0
Channel 4’s timer counter (TCNT4) operates independently
TCNT4 is preset and cleared independently of other channels
1
Channel 4 operates synchronously
TCNT4 can be synchronously preset and cleared
Rev. 7.00 Sep 21, 2005 page 328 of 878
REJ09B0259-0700
(Initial value)
Section 10 16-Bit Integrated Timer Unit (ITU)
Bit 3—Timer Sync 3 (SYNC3): Selects whether channel 3 operates independently or
synchronously.
Bit 3: SYNC3
Description
0
Channel 3’s timer counter (TCNT3) operates independently
(Initial value)
TCNT3 is preset and cleared independently of other channels
1
Channel 3 operates synchronously
TCNT3 can be synchronously preset and cleared
Bit 2—Timer Sync 2 (SYNC2): Selects whether channel 2 operates independently or
synchronously.
Bit 2: SYNC2
Description
0
Channel 2’s timer counter (TCNT2) operates independently
1
Channel 2 operates synchronously
(Initial value)
TCNT2 is preset and cleared independently of other channels
TCNT2 can be synchronously preset and cleared
Bit 1—Timer Sync 1 (SYNC1): Selects whether channel 1 operates independently or
synchronously.
Bit 1: SYNC1
Description
0
Channel 1’s timer counter (TCNT1) operates independently
1
Channel 1 operates synchronously
(Initial value)
TCNT1 is preset and cleared independently of other channels
TCNT1 can be synchronously preset and cleared
Bit 0—Timer Sync 0 (SYNC0): Selects whether channel 0 operates independently or
synchronously.
Bit 0: Bit 0
Description
0
Channel 0’s timer counter (TCNT0) operates independently
1
Channel 0 operates synchronously
(Initial value)
TCNT0 is preset and cleared independently of other channels
TCNT0 can be synchronously preset and cleared
Rev. 7.00 Sep 21, 2005 page 329 of 878
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Section 10 16-Bit Integrated Timer Unit (ITU)
10.2.3
Timer Mode Register (TMDR)
TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 4. It also
selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2.
Bit
7
6
5
4
3
2
1
0
—
MDF
FDIR
PWM4
PWM3
PWM2
PWM1
PWM0
Initial value
1
0
0
0
0
0
0
0
Read/Write
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PWM mode 4 to 0
These bits select PWM
mode for channels 4 to 0
Flag direction
Selects the setting condition for the overflow
flag (OVF) in timer status register 2 (TSR2)
Phase counting mode flag
Selects phase counting mode for channel 2
Reserved bit
TMDR is initialized to H'80 by a reset and in standby mode.
Bit 7—Reserved: Read-only bit, always read as 1.
Bit 6—Phase Counting Mode Flag (MDF): Selects whether channel 2 operates normally or in
phase counting mode.
Bit 6: MDF
Description
0
Channel 2 operates normally
1
Channel 2 operates in phase counting mode
Rev. 7.00 Sep 21, 2005 page 330 of 878
REJ09B0259-0700
(Initial value)
Section 10 16-Bit Integrated Timer Unit (ITU)
When MDF is set to 1 to select phase counting mode, TCNT2 operates as an up/down-counter and
pins TCLKA and TCLKB become counter clock input pins. TCNT2 counts both rising and falling
edges of TCLKA and TCLKB, and counts up or down as follows.
Counting Direction
Down-Counting
TCLKA pin
↑
Low
TCLKB pin
High
↑
Up-Counting
↓
High
Low
↓
↑
High
Low
↓
↓
Low
High
↓
In phase counting mode channel 2 operates as above regardless of the external clock edges
selected by bits CKEG1 and CKEG0 and the clock source selected by bits TPSC2 to TPSC0 in
TCR2. Phase counting mode takes precedence over these settings.
The counter clearing condition selected by the CCLR1 and CCLR0 bits in TCR2 and the compare
match/input capture settings and interrupt functions of TIOR2, TIER2, and TSR2 remain effective
in phase counting mode.
Bit 5—Flag Direction (FDIR): Designates the setting condition for the OVF flag in TSR2. The
FDIR designation is valid in all modes in channel 2.
Bit 5: FDIR
Description
0
OVF is set to 1 in TSR2 when TCNT2 overflows or underflows
1
OVF is set to 1 in TSR2 when TCNT2 overflows
(Initial value)
Bit 4—PWM Mode 4 (PWM4): Selects whether channel 4 operates normally or in PWM mode.
Bit 4: PWM4
Description
0
Channel 4 operates normally
1
Channel 4 operates in PWM mode
(Initial value)
When bit PWM4 is set to 1 to select PWM mode, pin TIOCA4 becomes a PWM output pin. The
output goes to 1 at compare match with GRA4, and to 0 at compare match with GRB4.
If complementary PWM mode or reset-synchronized PWM mode is selected by bits CMD1 and
CMD0 in TFCR, the CMD1 and CMD0 setting takes precedence and the PWM4 setting is
ignored.
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Section 10 16-Bit Integrated Timer Unit (ITU)
Bit 3—PWM Mode 3 (PWM3): Selects whether channel 3 operates normally or in PWM mode.
Bit 3: PWM3
Description
0
Channel 3 operates normally
1
Channel 3 operates in PWM mode
(Initial value)
When bit PWM3 is set to 1 to select PWM mode, pin TIOCA3 becomes a PWM output pin. The
output goes to 1 at compare match with GRA3, and to 0 at compare match with GRB3.
If complementary PWM mode or reset-synchronized PWM mode is selected by bits CMD1 and
CMD0 in TFCR, the CMD1 and CMD0 setting takes precedence and the PWM3 setting is
ignored.
Bit 2—PWM Mode 2 (PWM2): Selects whether channel 2 operates normally or in PWM mode.
Bit 2: PWM2
Description
0
Channel 2 operates normally
1
Channel 2 operates in PWM mode
(Initial value)
When bit PWM2 is set to 1 to select PWM mode, pin TIOCA2 becomes a PWM output pin. The
output goes to 1 at compare match with GRA2, and to 0 at compare match with GRB2.
Bit 1—PWM Mode 1 (PWM1): Selects whether channel 1 operates normally or in PWM mode.
Bit 1: PWM1
Description
0
Channel 1 operates normally
1
Channel 1 operates in PWM mode
(Initial value)
When bit PWM1 is set to 1 to select PWM mode, pin TIOCA1 becomes a PWM output pin. The
output goes to 1 at compare match with GRA1, and to 0 at compare match with GRB1.
Bit 0—PWM Mode 0 (PWM0): Selects whether channel 0 operates normally or in PWM mode.
Bit 0: PWM0
Description
0
Channel 0 operates normally
1
Channel 0 operates in PWM mode
(Initial value)
When bit PWM0 is set to 1 to select PWM mode, pin TIOCA0 becomes a PWM output pin. The
output goes to 1 at compare match with GRA0, and to 0 at compare match with GRB0.
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Section 10 16-Bit Integrated Timer Unit (ITU)
10.2.4
Timer Function Control Register (TFCR)
TFCR is an 8-bit readable/writable register that selects complementary PWM mode, resetsynchronized PWM mode, and buffering for channels 3 and 4.
Bit
7
6
5
4
3
2
1
0
—
—
CMD1
CMD0
BFB4
BFA4
BFB3
BFA3
Initial value
1
1
0
0
0
0
0
0
Read/Write
—
—
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bits
Combination mode 1/0
These bits select complementary
PWM mode or reset-synchronized
PWM mode for channels 3 and 4
Buffer mode B4 and A4
These bits select buffering of
general registers (GRB4 and
GRA4) by buffer registers
(BRB4 and BRA4) in channel 4
Buffer mode B3 and A3
These bits select buffering
of general registers (GRB3
and GRA3) by buffer
registers (BRB3 and BRA3)
in channel 3
TFCR is initialized to H'C0 by a reset and in standby mode.
Bits 7 and 6—Reserved: Read-only bits, always read as 1.
Bits 5 and 4—Combination Mode 1 and 0 (CMD1, CMD0): These bits select whether channels
3 and 4 operate in normal mode, complementary PWM mode, or reset-synchronized PWM mode.
Bit 5: CMD1
Bit 4: CMD0
Description
0
0
Channels 3 and 4 operate normally
(Initial value)
1
1
0
Channels 3 and 4 operate together in complementary
PWM mode
1
Channels 3 and 4 operate together in reset-synchronized
PWM mode
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Section 10 16-Bit Integrated Timer Unit (ITU)
Before selecting reset-synchronized PWM mode or complementary PWM mode, halt the timer
counter or counters that will be used in these modes.
When these bits select complementary PWM mode or reset-synchronized PWM mode, they take
precedence over the setting of the PWM mode bits (PWM4 and PWM3) in TMDR. Settings of
complementary PWM mode or reset-synchronized PWM mode and settings of timer sync bits
SYNC4 and SYNC3 in TSNC are valid simultaneously, however, when complementary PWM
mode is selected, channels 3 and 4 must not be synchronized (do not set bits SYNC3 and SYNC4
both to 1 in TSNC).
Bit 3—Buffer Mode B4 (BFB4): Selects whether GRB4 operates normally in channel 4, or
whether GRB4 is buffered by BRB4.
Bit 3: BFB4
Description
0
GRB4 operates normally
1
GRB4 is buffered by BRB4
(Initial value)
Bit 2—Buffer Mode A4 (BFA4): Selects whether GRA4 operates normally in channel 4, or
whether GRA4 is buffered by BRA4.
Bit 2: BFA4
Description
0
GRA4 operates normally
1
GRA4 is buffered by BRA4
(Initial value)
Bit 1—Buffer Mode B3 (BFB3): Selects whether GRB3 operates normally in channel 3, or
whether GRB3 is buffered by BRB3.
Bit 1: BFB3
Description
0
GRB3 operates normally
1
GRB3 is buffered by BRB3
(Initial value)
Bit 0—Buffer Mode A3 (BFA3): Selects whether GRA3 operates normally in channel 3, or
whether GRA3 is buffered by BRA3.
Bit 0: BFA3
Description
0
GRA3 operates normally
1
GRA3 is buffered by BRA3
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(Initial value)
Section 10 16-Bit Integrated Timer Unit (ITU)
10.2.5
Timer Output Master Enable Register (TOER)
TOER is an 8-bit readable/writable register that enables or disables output settings for channels 3
and 4.
Bit
7
6
5
4
3
2
1
0
—
—
EXB4
EXA4
EB3
EB4
EA4
EA3
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bits
Master enable TOCXA4, TOCXB4
These bits enable or disable output
settings for pins TOCXA4 and TOCXB4
Master enable TIOCA3, TIOCB3 , TIOCA4, TIOCB4
These bits enable or disable output settings for pins
TIOCA3, TIOCB3 , TIOCA4, and TIOCB4
TOER is initialized to H'FF by a reset and in standby mode.
Bits 7 and 6—Reserved: Read-only bits, always read as 1.
Bit 5—Master Enable TOCXB4 (EXB4): Enables or disables ITU output at pin TOCXB4.
Bit 5: EXB4
Description
0
TOCXB4 output is disabled regardless of TFCR settings (TOCXB4 operates as
a generic input/output pin).
If XTGD = 0, EXB4 is cleared to 0 when input capture A occurs in channel 1.
1
TOCXB4 is enabled for output according to TFCR settings
(Initial value)
Bit 4—Master Enable TOCXA4 (EXA4): Enables or disables ITU output at pin TOCXA4.
Bit 4: EXA4
Description
0
TOCXA4 output is disabled regardless of TFCR settings (TOCXA4 operates as
a generic input/output pin).
If XTGD = 0, EXA4 is cleared to 0 when input capture A occurs in channel 1.
1
TOCXA4 is enabled for output according to TFCR settings
(Initial value)
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Section 10 16-Bit Integrated Timer Unit (ITU)
Bit 3—Master Enable TIOCB3 (EB3): Enables or disables ITU output at pin TIOCB3.
Bit 3: EB3
Description
0
TIOCB3 output is disabled regardless of TIOR3 and TFCR settings (TIOCB3
operates as a generic input/output pin).
If XTGD = 0, EB3 is cleared to 0 when input capture A occurs in channel 1.
1
TIOCB3 is enabled for output according to TIOR3 and TFCR settings
(Initial value)
Bit 2—Master Enable TIOCB4 (EB4): Enables or disables ITU output at pin TIOCB4.
Bit 2: EB4
Description
0
TIOCB4 output is disabled regardless of TIOR4 and TFCR settings (TIOCB4
operates as a generic input/output pin).
1
TIOCB4 is enabled for output according to TIOR4 and TFCR settings
(Initial value)
If XTGD = 0, EB4 is cleared to 0 when input capture A occurs in channel 1.
Bit 1—Master Enable TIOCA4 (EA4): Enables or disables ITU output at pin TIOCA4.
Bit 1: EA4
Description
0
TIOCA4 output is disabled regardless of TIOR4, TMDR, and TFCR settings
(TIOCA4 operates as a generic input/output pin).
If XTGD = 0, EA4 is cleared to 0 when input capture A occurs in channel 1.
1
TIOCA4 is enabled for output according to TIOR4, TMDR, and TFCR settings
(Initial value)
Bit 0—Master Enable TIOCA3 (EA3): Enables or disables ITU output at pin TIOCA3.
Bit 0: EA3
Description
0
TIOCA3 output is disabled regardless of TIOR3, TMDR, and TFCR settings
(TIOCA3 operates as a generic input/output pin).
1
TIOCA3 is enabled for output according to TIOR3, TMDR, and TFCR settings
(Initial value)
If XTGD = 0, EA3 is cleared to 0 when input capture A occurs in channel 1.
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Section 10 16-Bit Integrated Timer Unit (ITU)
10.2.6
Timer Output Control Register (TOCR)
TOCR is an 8-bit readable/writable register that selects externally triggered disabling of output in
complementary PWM mode and reset-synchronized PWM mode, and inverts the output levels.
Bit
7
6
5
4
3
2
1
0
—
—
—
XTGD
—
—
OLS4
OLS3
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
R/W
—
—
R/W
R/W
Reserved bits
Output level select 3, 4
These bits select output
levels in complementary
PWM mode and resetsynchronized PWM mode
Reserved bits
External trigger disable
Selects externally triggered disabling of output in
complementary PWM mode and reset-synchronized
PWM mode
The settings of the XTGD, OLS4, and OLS3 bits are valid only in complementary PWM mode
and reset-synchronized PWM mode. These settings do not affect other modes.
TOCR is initialized to H'FF by a reset and in standby mode.
Bits 7 to 5—Reserved: Read-only bits, always read as 1.
Bit 4—External Trigger Disable (XTGD): Selects externally triggered disabling of ITU output
in complementary PWM mode and reset-synchronized PWM mode.
Bit 4: XTGD
Description
0
Input capture A in channel 1 is used as an external trigger signal in
complementary PWM mode and reset-synchronized PWM mode.
When an external trigger occurs, bits 5 to 0 in TOER are cleared to 0, disabling
ITU output.
1
External triggering is disabled
(Initial value)
Bits 3 and 2—Reserved: Read-only bits, always read as 1.
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Section 10 16-Bit Integrated Timer Unit (ITU)
Bit 1—Output Level Select 4 (OLS4): Selects output levels in complementary PWM mode and
reset-synchronized PWM mode.
Bit 1: OLS4
Description
0
TIOCA3, TIOCA4, and TIOCB4 outputs are inverted
1
TIOCA3, TIOCA4, and TIOCB4 outputs are not inverted
(Initial value)
Bit 0—Output Level Select 3 (OLS3): Selects output levels in complementary PWM mode and
reset-synchronized PWM mode.
Bit 0: OLS3
Description
0
TIOCB3, TOCXA4, and TOCXB4 outputs are inverted
1
TIOCB3, TOCXA4, and TOCXB4 outputs are not inverted
10.2.7
(Initial value)
Timer Counters (TCNT)
TCNT is a 16-bit counter. The ITU has five TCNTs, one for each channel.
Channel
Abbreviation
Function
0
TCNT0
Up-counter
1
TCNT1
2
TCNT2
Phase counting mode: up/down-counter
Other modes: up-counter
3
TCNT3
Complementary PWM mode: up/down-counter
4
TCNT4
Other modes: up-counter
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Each TCNT is a 16-bit readable/writable register that counts pulse inputs from a clock source. The
clock source is selected by bits TPSC2 to TPSC0 in TCR.
TCNT0 and TCNT1 are up-counters. TCNT2 is an up/down-counter in phase counting mode and
an up-counter in other modes. TCNT3 and TCNT4 are up/down-counters in complementary PWM
mode and up-counters in other modes.
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Section 10 16-Bit Integrated Timer Unit (ITU)
TCNT can be cleared to H'0000 by compare match with GRA or GRB or by input capture to GRA
or GRB (counter clearing function) in the same channel.
When TCNT overflows (changes from H'FFFF to H'0000), the OVF flag is set to 1 in TSR of the
corresponding channel.
When TCNT underflows (changes from H'0000 to H'FFFF), the OVF flag is set to 1 in TSR of the
corresponding channel.
The TCNTs are linked to the CPU by an internal 16-bit bus and can be written or read by either
word access or byte access.
Each TCNT is initialized to H'0000 by a reset and in standby mode.
10.2.8
General Registers (GRA, GRB)
The general registers are 16-bit registers. The ITU has 10 general registers, two in each channel.
Channel
Abbreviation
Function
0
GRA0, GRB0
Output compare/input capture register
1
GRA1, GRB1
2
GRA2, GRB2
3
GRA3, GRB3
4
GRA4, GRB4
Bit
Initial value
Read/Write
Output compare/input capture register; can be buffered by
buffer registers BRA and BRB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
A general register is a 16-bit readable/writable register that can function as either an output
compare register or an input capture register. The function is selected by settings in TIOR.
When a general register is used as an output compare register, its value is constantly compared
with the TCNT value. When the two values match (compare match), the IMFA or IMFB flag is set
to 1 in TSR. Compare match output can be selected in TIOR.
When a general register is used as an input capture register, rising edges, falling edges, or both
edges of an external input capture signal are detected and the current TCNT value is stored in the
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Section 10 16-Bit Integrated Timer Unit (ITU)
general register. The corresponding IMFA or IMFB flag in TSR is set to 1 at the same time. The
valid edge or edges of the input capture signal are selected in TIOR.
TIOR settings are ignored in PWM mode, complementary PWM mode, and reset-synchronized
PWM mode.
General registers are linked to the CPU by an internal 16-bit bus and can be written or read by
either word access or byte access.
General registers are initialized to the output compare function (with no output signal) by a reset
and in standby mode. The initial value is H'FFFF.
10.2.9
Buffer Registers (BRA, BRB)
The buffer registers are 16-bit registers. The ITU has four buffer registers, two each in channels 3
and 4.
Channel
Abbreviation
Function
3
BRA3, BRB3
Used for buffering
4
BRA4, BRB4
•
When the corresponding GRA or GRB functions as an
output compare register, BRA or BRB can function as an
output compare buffer register: the BRA or BRB value is
automatically transferred to GRA or GRB at compare match
•
When the corresponding GRA or GRB functions as an input
capture register, BRA or BRB can function as an input
capture buffer register: the GRA or GRB value is
automatically transferred to BRA or BRB at input capture
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
A buffer register is a 16-bit readable/writable register that is used when buffering is selected.
Buffering can be selected independently by bits BFB4, BFA4, BFB3, and BFA3 in TFCR.
The buffer register and general register operate as a pair. When the general register functions as an
output compare register, the buffer register functions as an output compare buffer register. When
the general register functions as an input capture register, the buffer register functions as an input
capture buffer register.
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Section 10 16-Bit Integrated Timer Unit (ITU)
The buffer registers are linked to the CPU by an internal 16-bit bus and can be written or read by
either word or byte access.
Buffer registers are initialized to H'FFFF by a reset and in standby mode.
10.2.10 Timer Control Registers (TCR)
TCR is an 8-bit register. The ITU has five TCRs, one in each channel.
Channel
Abbreviation
Function
0
TCR0
1
TCR1
2
TCR2
TCR controls the timer counter. The TCRs in all channels are
functionally identical. When phase counting mode is selected in
channel 2, the settings of bits CKEG1 and CKEG0 and TPSC2
to TPSC0 in TCR2 are ignored.
3
TCR3
4
TCR4
Bit
7
6
5
—
CCLR1
CCLR0
4
3
CKEG1 CKEG0
2
1
0
TPSC2
TPSC1
TPSC0
Initial value
1
0
0
0
0
0
0
0
Read/Write
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Timer prescaler 2 to 0
These bits select the
counter clock
Clock edge 1/0
These bits select external clock edges
Counter clear 1/0
These bits select the counter clear source
Reserved bit
Each TCR is an 8-bit readable/writable register that selects the timer counter clock source, selects
the edge or edges of external clock sources, and selects how the counter is cleared.
TCR is initialized to H'80 by a reset and in standby mode.
Bit 7—Reserved: Read-only bit, always read as 1.
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Section 10 16-Bit Integrated Timer Unit (ITU)
Bits 6 and 5—Counter Clear 1/0 (CCLR1, CCLR0): These bits select how TCNT is cleared.
Bit 6: CCLR1
Bit 5: CCLR0
Description
0
0
TCNT is not cleared
1
TCNT is cleared by GRA compare match or input
1
capture*
0
TCNT is cleared by GRB compare match or input
1
capture*
1
Synchronous clear: TCNT is cleared in synchronization
2
with other synchronized timers*
1
(Initial value)
Notes: 1. TCNT is cleared by compare match when the general register functions as an output
compare register, and by input capture when the general register functions as an input
capture register.
2. Selected in TSNC.
Bits 4 and 3—Clock Edge 1/0 (CKEG1, CKEG0): These bits select external clock input edges
when an external clock source is used.
Bit 4: CKEG1
Bit 3: CKEG0
Description
0
0
Count rising edges
1
Count falling edges
—
Count both edges
1
(Initial value)
When channel 2 is set to phase counting mode, bits CKEG1 and CKEG0 in TCR2 are ignored.
Phase counting takes precedence.
Bits 2 to 0—Timer Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the counter clock
source.
Bit 2: TPSC2
Bit 1: TPSC1
Bit 0: TPSC0
Description
0
0
0
Internal clock: φ
1
Internal clock: φ/2
0
Internal clock: φ/4
1
Internal clock: φ/8
0
External clock A: TCLKA input
1
External clock B: TCLKB input
0
External clock C: TCLKC input
1
External clock D: TCLKD input
1
1
0
1
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(Initial value)
Section 10 16-Bit Integrated Timer Unit (ITU)
When bit TPSC2 is cleared to 0 an internal clock source is selected, and the timer counts only
falling edges. When bit TPSC2 is set to 1 an external clock source is selected, and the timer counts
the edge or edges selected by bits CKEG1 and CKEG0.
When channel 2 is set to phase counting mode (MDF = 1 in TMDR), the settings of bits TPSC2 to
TPSC0 in TCR2 are ignored. Phase counting takes precedence.
10.2.11 Timer I/O Control Register (TIOR)
TIOR is an 8-bit register. The ITU has five TIORs, one in each channel.
Channel
Abbreviation
Function
0
TIOR0
1
TIOR1
2
TIOR2
TIOR controls the general registers. Some functions differ in
PWM mode. TIOR3 and TIOR4 settings are ignored when
complementary PWM mode or reset-synchronized PWM mode
is selected in channels 3 and 4.
3
TIOR3
4
TIOR4
Bit
7
6
5
4
3
2
1
0
—
IOB2
IOB1
IOB0
—
IOA2
IOA1
IOA0
Initial value
1
0
0
0
1
0
0
0
Read/Write
—
R/W
R/W
R/W
—
R/W
R/W
R/W
I/O control A2 to A0
These bits select GRA
functions
Reserved bit
I/O control B2 to B0
These bits select GRB functions
Reserved bit
Each TIOR is an 8-bit readable/writable register that selects the output compare or input capture
function for GRA and GRB, and specifies the functions of the TIOCA and TIOCB pins. If the
output compare function is selected, TIOR also selects the type of output. If input capture is
selected, TIOR also selects the edge or edges of the input capture signal.
TIOR is initialized to H'88 by a reset and in standby mode.
Bit 7—Reserved: Read-only bit, always read as 1.
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Section 10 16-Bit Integrated Timer Unit (ITU)
Bits 6 to 4—I/O Control B2 to B0 (IOB2 to IOB0): These bits select the GRB function.
Bit 6:
IOB2
Bit 5:
IOB1
Bit 4:
IOB0
0
0
0
1
1
1
0
No output at compare match (Initial value)
1
0 output at GRB compare match*
1
0
1 output at GRB compare match*
1
Output toggles at GRB compare match
1 2
(1 output in channel 2)* *
0
1
1
Description
GRB is an output
compare register
GRB is an input
capture register
0
GRB captures rising edge of input
GRB captures falling edge of input
GRB captures both edges of input
1
Notes: 1. After a reset, the output is 0 until the first compare match.
2. Channel 2 output cannot be toggled by compare match. This setting selects 1 output
instead.
Bit 3—Reserved: Read-only bit, always read as 1.
Bits 2 to 0—I/O Control A2 to A0 (IOA2 to IOA0): These bits select the GRA function.
Bit 2:
IOA2
Bit 1:
IOA1
Bit 0:
IOA0
0
0
0
1
1
1
0
GRA is an output
compare register
No output at compare match (Initial value)
1
0 output at GRA compare match*
1
0
1 output at GRA compare match*
1
Output toggles at GRA compare match
1 2
(1 output in channel 2)* *
0
1
1
Description
GRA is an input
capture register
0
GRA captures rising edge of input
GRA captures falling edge of input
GRA captures both edges of input
1
Notes: 1. After a reset, the output is 0 until the first compare match.
2. Channel 2 output cannot be toggled by compare match. This setting selects 1 output
instead.
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Section 10 16-Bit Integrated Timer Unit (ITU)
10.2.12 Timer Status Register (TSR)
TSR is an 8-bit register. The ITU has five TSRs, one in each channel.
Channel
Abbreviation
Function
0
TSR0
Indicates input capture, compare match, and overflow status
1
TSR1
2
TSR2
3
TSR3
4
TSR4
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
OVF
IMFB
IMFA
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
R/(W)*
R/(W)*
R/(W)*
Reserved bits
Overflow flag
Status flag indicating
overflow or underflow
Input capture/compare match flag B
Status flag indicating GRB compare
match or input capture
Input capture/compare match flag A
Status flag indicating GRA compare
match or input capture
Note: * Only 0 can be written, to clear the flag.
Each TSR is an 8-bit readable/writable register containing flags that indicate TCNT overflow or
underflow and GRA or GRB compare match or input capture. These flags are interrupt sources
and generate CPU interrupts if enabled by corresponding bits in TIER.
TSR is initialized to H'F8 by a reset and in standby mode.
Bits 7 to 3—Reserved: Read-only bits, always read as 1.
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Section 10 16-Bit Integrated Timer Unit (ITU)
Bit 2—Overflow Flag (OVF): This status flag indicates TCNT overflow or underflow.
Bit 2: OVF
Description
0
[Clearing condition]
(Initial value)
Read OVF when OVF = 1, then write 0 in OVF
1
[Setting condition]
TCNT overflowed from H'FFFF to H'0000, or underflowed from H'0000 to
H'FFFF*
Notes: 1. Channel 2 operates in phase counting mode (MDF = 1 in TMDR)
2. Channel 3 and 4 operate in complementary PWM mode (CMD1 = 1 and CMD0 = 0 in
TFCR)
* TCNT underflow occurs when TCNT operates as an up/down-counter. Underflow
occurs only under the following conditions:
Bit 1—Input Capture/Compare Match Flag B (IMFB): This status flag indicates GRB
compare match or input capture events.
Bit 1: IMFB
Description
0
[Clearing condition]
(Initial value)
Read IMFB when IMFB = 1, then write 0 in IMFB
1
[Setting conditions]
TCNT = GRB when GRB functions as an output compare register.
TCNT value is transferred to GRB by an input capture signal, when GRB
functions as an input capture register.
Bit 0—Input Capture/Compare Match Flag A (IMFA): This status flag indicates GRA
compare match or input capture events.
Bit 0: IMFA
Description
0
[Clearing condition]
(Initial value)
Read IMFA when IMFA = 1, then write 0 in IMFA.
DMAC activated by IMIA interrupt (channels 0 to 3 only).
1
[Setting conditions]
TCNT = GRA when GRA functions as an output compare register.
TCNT value is transferred to GRA by an input capture signal, when GRA
functions as an input capture register.
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Section 10 16-Bit Integrated Timer Unit (ITU)
10.2.13 Timer Interrupt Enable Register (TIER)
TIER is an 8-bit register. The ITU has five TIERs, one in each channel.
Channel
Abbreviation
Function
0
TIER0
Enables or disables interrupt requests.
1
TIER1
2
TIER2
3
TIER3
4
TIER4
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
OVIE
IMIEB
IMIEA
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
R/W
R/W
R/W
Reserved bits
Overflow interrupt enable
Enables or disables OVF
interrupts
Input capture/compare match
interrupt enable B
Enables or disables IMFB interrupts
Input capture/compare match
interrupt enable A
Enables or disables IMFA
interrupts
Each TIER is an 8-bit readable/writable register that enables and disables overflow interrupt
requests and general register compare match and input capture interrupt requests.
TIER is initialized to H'F8 by a reset and in standby mode.
Bits 7 to 3—Reserved: Read-only bits, always read as 1.
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Section 10 16-Bit Integrated Timer Unit (ITU)
Bit 2—Overflow Interrupt Enable (OVIE): Enables or disables the interrupt requested by the
OVF flag in TSR when OVF is set to 1.
Bit 2: OVIE
Description
0
OVI interrupt requested by OVF is disabled
1
OVI interrupt requested by OVF is enabled
(Initial value)
Bit 1—Input Capture/Compare Match Interrupt Enable B (IMIEB): Enables or disables the
interrupt requested by the IMFB flag in TSR when IMFB is set to 1.
Bit 1: IMIEB
Description
0
IMIB interrupt requested by IMFB is disabled
1
IMIB interrupt requested by IMFB is enabled
(Initial value)
Bit 0—Input Capture/Compare Match Interrupt Enable A (IMIEA): Enables or disables the
interrupt requested by the IMFA flag in TSR when IMFA is set to 1.
Bit 0: IMIEA
Description
0
IMIA interrupt requested by IMFA is disabled
1
IMIA interrupt requested by IMFA is enabled
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(Initial value)
Section 10 16-Bit Integrated Timer Unit (ITU)
10.3
CPU Interface
10.3.1
16-Bit Accessible Registers
The timer counters (TCNTs), general registers A and B (GRAs and GRBs), and buffer registers A
and B (BRAs and BRBs) are 16-bit registers, and are linked to the CPU by an internal 16-bit data
bus. These registers can be written or read a word at a time, or a byte at a time.
Figures 10.6 and 10.7 show examples of word access to a timer counter (TCNT). Figures 10.8 to
10.11 show examples of byte access to TCNTH and TCNTL.
On-chip data bus
H
CPU
H
L
Bus interface
L
TCNTH
Module
data bus
TCNTL
Figure 10.6 Access to Timer Counter (CPU Writes to TCNT, Word)
On-chip data bus
H
CPU
L
H
Bus interface
L
TCNTH
Module
data bus
TCNTL
Figure 10.7 Access to Timer Counter (CPU Reads TCNT, Word)
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Section 10 16-Bit Integrated Timer Unit (ITU)
On-chip data bus
H
CPU
L
H
Bus interface
L
TCNTH
Module
data bus
TCNTL
Figure 10.8 Access to Timer Counter (CPU Writes to TCNT, Upper Byte)
On-chip data bus
H
CPU
L
H
Bus interface
L
TCNTH
Module
data bus
TCNTL
Figure 10.9 Access to Timer Counter (CPU Writes to TCNT, Lower Byte)
On-chip data bus
H
CPU
L
H
Bus interface
L
TCNTH
Module
data bus
TCNTL
Figure 10.10 Access to Timer Counter (CPU Reads TCNT, Upper Byte)
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Section 10 16-Bit Integrated Timer Unit (ITU)
On-chip data bus
H
CPU
H
L
Bus interface
L
TCNTH
Module
data bus
TCNTL
Figure 10.11 Access to Timer Counter (CPU Reads TCNT, Lower Byte)
10.3.2
8-Bit Accessible Registers
The registers other than the timer counters, general registers, and buffer registers are 8-bit
registers. These registers are linked to the CPU by an internal 8-bit data bus.
Figures 10.12 and 10.13 show examples of byte read and write access to a TCR.
If a word-size data transfer instruction is executed, two byte transfers are performed.
On-chip data bus
H
CPU
L
H
Bus interface
L
Module
data bus
TCR
Figure 10.12 Access to Timer Counter (CPU Writes to TCR)
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Section 10 16-Bit Integrated Timer Unit (ITU)
On-chip data bus
H
CPU
H
L
Bus interface
L
Module
data bus
TCR
Figure 10.13 Access to Timer Counter (CPU Reads TCR)
10.4
Operation
10.4.1
Overview
A summary of operations in the various modes is given below.
Normal Operation: Each channel has a timer counter and general registers. The timer counter
counts up, and can operate as a free-running counter, periodic counter, or external event counter.
General registers A and B can be used for input capture or output compare.
Synchronous Operation: The timer counters in designated channels are preset synchronously.
Data written to the timer counter in any one of these channels is simultaneously written to the
timer counters in the other channels as well. The timer counters can also be cleared synchronously
if so designated by the CCLR1 and CCLR0 bits in the TCRs.
PWM Mode: A PWM waveform is output from the TIOCA pin. The output goes to 1 at compare
match A and to 0 at compare match B. The duty cycle can be varied from 0% to 100% depending
on the settings of GRA and GRB. When a channel is set to PWM mode, its GRA and GRB
automatically become output compare registers.
Reset-Synchronized PWM Mode: Channels 3 and 4 are paired for three-phase PWM output with
complementary waveforms. (The three phases are related by having a common transition point.)
When reset-synchronized PWM mode is selected GRA3, GRB3, GRA4, and GRB4 automatically
function as output compare registers, TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and
TOCXB4 function as PWM output pins, and TCNT3 operates as an up-counter. TCNT4 operates
independently, and is not compared with GRA4 or GRB4.
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Section 10 16-Bit Integrated Timer Unit (ITU)
Complementary PWM Mode: Channels 3 and 4 are paired for three-phase PWM output with
non-overlapping complementary waveforms. When complementary PWM mode is selected
GRA3, GRB3, GRA4, and GRB4 automatically function as output compare registers, and
TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and TOCXB4 function as PWM output pins.
TCNT3 and TCNT4 operate as up/down-counters.
Phase Counting Mode: The phase relationship between two clock signals input at TCLKA and
TCLKB is detected and TCNT2 counts up or down accordingly. When phase counting mode is
selected TCLKA and TCLKB become clock input pins and TCNT2 operates as an up/downcounter.
Buffering
• If the general register is an output compare register
When compare match occurs the buffer register value is transferred to the general register.
• If the general register is an input capture register
When input capture occurs the TCNT value is transferred to the general register, and the
previous general register value is transferred to the buffer register.
• Complementary PWM mode
The buffer register value is transferred to the general register when TCNT3 and TCNT4
change counting direction.
• Reset-synchronized PWM mode
The buffer register value is transferred to the general register at GRA3 compare match.
10.4.2
Basic Functions
Counter Operation: When one of bits STR0 to STR4 is set to 1 in the timer start register (TSTR),
the timer counter (TCNT) in the corresponding channel starts counting. The counting can be freerunning or periodic.
• Sample setup procedure for counter
Figure 10.14 shows a sample procedure for setting up a counter.
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Section 10 16-Bit Integrated Timer Unit (ITU)
Counter setup
Select counter clock
Type of counting?
1
No
Yes
Free-running counting
Periodic counting
Select counter clear source
2
Select output compare
register function
3
Set period
4
Start counter
5
Periodic counter
Start counter
5
Free-running counter
Figure 10.14 Counter Setup Procedure (Example)
1. Set bits TPSC2 to TPSC0 in TCR to select the counter clock source. If an external clock source
is selected, set bits CKEG1 and CKEG0 in TCR to select the desired edge(s) of the external
clock signal.
2. For periodic counting, set CCLR1 and CCLR0 in TCR to have TCNT cleared at GRA compare
match or GRB compare match.
3. Set TIOR to select the output compare function of GRA or GRB, whichever was selected in
step 2.
4. Write the count period in GRA or GRB, whichever was selected in step 2.
5. Set the STR bit to 1 in TSTR to start the timer counter.
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Section 10 16-Bit Integrated Timer Unit (ITU)
• Free-running and periodic counter operation
A reset leaves the counters (TCNTs) in ITU channels 0 to 4 all set as free-running counters. A
free-running counter starts counting up when the corresponding bit in TSTR is set to 1. When
the count overflows from H'FFFF to H'0000, the OVF flag is set to 1 in TSR. If the
corresponding OVIE bit is set to 1 in TIER, a CPU interrupt is requested. After the overflow,
the counter continues counting up from H'0000. Figure 10.15 illustrates free-running counting.
TCNT value
H'FFFF
H'0000
Time
STR0 to
STR4 bit
OVF
Figure 10.15 Free-Running Counter Operation
When a channel is set to have its counter cleared by compare match, in that channel TCNT
operates as a periodic counter. Select the output compare function of GRA or GRB, set bit
CCLR1 or CCLR0 in TCR to have the counter cleared by compare match, and set the count
period in GRA or GRB. After these settings, the counter starts counting up as a periodic
counter when the corresponding bit is set to 1 in TSTR. When the count matches GRA or
GRB, the IMFA or IMFB flag is set to 1 in TSR and the counter is cleared to H'0000. If the
corresponding IMIEA or IMIEB bit is set to 1 in TIER, a CPU interrupt is requested at this
time. After the compare match, TCNT continues counting up from H'0000. Figure 10.16
illustrates periodic counting.
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Section 10 16-Bit Integrated Timer Unit (ITU)
TCNT value
Counter cleared by general
register compare match
GR
H'0000
Time
STR bit
IMF
Figure 10.16 Periodic Counter Operation
• TCNT count timing
Internal clock source
Bits TPSC2 to TPSC0 in TCR select the system clock (φ) or one of three internal clock
sources obtained by prescaling the system clock (φ/2, φ/4, φ/8).
Figure 10.17 shows the timing.
φ
Internal
clock
TCNT input
TCNT
N–1
N
N+1
Figure 10.17 Count Timing for Internal Clock Sources
External clock source
Bits TPSC2 to TPSC0 in TCR select an external clock input pin (TCLKA to TCLKD), and
its valid edge or edges are selected by bits CKEG1 and CKEG0. The rising edge, falling
edge, or both edges can be selected.
The pulse width of the external clock signal must be at least 1.5 system clocks when a
single edge is selected, and at least 2.5 system clocks when both edges are selected. Shorter
pulses will not be counted correctly.
Figure 10.18 shows the timing when both edges are detected.
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Section 10 16-Bit Integrated Timer Unit (ITU)
φ
External
clock input
TCNT input
TCNT
N–1
N
N+1
Figure 10.18 Count Timing for External Clock Sources (when Both Edges are Detected)
Waveform Output by Compare Match: In ITU channels 0, 1, 3, and 4, compare match A or B
can cause the output at the TIOCA or TIOCB pin to go to 0, go to 1, or toggle. In channel 2 the
output can only go to 0 or go to 1.
• Sample setup procedure for waveform output by compare match
Figure 10.19 shows a sample procedure for setting up waveform output by compare match.
Output setup
1. Select the compare match output mode (0, 1, or
toggle) in TIOR. When a waveform output mode
is selected, the pin switches from its generic input/
output function to the output compare function
(TIOCA or TIOCB). An output compare pin outputs
0 until the first compare match occurs.
Select waveform
output mode
1
Set output timing
2
2. Set a value in GRA or GRB to designate the
compare match timing.
Start counter
3
3. Set the STR bit to 1 in TSTR to start the timer
counter.
Waveform output
Figure 10.19 Setup Procedure for Waveform Output by Compare Match (Example)
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Section 10 16-Bit Integrated Timer Unit (ITU)
• Examples of waveform output
Figure 10.20 shows examples of 0 and 1 output. TCNT operates as a free-running counter, 0
output is selected for compare match A, and 1 output is selected for compare match B. When
the pin is already at the selected output level, the pin level does not change.
TCNT value
H'FFFF
GRB
GRA
H'0000
Time
TIOCB
No change
No change
TIOCA
No change
No change
1 output
0 output
Figure 10.20 0 and 1 Output (Examples)
Figure 10.21 shows examples of toggle output. TCNT operates as a periodic counter, cleared
by compare match B. Toggle output is selected for both compare match A and B.
TCNT value
Counter cleared by compare match with GRB
GRB
GRA
H'0000
Time
TIOCB
Toggle
output
TIOCA
Toggle
output
Figure 10.21 Toggle Output (Example)
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Section 10 16-Bit Integrated Timer Unit (ITU)
• Output compare timing
The compare match signal is generated in the last state in which TCNT and the general register
match (when TCNT changes from the matching value to the next value). When the compare
match signal is generated, the output value selected in TIOR is output at the output compare
pin (TIOCA or TIOCB). When TCNT matches a general register, the compare match signal is
not generated until the next counter clock pulse.
Figure 10.22 shows the output compare timing.
φ
TCNT input
clock
TCNT
N
GR
N
N+1
Compare
match signal
TIOCA,
TIOCB
Figure 10.22 Output Compare Timing
Input Capture Function: The TCNT value can be captured into a general register when a
transition occurs at an input capture/output compare pin (TIOCA or TIOCB). Capture can take
place on the rising edge, falling edge, or both edges. The input capture function can be used to
measure pulse width or period.
• Sample setup procedure for input capture
Figure 10.23 shows a sample procedure for setting up input capture.
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Section 10 16-Bit Integrated Timer Unit (ITU)
Input selection
Select input-capture input
1
Start counter
2
1. Set TIOR to select the input capture function of a
general register and the rising edge, falling edge,
or both edges of the input capture signal. Clear the
port data direction bit to 0 before making these
TIOR settings.
2. Set the STR bit to 1 in TSTR to start the timer
counter.
Input capture
Figure 10.23 Setup Procedure for Input Capture (Example)
• Examples of input capture
Figure 10.24 illustrates input capture when the falling edge of TIOCB and both edges of
TIOCA are selected as capture edges. TCNT is cleared by input capture into GRB.
TCNT value
Counter cleared by TIOCB
input (falling edge)
H'0180
H'0160
H'0005
H'0000
Time
TIOCB
TIOCA
GRA
H'0005
GRB
H'0160
H'0180
Figure 10.24 Input Capture (Example)
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Section 10 16-Bit Integrated Timer Unit (ITU)
• Input capture signal timing
Input capture on the rising edge, falling edge, or both edges can be selected by settings in
TIOR. Figure 10.25 shows the timing when the rising edge is selected. The pulse width of the
input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system
clocks for capture of both edges.
φ
Input-capture input
Internal input
capture signal
TCNT
N
N
GRA, GRB
Figure 10.25 Input Capture Signal Timing
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Section 10 16-Bit Integrated Timer Unit (ITU)
10.4.3
Synchronization
The synchronization function enables two or more timer counters to be synchronized by writing
the same data to them simultaneously (synchronous preset). With appropriate TCR settings, two or
more timer counters can also be cleared simultaneously (synchronous clear). Synchronization
enables additional general registers to be associated with a single time base. Synchronization can
be selected for all channels (0 to 4).
Sample Setup Procedure for Synchronization: Figure 10.26 shows a sample procedure for
setting up synchronization.
Setup for synchronization
Select synchronization
1
Synchronous preset
Write to TCNT
Synchronous clear
2
Clearing
synchronized to this
channel?
No
Yes
Select counter clear source
3
Select counter clear source
4
Start counter
5
Start counter
5
Synchronous preset
Counter clear
Synchronous clear
1. Set the SYNC bits to 1 in TSNC for the channels to be synchronized.
2. When a value is written in TCNT in one of the synchronized channels, the same value is
simultaneously written in TCNT in the other channels (synchronized preset).
3. Set the CCLR1 or CCLR0 bit in TCR to have the counter cleared by compare match or input capture.
4. Set the CCLR1 and CCLR0 bits in TCR to have the counter cleared synchronously.
5. Set the STR bits in TSTR to 1 to start the synchronized counters.
Figure 10.26 Setup Procedure for Synchronization (Example)
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Section 10 16-Bit Integrated Timer Unit (ITU)
Example of Synchronization: Figure 10.27 shows an example of synchronization. Channels 0, 1,
and 2 are synchronized, and are set to operate in PWM mode. Channel 0 is set for counter clearing
by compare match with GRB0. Channels 1 and 2 are set for synchronous counter clearing. The
timer counters in channels 0, 1, and 2 are synchronously preset, and are synchronously cleared by
compare match with GRB0. A three-phase PWM waveform is output from pins TIOCA0, TIOCA1,
and TIOCA2. For further information on PWM mode, see section 10.4.4, PWM Mode.
Value of TCNT0 to TCNT2
Cleared by compare match with GRB0
GRB0
GRB1
GRA0
GRB2
GRA1
GRA2
Time
H'0000
TIOCA0
TIOCA1
TIOCA2
Figure 10.27 Synchronization (Example)
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Section 10 16-Bit Integrated Timer Unit (ITU)
10.4.4
PWM Mode
In PWM mode GRA and GRB are paired and a PWM waveform is output from the TIOCA pin.
GRA specifies the time at which the PWM output changes to 1. GRB specifies the time at which
the PWM output changes to 0. If either GRA or GRB is selected as the counter clear source, a
PWM waveform with a duty cycle from 0% to 100% is output at the TIOCA pin. PWM mode can
be selected in all channels (0 to 4).
Table 10.4 summarizes the PWM output pins and corresponding registers. If the same value is set
in GRA and GRB, the output does not change when compare match occurs.
Table 10.4 PWM Output Pins and Registers
Channel
Output Pin
1 Output
0 Output
0
TIOCA0
GRA0
GRB0
1
TIOCA1
GRA1
GRB1
2
TIOCA2
GRA2
GRB2
3
TIOCA3
GRA3
GRB3
4
TIOCA4
GRA4
GRB4
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Section 10 16-Bit Integrated Timer Unit (ITU)
Sample Setup Procedure for PWM Mode: Figure 10.28 shows a sample procedure for setting
up PWM mode.
PWM mode
Select counter clock
1
Select counter clear source
2
Set GRA
3
Set GRB
4
Select PWM mode
5
Start counter
6
PWM mode
1. Set bits TPSC2 to TPSC0 in TCR to
select the counter clock source. If an
external clock source is selected, set
bits CKEG1 and CKEG0 in TCR to
select the desired edge(s) of the
external clock signal.
2. Set bits CCLR1 and CCLR0 in TCR
to select the counter clear source.
3. Set the time at which the PWM
waveform should go to 1 in GRA.
4. Set the time at which the PWM
waveform should go to 0 in GRB.
5. Set the PWM bit in TMDR to select
PWM mode. When PWM mode is
selected, regardless of the TIOR
contents, GRA and GRB become
output compare registers specifying
the times at which the PWM output
goes to 1 and 0. The TIOCA pin
automatically becomes the PWM
output pin. The TIOCB pin conforms
to the settings of bits IOB1 and IOB0
in TIOR. If TIOCB output is not
desired, clear both IOB1 and IOB0 to 0.
6. Set the STR bit to 1 in TSTR to start
the timer counter.
Figure 10.28 Setup Procedure for PWM Mode (Example)
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Section 10 16-Bit Integrated Timer Unit (ITU)
Examples of PWM Mode: Figure 10.29 shows examples of operation in PWM mode. In PWM
mode TIOCA becomes an output pin. The output goes to 1 at compare match with GRA, and to 0
at compare match with GRB.
In the examples shown, TCNT is cleared by compare match with GRA or GRB. Synchronized
operation and free-running counting are also possible.
TCNT value
Counter cleared by compare match with GRA
GRA
GRB
Time
H'0000
TIOCA
a. Counter cleared by GRA
TCNT value
Counter cleared by compare match with GRB
GRB
GRA
Time
H'0000
TIOCA
b. Counter cleared by GRB
Figure 10.29 PWM Mode (Example 1)
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Section 10 16-Bit Integrated Timer Unit (ITU)
Figure 10.30 shows examples of the output of PWM waveforms with duty cycles of 0% and
100%. If the counter is cleared by compare match with GRB, and GRA is set to a higher value
than GRB, the duty cycle is 0%. If the counter is cleared by compare match with GRA, and GRB
is set to a higher value than GRA, the duty cycle is 100%.
TCNT value
Counter cleared by compare match with GRB
GRB
GRA
H'0000
Time
TIOCA
Write to GRA
Write to GRA
a. 0% duty cycle
TCNT value
Counter cleared by compare match with GRA
GRA
GRB
H'0000
Time
TIOCA
Write to GRB
Write to GRB
b. 100% duty cycle
Figure 10.30 PWM Mode (Example 2)
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Section 10 16-Bit Integrated Timer Unit (ITU)
10.4.5
Reset-Synchronized PWM Mode
In reset-synchronized PWM mode channels 3 and 4 are combined to produce three pairs of
complementary PWM waveforms, all having one waveform transition point in common.
When reset-synchronized PWM mode is selected TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4,
and TOCXB4 automatically become PWM output pins, and TCNT3 functions as an up-counter.
Table 10.5 lists the PWM output pins. Table 10.6 summarizes the register settings.
Table 10.5
Output Pins in Reset-Synchronized PWM Mode
Channel
Output Pin
Description
3
TIOCA3
PWM output 1
TIOCB3
PWM output 1´ (complementary waveform to PWM output 1)
4
TIOCA4
PWM output 2
TOCXA4
PWM output 2´ (complementary waveform to PWM output 2)
TIOCB4
PWM output 3
TOCXB4
PWM output 3´ (complementary waveform to PWM output 3)
Table 10.6
Register Settings in Reset-Synchronized PWM Mode
Register
Setting
TCNT3
Initially set to H'0000
TCNT4
Not used (operates independently)
GRA3
Specifies the count period of TCNT3
GRB3
Specifies a transition point of PWM waveforms output from TIOCA3 and TIOCB3
GRA4
Specifies a transition point of PWM waveforms output from TIOCA4 and TOCXA4
GRB4
Specifies a transition point of PWM waveforms output from TIOCB4 and TOCXB4
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Section 10 16-Bit Integrated Timer Unit (ITU)
Sample Setup Procedure for Reset-Synchronized PWM Mode: Figure 10.31 shows a sample
procedure for setting up reset-synchronized PWM mode.
Reset-synchronized PWM mode
Stop counter
1
Select counter clock
2
Select counter clear source
3
Select reset-synchronized
PWM mode
4
Set TCNT
5
Set general registers
6
Start counter
7
Reset-synchronized PWM mode
1. Clear the STR3 bit in TSTR to 0 to
halt TCNT3. Reset-synchronized
PWM mode must be set up while
TCNT3 is halted.
2. Set bits TPSC2 to TPSC0 in TCR to
select the counter clock source for
channel 3. If an external clock source
is selected, select the external clock
edge(s) with bits CKEG1 and CKEG0
in TCR.
3. Set bits CCLR1 and CCLR0 in TCR3
to select GRA3 compare match as
the counter clear source.
4. Set bits CMD1 and CMD0 in TFCR to
select reset-synchronized PWM mode.
TIOCA3, TIOCB3, TIOCA4, TIOCB4,
TOCXA4, and TOCXB4 automatically
become PWM output pins.
5. Preset TCNT3 to H'0000. TCNT4
need not be preset.
6. GRA3 is the waveform period register.
Set the waveform period value in
GRA3. Set transition times of the
PWM output waveforms in GRB3,
GRA4, and GRB4. Set times within
the compare match range of TCNT3.
X ≤ GRA3 (X: setting value)
7. Set the STR3 bit in TSTR to 1 to start
TCNT3.
Figure 10.31 Setup Procedure for Reset-Synchronized PWM Mode (Example)
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Section 10 16-Bit Integrated Timer Unit (ITU)
Example of Reset-Synchronized PWM Mode: Figure 10.32 shows an example of operation in
reset-synchronized PWM mode. TCNT3 operates as an up-counter in this mode. TCNT4 operates
independently, detached from GRA4 and GRB4. When TCNT3 matches GRA3, TCNT3 is cleared
and resumes counting from H'0000. The PWM outputs toggle at compare match of TCNT3 with
GRB3, GRA4, and GRB4 respectively, and all toggle when the counter is cleared.
TCNT3 value
Counter cleared at compare match with GRA3
GRA3
GRB3
GRA4
GRB4
H'0000
Time
TIOCA3
TIOCB3
TIOCA4
TOCXA4
TIOCB4
TOCXB4
Figure 10.32 Operation in Reset-Synchronized PWM Mode (Example)
(when OLS3 = OLS4 = 1)
For the settings and operation when reset-synchronized PWM mode and buffer mode are both
selected, see section 10.4.8, Buffering.
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Section 10 16-Bit Integrated Timer Unit (ITU)
10.4.6
Complementary PWM Mode
In complementary PWM mode channels 3 and 4 are combined to output three pairs of
complementary, non-overlapping PWM waveforms.
When complementary PWM mode is selected TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4,
and TOCXB4 automatically become PWM output pins, and TCNT3 and TCNT4 function as
up/down-counters.
Table 10.7 lists the PWM output pins. Table 10.8 summarizes the register settings.
Table 10.7 Output Pins in Complementary PWM Mode
Channel
Output Pin
Description
3
TIOCA3
PWM output 1
TIOCB3
PWM output 1´ (non-overlapping complementary waveform
to PWM output 1)
TIOCA4
PWM output 2
TOCXA4
PWM output 2´ (non-overlapping complementary waveform
to PWM output 2)
TIOCB4
PWM output 3
TOCXB4
PWM output 3´ (non-overlapping complementary waveform
to PWM output 3)
4
Table 10.8 Register Settings in Complementary PWM Mode
Register
Setting
TCNT3
Initially specifies the non-overlap margin (difference to TCNT4)
TCNT4
Initially set to H'0000
GRA3
Specifies the upper limit value of TCNT3 minus 1
GRB3
Specifies a transition point of PWM waveforms output from TIOCA3 and TIOCB3
GRA4
Specifies a transition point of PWM waveforms output from TIOCA4 and TOCXA4
GRB4
Specifies a transition point of PWM waveforms output from TIOCB4 and TOCXB4
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Section 10 16-Bit Integrated Timer Unit (ITU)
Setup Procedure for Complementary PWM Mode: Figure 10.33 shows a sample procedure for
setting up complementary PWM mode.
Complementary PWM mode
Stop counting
1
Select counter clock
2
Select complementary
PWM mode
3
Set TCNTs
4
Set general registers
5
Start counters
6
Complementary PWM mode
1. Clear bits STR3 and STR4 to 0 in
TSTR to halt the timer counters.
Complementary PWM mode must be
set up while TCNT3 and TCNT4 are
halted.
2. Set bits TPSC2 to TPSC0 in TCR to
select the same counter clock source
for channels 3 and 4. If an external
clock source is selected, select the
external clock edge(s) with bits
CKEG1 and CKEG0 in TCR. Do not
select any counter clear source
with bits CCLR1 and CCLR0 in TCR.
3. Set bits CMD1 and CMD0 in TFCR
to select complementary PWM mode.
TIOCA3, TIOCB3, TIOCA4, TIOCB4,
TOCXA4, and TOCXB4 automatically
become PWM output pins.
4. Clear TCNT4 to H'0000. Set the
non-overlap margin in TCNT3. Do not
set TCNT3 and TCNT4 to the same
value.
5. GRA3 is the waveform period
register. Set the upper limit value of
TCNT3 minus 1 in GRA3. Set
transition times of the PWM output
waveforms in GRB3, GRA4, and
GRB4. Set times within the compare
match range of TCNT3 and TCNT4.
T ≤ X (X: initial setting of GRB3,
GRA4, or GRB4. T: initial setting of
TCNT3)
6. Set bits STR3 and STR4 in TSTR to
1 to start TCNT3 and TCNT4.
Note: After exiting complementary PWM mode, to resume operating in complementary
PWM mode, follow the entire setup procedure from step 1 again.
Figure 10.33 Setup Procedure for Complementary PWM Mode (Example)
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Section 10 16-Bit Integrated Timer Unit (ITU)
Clearing Procedure for Complementary PWM Mode: Figure 10.34 shows the steps to clear
complementary PWM mode.
Complementary PWM mode
1. Clear the CMD1 bit of TFCR to 0 to
set channels 3 and 4 to normal
operating mode.
Clear complementary PWM mode
1
Stop counter operation
2
2. After setting channels 3 and 4 to
normal operating mode, wait at least
one counter clock period, then clear
bits STR3 and STR4 of TSTR to 0 to
stop counter operation of TCNT3 and
TCNT4.
Normal operating mode
Figure 10.34 Clearing Procedure for Complementary PWM Mode
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Section 10 16-Bit Integrated Timer Unit (ITU)
Examples of Complementary PWM Mode: Figure 10.35 shows an example of operation in
complementary PWM mode. TCNT3 and TCNT4 operate as up/down-counters, counting down
from compare match between TCNT3 and GRA3 and counting up from the point at which TCNT4
underflows. During each up-and-down counting cycle, PWM waveforms are generated by
compare match with general registers GRB3, GRA4, and GRB4. Since TCNT3 is initially set to a
higher value than TCNT4, compare match events occur in the sequence TCNT3, TCNT4, TCNT4,
TCNT3.
TCNT3 and
TCNT4 values
Down-counting starts at compare
match between TCNT3 and GRA3
GRA3
TCNT3
GRB3
GRA4
GRB4
TCNT4
Time
H'0000
TIOCA3
Up-counting starts when
TCNT4 underflows
TIOCB3
TIOCA4
TOCXA4
TIOCB4
TOCXB4
Figure 10.35 Operation in Complementary PWM Mode (Example 1, OLS3 = OLS4 = 1)
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Section 10 16-Bit Integrated Timer Unit (ITU)
Figure 10.36 shows examples of waveforms with 0% and 100% duty cycles (in one phase) in
complementary PWM mode. In this example the outputs change at compare match with GRB3, so
waveforms with duty cycles of 0% or 100% can be output by setting GRB3 to a value larger than
GRA3. The duty cycle can be changed easily during operation by use of the buffer registers. For
further information see section 10.4.8, Buffering.
TCNT3 and
TCNT4 values
GRA3
GRB3
H'0000
Time
TIOCA3
TIOCB3
0% duty cycle
a. 0% duty cycle
TCNT3 and
TCNT4 values
GRA3
GRB3
Time
H'0000
TIOCA3
TIOCB3
100% duty cycle
b. 100% duty cycle
Figure 10.36 Operation in Complementary PWM Mode (Example 2, OLS3 = OLS4 = 1)
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Section 10 16-Bit Integrated Timer Unit (ITU)
In complementary PWM mode, TCNT3 and TCNT4 overshoot and undershoot at the transitions
between up-counting and down-counting. The setting conditions for the IMFA bit in channel 3 and
the OVF bit in channel 4 differ from the usual conditions. In buffered operation the buffer transfer
conditions also differ. Timing diagrams are shown in figures 10.37 and 10.38.
TCNT3
N–1
GRA3
N
N+1
N
N–1
N
Flag not set
IMFA
Set to 1
Buffer transfer
signal (BR to GR)
GR
Buffer transfer
No buffer transfer
Figure 10.37 Overshoot Timing
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Section 10 16-Bit Integrated Timer Unit (ITU)
Underflow
TCNT4
H'0001
H'0000
Overflow
H'FFFF
H'0000
Flag not set
OVF
Set to 1
Buffer transfer
signal (BR to GR)
GR
Buffer transfer
No buffer transfer
Figure 10.38 Undershoot Timing
In channel 3, IMFA is set to 1 only during up-counting. In channel 4, OVF is set to 1 only when
an underflow occurs. When buffering is selected, buffer register contents are transferred to the
general register at compare match A3 during up-counting, and when TCNT4 underflows.
General Register Settings in Complementary PWM Mode: When setting up general registers
for complementary PWM mode or changing their settings during operation, note the following
points.
• Initial settings
Do not set values from H'0000 to T – 1 (where T is the initial value of TCNT3). After the
counters start and the first compare match A3 event has occurred, however, settings in this
range also become possible.
• Changing settings
Use the buffer registers. Correct waveform output may not be obtained if a general register is
written to directly.
• Cautions on changes of general register settings
Figure 10.39 shows six correct examples and one incorrect example.
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Section 10 16-Bit Integrated Timer Unit (ITU)
GRA3
GR
H'0000
Not allowed
BR
GR
Figure 10.39 Changing a General Register Setting by Buffer Transfer (Example 1)
Buffer transfer at transition from up-counting to down-counting
If the general register value is in the range from GRA3 – T + 1 to GRA3, do not transfer a
buffer register value outside this range. Conversely, if the general register value is outside
this range, do not transfer a value within this range. See figure 10.40.
GRA3 + 1
GRA3
GRA3 – T + 1
GRA3 – T
Illegal changes
TCNT3
TCNT4
Figure 10.40 Changing a General Register Setting by Buffer Transfer (Caution 1)
Buffer transfer at transition from down-counting to up-counting
If the general register value is in the range from H'0000 to T – 1, do not transfer a buffer
register value outside this range. Conversely, when a general register value is outside this
range, do not transfer a value within this range. See figure 10.41.
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Section 10 16-Bit Integrated Timer Unit (ITU)
TCNT3
TCNT4
T
T–1
Illegal changes
H'0000
H'FFFF
Figure 10.41 Changing a General Register Setting by Buffer Transfer (Caution 2)
General register settings outside the counting range (H'0000 to GRA3)
Waveforms with a duty cycle of 0% or 100% can be output by setting a general register to
a value outside the counting range. When a buffer register is set to a value outside the
counting range, then later restored to a value within the counting range, the counting
direction (up or down) must be the same both times. See figure 10.42.
GRA3
GR
H'0000
0% duty cycle
100% duty cycle
Output pin
Output pin
BR
GR
Write during down-counting
Write during up-counting
Figure 10.42 Changing a General Register Setting by Buffer Transfer (Example 2)
Settings can be made in this way by detecting GRA3 compare match or TCNT4 underflow
before writing to the buffer register. They can also be made by using GRA3 compare match
to activate the DMAC.
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Section 10 16-Bit Integrated Timer Unit (ITU)
10.4.7
Phase Counting Mode
In phase counting mode the phase difference between two external clock inputs (at the TCLKA
and TCLKB pins) is detected, and TCNT2 counts up or down accordingly.
In phase counting mode, the TCLKA and TCLKB pins automatically function as external clock
input pins and TCNT2 becomes an up/down-counter, regardless of the settings of bits TPSC2 to
TPSC0, CKEG1, and CKEG0 in TCR2. Settings of bits CCLR1, CCLR0 in TCR2, and settings in
TIOR2, TIER2, TSR2, GRA2, and GRB2 are valid. The input capture and output compare
functions can be used, and interrupts can be generated.
Phase counting is available only in channel 2.
Sample Setup Procedure for Phase Counting Mode: Figure 10.43 shows a sample procedure
for setting up phase counting mode.
Phase counting mode
Select phase counting mode
1
Select flag setting condition
2
Start counter
3
1. Set the MDF bit in TMDR to 1 to select
phase counting mode.
2. Select the flag setting condition with
the FDIR bit in TMDR.
3. Set the STR2 bit to 1 in TSTR to start
the timer counter.
Phase counting mode
Figure 10.43 Setup Procedure for Phase Counting Mode (Example)
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Section 10 16-Bit Integrated Timer Unit (ITU)
Example of Phase Counting Mode: Figure 10.44 shows an example of operations in phase
counting mode. Table 10.9 lists the up-counting and down-counting conditions for TCNT2.
In phase counting mode both the rising and falling edges of TCLKA and TCLKB are counted. The
phase difference between TCLKA and TCLKB must be at least 1.5 states, the phase overlap must
also be at least 1.5 states, and the pulse width must be at least 2.5 states. See figure 10.45.
TCNT2 value
Counting up
Counting down
Time
TCLKB
TCLKA
Figure 10.44 Operation in Phase Counting Mode (Example)
Table 10.9 Up/Down Counting Conditions
Counting Direction
Up-Counting
TCLKB
↑
Low
TCLKA
Phase
difference
High
↑
Down-Counting
↓
High
Phase
difference
Low
High
↓
↓
Pulse width
↓
Low
Low
↑
↑
High
Pulse width
TCLKA
TCLKB
Overlap
Overlap
Phase difference and overlap: at least 1.5 states
Pulse width:
at least 2.5 states
Figure 10.45 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
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Section 10 16-Bit Integrated Timer Unit (ITU)
10.4.8
Buffering
Buffering operates differently depending on whether a general register is an output compare
register or an input capture register, with further differences in reset-synchronized PWM mode and
complementary PWM mode. Buffering is available only in channels 3 and 4. Buffering operations
under the conditions mentioned above are described next.
• General register used for output compare
The buffer register value is transferred to the general register at compare match.
See figure 10.46.
Compare match signal
BR
GR
Comparator
TCNT
Figure 10.46 Compare Match Buffering
• General register used for input capture
The TCNT value is transferred to the general register at input capture. The previous general
register value is transferred to the buffer register.
See figure 10.47.
Input capture signal
BR
GR
Figure 10.47 Input Capture Buffering
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TCNT
Section 10 16-Bit Integrated Timer Unit (ITU)
• Complementary PWM mode
The buffer register value is transferred to the general register when TCNT3 and TCNT4
change counting direction. This occurs at the following two times:
When TCNT3 compare matches GRA3
When TCNT4 underflows
• Reset-synchronized PWM mode
The buffer register value is transferred to the general register at compare match A3.
Sample Buffering Setup Procedure: Figure 10.48 shows a sample buffering setup procedure.
Buffering
Select general register functions
1
Set buffer bits
2
Start counters
3
1. Set TIOR to select the output compare or input
capture function of the general registers.
2. Set bits BFA3, BFA4, BFB3, and BFB4 in TFCR
to select buffering of the required general registers.
3. Set the STR bits to 1 in TSTR to start the timer
counters.
Buffered operation
Figure 10.48 Buffering Setup Procedure (Example)
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Section 10 16-Bit Integrated Timer Unit (ITU)
Examples of Buffering: Figure 10.49 shows an example in which GRA is set to function as an
output compare register buffered by BRA, TCNT is set to operate as a periodic counter cleared by
GRB compare match, and TIOCA and TIOCB are set to toggle at compare match A and B.
Because of the buffer setting, when TIOCA toggles at compare match A, the BRA value is
simultaneously transferred to GRA. This operation is repeated each time compare match A occurs.
Figure 10.50 shows the transfer timing.
TCNT value
Counter cleared by compare match B
GRB
H'0250
H'0200
H'0100
H'0000
Time
BRA
H'0200
GRA
H'0250
H'0200
H'0100
H'0200
H'0100
H'0200
TIOCB
Toggle
output
TIOCA
Toggle
output
Compare match A
Figure 10.49 Register Buffering (Example 1: Buffering of Output Compare Register)
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Section 10 16-Bit Integrated Timer Unit (ITU)
φ
n
TCNT
n+1
Compare
match signal
Buffer transfer
signal
N
BR
GR
n
N
Figure 10.50 Compare Match and Buffer Transfer Timing (Example)
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Section 10 16-Bit Integrated Timer Unit (ITU)
Figure 10.51 shows an example in which GRA is set to function as an input capture register
buffered by BRA, and TCNT is cleared by input capture B. The falling edge is selected as the
input capture edge at TIOCB. Both edges are selected as input capture edges at TIOCA. Because
of the buffer setting, when the TCNT value is captured into GRA at input capture A, the previous
GRA value is simultaneously transferred to BRA. Figure 10.52 shows the transfer timing.
TCNT value
Counter cleared by
input capture B
H'0180
H'0160
H'0005
H'0000
Time
TIOCB
TIOCA
GRA
H'0005
H'0160
H'0005
BRA
GRB
H'0160
H'0180
Input capture A
Figure 10.51 Register Buffering (Example 2: Buffering of Input Capture Register)
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Section 10 16-Bit Integrated Timer Unit (ITU)
φ
TIOC pin
Input capture
signal
TCNT
n
n+1
N
N+1
GR
M
n
n
N
BR
m
M
M
n
Figure 10.52 Input Capture and Buffer Transfer Timing (Example)
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Section 10 16-Bit Integrated Timer Unit (ITU)
Figure 10.53 shows an example in which GRB3 is buffered by BRB3 in complementary PWM
mode. Buffering is used to set GRB3 to a higher value than GRA3, generating a PWM waveform
with 0% duty cycle. The BRB3 value is transferred to GRB3 when TCNT3 matches GRA3, and
when TCNT4 underflows.
TCNT3 and
TCNT4 values
TCNT3
H'1FFF
GRA3
GRB3
TCNT4
H'0999
H'0000
BRB3
GRB3
Time
H'1FFF
H'0999
H'0999
H'0999
H'1FFF
H'0999
H'1FFF
H'0999
TIOCA3
TIOCB3
Figure 10.53 Register Buffering (Example 3: Buffering in Complementary PWM Mode)
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Section 10 16-Bit Integrated Timer Unit (ITU)
10.4.9
ITU Output Timing
The ITU outputs from channels 3 and 4 can be disabled by bit settings in TOER or by an external
trigger, or inverted by bit settings in TOCR.
Timing of Enabling and Disabling of ITU Output by TOER: In this example an ITU output is
disabled by clearing a master enable bit to 0 in TOER. An arbitrary value can be output by
appropriate settings of the data register (DR) and data direction register (DDR) of the
corresponding input/output port. Figure 10.54 illustrates the timing of the enabling and disabling
of ITU output by TOER.
T1
T2
T3
φ
Address bus
TOER address
TOER
ITU output pin
Timer output
ITU output
I/O port
Generic input/output
Figure 10.54 Timing of Disabling of ITU Output by Writing to TOER (Example)
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Section 10 16-Bit Integrated Timer Unit (ITU)
Timing of Disabling of ITU Output by External Trigger: If the XTGD bit is cleared to 0 in
TOCR in reset-synchronized PWM mode or complementary PWM mode, when an input capture A
signal occurs in channel 1, the master enable bits are cleared to 0 in TOER, disabling ITU output.
Figure 10.55 shows the timing.
φ
TIOCA1 pin
Input capture
signal
N
TOER
ITU output
pins
H'C0
N
ITU output
I/O port
ITU output
Generic
input/output
ITU output
ITU output
H'C0
I/O port
Generic
input/output
N: Arbitrary setting (H'C1 to H'FF)
Figure 10.55 Timing of Disabling of ITU Output by External Trigger (Example)
Timing of Output Inversion by TOCR: The output levels in reset-synchronized PWM mode and
complementary PWM mode can be inverted by inverting the output level select bits (OLS4 and
OLS3) in TOCR. Figure 10.56 shows the timing.
T1
T2
T3
φ
Address bus
TOCR address
TOCR
ITU output pin
Inverted
Figure 10.56 Timing of Inverting of ITU Output Level by Writing to TOCR (Example)
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Section 10 16-Bit Integrated Timer Unit (ITU)
10.5
Interrupts
The ITU has two types of interrupts: input capture/compare match interrupts, and overflow
interrupts.
10.5.1
Setting of Status Flags
Timing of Setting of IMFA and IMFB at Compare Match: IMFA and IMFB are set to 1 by a
compare match signal generated when TCNT matches a general register (GR). The compare match
signal is generated in the last state in which the values match (when TCNT is updated from the
matching count to the next count). Therefore, when TCNT matches a general register, the compare
match signal is not generated until the next timer clock input. Figure 10.57 shows the timing of the
setting of IMFA and IMFB.
φ
TCNT input
clock
TCNT
GR
N
N+1
N
Compare
match signal
IMF
IMI
Figure 10.57 Timing of Setting of IMFA and IMFB by Compare Match
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Section 10 16-Bit Integrated Timer Unit (ITU)
Timing of Setting of IMFA and IMFB by Input Capture: IMFA and IMFB are set to 1 by an
input capture signal. The TCNT contents are simultaneously transferred to the corresponding
general register. Figure 10.58 shows the timing.
φ
Input capture
signal
IMF
N
TCNT
GR
N
IMI
Figure 10.58 Timing of Setting of IMFA and IMFB by Input Capture
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Section 10 16-Bit Integrated Timer Unit (ITU)
Timing of Setting of Overflow Flag (OVF): OVF is set to 1 when TCNT overflows from
H'FFFF to H'0000 or underflows from H'0000 to H'FFFF. Figure 10.59 shows the timing.
φ
TCNT
H'FFFF
H'0000
Overflow
signal
OVF
OVI
Figure 10.59 Timing of Setting of OVF
10.5.2
Clearing of Status Flags
If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is
cleared. Figure 10.60 shows the timing.
TSR write cycle
T1
T2
T3
φ
Address
TSR address
IMF, OVF
Figure 10.60 Timing of Clearing of Status Flags
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Section 10 16-Bit Integrated Timer Unit (ITU)
10.5.3
Interrupt Sources and DMA Controller Activation
Each ITU channel can generate a compare match/input capture A interrupt, a compare match/input
capture B interrupt, and an overflow interrupt. In total there are 15 interrupt sources, all
independently vectored. An interrupt is requested when the interrupt request flag and interrupt
enable bit are both set to 1.
The priority order of the channels can be modified in interrupt priority registers A and B (IPRA
and IPRB). For details see section 5, Interrupt Controller.
Compare match/input capture A interrupts in channels 0 to 3 can activate the DMA controller
(DMAC). When the DMAC is activated a CPU interrupt is not requested.
Table 10.10 lists the interrupt sources.
Table 10.10 ITU Interrupt Sources
Channel
Interrupt
Source
Description
DMAC
Activatable
Priority*
0
IMIA0
Compare match/input capture A0
Yes
High
IMIB0
Compare match/input capture B0
No
OVI0
Overflow 0
No
IMIA1
Compare match/input capture A1
Yes
IMIB1
Compare match/input capture B1
No
↑
1
2
3
4
OVI1
Overflow 1
No
IMIA2
Compare match/input capture A2
Yes
IMIB2
Compare match/input capture B2
No
OVI2
Overflow 2
No
IMIA3
Compare match/input capture A3
Yes
IMIB3
Compare match/input capture B3
No
OVI3
Overflow 3
No
IMIA4
Compare match/input capture A4
No
IMIB4
Compare match/input capture B4
No
OVI4
Overflow 4
No
Low
Note: * The priority immediately after a reset is indicated. Inter-channel priorities can be changed
by settings in IPRA and IPRB.
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Section 10 16-Bit Integrated Timer Unit (ITU)
10.6
Usage Notes
This section describes contention and other matters requiring special attention during ITU
operations.
Contention between TCNT Write and Clear: If a counter clear signal occurs in the T3 state of a
TCNT write cycle, clearing of the counter takes priority and the write is not performed. See figure
10.61.
TCNT write cycle
T2
T1
T3
φ
Address bus
TCNT address
Internal write signal
Counter clear signal
TCNT
N
H'0000
Figure 10.61 Contention between TCNT Write and Clear
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Section 10 16-Bit Integrated Timer Unit (ITU)
Contention between TCNT Word Write and Increment: If an increment pulse occurs in the T3
state of a TCNT word write cycle, writing takes priority and TCNT is not incremented. See figure
10.62.
TCNT word write cycle
T2
T1
T3
φ
Address bus
TCNT address
Internal write signal
TCNT input clock
TCNT
N
M
TCNT write data
Figure 10.62 Contention between TCNT Word Write and Increment
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Section 10 16-Bit Integrated Timer Unit (ITU)
Contention between TCNT Byte Write and Increment: If an increment pulse occurs in the T2
or T3 state of a TCNT byte write cycle, writing takes priority and TCNT is not incremented. The
TCNT byte that was not written retains its previous value. See figure 10.63, which shows an
increment pulse occurring in the T2 state of a byte write to TCNTH.
TCNTH byte write cycle
T1
T2
T3
φ
TCNTH address
Address bus
Internal write signal
TCNT input clock
TCNTH
N
M
TCNT write data
TCNTL
X
X+1
X
Figure 10.63 Contention between TCNT Byte Write and Increment
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Section 10 16-Bit Integrated Timer Unit (ITU)
Contention between General Register Write and Compare Match: If a compare match occurs
in the T3 state of a general register write cycle, writing takes priority and the compare match signal
is inhibited. See figure 10.64.
General register write cycle
T1
T2
T3
φ
GR address
Address bus
Internal write signal
TCNT
N
GR
N
N+1
M
General register write data
Compare match signal
Inhibited
Figure 10.64 Contention between General Register Write and Compare Match
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Section 10 16-Bit Integrated Timer Unit (ITU)
Contention between TCNT Write and Overflow or Underflow: If an overflow occurs in the T3
state of a TCNT write cycle, writing takes priority and the counter is not incremented. OVF is set
to 1. The same holds for underflow. See figure 10.65.
TCNT write cycle
T1
T2
T3
φ
Address bus
TCNT address
Internal write signal
TCNT input clock
Overflow signal
TCNT
H'FFFF
M
TCNT write data
OVF
Figure 10.65 Contention between TCNT Write and Overflow
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Section 10 16-Bit Integrated Timer Unit (ITU)
Contention between General Register Read and Input Capture: If an input capture signal
occurs during the T3 state of a general register read cycle, the value before input capture is read.
See figure 10.66.
General register read cycle
T2
T1
T3
φ
GR address
Address bus
Internal read signal
Input capture signal
GR
Internal data bus
X
M
X
Figure 10.66 Contention between General Register Read and Input Capture
Rev. 7.00 Sep 21, 2005 page 400 of 878
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Section 10 16-Bit Integrated Timer Unit (ITU)
Contention between Counter Clearing by Input Capture and Counter Increment: If an input
capture signal and counter increment signal occur simultaneously, the counter is cleared according
to the input capture signal. The counter is not incremented by the increment signal. The value
before the counter is cleared is transferred to the general register. See figure 10.67.
φ
Input capture signal
Counter clear signal
TCNT input clock
TCNT
GR
N
H'0000
N
Figure 10.67 Contention between Counter Clearing by Input Capture and Counter
Increment
Rev. 7.00 Sep 21, 2005 page 401 of 878
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Section 10 16-Bit Integrated Timer Unit (ITU)
Contention between General Register Write and Input Capture: If an input capture signal
occurs in the T3 state of a general register write cycle, input capture takes priority and the write to
the general register is not performed. See figure 10.68.
General register write cycle
T1
T2
T3
φ
Address bus
GR address
Internal write signal
Input capture signal
TCNT
GR
M
M
Figure 10.68 Contention between General Register Write and Input Capture
Note on Waveform Period Setting: When a counter is cleared by compare match, the counter is
cleared in the last state at which the TCNT value matches the general register value, at the time
when this value would normally be updated to the next count. The actual counter frequency is
therefore given by the following formula:
f=
φ
(N + 1)
(f: counter frequency. φ: system clock frequency. N: value set in general register.)
Rev. 7.00 Sep 21, 2005 page 402 of 878
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Section 10 16-Bit Integrated Timer Unit (ITU)
Contention between Buffer Register Write and Input Capture: If a buffer register is used for
input capture buffering and an input capture signal occurs in the T3 state of a write cycle, input
capture takes priority and the write to the buffer register is not performed. See figure 10.69.
Buffer register write cycle
T2
T1
T3
φ
BR address
Address bus
Internal write signal
Input capture signal
GR
N
X
TCNT value
BR
M
N
Figure 10.69 Contention between Buffer Register Write and Input Capture
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Section 10 16-Bit Integrated Timer Unit (ITU)
Note on Synchronous Preset: When channels are synchronized, if a TCNT value is modified by
byte write access, all 16 bits of all synchronized counters assume the same value as the counter
that was addressed.
Example: When channels 2 and 3 are synchronized
• Byte write to channel 2 or byte write to channel 3
TCNT2
W
X
TCNT3
Y
Z
Upper byte Lower byte
Write A to upper byte
of channel 2
TCNT2
A
X
TCNT3
A
X
Upper byte Lower byte
Write A to lower byte
of channel 3
TCNT2
Y
A
TCNT3
Y
A
Upper byte Lower byte
• Word write to channel 2 or word write to channel 3
TCNT2
W
X
TCNT3
Y
Z
Write AB word to
channel 2 or 3
Upper byte Lower byte
TCNT2
A
B
TCNT3
A
B
Upper byte Lower byte
Note on Setup of Reset-Synchronized PWM Mode and Complementary PWM Mode: When
setting bits CMD1 and CMD0 in TFCR, take the following precautions:
• Write to bits CMD1 and CMD0 only when TCNT3 and TCNT4 are stopped.
• Do not switch directly between reset-synchronized PWM mode and complementary PWM
mode. First switch to normal mode (by clearing bit CMD1 to 0), then select reset-synchronized
PWM mode or complementary PWM mode.
Rev. 7.00 Sep 21, 2005 page 404 of 878
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: Setting available (valid).
—: Setting does not affect this mode.
—
—
—
—
—
—
—
—
—
FDIR
TMDR
PWM0 = 0
PWM0 = 0
PWM0 = 0
PWM0 = 1
PWM
TOCR
Register Settings
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ResetOutput
CompleSynchro- BufferXTGD Level
mentary
nized
ing
Select
PWM
PWM
TFCR
—
—
—
—
—
—
—
—
—
Master
Enable
TOER
IOA2 = 1
Other bits
unrestricted
IOA2 = 0
Other bits
unrestricted
—
IOA
*
IOB
IOB2 = 1
Other bits
unrestricted
IOB2 = 0
Other bits
unrestricted
TIOR0
CCLR1 = 1
CCLR0 = 1
CCLR1 = 1
CCLR0 = 0
CCLR1 = 0
CCLR0 = 1
Clear
Select
TCR0
Clock
Select
Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
Legend:
—
—
Counter By compare
clearing match/input
capture A
SYNC0 = 1
—
Input capture B
Synchronous
clear
—
Input capture A
—
—
Output compare B
By compare
match/input
capture B
—
Output compare A
—
MDF
—
SYNC0 = 1
Synchronization
PWM mode
Synchronous preset
Operating Mode
TSNC
Section 10 16-Bit Integrated Timer Unit (ITU)
ITU Operating Modes
Table 10.11 (a) ITU Operating Modes (Channel 0)
Rev. 7.00 Sep 21, 2005 page 405 of 878
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—
—
Counter By compare
clearing match/input
capture A
By compare
match/input
capture B
: Setting available (valid).
—: Setting does not affect this mode.
—
—
—
—
—
—
—
—
—
FDIR
TMDR
PWM1 = 0
PWM1 = 0
PWM1 = 0
PWM1 = 1
PWM
TOCR
Register Settings
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
*2
—
—
—
—
—
—
—
—
—
—
—
—
—
ResetOutput
CompleSynchro- BufferXTGD Level
mentary
nized
ing
Select
PWM
PWM
TFCR
—
—
—
—
—
—
—
—
—
Master
Enable
TOER
IOA2 = 1
Other bits
unrestricted
IOA2 = 0
Other bits
unrestricted
—
IOA
*1
IOB
IOB2 = 1
Other bits
unrestricted
IOB2 = 0
Other bits
unrestricted
TIOR1
CCLR1 = 1
CCLR0 = 1
CCLR1 = 1
CCLR0 = 0
CCLR1 = 0
CCLR0 = 1
Clear
Select
TCR1
Clock
Select
Notes: 1. The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
2. Valid only when channels 3 and 4 are operating in complementary PWM mode or reset-synchronized PWM mode.
Legend:
—
Input capture B
—
—
Input capture A
SYNC1 = 1
—
Output compare B
Synchronous
clear
—
Output compare A
—
MDF
—
SYNC1 = 1
Synchronization
PWM mode
Synchronous preset
Operating Mode
TSNC
Section 10 16-Bit Integrated Timer Unit (ITU)
Table 10.11 (b) ITU Operating Modes (Channel 1)
: Setting available (valid).
—: Setting does not affect this mode.
MDF = 1
—
—
—
—
—
—
—
—
—
FDIR
TMDR
PWM2 = 0
PWM2 = 0
PWM2 = 0
PWM2 = 1
PWM
TOCR
Register Settings
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ResetOutput
CompleSynchro- BufferXTGD Level
mentary
nized
ing
Select
PWM
PWM
TFCR
—
—
—
—
—
—
—
—
—
—
Master
Enable
TOER
IOA2 = 1
Other bits
unrestricted
IOA2 = 0
Other bits
unrestricted
—
IOA
*
IOB
IOB2 = 1
Other bits
unrestricted
IOB2 = 0
Other bits
unrestricted
TIOR2
CCLR1 = 1
CCLR0 = 1
CCLR1 = 1
CCLR0 = 0
CCLR1 = 0
CCLR0 = 1
Clear
Select
TCR2
—
Clock
Select
Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
Legend:
Phase counting
mode
—
—
Counter By compare
clearing match/input
capture A
SYNC2 = 1
—
Input capture B
Synchronous
clear
—
Input capture A
—
—
Output compare B
By compare
match/input
capture B
—
Output compare A
—
MDF
—
SYNC2 = 1
Synchronization
PWM mode
Synchronous preset
Operating Mode
TSNC
Section 10 16-Bit Integrated Timer Unit (ITU)
Table 10.11 (c) ITU Operating Modes (Channel 2)
Rev. 7.00 Sep 21, 2005 page 407 of 878
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REJ09B0259-0700
—
—
—
Counter By compare
clearing match/input
capture A
By compare
match/input
capture B
Synchronous
clear
—
Buffering
(BRB)
—
—
—
—
—
—
—
—
—
—
—
—
—
Notes: 1.
2.
3.
4.
5.
6.
*3
—
—
CMD1 = 1
CMD0 = 1
CMD1 = 1
CMD0 = 0
Illegal setting:
CMD1 = 1
CMD0 = 0
CMD1 = 0
Illegal setting:
CMD1 = 1
CMD0 = 0
PWM3 = 0 CMD1 = 0
PWM3 = 0 CMD1 = 0
CMD1 = 0
PWM3 = 0 CMD1 = 0
CMD1 = 1
CMD0 = 1
CMD1 = 1
CMD0 = 0
CMD1 = 0
*4
CMD1 = 0
CMD1 = 0
CMD1 = 0
CMD1 = 0
CMD1 = 0
ResetSynchronized
PWM
TFCR
BFA3 = 1
Other bits
unrestricted
BFA3 = 1
Other bits
unrestricted
Buffering
—
—
—
—
—
—
—
—
—
—
—
IOA2 = 0
Other bits
unrestricted
—
IOA
*1
—
—
—
*6
*1
CCLR1 = 1
CCLR0 = 1
*1
—
CCLR1 = 1
CCLR0 = 0
*1
CCLR1 = 0
CCLR0 = 1
CCLR1 = 0
CCLR0 = 0
CCLR1 = 0
CCLR0 = 1
—
IOA2 = 1
Other bits
unrestricted
Clear
Select
TCR3
*1
EB3 ignored
Other bits
unrestricted
*2
IOB
IOB2 = 0
Other bits
unrestricted
TIOR3
EA3 ignored IOA2 = 1
Other bits
Other bits
unrestricted unrestricted
*1
Master
Enable
TOER
*6
—
—
—
—
—
—
—
—
—
—
Output
XTGD Level
Select
TOCR
Register Settings
*5
Clock
Select
Master enable bit settings are valid only during waveform output.
The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
Do not set both channels 3 and 4 for synchronous operation when complementary PWM mode is selected.
The counter cannot be cleared by input capture A when reset-synchronized PWM mode is selected.
In complementary PWM mode, select the same clock source for channels 3 and 4.
Use the input capture A function in channel 1.
: Setting available (valid).
—: Setting does not affect this mode.
—
Buffering
(BRA)
Legend:
—
Reset-synchronized
PWM mode
—
—
Input capture B
*3
—
Input capture A
Complementary
PWM mode
—
Output compare B
SYNC3 = 1
—
Output compare A
—
—
SYNC3 = 1
PWM
Complementary
PWM
PWM3 = 1 CMD1 = 0
TMDR
Synchro- MDF FDIR
nization
PWM mode
Synchronous preset
Operating Mode
TSNC
Section 10 16-Bit Integrated Timer Unit (ITU)
Table 10.11 (d) ITU Operating Modes (Channel 3)
—
—
—
Counter By compare
clearing match/input
capture A
By compare
match/input
capture B
Synchronous
clear
—
Buffering
(BRB)
—
—
—
—
—
—
—
—
—
—
—
—
—
Notes: 1.
2.
3.
4.
5.
6.
*3
—
—
CMD1 = 1
CMD0 = 1
CMD1 = 1
CMD0 = 0
Illegal setting:
CMD1 = 1
CMD0 = 0
Illegal setting:
CMD1 = 1
CMD0 = 0
Illegal setting:
CMD1 = 1
CMD0 = 0
PWM4 = 0 CMD1 = 0
PWM4 = 0 CMD1 = 0
CMD1 = 0
PWM4 = 0 CMD1 = 0
CMD1 = 1
CMD0 = 1
BFA4 = 1
Other bits
unrestricted
—
—
—
*4
CMD1 = 1
CMD0 = 0
—
*4
—
—
—
—
—
—
—
BFA4 = 1
Other bits
unrestricted
Buffering
—
—
—
—
—
—
—
—
—
—
—
Output
XTGD Level
Select
TOCR
Register Settings
*4
CMD1 = 0
CMD1 = 0
CMD1 = 0
CMD1 = 0
CMD1 = 0
ResetSynchronized
PWM
TFCR
IOA2 = 0
Other bits
unrestricted
—
IOA
*1
*1
*1
*1
*1
EB4 ignored
Other bits
unrestricted
—
—
*2
IOB
—
—
IOA2 = 1
Other bits
unrestricted
IOB2 = 0
Other bits
unrestricted
TIOR4
EA4 ignored IOA2 = 1
Other bits
Other bits
unrestricted unrestricted
*1
Master
Enable
TOER
*6
CCLR1 = 0
CCLR0 = 0
CCLR1 = 1
CCLR0 = 1
CCLR1 = 1
CCLR0 = 0
CCLR1 = 0
CCLR0 = 1
Clear
Select
TCR4
*6
*5
Clock
Select
Master enable bit settings are valid only during waveform output.
The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
Do not set both channels 3 and 4 for synchronous operation when complementary PWM mode is selected.
When reset-synchronized PWM mode is selected, TCNT4 operates independently and the counter clearing function is available. Waveform output is not affected.
In complementary PWM mode, select the same clock source for channels 3 and 4.
TCR4 settings are valid in reset-synchronized PWM mode, but TCNT4 operates independently, without affecting waveform output.
: Setting available (valid).
—: Setting does not affect this mode.
—
Buffering
(BRA)
Legend:
—
Reset-synchronized
PWM mode
—
—
Input capture B
*3
—
Input capture A
Complementary
PWM mode
—
Output compare B
SYNC4 = 1
—
Output compare A
—
—
SYNC4 = 1
PWM
Complementary
PWM
PWM4 = 1 CMD1 = 0
TMDR
Synchro- MDF FDIR
nization
PWM mode
Synchronous preset
Operating Mode
TSNC
Section 10 16-Bit Integrated Timer Unit (ITU)
Table 10.11 (e) ITU Operating Modes (Channel 4)
Rev. 7.00 Sep 21, 2005 page 409 of 878
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Section 10 16-Bit Integrated Timer Unit (ITU)
Rev. 7.00 Sep 21, 2005 page 410 of 878
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Section 11 Programmable Timing Pattern Controller
Section 11 Programmable Timing Pattern Controller
11.1
Overview
The H8/3048 Group has a built-in programmable timing pattern controller (TPC) that provides
pulse outputs by using the 16-bit integrated timer unit (ITU) as a time base. The TPC pulse
outputs are divided into 4-bit groups (group 3 to group 0) that can operate simultaneously and
independently.
11.1.1
Features
TPC features are listed below.
• 16-bit output data
Maximum 16-bit data can be output. TPC output can be enabled on a bit-by-bit basis.
• Four output groups
Output trigger signals can be selected in 4-bit groups to provide up to four different 4-bit
outputs.
• Selectable output trigger signals
Output trigger signals can be selected for each group from the compare-match signals of four
ITU channels.
• Non-overlap mode
A non-overlap margin can be provided between pulse outputs.
• Can operate together with the DMA controller (DMAC)
The compare-match signals selected as trigger signals can activate the DMAC for sequential
output of data without CPU intervention.
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Section 11 Programmable Timing Pattern Controller
11.1.2
Block Diagram
Figure 11.1 shows a block diagram of the TPC.
ITU compare match signals
Control logic
TP15
TP14
TP13
TP12
TP11
TP10
TP 9
TP 8
TP 7
TP 6
TP 5
TP 4
TP 3
TP 2
TP 1
TP 0
Legend
TPMR:
TPCR:
NDERB:
NDERA:
PBDDR:
PADDR:
NDRB:
NDRA:
PBDR:
PADR:
PADDR
PBDDR
NDERA
NDERB
TPMR
TPCR
Internal
data bus
Pulse output
pins, group 3
PBDR
NDRB
PADR
NDRA
Pulse output
pins, group 2
Pulse output
pins, group 1
Pulse output
pins, group 0
TPC output mode register
TPC output control register
Next data enable register B
Next data enable register A
Port B data direction register
Port A data direction register
Next data register B
Next data register A
Port B data register
Port A data register
Figure 11.1 TPC Block Diagram
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Section 11 Programmable Timing Pattern Controller
11.1.3
TPC Pins
Table 11.1 summarizes the TPC output pins.
Table 11.1 TPC Pins
Name
Symbol
I/O
Function
TPC output 0
TP0
Output
Group 0 pulse output
TPC output 1
TP1
Output
TPC output 2
TP2
Output
TPC output 3
TP3
Output
TPC output 4
TP4
Output
TPC output 5
TP5
Output
TPC output 6
TP6
Output
TPC output 7
TP7
Output
TPC output 8
TP8
Output
TPC output 9
TP9
Output
TPC output 10
TP10
Output
TPC output 11
TP11
Output
TPC output 12
TP12
Output
TPC output 13
TP13
Output
TPC output 14
TP14
Output
TPC output 15
TP15
Output
Group 1 pulse output
Group 2 pulse output
Group 3 pulse output
Rev. 7.00 Sep 21, 2005 page 413 of 878
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Section 11 Programmable Timing Pattern Controller
11.1.4
Registers
Table 11.2 summarizes the TPC registers.
Table 11.2 TPC Registers
Address*
H'FFD1
1
Name
Abbreviation
R/W
Port A data direction register
PADDR
W
Initial Value
H'00
2
H'FFD3
Port A data register
PADR
R/(W)*
H'00
H'FFD4
Port B data direction register
PBDDR
W
H'00
H'00
H'FFD6
Port B data register
PBDR
2
R/(W)*
H'FFA0
TPC output mode register
TPMR
R/W
H'F0
H'FFA1
TPC output control register
TPCR
R/W
H'FF
H'FFA2
Next data enable register B
NDERB
R/W
H'00
H'FFA3
Next data enable register A
NDERA
R/W
H'00
H'FFA5/
3
H'FFA7*
Next data register A
NDRA
R/W
H'00
H'FFA4
3
H'FFA6*
Next data register B
NDRB
R/W
H'00
Notes: 1. Lower 16 bits of the address.
2. Bits used for TPC output cannot be written.
3. The NDRA address is H'FFA5 when the same output trigger is selected for TPC output
groups 0 and 1 by settings in TPCR. When the output triggers are different, the NDRA
address is H'FFA7 for group 0 and H'FFA5 for group 1. Similarly, the address of NDRB
is H'FFA4 when the same output trigger is selected for TPC output groups 2 and 3 by
settings in TPCR. When the output triggers are different, the NDRB address is H'FFA6
for group 2 and H'FFA4 for group 3.
Rev. 7.00 Sep 21, 2005 page 414 of 878
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Section 11 Programmable Timing Pattern Controller
11.2
Register Descriptions
11.2.1
Port A Data Direction Register (PADDR)
PADDR is an 8-bit write-only register that selects input or output for each pin in port A.
Bit
7
6
5
4
3
2
1
0
PA7 DDR PA6 DDR PA5 DDR PA4 DDR PA3 DDR PA2 DDR PA1 DDR PA0 DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port A data direction 7 to 0
These bits select input or
output for port A pins
Port A is multiplexed with pins TP7 to TP0. Bits corresponding to pins used for TPC output must
be set to 1. For further information about PADDR, see section 9.11, Port A.
11.2.2
Port A Data Register (PADR)
PADR is an 8-bit readable/writable register that stores TPC output data for groups 0 and 1, when
these TPC output groups are used.
Bit
7
6
5
4
3
2
1
0
PA 7
PA 6
PA 5
PA 4
PA 3
PA 2
PA 1
PA 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
Port A data 7 to 0
These bits store output data
for TPC output groups 0 and 1
Note: * Bits selected for TPC output by NDERA settings become read-only bits.
For further information about PADR, see section 9.11, Port A.
Rev. 7.00 Sep 21, 2005 page 415 of 878
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Section 11 Programmable Timing Pattern Controller
11.2.3
Port B Data Direction Register (PBDDR)
PBDDR is an 8-bit write-only register that selects input or output for each pin in port B.
Bit
7
6
5
4
3
2
1
0
PB7 DDR PB6 DDR PB5 DDR PB4 DDR PB3 DDR PB2 DDR PB1 DDR PB0 DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port B data direction 7 to 0
These bits select input or
output for port B pins
Port B is multiplexed with pins TP15 to TP8. Bits corresponding to pins used for TPC output must
be set to 1. For further information about PBDDR, see section 9.12, Port B.
11.2.4
Port B Data Register (PBDR)
PBDR is an 8-bit readable/writable register that stores TPC output data for groups 2 and 3, when
these TPC output groups are used.
Bit
7
6
5
4
3
2
1
0
PB 7
PB 6
PB 5
PB 4
PB 3
PB 2
PB 1
PB 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
Port B data 7 to 0
These bits store output data
for TPC output groups 2 and 3
Note: * Bits selected for TPC output by NDERB settings become read-only bits.
For further information about PBDR, see section 9.12, Port B.
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Section 11 Programmable Timing Pattern Controller
11.2.5
Next Data Register A (NDRA)
NDRA is an 8-bit readable/writable register that stores the next output data for TPC output groups
1 and 0 (pins TP7 to TP0). During TPC output, when an ITU compare match event specified in
TPCR occurs, NDRA contents are transferred to the corresponding bits in PADR. The address of
NDRA differs depending on whether TPC output groups 0 and 1 have the same output trigger or
different output triggers.
NDRA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Same Trigger for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by
the same compare match event, the NDRA address is H'FFA5. The upper 4 bits belong to group 1
and the lower 4 bits to group 0. Address H'FFA7 consists entirely of reserved bits that cannot be
modified and are always read as 1.
Address H'FFA5
Bit
7
6
5
4
3
2
1
0
NDR7
NDR6
NDR5
NDR4
NDR3
NDR2
NDR1
NDR0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Next data 7 to 4
These bits store the next output
data for TPC output group 1
Next data 3 to 0
These bits store the next output
data for TPC output group 0
Address H'FFA7
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
—
—
—
—
—
Reserved bits
Rev. 7.00 Sep 21, 2005 page 417 of 878
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Section 11 Programmable Timing Pattern Controller
Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered
by different compare match events, the address of the upper 4 bits of NDRA (group 1) is H'FFA5
and the address of the lower 4 bits (group 0) is H'FFA7. Bits 3 to 0 of address H'FFA5 and bits 7
to 4 of address H'FFA7 are reserved bits that cannot be modified and are always read as 1.
Address H'FFA5
Bit
7
6
5
4
3
2
1
0
NDR7
NDR6
NDR5
NDR4
—
—
—
—
Initial value
0
0
0
0
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
—
—
—
—
Next data 7 to 4
These bits store the next output
data for TPC output group 1
Reserved bits
Address H'FFA7
Bit
7
6
5
4
3
2
1
0
—
—
—
—
NDR3
NDR2
NDR1
NDR0
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
Reserved bits
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Next data 3 to 0
These bits store the next output
data for TPC output group 0
Section 11 Programmable Timing Pattern Controller
11.2.6
Next Data Register B (NDRB)
NDRB is an 8-bit readable/writable register that stores the next output data for TPC output groups
3 and 2 (pins TP15 to TP8). During TPC output, when an ITU compare match event specified in
TPCR occurs, NDRB contents are transferred to the corresponding bits in PBDR. The address of
NDRB differs depending on whether TPC output groups 2 and 3 have the same output trigger or
different output triggers.
NDRB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Same Trigger for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by
the same compare match event, the NDRB address is H'FFA4. The upper 4 bits belong to group 3
and the lower 4 bits to group 2. Address H'FFA6 consists entirely of reserved bits that cannot be
modified and are always read as 1.
Address H'FFA4
Bit
7
6
5
4
3
2
1
0
NDR15
NDR14
NDR13
NDR12
NDR11
NDR10
NDR9
NDR8
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Next data 15 to 12
These bits store the next output
data for TPC output group 3
Next data 11 to 8
These bits store the next output
data for TPC output group 2
Address H'FFA6
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
—
—
—
—
—
Reserved bits
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Section 11 Programmable Timing Pattern Controller
Different Triggers for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered
by different compare match events, the address of the upper 4 bits of NDRB (group 3) is H'FFA4
and the address of the lower 4 bits (group 2) is H'FFA6. Bits 3 to 0 of address H'FFA4 and bits 7
to 4 of address H'FFA6 are reserved bits that cannot be modified and are always read as 1.
Address H'FFA4
Bit
7
6
5
4
3
2
1
0
NDR15
NDR14
NDR13
NDR12
—
—
—
—
Initial value
0
0
0
0
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
—
—
—
—
Next data 15 to 12
These bits store the next output
data for TPC output group 3
Reserved bits
Address H'FFA6
Bit
7
6
5
4
3
2
1
0
—
—
—
—
NDR11
NDR10
NDR9
NDR8
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
Reserved bits
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Next data 11 to 8
These bits store the next output
data for TPC output group 2
Section 11 Programmable Timing Pattern Controller
11.2.7
Next Data Enable Register A (NDERA)
NDERA is an 8-bit readable/writable register that enables or disables TPC output groups 1 and 0
(TP7 to TP0) on a bit-by-bit basis.
Bit
6
7
NDER7
5
NDER6 NDER5
4
3
NDER4 NDER3
2
NDER2
1
0
NDER1 NDER0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Next data enable 7 to 0
These bits enable or disable
TPC output groups 1 and 0
If a bit is enabled for TPC output by NDERA, then when the ITU compare match event selected in
the TPC output control register (TPCR) occurs, the NDRA value is automatically transferred to
the corresponding PADR bit, updating the output value. If TPC output is disabled, the bit value is
not transferred from NDRA to PADR and the output value does not change.
NDERA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or disable TPC
output groups 1 and 0 (TP7 to TP0) on a bit-by-bit basis.
Bits 7 to 0:
NDER7 to NDER0
Description
0
TPC outputs TP7 to TP0 are disabled
(NDR7 to NDR0 are not transferred to PA7 to PA0)
1
TPC outputs TP7 to TP0 are enabled
(NDR7 to NDR0 are transferred to PA7 to PA0)
(Initial value)
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Section 11 Programmable Timing Pattern Controller
11.2.8
Next Data Enable Register B (NDERB)
NDERB is an 8-bit readable/writable register that enables or disables TPC output groups 3 and 2
(TP15 to TP8) on a bit-by-bit basis.
Bit
7
6
4
5
3
2
1
0
NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Next data enable 15 to 8
These bits enable or disable
TPC output groups 3 and 2
If a bit is enabled for TPC output by NDERB, then when the ITU compare match event selected in
the TPC output control register (TPCR) occurs, the NDRB value is automatically transferred to the
corresponding PBDR bit, updating the output value. If TPC output is disabled, the bit value is not
transferred from NDRB to PBDR and the output value does not change.
NDERB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Next Data Enable 15 to 8 (NDER15 to NDER8): These bits enable or disable TPC
output groups 3 and 2 (TP15 to TP8) on a bit-by-bit basis.
Bits 7 to 0:
NDER15 to NDER8
Description
0
TPC outputs TP15 to TP8 are disabled
(NDR15 to NDR8 are not transferred to PB7 to PB0)
1
TPC outputs TP15 to TP8 are enabled
(NDR15 to NDR8 are transferred to PB7 to PB0)
Rev. 7.00 Sep 21, 2005 page 422 of 878
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(Initial value)
Section 11 Programmable Timing Pattern Controller
11.2.9
TPC Output Control Register (TPCR)
TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on a
group-by-group basis.
Bit
7
6
5
4
3
2
1
0
G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Group 3 compare
match select 1 and 0
These bits select
the compare match
Group 2 compare
event that triggers
TPC output group 3 match select 1 and 0
These bits select
(TP15 to TP12 )
the compare match
event that triggers Group 1 compare
TPC output group 2 match select 1 and 0
These bits select
(TP11 to TP8 )
the compare match
event that triggers Group 0 compare
TPC output group 1 match select 1 and 0
These bits select
(TP7 to TP4 )
the compare match
event that triggers
TPC output group 0
(TP3 to TP0 )
TPCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 and 6—Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits
select the compare match event that triggers TPC output group 3 (TP15 to TP12).
Bit 7: G3CMS1
Bit 6: G3CMS0
Description
0
0
TPC output group 3 (TP15 to TP12) is triggered by compare
match in ITU channel 0
1
TPC output group 3 (TP15 to TP12) is triggered by compare
match in ITU channel 1
0
TPC output group 3 (TP15 to TP12) is triggered by compare
match in ITU channel 2
1
TPC output group 3 (TP15 to TP12) is triggered by compare
match in ITU channel 3
(Initial value)
1
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Section 11 Programmable Timing Pattern Controller
Bits 5 and 4—Group 2 Compare Match Select 1 and 0 (G2CMS1, G2CMS0): These bits
select the compare match event that triggers TPC output group 2 (TP11 to TP8).
Bit 5: G2CMS1
Bit 4: G2CMS0
Description
0
0
TPC output group 2 (TP11 to TP8) is triggered by compare
match in ITU channel 0
1
TPC output group 2 (TP11 to TP8) is triggered by compare
match in ITU channel 1
0
TPC output group 2 (TP11 to TP8) is triggered by compare
match in ITU channel 2
1
TPC output group 2 (TP11 to TP8) is triggered by compare
match in ITU channel 3
(Initial value)
1
Bits 3 and 2—Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits
select the compare match event that triggers TPC output group 1 (TP7 to TP4).
Bit 3: G1CMS1
Bit 2: G1CMS0
Description
0
0
TPC output group 1 (TP7 to TP4) is triggered by compare
match in ITU channel 0
1
TPC output group 1 (TP7 to TP4) is triggered by compare
match in ITU channel 1
0
TPC output group 1 (TP7 to TP4) is triggered by compare
match in ITU channel 2
1
TPC output group 1 (TP7 to TP4) is triggered by compare
match in ITU channel 3
(Initial value)
1
Bits 1 and 0—Group 0 Compare Match Select 1 and 0 (G0CMS1, G0CMS0): These bits
select the compare match event that triggers TPC output group 0 (TP3 to TP0).
Bit 1: G0CMS1
Bit 0: G0CMS0
Description
0
0
TPC output group 0 (TP3 to TP0) is triggered by compare
match in ITU channel 0
1
TPC output group 0 (TP3 to TP0) is triggered by compare
match in ITU channel 1
0
TPC output group 0 (TP3 to TP0) is triggered by compare
match in ITU channel 2
1
TPC output group 0 (TP3 to TP0) is triggered by compare
match in ITU channel 3
(Initial value)
1
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Section 11 Programmable Timing Pattern Controller
11.2.10 TPC Output Mode Register (TPMR)
TPMR is an 8-bit readable/writable register that selects normal or non-overlapping TPC output for
each group.
Bit
7
6
5
4
—
—
—
—
3
2
G3NOV G2NOV
1
0
G1NOV G0NOV
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
Reserved bits
Group 3 non-overlap
Selects non-overlapping TPC
output for group 3 (TP15 to TP12 )
Group 2 non-overlap
Selects non-overlapping TPC
output for group 2 (TP11 to TP8 )
Group 1 non-overlap
Selects non-overlapping TPC
output for group 1 (TP7 to TP4 )
Group 0 non-overlap
Selects non-overlapping TPC
output for group 0 (TP3 to TP0 )
The output trigger period of a non-overlapping TPC output waveform is set in general register B
(GRB) in the ITU channel selected for output triggering. The non-overlap margin is set in general
register A (GRA). The output values change at compare match A and B. For details see section
11.3.4, Non-Overlapping TPC Output.
TPMR is initialized to H'F0 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 4—Reserved: Read-only bits, always read as 1.
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Section 11 Programmable Timing Pattern Controller
Bit 3—Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping TPC output for
group 3 (TP15 to TP12).
Bit 3: G3NOV
Description
0
Normal TPC output in group 3 (output values change at compare match A in
the selected ITU channel)
(Initial value)
1
Non-overlapping TPC output in group 3 (independent 1 and 0 output at
compare match A and B in the selected ITU channel)
Bit 2—Group 2 Non-Overlap (G2NOV): Selects normal or non-overlapping TPC output for
group 2 (TP11 to TP8).
Bit 2: G2NOV
Description
0
Normal TPC output in group 2 (output values change at compare match A in
the selected ITU channel)
(Initial value)
1
Non-overlapping TPC output in group 2 (independent 1 and 0 output at
compare match A and B in the selected ITU channel)
Bit 1—Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping TPC output for
group 1 (TP7 to TP4).
Bit 1: G1NOV
Description
0
Normal TPC output in group 1 (output values change at compare match A in
the selected ITU channel)
(Initial value)
1
Non-overlapping TPC output in group 1 (independent 1 and 0 output at
compare match A and B in the selected ITU channel)
Bit 0—Group 0 Non-Overlap (G0NOV): Selects normal or non-overlapping TPC output for
group 0 (TP3 to TP0).
Bit 0: G0NOV
Description
0
Normal TPC output in group 0 (output values change at compare match A in
the selected ITU channel)
(Initial value)
1
Non-overlapping TPC output in group 0 (independent 1 and 0 output at
compare match A and B in the selected ITU channel)
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Section 11 Programmable Timing Pattern Controller
11.3
Operation
11.3.1
Overview
When corresponding bits in PADDR or PBDDR and NDERA or NDERB are set to 1, TPC output
is enabled. The TPC output initially consists of the corresponding PADR or PBDR contents.
When a compare-match event selected in TPCR occurs, the corresponding NDRA or NDRB bit
contents are transferred to PADR or PBDR to update the output values.
Figure 11.2 illustrates the TPC output operation. Table 11.3 summarizes the TPC operating
conditions.
DDR
NDER
Q
Q
Output trigger signal
C
Q
DR
D
Q NDR
D
Internal
data bus
TPC output pin
Figure 11.2 TPC Output Operation
Table 11.3 TPC Operating Conditions
NDER
DDR
Pin Function
0
0
Generic input port
1
Generic output port
1
0
Generic input port (but the DR bit is a read-only bit, and when compare
match occurs, the NDR bit value is transferred to the DR bit)
1
TPC pulse output
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Section 11 Programmable Timing Pattern Controller
Sequential output of up to 16-bit patterns is possible by writing new output data to NDRA and
NDRB before the next compare match. For information on non-overlapping operation, see section
11.3.4, Non-Overlapping TPC Output.
11.3.2
Output Timing
If TPC output is enabled, NDRA/NDRB contents are transferred to PADR/PBDR and output
when the selected compare match event occurs. Figure 11.3 shows the timing of these operations
for the case of normal output in groups 2 and 3, triggered by compare match A.
φ
TCNT
N
GRA
N+1
N
Compare
match A signal
NDRB
n
PBDR
m
n
TP8 to TP15
m
n
Figure 11.3 Timing of Transfer of Next Data Register Contents and Output (Example)
Rev. 7.00 Sep 21, 2005 page 428 of 878
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Section 11 Programmable Timing Pattern Controller
11.3.3
Normal TPC Output
Sample Setup Procedure for Normal TPC Output: Figure 11.4 shows a sample procedure for
setting up normal TPC output.
Normal TPC output
Select GR functions
1
Set GRA value
2
Select counting operation
3
Select interrupt request
4
Set initial output data
5
Select port output
6
Enable TPC output
7
Select TPC output trigger
8
Set next TPC output data
9
Start counter
10
ITU setup
Port and
TPC setup
ITU setup
Compare match?
1.
Set TIOR to make GRA an output compare
register (with output inhibited).
2. Set the TPC output trigger period.
3. Select the counter clock source with bits
TPSC2 to TPSC0 in TCR. Select the counter
clear source with bits CCLR1 and CCLR0.
4. Enable the IMFA interrupt in TIER.
The DMAC can also be set up to transfer
data to the next data register.
5. Set the initial output values in the DR bits
of the input/output port pins to be used for
TPC output.
6. Set the DDR bits of the input/output port
pins to be used for TPC output to 1.
7. Set the NDER bits of the pins to be used for
TPC output to 1.
8. Select the ITU compare match event to be
used as the TPC output trigger in TPCR.
9. Set the next TPC output values in the NDR bits.
10. Set the STR bit to 1 in TSTR to start the
timer counter.
11. At each IMFA interrupt, set the next output
values in the NDR bits.
No
Yes
Set next TPC output data
11
Figure 11.4 Setup Procedure for Normal TPC Output (Example)
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Section 11 Programmable Timing Pattern Controller
Example of Normal TPC Output (Example of Five-Phase Pulse Output): Figure 11.5 shows
an example in which the TPC is used for cyclic five-phase pulse output.
TCNT value
Compare match
TCNT
GRA
H'0000
Time
NDRB
80
PBDR
00
C0
80
40
C0
60
40
20
60
30
20
10
30
18
10
08
18
88
08
80
88
C0
80
40
C0
TP15
TP14
TP13
TP12
TP11
•
•
•
•
The ITU channel to be used as the output trigger channel is set up so that GRA is an output compare
register and the counter will be cleared by compare match A. The trigger period is set in GRA.
The IMIEA bit is set to 1 in TIER to enable the compare match A interrupt.
H'F8 is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set in
TPCR to select compare match in the ITU channel set up in step 1 as the output trigger.
Output data H'80 is written in NDRB.
The timer counter in this ITU channel is started. When compare match A occurs, the NDRB contents
are transferred to PBDR and output. The compare match/input capture A (IMFA) interrupt service routine
writes the next output data (H'C0) in NDRB.
Five-phase overlapping pulse output (one or two phases active at a time) can be obtained by writing
H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88… at successive IMFA interrupts. If the DMAC is set for
activation by this interrupt, pulse output can be obtained without loading the CPU.
Figure 11.5 Normal TPC Output Example (Five-Phase Pulse Output)
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Section 11 Programmable Timing Pattern Controller
11.3.4
Non-Overlapping TPC Output
Sample Setup Procedure for Non-Overlapping TPC Output: Figure 11.6 shows a sample
procedure for setting up non-overlapping TPC output.
Non-overlapping
TPC output
Select GR functions
1
Set GR values
2
Select counting operation
3
Select interrupt requests
4
Set initial output data
5
Set up TPC output
6
Enable TPC transfer
7
Select TPC transfer trigger
8
Select non-overlapping groups
9
Set next TPC output data
10
Start counter
11
ITU setup
Port and
TPC setup
ITU setup
Compare match A?
1. Set TIOR to make GRA and GRB output
compare registers (with output inhibited).
2. Set the TPC output trigger period in GRB
and the non-overlap margin in GRA.
3. Select the counter clock source with bits
TPSC2 to TPSC0 in TCR. Select the counter
clear source with bits CCLR1 and CCLR0.
4. Enable the IMFA interrupt in TIER.
The DMAC can also be set up to transfer
data to the next data register.
5. Set the initial output values in the DR bits
of the input/output port pins to be used for
TPC output.
6. Set the DDR bits of the input/output port pins
to be used for TPC output to 1.
7. Set the NDER bits of the pins to be used for
TPC output to 1.
8. In TPCR, select the ITU compare match
event to be used as the TPC output trigger.
9. In TPMR, select the groups that will operate
in non-overlap mode.
10. Set the next TPC output values in the NDR
bits.
11. Set the STR bit to 1 in TSTR to start the timer
counter.
12. At each IMFA interrupt, write the next output
value in the NDR bits.
No
Yes
Set next TPC output data
12
Figure 11.6 Setup Procedure for Non-Overlapping TPC Output (Example)
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Section 11 Programmable Timing Pattern Controller
Example of Non-Overlapping TPC Output (Example of Four-Phase Complementary NonOverlapping Output): Figure 11.7 shows an example of the use of TPC output for four-phase
complementary non-overlapping pulse output.
TCNT value
GRB
TCNT
GRA
H'0000
Time
NDRB
95
PBDR
00
65
95
59
05
65
56
41
59
95
50
56
65
14
95
05
65
Non-overlap margin
TP15
TP14
TP13
TP12
TP11
TP10
TP9
TP8
This operation example is described below.
• The output trigger ITU channel is set up so that GRA and GRB are output compare registers and the
counter will be cleared by compare match B. The TPC output trigger period is set in GRB. The nonoverlap margin is set in GRA. The IMIEA bit is set to 1 in TIER to enable IMFA interrupts.
• H'FF is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set
in TPCR to select compare match in the ITU channel set up in step 1 as the output trigger.
Bits G3NOV and G2NOV are set to 1 in TPMR to select non-overlapping output. Output data H'95 is
written in NDRB.
• The timer counter in this ITU channel is started. When compare match B occurs, outputs change from
1 to 0. When compare match A occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed
by the value of GRA). The IMFA interrupt service routine writes the next output data (H'65) in NDRB.
• Four-phase complementary non-overlapping pulse output can be obtained by writing H'59, H'56, H'95…
at successive IMFA interrupts. If the DMAC is set for activation by this interrupt, pulse output can be
obtained without loading the CPU.
Figure 11.7 Non-Overlapping TPC Output Example
(Four-Phase Complementary Non-Overlapping Pulse Output)
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Section 11 Programmable Timing Pattern Controller
11.3.5
TPC Output Triggering by Input Capture
TPC output can be triggered by ITU input capture as well as by compare match. If GRA and GRB
functions as an input capture register in the ITU channel selected in TPCR, TPC output will be
triggered by the input capture signal. Figure 11.8 shows the timing.
φ
TIOC pin
Input capture
signal
N
NDR
DR
M
N
Figure 11.8 TPC Output Triggering by Input Capture (Example)
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Section 11 Programmable Timing Pattern Controller
11.4
Usage Notes
11.4.1
Operation of TPC Output Pins
TP0 to TP15 are multiplexed with ITU, DMAC, address bus, and other pin functions. When ITU,
DMAC, or address output is enabled, the corresponding pins cannot be used for TPC output. The
data transfer from NDR bits to DR bits takes place, however, regardless of the usage of the pin.
Pin functions should be changed only under conditions in which the output trigger event will not
occur.
11.4.2
Note on Non-Overlapping Output
During non-overlapping operation, the transfer of NDR bit values to DR bits takes place as
follows.
1. NDR bits are always transferred to DR bits at compare match A.
2. At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred
if their value is 1.
Figure 11.9 illustrates the non-overlapping TPC output operation.
DDR
NDER
Q
Q
Compare match A
Compare match B
C
Q
DR
D
Q NDR
TPC output pin
Figure 11.9 Non-Overlapping TPC Output
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D
Internal
data bus
Section 11 Programmable Timing Pattern Controller
Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before
compare match A. NDR contents should not be altered during the interval from compare match B
to compare match A (the non-overlap margin).
This can be accomplished by having the IMFA interrupt service routine write the next data in
NDR, or by having the IMFA interrupt activate the DMAC. The next data must be written before
the next compare match B occurs.
Figure 11.10 shows the timing relationships.
Compare
match A
Compare
match B
NDR write
NDR write
NDR
DR
0 output
0/1 output
0 output
0/1 output
Write to NDR
in this interval
Do not write
to NDR in this
interval
Write to NDR
in this interval
Do not write
to NDR in this
interval
Figure 11.10 Non-Overlapping Operation and NDR Write Timing
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Section 11 Programmable Timing Pattern Controller
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Section 12 Watchdog Timer
Section 12 Watchdog Timer
12.1
Overview
The H8/3048 Group has an on-chip watchdog timer (WDT). The WDT has two selectable
functions: it can operate as a watchdog timer to supervise system operation, or it can operate as an
interval timer. As a watchdog timer, it generates a reset signal for the chip if a system crash allows
the timer counter (TCNT) to overflow before being rewritten. In interval timer operation, an
interval timer interrupt is requested at each TCNT overflow.
12.1.1
Features
WDT features are listed below.
• Selection of eight counter clock sources
φ/2, φ/32, φ/64, φ/128, φ/256, φ/512, φ/2048, or φ/4096
• Interval timer option
• Timer counter overflow generates a reset signal or interrupt.
The reset signal is generated in watchdog timer operation. An interval timer interrupt is
generated in interval timer operation.
• Watchdog timer reset signal resets the entire chip internally, and can also be output externally.
The reset signal generated by timer counter overflow during watchdog timer operation resets
the entire chip internally. An external reset signal can be output from the RESO pin to reset
other system devices simultaneously.
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Section 12 Watchdog Timer
12.1.2
Block Diagram
Figure 12.1 shows a block diagram of the WDT.
Overflow
TCNT
Interrupt signal
Interrupt
control
(interval timer)
TCSR
Reset control
Internal
data bus
Internal clock sources
φ/2
RSTCSR
Reset
(internal, external)
Read/
write
control
φ/32
φ/64
Clock
Clock
selector
φ/128
φ/256
φ/512
Legend
TCNT:
Timer counter
TCSR:
Timer control/status register
RSTCSR: Reset control/status register
φ/2048
φ/4096
Figure 12.1 WDT Block Diagram
12.1.3
Pin Configuration
Table 12.1 describes the WDT output pin.
Table 12.1 WDT Pin
Name
Abbreviation
I/O
Function
Reset output
RESO
Output*
External output of the watchdog timer reset
signal
Note: * Open-drain output.
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Section 12 Watchdog Timer
12.1.4
Register Configuration
Table 12.2 summarizes the WDT registers.
Table 12.2 WDT Registers
Address*
Write*
2
H'FFA8
H'FFAA
1
Read
Name
Abbreviation
R/W
Initial
Value
H'FFA8
Timer control/status register
TCSR
3
R/(W)*
H'18
H'FFA9
Timer counter
TCNT
R/W
H'00
H'FFAB
Reset control/status register
RSTCSR
3
R/(W)*
H'3F
Notes: 1. Lower 16 bits of the address.
2. Write word data starting at this address.
3. Only 0 can be written in bit 7, to clear the flag.
12.2
Register Descriptions
12.2.1
Timer Counter (TCNT)
TCNT is an 8-bit readable and writable* up-counter.
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from an internal
clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from
H'FF to H'00), the OVF bit is set to 1 in TCSR. TCNT is initialized to H'00 by a reset and when
the TME bit is cleared to 0.
Note: * TCNT is write-protected by a password. For details see section 12.2.4, Notes on Register
Access.
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Section 12 Watchdog Timer
12.2.2
Timer Control/Status Register (TCSR)
TCSR is an 8-bit readable and writable* register. Its functions include selecting the timer mode
and clock source.
Note: * TCSR differs from other registers in being more difficult to write. For details see section
12.2.4, Notes on Register Access.
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
OVF
WT/IT
TME
—
—
CKS2
CKS1
CKS0
0
R/(W)*
0
0
1
1
0
0
0
R/W
R/W
—
—
R/W
R/W
R/W
Clock select
These bits select the
TCNT clock source
Reserved bits
Timer enable
Selects whether TCNT runs or halts
Timer mode select
Selects the mode
Overflow flag
Status flag indicating overflow
Note: * Only 0 can be written, to clear the flag.
Bits 7 to 5 are initialized to 0 by a reset and in standby mode. Bits 2 to 0 are initialized to 0 by a
reset. In software standby mode bits 2 to 0 are not initialized, but retain their previous values.
Bit 7—Overflow Flag (OVF): This status flag indicates that the timer counter has overflowed
from H'FF to H'00.
Bit 7: OVF
Description
0
[Clearing condition]
Cleared by reading OVF when OVF = 1, then writing 0 in OVF
1
[Setting condition]
Set when TCNT changes from H'FF to H'00
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(Initial value)
Section 12 Watchdog Timer
Bit 6—Timer Mode Select (WT/IT
IT):
IT Selects whether to use the WDT as a watchdog timer or
interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request
when TCNT overflows. If used as a watchdog timer, the WDT generates a reset signal when
TCNT overflows.
Bit 6: WT/IT
IT
Description
0
Interval timer: requests interval timer interrupts
1
Watchdog timer: generates a reset signal
(Initial value)
Bit 5—Timer Enable (TME): Selects whether TCNT runs or is halted.
When WT/IT = 1, clear the SYSCR software standby bit (SSBY) to 0, then set the TME to 1.
When SSBY is set to 1, clear TME to 0.
Bit 5: TME
Description
0
TCNT is initialized to H'00 and halted
1
TCNT is counting and CPU interrupt requests are enabled
(Initial value)
Bits 4 and 3—Reserved: Read-only bits, always read as 1.
Bits 2 to 0—Clock Select 2 to 0 (CKS2/1/0): These bits select one of eight internal clock sources,
obtained by prescaling the system clock (φ), for input to TCNT.
Bit 2: CKS2
Bit 1: CKS1
Bit 0: CKS0
Description
0
0
0
φ/2
1
φ/32
1
0
φ/64
1
φ/128
0
φ/256
1
φ/512
0
φ/2048
1
φ/4096
1
0
1
(Initial value)
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Section 12 Watchdog Timer
12.2.3
Reset Control/Status Register (RSTCSR)
RSTCSR is an 8-bit readable and writable* register that indicates when a reset signal has been
generated by watchdog timer overflow, and controls external output of the reset signal.
Note: * RSTCSR differs from other registers in being more difficult to write. For details see
section 12.2.4, Notes on Register Access.
Bit
7
6
5
4
3
2
1
0
WRST
RSTOE
—
—
—
—
—
—
Initial value
0
0
1
1
1
1
1
1
Read/Write
R/(W)*
R/W
—
—
—
—
—
—
Reserved bits
Reset output enable
Enables or disables external output of the reset signal
Watchdog timer reset
Indicates that a reset signal has been generated
Note: * Only 0 can be written in bit 7, to clear the flag.
Bits 7 and 6 are initialized by input of a reset signal at the RES pin. They are not initialized by
reset signals generated by watchdog timer overflow.
Bit 7—Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that
TCNT has overflowed and generated a reset signal. This reset signal resets the entire chip
internally. If bit RSTOE is set to 1, this reset signal is also output (low) at the RESO pin to
initialize external system devices.
Bit 7: WRST
Description
0
[Clearing conditions]
Cleared to 0 by reset signal input at RES pin
(Initial value)
Cleared by reading WRST when WRST = 1, then writing 0 in WRST
1
[Setting condition]
Set when TCNT overflow generates a reset signal during watchdog timer
operation
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Section 12 Watchdog Timer
Bit 6—Reset Output Enable (RSTOE): Enables or disables external output at the RESO pin of
the reset signal generated if TCNT overflows during watchdog timer operation.
Bit 6: RSTOE
Description
0
Reset signal is not output externally
1
Reset signal is output externally
(Initial value)
Bits 5 to 0—Reserved: Read-only bits, always read as 1.
12.2.4
Notes on Register Access
The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write. The procedures for writing and reading these registers are given below.
Writing to TCNT and TCSR: These registers must be written by a word transfer instruction.
They cannot be written by byte instructions. Figure 12.2 shows the format of data written to
TCNT and TCSR. TCNT and TCSR both have the same write address. The write data must be
contained in the lower byte of the written word. The upper byte must contain H'5A (password for
TCNT) or H'A5 (password for TCSR). This transfers the write data from the lower byte to TCNT
or TCSR.
15
TCNT write
Address
H'FFA8*
H'5A
15
TCSR write
Address
8 7
H'FFA8*
0
Write data
8 7
H'A5
0
Write data
Note: * Lower 16 bits of the address.
Figure 12.2 Format of Data Written to TCNT and TCSR
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Section 12 Watchdog Timer
Writing to RSTCSR: RSTCSR must be written by a word transfer instruction. It cannot be
written by byte transfer instructions. Figure 12.3 shows the format of data written to RSTCSR. To
write 0 in the WRST bit, the write data must have H'A5 in the upper byte and H'00 in the lower
byte. The H'00 in the lower byte clears the WRST bit in RSTCSR to 0. To write to the RSTOE bit,
the upper byte must contain H'5A and the lower byte must contain the write data. Writing this
word transfers a write data value into the RSTOE bit.
Writing 0 in WRST bit
Address
H'FFAA*
Writing to RSTOE bit
Address
15
8 7
H'A5
15
H'FFAA*
0
H'00
8 7
H'5A
0
Write data
Note: * Lower 16 bits of the address.
Figure 12.3 Format of Data Written to RSTCSR
Reading TCNT, TCSR, and RSTCSR: These registers are read like other registers. Byte access
instructions can be used. The read addresses are H'FFA8 for TCSR, H'FFA9 for TCNT, and
H'FFAB for RSTCSR, as listed in table 12.3.
Table 12.3 Read Addresses of TCNT, TCSR, and RSTCSR
Address*
Register
H'FFA8
TCSR
H'FFA9
TCNT
H'FFAB
RSTCSR
Note: * Lower 16 bits of the address.
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Section 12 Watchdog Timer
12.3
Operation
Operations when the WDT is used as a watchdog timer and as an interval timer are described
below.
12.3.1
Watchdog Timer Operation
Figure 12.4 illustrates watchdog timer operation. To use the WDT as a watchdog timer, set the
WT/IT and TME bits to 1 in TCSR. Software must prevent TCNT overflow by rewriting the
TCNT value (normally by writing H'00) before overflow occurs. If TCNT fails to be rewritten and
overflows due to a system crash etc., the chip is internally reset for a duration of 518 states.
The watchdog reset signal can be externally output from the RESO pin to reset external system
devices. The reset signal is output externally for 132 states. External output can be enabled or
disabled by the RSTOE bit in RSTCSR.
A watchdog reset has the same vector as a reset generated by input at the RES pin. Software can
distinguish a RES reset from a watchdog reset by checking the WRST bit in RSTCSR.
If a RES reset and a watchdog reset occur simultaneously, the RES reset takes priority.
WDT overflow
H'FF
TME set to 1
TCNT count
value
H'00
OVF = 1
Start
Internal
reset signal
H'00 written
in TCNT
Reset
H'00 written
in TCNT
518 states
RESO
132 states
Figure 12.4 Watchdog Timer Operation
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Section 12 Watchdog Timer
12.3.2
Interval Timer Operation
Figure 12.5 illustrates interval timer operation. To use the WDT as an interval timer, clear bit
WT/IT to 0 and set bit TME to 1 in TCSR. An interval timer interrupt request is generated at each
TCNT overflow. This function can be used to generate interval timer interrupts at regular
intervals.
H'FF
TCNT
count value
Time t
H'00
WT/ IT = 0
TME = 1
Interval
timer
interrupt
Interval
timer
interrupt
Interval
timer
interrupt
Interval
timer
interrupt
Figure 12.5 Interval Timer Operation
12.3.3
Timing of Setting of Overflow Flag (OVF)
Figure 12.6 shows the timing of setting of the OVF flag in TCSR. The OVF flag is set to 1 when
TCNT overflows. At the same time, a reset signal is generated in watchdog timer operation, or an
interval timer interrupt is generated in interval timer operation.
φ
TCNT
H'FF
H'00
Overflow signal
OVF
Figure 12.6 Timing of Setting of OVF
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Section 12 Watchdog Timer
12.3.4
Timing of Setting of Watchdog Timer Reset Bit (WRST)
The WRST bit in RSTCSR is valid when bits WT/IT and TME are both set to 1 in TCSR.
Figure 12.7 shows the timing of setting of WRST and the internal reset timing. The WRST bit is
set to 1 when TCNT overflows and OVF is set to 1. At the same time an internal reset signal is
generated for the entire chip. This internal reset signal clears OVF to 0, but the WRST bit remains
set to 1. The reset routine must therefore clear the WRST bit.
φ
H'FF
TCNT
H'00
Overflow signal
OVF
WDT internal
reset
WRST
Figure 12.7 Timing of Setting of WRST Bit and Internal Reset
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Section 12 Watchdog Timer
12.4
Interrupts
During interval timer operation, an overflow generates an interval timer interrupt (WOVI). The
interval timer interrupt is requested whenever the OVF bit is set to 1 in TCSR.
12.5
Usage Notes
Contention between TCNT Write and Increment: If a timer counter clock pulse is generated
during the T3 state of a write cycle to TCNT, the write takes priority and the timer count is not
incremented. See figure 12.8.
Write cycle: CPU writes to TCNT
T1
T2
T3
φ
TCNT
Internal write
signal
TCNT input
clock
TCNT
N
M
Counter write data
Figure 12.8 Contention between TCNT Write and Increment
Changing CKS2 to CKS0 Values: Halt TCNT by clearing the TME bit to 0 in TCSR before
changing the values of bits CKS2 to CKS0.
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Section 12 Watchdog Timer
12.6
Notes
This chip incorporates an WDT. The timer counter value of the on-chip WDT is not rewritten,
even if a system crash occurs. If an overflow occurs, a reset signal is generated and the chip is
reset.
However, if the following three events occur due to a CPU overrun, for example, the above
operations cannot be guaranteed since the WDT and the CPU are incorporated in the same chip.
• When the internal I/O registers related to the on-chip WDT are rewritten.
• When software standby mode is incorrectly entered.
• When the break mode is incorrectly entered.
In addition, as stated in the NMI above, if an abnormal level is input into the power supply pins or
the system control pins, correct operations cannot be guaranteed.
Except the above cases, the on-chip WDT functions as a device that supports recovery from a
system crash. Accordingly, when a fail-safe function is required in your system, an additional
circuit may be required as necessary.
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Section 12 Watchdog Timer
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Section 13 Serial Communication Interface
Section 13 Serial Communication Interface
13.1
Overview
The H8/3048 Group has a serial communication interface (SCI) with two independent channels.
The two channels are functionally identical. The SCI can communicate in asynchronous or
synchronous mode. It also has a multiprocessor communication function for serial communication
among two or more processors.
When the SCI is not used, it can be halted to conserve power. Each SCI channel can be halted
independently. For details see section 21.6, Module Standby Function.
Channel 0 (SCI0) also has a smart card interface function conforming to the ISO/IEC7816-3
(Identification Card) standard. This function supports serial communication with a smart card. For
details, see section 14, Smart Card Interface.
13.1.1
Features
SCI features are listed below.
• Selection of asynchronous or synchronous mode for serial communication
Asynchronous mode
Serial data communication is synchronized one character at a time. The SCI can
communicate with a universal asynchronous receiver/transmitter (UART), asynchronous
communication interface adapter (ACIA), or other chip that employs standard
asynchronous serial communication. It can also communicate with two or more other
processors using the multiprocessor communication function. There are twelve selectable
serial data communication formats.
• Data length: 7 or 8 bits
• Stop bit length: 1 or 2 bits
• Parity bit: even, odd, or none
• Multiprocessor bit: 1 or 0
• Receive error detection: parity, overrun, and framing errors
• Break detection: by reading the RxD level directly when a framing error occurs
Synchronous mode
Serial data communication is synchronized with a clock signal. The SCI can communicate
with other chips having a synchronous communication function. There is one serial data
communication format.
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Section 13 Serial Communication Interface
• Data length: 8 bits
• Receive error detection: overrun errors
• Full duplex communication
The transmitting and receiving sections are independent, so the SCI can transmit and receive
simultaneously. The transmitting and receiving sections are both double-buffered, so serial
data can be transmitted and received continuously.
• Built-in baud rate generator with selectable bit rates
• Selectable transmit/receive clock sources: internal clock from baud rate generator, or external
clock from the SCK pin.
• Four types of interrupts
Transmit-data-empty, transmit-end, receive-data-full, and receive-error interrupts are requested
independently. The transmit-data-empty and receive-data-full interrupts from SCI0 can
activate the DMA controller (DMAC) to transfer data.
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Section 13 Serial Communication Interface
13.1.2
Block Diagram
Bus interface
Figure 13.1 shows a block diagram of the SCI.
Module data bus
RxD
RDR
TDR
RSR
TSR
SSR
SCR
SMR
BRR
Transmit/
receive control
TxD
SCK
Parity generate
Parity check
Internal
data bus
Baud rate
generator
φ
φ/4
φ/16
φ/64
Clock
External clock
TEI
TXI
RXI
ERI
Legend
RSR: Receive shift register
RDR: Receive data register
TSR: Transmit shift register
TDR: Transmit data register
SMR: Serial mode register
SCR: Serial control register
SSR: Serial status register
BRR: Bit rate register
Figure 13.1 SCI Block Diagram
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Section 13 Serial Communication Interface
13.1.3
Input/Output Pins
The SCI has serial pins for each channel as listed in table 13.1.
Table 13.1 SCI Pins
Channel
Name
Abbreviation
I/O
Function
0
Serial clock pin
SCK0
Input/output
SCI0 clock input/output
Receive data pin
RxD0
Input
SCI0 receive data input
Transmit data pin
TxD0
Output
SCI0 transmit data output
Serial clock pin
SCK1
Input/output
SCI1 clock input/output
Receive data pin
RxD1
Input
SCI1 receive data input
Transmit data pin
TxD1
Output
SCI1 transmit data output
1
13.1.4
Register Configuration
The SCI has internal registers as listed in table 13.2. These registers select asynchronous or
synchronous mode, specify the data format and bit rate, and control the transmitter and receiver
sections.
Table 13.2 Registers
Channel
Address*
0
1
1
Name
Abbreviation
R/W
Initial Value
H'FFB0
Serial mode register
SMR
R/W
H'00
H'FFB1
Bit rate register
BRR
R/W
H'FF
H'FFB2
Serial control register
SCR
R/W
H'00
H'FFB3
Transmit data register
TDR
R/W
H'FFB4
Serial status register
SSR
R/(W)*
H'84
H'FFB5
Receive data register
RDR
R
H'00
H'FFB8
Serial mode register
SMR
R/W
H'00
H'FFB9
Bit rate register
BRR
R/W
H'FF
H'FFBA
Serial control register
SCR
R/W
H'00
H'FFBB
Transmit data register
TDR
R/W
H'FF
H'FFBC
Serial status register
SSR
R/(W)*
H'84
H'FFBD
Receive data register
RDR
R
H'00
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written, to clear flags.
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H'FF
2
2
Section 13 Serial Communication Interface
13.2
Register Descriptions
13.2.1
Receive Shift Register (RSR)
RSR is the register that receives serial data.
Bit
7
6
5
4
3
2
1
0
Read/Write
—
—
—
—
—
—
—
—
The SCI loads serial data input at the RxD pin into RSR in the order received, LSB (bit 0) first,
thereby converting the data to parallel data. When 1 byte has been received, it is automatically
transferred to RDR. The CPU cannot read or write RSR directly.
13.2.2
Receive Data Register (RDR)
RDR is the register that stores received serial data.
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
When the SCI finishes receiving 1 byte of serial data, it transfers the received data from RSR into
RDR for storage. RSR is then ready to receive the next data. This double buffering allows data to
be received continuously.
RDR is a read-only register. Its contents cannot be modified by the CPU. RDR is initialized to
H'00 by a reset and in standby mode.
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Section 13 Serial Communication Interface
13.2.3
Transmit Shift Register (TSR)
TSR is the register that transmits serial data.
Bit
7
6
5
4
3
2
1
0
Read/Write
—
—
—
—
—
—
—
—
The SCI loads transmit data from TDR into TSR, then transmits the data serially from the TxD
pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next
transmit data from TDR into TSR and starts transmitting it. If the TDRE flag is set to 1 in SSR,
however, the SCI does not load the TDR contents into TSR. The CPU cannot read or write TSR
directly.
13.2.4
Transmit Data Register (TDR)
TDR is an 8-bit register that stores data for serial transmission.
Bit
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
When the SCI detects that TSR is empty, it moves transmit data written in TDR from TDR into
TSR and starts serial transmission. Continuous serial transmission is possible by writing the next
transmit data in TDR during serial transmission from TSR.
The CPU can always read and write TDR. TDR is initialized to H'FF by a reset and in standby
mode.
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Section 13 Serial Communication Interface
13.2.5
Serial Mode Register (SMR)
SMR is an 8-bit register that specifies the SCI serial communication format and selects the clock
source for the baud rate generator.
Bit
7
6
5
4
3
2
1
0
C/A
CHR
PE
O/E
STOP
MP
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock select 1/0
These bits select the
baud rate generator’s
clock source
Multiprocessor mode
Selects the multiprocessor
function
Stop bit length
Selects the stop bit length
Parity mode
Selects even or odd parity
Parity enable
Selects whether a parity bit is added
Character length
Selects character length in asynchronous mode
Communication mode
Selects asynchronous or synchronous mode
The CPU can always read and write SMR. SMR is initialized to H'00 by a reset and in standby
mode.
Bit 7—Communication Mode (C/A
A): Selects whether the SCI operates in asynchronous or
synchronous mode.
Bit 7: C/A
A
Description
0
Asynchronous mode
1
Synchronous mode
(Initial value)
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Section 13 Serial Communication Interface
Bit 6—Character Length (CHR): Selects 7-bit or 8-bit data length in asynchronous mode. In
synchronous mode the data length is 8 bits regardless of the CHR setting.
Bit 6: CHR
Description
0
8-bit data
1
7-bit data*
(Initial value)
Note: * When 7-bit data is selected, the MSB (bit 7) in TDR is not transmitted.
Bit 5—Parity Enable (PE): In asynchronous mode, this bit enables or disables the addition of a
parity bit to transmit data, and the checking of the parity bit in receive data. In synchronous mode
the parity bit is neither added nor checked, regardless of the PE setting.
Bit 5: PE
Description
0
Parity bit not added or checked
1
Parity bit added and checked*
(Initial value)
Note: * When PE is set to 1, an even or odd parity bit is added to transmit data according to the
even or odd parity mode selected by the O/E bit, and the parity bit in receive data is
checked to see that it matches the even or odd mode selected by the O/E bit.
Bit 4—Parity Mode (O/E
E): Selects even or odd parity. The O/E bit setting is valid in
asynchronous mode when the PE bit is set to 1 to enable the adding and checking of a parity bit.
The O/E setting is ignored in synchronous mode, or when parity adding and checking is disabled
in asynchronous mode.
Bit 4: O/E
E
Description
0
Even parity*
1
Odd parity*
1
(Initial value)
2
Notes: 1. When even parity is selected, the parity bit added to transmit data makes an even
number of 1s in the transmitted character and parity bit combined. Receive data must
have an even number of 1s in the received character and parity bit combined.
2. When odd parity is selected, the parity bit added to transmit data makes an odd number
of 1s in the transmitted character and parity bit combined. Receive data must have an
odd number of 1s in the received character and parity bit combined.
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Section 13 Serial Communication Interface
Bit 3—Stop Bit Length (STOP): Selects one or two stop bits in asynchronous mode. This setting
is used only in asynchronous mode. In synchronous mode no stop bit is added, so the STOP bit
setting is ignored.
Bit 3: STOP
Description
0
One stop bit*
1
1
(Initial value)
2
Two stop bits*
Notes: 1. One stop bit (with value 1) is added at the end of each transmitted character.
2. Two stop bits (with value 1) are added at the end of each transmitted character.
In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1 it is treated as a stop bit. If the second stop bit is 0 it is treated as the start bit of the
next incoming character.
Bit 2—Multiprocessor Mode (MP): Selects a multiprocessor format. When a multiprocessor
format is selected, parity settings made by the PE and O/E bits are ignored. The MP bit setting is
valid only in asynchronous mode. It is ignored in synchronous mode.
For further information on the multiprocessor communication function, see section 13.3.3,
Multiprocessor Communication.
Bit 2: MP
Description
0
Multiprocessor function disabled
1
Multiprocessor format selected
(Initial value)
Bits 1 and 0—Clock Select 1 and 0 (CKS1/0): These bits select the clock source of the on-chip
baud rate generator. Four clock sources are available: φ, φ/4, φ/16, and φ/64.
For the relationship between the clock source, bit rate register setting, and baud rate, see section
13.2.8, Bit Rate Register (BRR).
Bit 1: CKS1
Bit 0: CKS0
Description
0
0
φ
1
φ/4
0
φ/16
1
φ/64
1
(Initial value)
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Section 13 Serial Communication Interface
13.2.6
Serial Control Register (SCR)
SCR enables the SCI transmitter and receiver, enables or disables serial clock output in
asynchronous mode, enables or disables interrupts, and selects the transmit/receive clock source.
Bit
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock enable 1/0
These bits select the
SCI clock source
Transmit-end interrupt enable
Enables or disables transmitend interrupts (TEI)
Multiprocessor interrupt enable
Enables or disables multiprocessor
interrupts
Receive enable
Enables or disables the receiver
Transmit enable
Enables or disables the transmitter
Receive interrupt enable
Enables or disables receive-data-full interrupts (RXI) and
receive-error interrupts (ERI)
Transmit interrupt enable
Enables or disables transmit-data-empty interrupts (TXI)
The CPU can always read and write SCR. SCR is initialized to H'00 by a reset and in standby
mode.
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Section 13 Serial Communication Interface
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt
(TXI) requested when the TDRE flag in SSR is set to 1 due to transfer of serial transmit data from
TDR to TSR.
Bit 7: TIE
Description
0
Transmit-data-empty interrupt request (TXI) is disabled*
1
Transmit-data-empty interrupt request (TXI) is enabled
(Initial value)
Note: * TXI interrupt requests can be cleared by reading the value 1 from the TDRE flag, then
clearing it to 0; or by clearing the TIE bit to 0.
Bit 6—Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt (RXI)
requested when the RDRF flag is set to 1 in SSR due to transfer of serial receive data from RSR to
RDR; also enables or disables the receive-error interrupt (ERI).
Bit 6: RIE
Description
0
Receive-data-full (RXI) and receive-error (ERI) interrupt requests are disabled*
(Initial value)
1
Receive-data-full (RXI) and receive-error (ERI) interrupt requests are enabled
Note: * RXI and ERI interrupt requests can be cleared by reading the value 1 from the RDRF, FER,
PER, or ORER flag, then clearing it to 0; or by clearing the RIE bit to 0.
Bit 5—Transmit Enable (TE): Enables or disables the start of SCI serial transmitting operations.
Bit 5: TE
Description
0
Transmitting disabled*
1
2
Transmitting enabled*
1
(Initial value)
Notes: 1. The TDRE bit is locked at 1 in SSR.
2. In the enabled state, serial transmitting starts when the TDRE bit in SSR is cleared to 0
after writing of transmit data into TDR. Select the transmit format in SMR before setting
the TE bit to 1.
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Section 13 Serial Communication Interface
Bit 4—Receive Enable (RE): Enables or disables the start of SCI serial receiving operations.
Bit 4: RE
Description
0
Receiving disabled*
1
2
1
(Initial value)
Receiving enabled*
Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags. These
flags retain their previous values.
2. In the enabled state, serial receiving starts when a start bit is detected in asynchronous
mode, or serial clock input is detected in synchronous mode. Select the receive format
in SMR before setting the RE bit to 1.
Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.
The MPIE setting is valid only in asynchronous mode, and only if the MP bit is set to 1 in SMR.
The MPIE setting is ignored in synchronous mode or when the MP bit is cleared to 0.
Bit 3: MPIE
Description
0
Multiprocessor interrupts are disabled (normal receive operation) (Initial value)
[Clearing conditions]
The MPIE bit is cleared to 0.
MPB = 1 in received data.
1
Multiprocessor interrupts are enabled*
Receive-data-full interrupts (RXI), receive-error interrupts (ERI), and setting of
the RDRF, FER, and ORER status flags in SSR are disabled until data with the
multiprocessor bit set to 1 is received.
Note: * The SCI does not transfer receive data from RSR to RDR, does not detect receive errors,
and does not set the RDRF, FER, and ORER flags in SSR. When it receives data in which
MPB = 1, the SCI sets the MPB bit to 1 in SSR, automatically clears the MPIE bit to 0,
enables RXI and ERI interrupts (if the RIE bit is set to 1 in SCR), and allows the FER and
ORER flags to be set.
Bit 2—Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt
(TEI) requested if TDR does not contain new transmit data when the MSB is transmitted.
Bit 2: TEIE
Description
0
Transmit-end interrupt requests (TEI) are disabled*
1
Transmit-end interrupt requests (TEI) are enabled*
(Initial value)
Note: * TEI interrupt requests can be cleared by reading the value 1 from the TDRE flag in SSR,
then clearing the TDRE flag to 0, thereby also clearing the TEND flag to 0; or by clearing
the TEIE bit to 0.
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Section 13 Serial Communication Interface
Bits 1 and 0—Clock Enable 1 and 0 (CKE1/0): These bits select the SCI clock source and
enable or disable clock output from the SCK pin. Depending on the settings of CKE1 and CKE0,
the SCK pin can be used for generic input/output, serial clock output, or serial clock input.
The CKE0 setting is valid only in asynchronous mode, and only when the SCI is internally
clocked (CKE1 = 0). The CKE0 setting is ignored in synchronous mode, or when an external
clock source is selected (CKE1 = 1). Select the SCI operating mode in SMR before setting the
CKE1 and CKE0 bits. For further details on selection of the SCI clock source, see table 13.9 in
section 13.3, Operation.
Bit 1:
CKE1
Bit 0:
CKE0
Description
0
0
Asynchronous mode
Internal clock, SCK pin available for generic
1
input/output *
Synchronous mode
Internal clock, SCK pin used for serial clock output *
Asynchronous mode
Internal clock, SCK pin used for clock output*
Synchronous mode
Internal clock, SCK pin used for serial clock output
0
Asynchronous mode
External clock, SCK pin used for clock input *
Synchronous mode
External clock, SCK pin used for serial clock input
1
Asynchronous mode
External clock, SCK pin used for clock input *
Synchronous mode
External clock, SCK pin used for serial clock input
1
1
1
2
3
3
Notes: 1. Initial value
2. The output clock frequency is the same as the bit rate.
3. The input clock frequency is 16 times the bit rate.
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Section 13 Serial Communication Interface
13.2.7
Serial Status Register (SSR)
SSR is an 8-bit register containing multiprocessor bit values, and status flags that indicate SCI
operating status.
Bit
7
6
5
4
3
2
1
0
TDRE
RDRF
ORER
FER
PER
TEND
MPB
MPBT
Initial value
1
0
0
0
0
1
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R
R
R/W
Multiprocessor
bit transfer
Value of multiprocessor bit to
be transmitted
Multiprocessor bit
Stores the received
multiprocessor bit value
Transmit end
Status flag indicating end of
transmission
Parity error
Status flag indicating detection of
a receive parity error
Framing error
Status flag indicating detection of a receive
framing error
Overrun error
Status flag indicating detection of a receive overrun error
Receive data register full
Status flag indicating that data has been received and stored in RDR
Transmit data register empty
Status flag indicating that transmit data has been transferred from TDR into
TSR and new data can be written in TDR
Note: * Only 0 can be written, to clear the flag.
The CPU can always read and write SSR, but cannot write 1 in the TDRE, RDRF, ORER, PER,
and FER flags. These flags can be cleared to 0 only if they have first been read while set to 1. The
TEND and MPB flags are read-only bits that cannot be written.
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Section 13 Serial Communication Interface
SSR is initialized to H'84 by a reset and in standby mode.
Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data
from TDR into TSR and the next serial transmit data can be written in TDR.
Bit 7: TDRE
Description
0
TDR contains valid transmit data
[Clearing conditions]
Software reads TDRE while it is set to 1, then writes 0.
The DMAC writes data in TDR.
1
TDR does not contain valid transmit data
(Initial value)
[Setting conditions]
The chip is reset or enters standby mode.
The TE bit in SCR is cleared to 0.
TDR contents are loaded into TSR, so new data can be written in TDR.
Bit 6—Receive Data Register Full (RDRF): Indicates that RDR contains new receive data.
Bit 6: RDRF
Description
0
RDR does not contain new receive data
(Initial value)
[Clearing conditions]
The chip is reset or enters standby mode.
Software reads RDRF while it is set to 1, then writes 0.
The DMAC reads data from RDR.
1
RDR contains new receive data
[Setting condition]
When serial data is received normally and transferred from RSR to RDR.
Note: The RDR contents and RDRF flag are not affected by detection of receive errors or by
clearing of the RE bit to 0 in SCR. They retain their previous values. If the RDRF flag is still
set to 1 when reception of the next data ends, an overrun error occurs and receive data is
lost.
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Section 13 Serial Communication Interface
Bit 5—Overrun Error (ORER): Indicates that data reception ended abnormally due to an
overrun error.
Bit 5: ORER
Description
0
Receiving is in progress or has ended normally
1
(Initial value)*
[Clearing conditions]
The chip is reset or enters standby mode.
Software reads ORER while it is set to 1, then writes 0.
1
2
A receive overrun error occurred*
[Setting condition]
Reception of the next serial data ends when RDRF = 1.
Notes: 1. Clearing the RE bit to 0 in SCR does not affect the ORER flag, which retains its
previous value.
2. RDR continues to hold the receive data before the overrun error, so subsequent receive
data is lost. Serial receiving cannot continue while the ORER flag is set to 1. In
synchronous mode, serial transmitting is also disabled.
Bit 4—Framing Error (FER): Indicates that data reception ended abnormally due to a framing
error in asynchronous mode.
Bit 4: FER
Description
0
Receiving is in progress or has ended normally
1
(Initial value)*
[Clearing conditions]
The chip is reset or enters standby mode.
Software reads FER while it is set to 1, then writes 0.
1
2
A receive framing error occurred*
[Setting condition]
The stop bit at the end of receive data is checked and found to be 0.
Notes: 1. Clearing the RE bit to 0 in SCR does not affect the FER flag, which retains its previous
value.
2. When the stop bit length is 2 bits, only the first bit is checked. The second stop bit is not
checked. When a framing error occurs the SCI transfers the receive data into RDR but
does not set the RDRF flag. Serial receiving cannot continue while the FER flag is set
to 1. In synchronous mode, serial transmitting is also disabled.
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Section 13 Serial Communication Interface
Bit 3—Parity Error (PER): Indicates that data reception ended abnormally due to a parity error
in asynchronous mode.
Bit 3: PER
Description
0
Receiving is in progress or has ended normally*
1
(Initial value)
[Clearing conditions]
The chip is reset or enters standby mode.
Software reads PER while it is set to 1, then writes 0.
1
2
A receive parity error occurred*
[Setting condition]
The number of 1s in receive data, including the parity bit, does not match the
even or odd parity setting of O/E in SMR.
Notes: 1. Clearing the RE bit to 0 in SCR does not affect the PER flag, which retains its previous
value.
2. When a parity error occurs the SCI transfers the receive data into RDR but does not set
the RDRF flag. Serial receiving cannot continue while the PER flag is set to 1. In
synchronous mode, serial transmitting is also disabled.
Bit 2—Transmit End (TEND): Indicates that when the last bit of a serial character was
transmitted TDR did not contain new transmit data, so transmission has ended. The TEND flag is
a read-only bit and cannot be written.
Bit 2: TEND
Description
0
Transmission is in progress
[Clearing conditions]
Software reads TDRE while it is set to 1, then writes 0 in the TDRE flag.
The DMAC writes data in TDR.
1
End of transmission
(Initial value)
[Setting conditions]
The chip is reset or enters standby mode.
The TE bit is cleared to 0 in SCR.
TDRE is 1 when the last bit of a serial character is transmitted.
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Section 13 Serial Communication Interface
Bit 1—Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in receive data
when a multiprocessor format is used in asynchronous mode. MPB is a read-only bit and cannot
be written.
Bit 1: MPB
Description
0
Multiprocessor bit value in receive data is 0*
1
Multiprocessor bit value in receive data is 1
(Initial value)
Note: * If the RE bit is cleared to 0 when a multiprocessor format is selected, MPB retains its
previous value.
Bit 0—Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to
transmit data when a multiprocessor format is selected for transmitting in asynchronous mode.
The MPBT setting is ignored in synchronous mode, when a multiprocessor format is not selected,
or when the SCI is not transmitting.
Bit 0: MPBT
Description
0
Multiprocessor bit value in transmit data is 0
1
Multiprocessor bit value in transmit data is 1
13.2.8
(Initial value)
Bit Rate Register (BRR)
BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in SMR that select the baud
rate generator clock source, determines the serial communication bit rate.
Bit
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The CPU can always read and write BRR. BRR is initialized to H'FF by a reset and in standby
mode. The two SCI channels have independent baud rate generator control, so different values can
be set in the two channels.
Table 13.3 shows examples of BRR settings in asynchronous mode. Table 13.4 shows examples of
BRR settings in synchronous mode.
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Section 13 Serial Communication Interface
Table 13.3 Examples of Bit Rates and BRR Settings in Asynchronous Mode
φ (MHz)
2
2.097152
2.4576
3
Bit Rate
(bits/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
1
141
0.03
1
148
–0.04
1
174
–0.26
1
212
0.03
150
1
103
0.16
1
108
0.21
1
127
0.00
1
155
0.16
300
0
207
0.16
0
217
0.21
0
255
0.00
1
77
0.16
600
0
103
0.16
0
108
0.21
0
127
0.00
0
155
0.16
1200
0
51
0.16
0
54
–0.70
0
63
0.00
0
77
0.16
2400
0
25
0.16
0
26
1.14
0
31
0.00
0
38
0.16
4800
0
12
0.16
0
13
–2.48
0
15
0.00
0
19
–2.34
9600
0
6
–6.99
0
6
–2.48
0
7
0.00
0
9
–2.34
19200
0
2
8.51
0
2
13.78
0
3
0.00
0
4
–2.34
31250
0
1
0.00
0
1
4.86
0
1
22.88
0
2
0.00
38400
0
1
–18.62
0
1
–14.67
0
1
0.00
—
—
—
φ (MHz)
3.6864
4
4.9152
5
Bit Rate
(bits/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
64
0.70
2
70
0.03
2
86
0.31
2
88
–0.25
150
1
191
0.00
1
207
0.16
1
255
0.00
2
64
0.16
300
1
95
0.00
1
103
0.16
1
127
0.00
1
129
0.16
600
0
191
0.00
0
207
0.16
0
255
0.00
1
64
0.16
1200
0
95
0.00
0
103
0.16
0
127
0.00
0
129
0.16
2400
0
47
0.00
0
51
0.16
0
63
0.00
0
64
0.16
4800
0
23
0.00
0
25
0.16
0
31
0.00
0
32
–1.36
9600
0
11
0.00
0
12
0.16
0
15
0.00
0
15
1.73
19200
0
5
0.00
0
6
–6.99
0
7
0.00
0
7
1.73
31250
—
—
—
0
3
0.00
0
4
–1.70
0
4
0.00
38400
0
2
0.00
0
2
8.51
0
3
0.00
0
3
1.73
Rev. 7.00 Sep 21, 2005 page 469 of 878
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Section 13 Serial Communication Interface
φ (MHz)
6
6.144
7.3728
8
Bit Rate
(bits/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
106
–0.44
2
108
0.08
2
130
–0.07
2
141
0.03
150
2
77
0.16
2
79
0.00
2
95
0.00
2
103
0.16
300
1
155
0.16
1
159
0.00
1
191
0.00
1
207
0.16
600
1
77
0.16
1
79
0.00
1
95
0.00
1
103
0.16
1200
0
155
0.16
0
159
0.00
0
191
0.00
0
207
0.16
2400
0
77
0.16
0
79
0.00
0
95
0.00
0
103
0.16
4800
0
38
0.16
0
39
0.00
0
47
0.00
0
51
0.16
9600
0
19
–2.34
0
19
0.00
0
23
0.00
0
25
0.16
19200
0
9
–2.34
0
9
0.00
0
11
0.00
0
12
0.16
31250
0
5
0.00
0
5
2.40
0
6
5.33
0
7
0.00
38400
0
4
–2.34
0
4
0.00
0
5
0.00
0
6
–6.99
φ (MHz)
9.8304
10
12
12.288
Bit Rate
(bits/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
174
–0.26
2
177
–0.25
2
212
0.03
2
217
0.08
150
2
127
0.00
2
129
0.16
2
155
0.16
2
159
0.00
300
1
255
0.00
2
64
0.16
2
77
0.16
2
79
0.00
600
1
127
0.00
1
129
0.16
1
155
0.16
1
159
0.00
1200
0
255
0.00
1
64
0.16
1
77
0.16
1
79
0.00
2400
0
127
0.00
0
129
0.16
0
155
0.16
0
159
0.00
4800
0
63
0.00
0
64
0.16
0
77
0.16
0
79
0.00
9600
0
31
0.00
0
32
–1.36
0
38
0.16
0
39
0.00
19200
0
15
0.00
0
15
1.73
0
19
–2.34
0
19
0.00
31250
0
9
–1.70
0
9
0.00
0
11
0.00
0
11
2.40
38400
0
7
0.00
0
7
1.73
0
9
–2.34
0
9
0.00
Rev. 7.00 Sep 21, 2005 page 470 of 878
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Section 13 Serial Communication Interface
φ (MHz)
13
14
14.7456
16
Bit Rate
(bits/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
230
–0.08
2
248
–0.17
3
64
0.70
3
70
0.03
150
2
168
0.16
2
181
0.16
2
191
0.00
2
207
0.16
300
2
84
–0.43
2
90
0.16
2
95
0.00
2
103
0.16
600
1
168
0.16
1
181
0.16
1
191
0.00
1
207
0.16
1200
1
84
–0.43
1
90
0.16
1
95
0.00
1
103
0.16
2400
0
168
0.16
0
181
0.16
0
191
0.00
0
207
0.16
4800
0
84
–0.43
0
90
0.16
0
95
0.00
0
103
0.16
9600
0
41
0.76
0
45
–0.93
0
47
0.00
0
51
0.16
19200
0
20
0.76
0
22
–0.93
0
23
0.00
0
25
0.16
31250
0
12
0.00
0
13
0.00
0
14
–1.70
0
15
0.00
38400
0
10
–3.82
0
10
3.57
0
11
0.00
0
12
0.16
n
N
Error
(%)
φ (MHz)
18
Bit Rate
(bits/s)
n
N
Error
(%)
110
3
79
–0.12
150
2
233
0.16
300
2
116
0.16
600
1
233
0.16
1200
1
116
0.16
2400
0
233
0.16
4800
0
116
0.16
9600
0
58
–0.69
19200
0
28
1.02
31250
0
17
0.00
38400
0
14
–2.34
Rev. 7.00 Sep 21, 2005 page 471 of 878
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Section 13 Serial Communication Interface
Table 13.4 Examples of Bit Rates and BRR Settings in Synchronous Mode
φ (MHz)
2
4
8
10
13
16
18
Bit Rate
(bits/s)
n
N
n
N
n
N
n
N
n
N
n
N
n
N
110
3
70
—
—
—
—
—
—
—
—
—
—
—
—
250
2
124
2
249
3
124
—
—
3
202
3
249
—
—
500
1
249
2
124
2
249
—
—
3
101
3
124
3
140
1k
1
124
1
249
2
124
—
—
2
202
2
249
3
69
2.5 k
0
199
1
99
1
199
1
249
2
80
2
99
2
112
5k
0
99
0
199
1
99
1
124
1
162
1
199
1
224
10 k
0
49
0
99
0
199
0
249
1
80
1
99
1
112
25 k
0
19
0
39
0
79
0
99
0
129
0
159
0
179
50 k
0
9
0
19
0
39
0
49
0
64
0
79
0
89
100 k
0
4
0
9
0
19
0
24
—
—
0
39
0
44
250 k
0
1
0
3
0
7
0
9
0
12
0
15
0
17
500 k
0
0*
0
1
0
3
0
4
—
—
0
7
0
8
0
0*
1M
0
1
—
—
—
—
0
3
0
4
2M
0
0*
—
—
—
—
0
1
—
—
2.5 M
—
—
0
0*
—
—
—
—
—
—
0
0*
—
—
4M
Note: Settings with an error of 1% or less are recommended.
Legend
Blank: No setting available
—:
Setting possible, but error occurs
*:
Continuous transmit/receive not possible
Rev. 7.00 Sep 21, 2005 page 472 of 878
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Section 13 Serial Communication Interface
The BRR setting is calculated as follows:
Asynchronous mode:
N=
φ
64 ×
22n–1
×B
× 106 – 1
Synchronous mode:
N=
B:
N:
φ:
n:
φ
8 × 22n–1 × B
× 106 – 1
Bit rate (bits/s)
BRR setting for baud rate generator (0 ≤ N ≤ 255)
System clock frequency (MHz)
Baud rate generator clock source (n = 0, 1, 2, 3)
(For the clock sources and values of n, see the following table.)
SMR Settings
n
Clock Source
CKS1
CKS0
0
φ
0
0
1
φ/4
0
1
2
φ/16
1
0
3
φ/64
1
1
The bit rate error in asynchronous mode is calculated as follows.
Error (%) =
φ × 106
(N + 1) × B × 64 × 22n–1
– 1 × 100
Rev. 7.00 Sep 21, 2005 page 473 of 878
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Section 13 Serial Communication Interface
Table 13.5 indicates the maximum bit rates in asynchronous mode for various system clock
frequencies. Tables 13.6 and 13.7 indicate the maximum bit rates with external clock input.
Table 13.5 Maximum Bit Rates for Various Frequencies (Asynchronous Mode)
Settings
φ (MHz)
Maximum Bit Rate (bits/s)
n
N
2
62500
0
0
2.097152
65536
0
0
2.4576
76800
0
0
3
93750
0
0
3.6864
115200
0
0
4
125000
0
0
4.9152
153600
0
0
5
156250
0
0
6
187500
0
0
6.144
192000
0
0
7.3728
230400
0
0
8
250000
0
0
9.8304
307200
0
0
10
312500
0
0
12
375000
0
0
12.288
384000
0
0
14
437500
0
0
14.7456
460800
0
0
16
500000
0
0
17.2032
537600
0
0
18
562500
0
0
Rev. 7.00 Sep 21, 2005 page 474 of 878
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Section 13 Serial Communication Interface
Table 13.6 Maximum Bit Rates with External Clock Input (Asynchronous Mode)
φ (MHz)
External Input Clock (MHz)
Maximum Bit Rate (bits/s)
2
0.5000
31250
2.097152
0.5243
32768
2.4576
0.6144
38400
3
0.7500
46875
3.6864
0.9216
57600
4
1.0000
62500
4.9152
1.2288
76800
5
1.2500
78125
6
1.5000
93750
6.144
1.5360
96000
7.3728
1.8432
115200
8
2.0000
125000
9.8304
2.4576
153600
10
2.5000
156250
12
3.0000
187500
12.288
3.0720
192000
14
3.5000
218750
14.7456
3.6864
230400
16
4.0000
250000
17.2032
4.3008
268800
18
4.5000
281250
Table 13.7 Maximum Bit Rates with External Clock Input (Synchronous Mode)
φ (MHz)
External Input Clock (MHz)
Maximum Bit Rate (bits/s)
2
0.3333
333333.3
4
0.6667
666666.7
6
1.0000
1000000.0
8
1.3333
1333333.3
10
1.6667
1666666.7
12
2.0000
2000000.0
14
2.3333
2333333.3
16
2.6667
2666666.7
18
3.0000
3000000.0
Rev. 7.00 Sep 21, 2005 page 475 of 878
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Section 13 Serial Communication Interface
13.3
Operation
13.3.1
Overview
The SCI has an asynchronous mode in which characters are synchronized individually, and a
synchronous mode in which communication is synchronized with clock pulses. Serial
communication is possible in either mode. Asynchronous or synchronous mode and the
communication format are selected in SMR, as shown in table 13.8. The SCI clock source is
selected by the C/A bit in SMR and the CKE1 and CKE0 bits in SCR, as shown in table 13.9.
Asynchronous Mode
• Data length is selectable: 7 or 8 bits.
• Parity and multiprocessor bits are selectable. So is the stop bit length (1 or 2 bits). These
selections determine the communication format and character length.
• In receiving, it is possible to detect framing errors, parity errors, overrun errors, and the break
state.
• An internal or external clock can be selected as the SCI clock source.
When an internal clock is selected, the SCI operates using the on-chip baud rate generator,
and can output a serial clock signal with a frequency matching the bit rate.
When an external clock is selected, the external clock input must have a frequency 16 times
the bit rate. (The on-chip baud rate generator is not used.)
Synchronous Mode
• The communication format has a fixed 8-bit data length.
• In receiving, it is possible to detect overrun errors.
• An internal or external clock can be selected as the SCI clock source.
When an internal clock is selected, the SCI operates using the on-chip baud rate generator,
and outputs a serial clock signal to external devices.
When an external clock is selected, the SCI operates on the input serial clock. The on-chip
baud rate generator is not used.
Rev. 7.00 Sep 21, 2005 page 476 of 878
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Section 13 Serial Communication Interface
Table 13.8 SMR Settings and Serial Communication Formats
SMR Settings
SCI Communication Format
Bit 7: Bit 6: Bit 2: Bit 5: Bit 3:
C/A
A
CHR MP
PE
STOP Mode
0
0
0
0
Asynchronous
mode
0
1
1
Data
Length
Multiprocessor Parity
Bit
Bit
Stop
Bit
Length
8-bit data
Absent
1 bit
Absent
2 bits
0
Present
1
1
0
2 bits
0
7-bit data
Absent
1
1
1
—
0
Present
0
0
Asynchronous
mode (multiprocessor
format)
8-bit data
Synchronous
mode
8-bit data
Present
Absent
—
—
—
1 bit
2 bits
7-bit data
1 bit
1
1
1 bit
2 bits
1
1
1 bit
2 bits
1
0
1 bit
2 bits
—
Absent
None
Table 13.9 SMR and SCR Settings and SCI Clock Source Selection
SMR
SCR Settings
Bit 7:
C/A
A
Bit 1:
CKE1
Bit 0:
CKE0
0
0
0
1
1
SCI Transmit/Receive Clock
Mode
Asynchronous
mode
0
Clock
Source
SCK Pin Function
Internal
SCI does not use the SCK pin
Outputs a clock with frequency
matching the bit rate
External
Inputs a clock with frequency 16
times the bit rate
Internal
Outputs the serial clock
External
Inputs the serial clock
1
1
0
0
1
0
1
Synchronous
mode
1
Rev. 7.00 Sep 21, 2005 page 477 of 878
REJ09B0259-0700
Section 13 Serial Communication Interface
13.3.2
Operation in Asynchronous Mode
In asynchronous mode each transmitted or received character begins with a start bit and ends with
a stop bit. Serial communication is synchronized one character at a time.
The transmitting and receiving sections of the SCI are independent, so full duplex communication
is possible. The transmitter and receiver are both double buffered, so data can be written and read
while transmitting and receiving are in progress, enabling continuous transmitting and receiving.
Figure 13.2 shows the general format of asynchronous serial communication. In asynchronous
serial communication the communication line is normally held in the mark (high) state. The SCI
monitors the line and starts serial communication when the line goes to the space (low) state,
indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit
(high or low), and stop bit (high), in that order.
When receiving in asynchronous mode, the SCI synchronizes at the falling edge of the start bit.
The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate.
Receive data is latched at the center of each bit.
1
Serial data
(LSB)
0
D0
Idle (mark) state
1
(MSB)
D1
D2
D3
D4
D5
Start
bit
Transmit or receive data
1 bit
7 bits or 8 bits
D6
D7
0/1
Parity
bit
1
Stop
bit
1 bit or 1 bit or
no bit 2 bits
One unit of data (character or frame)
Figure 13.2 Data Format in Asynchronous Communication
(Example: 8-Bit Data with Parity and 2 Stop Bits)
Rev. 7.00 Sep 21, 2005 page 478 of 878
REJ09B0259-0700
1
Section 13 Serial Communication Interface
Communication Formats: Table 13.10 shows the 12 communication formats that can be selected
in asynchronous mode. The format is selected by settings in SMR.
Table 13.10 Serial Communication Formats (Asynchronous Mode)
SMR Settings
Serial Communication Format and Frame Length
CHR
PE
MP
STOP
1
2
3
4
5
6
7
8
9
10
11
12
0
0
0
0
S
8-bit data
STOP
0
0
0
1
S
8-bit data
STOP STOP
0
1
0
0
S
8-bit data
P
STOP
0
1
0
1
S
8-bit data
P
STOP STOP
1
0
0
0
S
7-bit data
STOP
1
0
0
1
S
7-bit data
STOP STOP
1
1
0
0
S
7-bit data
P
STOP
1
1
0
1
S
7-bit data
P
STOP STOP
0
—
1
0
S
8-bit data
MPB STOP
0
—
1
1
S
8-bit data
MPB STOP STOP
1
—
1
0
S
7-bit data
MPB STOP
1
—
1
1
S
7-bit data
MPB STOP STOP
Legend
S:
Start bit
STOP: Stop bit
P:
Parity bit
MPB: Multiprocessor bit
Rev. 7.00 Sep 21, 2005 page 479 of 878
REJ09B0259-0700
Section 13 Serial Communication Interface
Clock: An internal clock generated by the on-chip baud rate generator or an external clock input
from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected
by the C/A bit in SMR and bits CKE1 and CKE0 in SCR. See table 13.9.
When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the
desired bit rate.
When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The
frequency of this output clock is equal to the bit rate. The phase is aligned as in figure 13.3 so that
the rising edge of the clock occurs at the center of each transmit data bit.
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1 frame
Figure 13.3 Phase Relationship between Output Clock and Serial Data
(Asynchronous Mode)
Transmitting and Receiving Data
• SCI Initialization (Asynchronous Mode)
Before transmitting or receiving, clear the TE and RE bits to 0 in SCR, then initialize the SCI
as follows.
When changing the communication mode or format, always clear the TE and RE bits to 0
before following the procedure given below. Clearing TE to 0 sets the TDRE flag to 1 and
initializes TSR. Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and
ORER flags and RDR, which retain their previous contents.
When an external clock is used, the clock should not be stopped during initialization or
subsequent operation. SCI operation becomes unreliable if the clock is stopped.
Figure 13.4 is a sample flowchart for initializing the SCI.
Rev. 7.00 Sep 21, 2005 page 480 of 878
REJ09B0259-0700
Section 13 Serial Communication Interface
Start of initialization
Clear TE and RE bits
to 0 in SCR
Set CKE1 and CKE0 bits
in SCR (leaving TE and
RE bits cleared to 0)
1
Select communication
format in SMR
2
Set value in BRR
3
1. Select the clock source in SCR. Clear the RIE, TIE, TEIE,
MPIE, TE, and RE bits to 0. If clock output is selected in
asynchronous mode, clock output starts immediately after
the setting is made in SCR.
2. Select the communication format in SMR.
3. Write the value corresponding to the bit rate in BRR.
This step is not necessary when an external clock is used.
4. Wait for at least the interval required to transmit or receive
1 bit, then set the TE or RE bit to 1 in SCR. Set the RIE,
TIE, TEIE, and MPIE bits as necessary. Setting the TE
or RE bit enables the SCI to use the TxD or RxD pin.
Wait
1 bit interval
elapsed?
No
Yes
Set TE or RE bit to 1 in SCR
Set RIE, TIE, TEIE, and
MPIE bits as necessary
4
Transmitting or receiving
Figure 13.4 Sample Flowchart for SCI Initialization
Rev. 7.00 Sep 21, 2005 page 481 of 878
REJ09B0259-0700
Section 13 Serial Communication Interface
• Transmitting Serial Data (Asynchronous Mode)
Figure 13.5 shows a sample flowchart for transmitting serial data and indicates the procedure
to follow.
1
Initialize
Start transmitting
2
Read TDRE flag in SSR
No
TDRE = 1?
Yes
Write transmit data
in TDR and clear TDRE
flag to 0 in SSR
All data
transmitted?
No
1. SCI initialization: the transmit data output function
of the TxD pin is selected automatically.
2. SCI status check and transmit data write: read SSR,
check that the TDRE flag is 1, then write transmit data
in TDR and clear the TDRE flag to 0.
3. To continue transmitting serial data: after checking
that the TDRE flag is 1, indicating that data can be
written, write data in TDR, then clear the TDRE
flag to 0. When the DMAC is activated by a transmitdata-empty interrupt request (TXI) to write data in TDR,
the TDRE flag is checked and cleared automatically.
4. To output a break signal at the end of serial transmission:
set the DDR bit to 1 and clear the DR bit to 0
(DDR and DR are I/O port registers), then clear the
TE bit to 0 in SCR.
3
Yes
Read TEND flag in SSR
TEND = 1?
No
Yes
Output break
signal?
No
4
Yes
Clear DR bit to 0,
set DDR bit to 1
Clear TE bit to 0 in SCR
End
Figure 13.5 Sample Flowchart for Transmitting Serial Data
Rev. 7.00 Sep 21, 2005 page 482 of 878
REJ09B0259-0700
Section 13 Serial Communication Interface
In transmitting serial data, the SCI operates as follows.
1. The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI
recognizes that TDR contains new data, and loads this data from TDR into TSR.
2. After loading the data from TDR into TSR, the SCI sets the TDRE flag to 1 and starts
transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty
interrupt (TXI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin:
a. Start bit: One 0 bit is output.
b. Transmit data: 7 or 8 bits are output, LSB first.
c. Parity bit or multiprocessor bit: One parity bit (even or odd parity) or one
multiprocessor bit is output. Formats in which neither a parity bit nor a
multiprocessor bit is output can also be selected.
d. Stop bit: One or two 1 bits (stop bits) are output.
e. Mark state: Output of 1 bits continues until the start bit of the next transmit data.
3. The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI
loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of
the next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, outputs the
stop bit, then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR,
a transmit-end interrupt (TEI) is requested at this time.
Figure 13.6 shows an example of SCI transmit operation in asynchronous mode.
1
Start
bit
0
Parity Stop Start
bit
bit
bit
Data
D0
D1
D7
0/1
1
0
Parity Stop
bit
bit
Data
D0
D1
D7
0/1
1
1
Idle (mark)
state
TDRE
TEND
TXI
interrupt
request
TXI interrupt handler
writes data in TDR and
clears TDRE flag to 0
TXI
interrupt
request
TEI interrupt request
1 frame
Figure 13.6 Example of SCI Transmit Operation in Asynchronous Mode
(8-Bit Data with Parity and 1 Stop Bit)
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Section 13 Serial Communication Interface
• Receiving Serial Data (Asynchronous Mode)
Figure 13.7 shows a sample flowchart for receiving serial data and indicates the procedure to
follow.
1
Initialize
Start receiving
Read ORER, PER,
and FER flags in SSR
PER ∨ FER ∨
ORER = 1?
2
Yes
3
No
Error handling
(continued on next page)
Read RDRF flag in SSR
4
No
RDRF = 1?
1. SCI initialization: the receive data function of
the RxD pin is selected automatically.
2, 3. Receive error handling and break
detection: if a receive error occurs, read the
ORER, PER, and FER flags in SSR to identify
the error. After executing the necessary error
handling, clear the ORER, PER, and FER
flags all to 0. Receiving cannot resume if any
of the ORER, PER, and FER flags remains
set to 1. When a framing error occurs, the
RxD pin can be read to detect the break state.
4. SCI status check and receive data read: read
SSR, check that RDRF is set to 1, then read
receive data from RDR and clear the RDRF
flag to 0. Notification that the RDRF flag has
changed from 0 to 1 can also be given by the
RXI interrupt.
5. To continue receiving serial data: check the
RDRF flag, read RDR, and clear the RDRF
flag to 0 before the stop bit of the current
frame is received. If the DMAC is activated
by an RXI interrupt to read the RDR value,
the RDRF flag is cleared automatically.
Yes
Read receive data
from RDR, and clear
RDRF flag to 0 in SSR
No
Finished
receiving?
5
Yes
Clear RE bit to 0 in SCR
End
Figure 13.7 Sample Flowchart for Receiving Serial Data (1)
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Section 13 Serial Communication Interface
3
Error handling
No
ORER = 1?
Yes
Overrun error handling
No
FER = 1?
Yes
Break?
Yes
No
Framing error handling
Clear RE bit to 0 in SCR
No
PER = 1?
Yes
Parity error handling
Clear ORER, PER, and
FER flags to 0 in SSR
End
Figure 13.7 Sample Flowchart for Receiving Serial Data (2)
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Section 13 Serial Communication Interface
In receiving, the SCI operates as follows.
1. The SCI monitors the receive data line. When it detects a start bit, the SCI synchronizes
internally and starts receiving.
2. Receive data is stored in RSR in order from LSB to MSB.
3. The parity bit and stop bit are received.
After receiving, the SCI makes the following checks:
a. Parity check: The number of 1s in the receive data must match the even or odd parity
setting of the O/E bit in SMR.
b. Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first
stop bit is checked.
c. Status check: The RDRF flag must be 0 so that receive data can be transferred from
RSR into RDR.
If these checks all pass, the RDRF flag is set to 1 and the received data is stored in RDR. If
one of the checks fails (receive error), the SCI operates as indicated in table 13.11.
Note: When a receive error occurs, further receiving is disabled. In receiving, the RDRF flag is
not set to 1. Be sure to clear the error flags to 0.
4. When the RDRF flag is set to 1, if the RIE bit is set to 1 in SCR, a receive-data-full
interrupt (RXI) is requested. If the ORER, PER, or FER flag is set to 1 and the RIE bit in
SCR is also set to 1, a receive-error interrupt (ERI) is requested.
Table 13.11 Receive Error Conditions
Receive Error
Abbreviation
Condition
Data Transfer
Overrun error
ORER
Receiving of next data ends
while RDRF flag is still set
to 1 in SSR
Receive data not transferred
from RSR to RDR
Framing error
FER
Stop bit is 0
Receive data transferred from
RSR to RDR
Parity error
PER
Parity of receive data differs
from even/odd parity setting
in SMR
Receive data transferred from
RSR to RDR
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Section 13 Serial Communication Interface
Figure 13.8 shows an example of SCI receive operation in asynchronous mode.
1
Start
bit
0
Parity Stop Start
bit
bit
bit
Data
D0
D1
D7
0/1
1
0
Parity Stop
bit
bit
Data
D0
D1
D7
0/1
1
1
Idle (mark)
state
RDRF
FER
RXI
request
1 frame
RXI interrupt handler
reads data in RDR and
clears RDRF flag to 0
Framing error,
ERI request
Figure 13.8 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit)
13.3.3
Multiprocessor Communication
The multiprocessor communication function enables several processors to share a single serial
communication line. The processors communicate in asynchronous mode using a format with an
additional multiprocessor bit (multiprocessor format).
In multiprocessor communication, each receiving processor is addressed by an ID. A serial
communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a
data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending
cycles.
The transmitting processor starts by sending the ID of the receiving processor with which it wants
to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends
transmit data with the multiprocessor bit cleared to 0.
Receiving processors skip incoming data until they receive data with the multiprocessor bit set
to 1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the
data with their IDs. The receiving processor with a matching ID continues to receive further
incoming data. Processors with IDs not matching the received data skip further incoming data
until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and
receive data in this way.
Figure 13.9 shows an example of communication among different processors using a
multiprocessor format.
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Section 13 Serial Communication Interface
Communication Formats: Four formats are available. Parity-bit settings are ignored when a
multiprocessor format is selected. For details see table 13.10.
Clock: See the description of asynchronous mode.
Transmitting
processor
Serial communication line
Receiving
processor A
Receiving
processor B
Receiving
processor C
Receiving
processor D
(ID = 01)
(ID = 02)
(ID = 03)
(ID = 04)
H'01
Serial data
(MPB = 1)
ID-sending cycle: receiving
processor address
H'AA
(MPB = 0)
Data-sending cycle:
data sent to receiving
processor specified by ID
Legend
MPB: Multiprocessor bit
Figure 13.9 Example of Communication among Processors using Multiprocessor Format
(Sending Data H'AA to Receiving Processor A)
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Section 13 Serial Communication Interface
Transmitting and Receiving Data
• Transmitting Multiprocessor Serial Data
Figure 13.10 shows a sample flowchart for transmitting multiprocessor serial data and
indicates the procedure to follow.
1
Initialize
Start transmitting
2
Read TDRE flag in SSR
TDRE = 1?
No
Yes
Write transmit data in
TDR and set MPBT bit in SSR
Clear TDRE flag to 0
All data transmitted?
No
3
Yes
1. SCI initialization: the transmit data
output function of the TxD pin is
selected automatically.
2. SCI status check and transmit data
write: read SSR, check that the TDRE
flag is 1, then write transmit
data in TDR. Also set the MPBT flag to
0 or 1 in SSR. Finally, clear the TDRE
flag to 0.
3. To continue transmitting serial data:
after checking that the TDRE flag is 1,
indicating that data can be
written, write data in TDR, then clear
the TDRE flag to 0. When the DMAC
is activated by a transmit-data-empty
interrupt request (TXI) to write data in
TDR, the TDRE flag is checked and
cleared automatically.
4. To output a break signal at the end of
serial transmission: set the DDR bit to
1 and clear the DR bit to 0 (DDR and
DR are I/O port registers), then clear
the TE bit to 0 in SCR.
Read TEND flag in SSR
TEND = 1?
No
Yes
Output break signal?
No
4
Yes
Clear DR bit to 0, set DDR bit to 1
Clear TE bit to 0 in SCR
End
Figure 13.10 Sample Flowchart for Transmitting Multiprocessor Serial Data
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Section 13 Serial Communication Interface
In transmitting serial data, the SCI operates as follows.
1. The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI
recognizes that TDR contains new data, and loads this data from TDR into TSR.
2. After loading the data from TDR into TSR, the SCI sets the TDRE flag to 1 and starts
transmitting. If the TIE bit in SCR is set to 1, the SCI requests a transmit-data-empty
interrupt (TXI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin:
a. Start bit: One 0 bit is output.
b. Transmit data: 7 or 8 bits are output, LSB first.
c. Multiprocessor bit: One multiprocessor bit (MPBT value) is output.
d. Stop bit: One or two 1 bits (stop bits) are output.
e. Mark state: Output of 1 bits continues until the start bit of the next transmit data.
3. The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI
loads data from TDR into TSR, outputs the stop bit, then begins serial transmission of the
next frame. If the TDRE flag is 1, the SCI sets the TEND flag in SSR to 1, outputs the stop
bit, then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a
transmit-end interrupt (TEI) is requested at this time.
Figure 13.11 shows an example of SCI transmit operation using a multiprocessor format.
Multiprocessor
bit
1
Start
bit
0
Stop Start
bit
bit
Data
D0
D1
Multiprocessor
bit
D7
0/1
1
0
Stop
bit
Data
D0
D1
D7
0/1
1
TDRE
TEND
TXI
request
TXI interrupt handler
writes data in TDR and
clears TDRE flag to 0
TXI
request
TEI request
1 frame
Figure 13.11 Example of SCI Transmit Operation
(8-Bit Data with Multiprocessor Bit and One Stop Bit)
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1
Idle (mark)
state
Section 13 Serial Communication Interface
• Receiving Multiprocessor Serial Data
Figure 13.12 shows a sample flowchart for receiving multiprocessor serial data and indicates
the procedure to follow.
Initialize
1. SCI initialization: the receive data function
of the RxD pin is selected automatically.
2. ID receive cycle: set the MPIE bit to 1 in SCR.
3. SCI status check and ID check: read SSR,
check that the RDRF flag is set to 1, then read
data from RDR and compare with the
processor’s own ID. If the ID does not match,
set the MPIE bit to 1 again and clear the
RDRF flag to 0. If the ID matches, clear the
RDRF flag to 0.
4. SCI status check and data receiving: read
SSR, check that the RDRF flag is set to 1,
then read data from RDR.
5. Receive error handling and break detection:
if a receive error occurs, read the
ORER and FER flags in SSR to identify the error.
After executing the necessary error handling,
clear the ORER and FER flags both to 0.
Receiving cannot resume while either the ORER
or FER flag remains set to 1. When a framing
error occurs, the RxD pin can be read to detect
the break state.
1
Start receiving
Set MPIE bit to 1 in SCR
2
Read ORER and FER flags in SSR
FER ∨ ORER = 1
Yes
No
Read RDRF flag in SSR
3
No
RDRF = 1?
Yes
Read receive data from RDR
No
Own ID?
Yes
Read ORER and FER flags in SSR
FER ∨ ORER = 1
Yes
No
Read RDRF flag in SSR
4
No
RDRF = 1?
Yes
Read receive data from RDR
No
No
Finished receiving?
Yes
5
Error handling
(continued on next page)
Clear RE bit to 0 in SCR
End
Figure 13.12 Sample Flowchart for Receiving Multiprocessor Serial Data (1)
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Section 13 Serial Communication Interface
5
Error handling
No
ORER = 1?
Yes
Overrun error handling
No
FER = 1?
Yes
Break?
Yes
No
Framing error handling
Clear RE bit to 0 in SCR
Clear ORER, PER, and FER
flags to 0 in SSR
End
Figure 13.12 Sample Flowchart for Receiving Multiprocessor Serial Data (2)
Figure 13.13 shows an example of SCI receive operation using a multiprocessor format.
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Section 13 Serial Communication Interface
1
Start
bit
0
MPB
Data (ID1)
D0
D1
D7
1
Stop Start
Data (data1)
bit
bit
1
D0
0
D1
MPB
D7
0
Stop
bit
1
1
Idle (mark)
state
MPIE
RDRF
RDR value
ID1
RXI request
(multiprocessor
interrupt)
MPB detection
MPIE= 0
RXI handler reads
RDR data and clears
RDRF flag to 0
Not own ID, so
MPIE bit is set
to 1 again
No RXI request,
RDR not updated
a. Own ID does not match data
1
Start
bit
0
MPB
Data (ID2)
D0
D1
D7
1
Stop Start
Data (data2)
bit
bit
1
D0
0
D1
MPB
D7
0
Stop
bit
1
1
Idle (mark)
state
MPIE
RDRF
RDR value
ID2
MPB detection
MPIE= 0
RXI request
(multiprocessor
interrupt)
Data 2
RXI interrupt handler Own ID, so receiving MPIE bit is set
reads RDR data and continues, with data to 1 again
clears RDRF flag to 0 received by RXI
interrupt handler
b. Own ID matches data
Figure 13.13 Example of SCI Receive Operation
(8-Bit Data with Multiprocessor Bit and One Stop Bit)
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Section 13 Serial Communication Interface
13.3.4
Synchronous Operation
In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses.
This mode is suitable for high-speed serial communication.
The SCI transmitter and receiver share the same clock but are otherwise independent, so full
duplex communication is possible. The transmitter and receiver are also double buffered, so
continuous transmitting or receiving is possible by reading or writing data while transmitting or
receiving is in progress.
Figure 13.14 shows the general format in synchronous serial communication.
One unit (character or frame) of serial data
*
*
Serial clock
LSB
Serial data
Bit 0
MSB
Bit 1
Bit 2
Bit 3
Bit 4
Don’t care
Bit 5
Bit 6
Bit 7
Don’t care
Note: * High except in continuous transmitting or receiving
Figure 13.14 Data Format in Synchronous Communication
In synchronous serial communication, each data bit is placed on the communication line from one
falling edge of the serial clock to the next. Data is guaranteed valid at the rise of the serial clock.
In each character, the serial data bits are transmitted in order from LSB (first) to MSB (last). After
output of the MSB, the communication line remains in the state of the MSB. In synchronous mode
the SCI receives data by synchronizing with the rise of the serial clock.
Communication Format: The data length is fixed at 8 bits. No parity bit or multiprocessor bit
can be added.
Clock: An internal clock generated by the on-chip baud rate generator or an external clock input
from the SCK pin can be selected by clearing or setting the CKE1 bit in SCR. See table 13.9.
When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock
pulses are output per transmitted or received character.
When the SCI operates on an internal clock, the serial clock outputs the clock signal at the SCK
pin. Eight clock pulses are output per transmitted or received character. When the SCI is not
transmitting or receiving, the clock signal remains in the high state. However, when receiving
only, overrun error may occur or the serial clock continues output until the RE bit clears at 0.
When transmitting or receiving in single characters, select the external clock.
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Section 13 Serial Communication Interface
Transmitting and Receiving Data
• SCI Initialization (Synchronous Mode)
Before transmitting or receiving, clear the TE and
RE bits to 0 in SCR, then initialize the SCI as follows.
When changing the communication mode or format, always clear the TE and RE bits to 0
before following the procedure given below. Clearing the TE bit to 0 sets the TDRE flag to 1
and initializes TSR. Clearing the RE bit to 0, however, does not initialize the RDRF, PER,
FER, and ORE flags and RDR, which retain their previous contents.
Figure 13.15 is a sample flowchart for initializing the SCI.
Start of initialization
Clear TE and RE
bits to 0 in SCR
Set RIE, TIE, TEIE, MPIE,
CKE1, and CKE0 bits in SCR
(leaving TE and RE bits
cleared to 0)
1
1. Select the clock source in SCR. Clear the RIE, TIE, TEIE,
MPIE, TE, and RE bits to 0.
2. Select the communication format in SMR.
3. Write the value corresponding to the bit rate in BRR.
This step is not necessary when an external clock is used.
4. Wait for at least the interval required to transmit or receive
one bit, then set the TE or RE bit to 1 in SCR. Also set
the RIE, TIE, TEIE, and MPIE bits as necessary.
Setting the TE or RE bit enables the SCI to use the
TxD or RxD pin.
2
Select communication
format in SMR
3
Set value in BRR
Wait
1 bit interval
elapsed?
No
Yes
Set TE or RE to 1 in SCR
Set RIE, TIE, TEIE, and
MPIE bits as necessary
Start transmitting or receiving
4
Note: In simultaneous transmitting and receiving, the TE and
RE bits should be cleared to 0 or set to 1 simultaneously.
Figure 13.15 Sample Flowchart for SCI Initialization
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Section 13 Serial Communication Interface
• Transmitting Serial Data (Synchronous Mode)
Figure 13.16 shows a sample flowchart for transmitting serial data and indicates the procedure
to follow.
1
Initialize
Start transmitting
Read TDRE flag in SSR
2
No
TDRE = 1?
1. SCI initialization: the transmit data output function
of the TxD pin is selected automatically.
2. SCI status check and transmit data write: read SSR,
check that the TDRE flag is 1, then write transmit
data in TDR and clear the TDRE flag to 0.
3. To continue transmitting serial data: after checking
that the TDRE flag is 1, indicating that data can be
written, write data in TDR, then clear the TDRE flag
to 0. When the DMAC is activated by a transmitdata-empty interrupt request (TXI) to write data in
TDR, the TDRE flag is checked and cleared
automatically.
Yes
Write transmit data in
TDR and clear TDRE flag
to 0 in SSR
All data
transmitted?
No
3
Yes
Read TEND flag in SSR
TEND = 1?
No
Yes
Clear TE bit to 0 in SCR
End
Figure 13.16 Sample Flowchart for Serial Transmitting
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Section 13 Serial Communication Interface
In transmitting serial data, the SCI operates as follows.
1. The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI
recognizes that TDR contains new data, and loads this data from TDR into TSR.
2. After loading the data from TDR into TSR, the SCI sets the TDRE flag to 1 and starts
transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty
interrupt (TXI) at this time.
If clock output is selected, the SCI outputs eight serial clock pulses. If an external clock
source is selected, the SCI outputs data in synchronization with the input clock. Data is
output from the TxD pin in order from LSB (bit 0) to MSB (bit 7).
3. The SCI checks the TDRE flag when it outputs the MSB (bit 7). If the TDRE flag is 0, the
SCI loads data from TDR into TSR and begins serial transmission of the next frame. If the
TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, and after transmitting the MSB,
holds the TxD pin in the MSB state. If the TEIE bit in SCR is set to 1, a transmit-end
interrupt (TEI) is requested at this time.
4. After the end of serial transmission, the SCK pin is held in a constant state.
Figure 13.17 shows an example of SCI transmit operation.
Transmit
direction
Serial clock
Serial data
Bit 0
Bit 1
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
TDRE
TEND
TXI
request
TXI interrupt handler
writes data in TDR
and clears TDRE
flag to 0
TXI
request
TEI
request
1 frame
Figure 13.17 Example of SCI Transmit Operation
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Section 13 Serial Communication Interface
• Receiving Serial Data
Figure 13.18 shows a sample flowchart for receiving serial data and indicates the procedure to
follow. When switching from asynchronous mode to synchronous mode, make sure that the
ORER, PER, and FER flags are cleared to 0. If the FER or PER flag is set to 1 the RDRF flag
will not be set and both transmitting and receiving will be disabled.
SCI initialization: the receive data function of
the RxD pin is selected automatically.
2, 3. Receive error handling: if a receive error
Start receiving
occurs, read the ORER flag in SSR, then after
executing the necessary error handling, clear
the ORER flag to 0. Neither transmitting nor
receiving can resume while the ORER flag
Read ORER flag in SSR
2
remains set to 1.
4. SCI status check and receive data read: read
SSR, check that the RDRF flag is set to 1,
Yes
ORER = 1?
then read receive data from RDR and clear
3
the RDRF flag to 0. Notification that the RDRF
Error handling
No
flag has changed from 0 to 1 can also be
given by the RXI interrupt.
continued on next page
5. To continue receiving serial data: check the
Read RDRF flag in SSR
4
RDRF flag, read RDR, and clear the RDRF
flag to 0 before the MSB (bit 7) of the current
frame is received. If the DMAC is activated
No
by a receive-data-full interrupt request (RXI)
RDRF = 1?
to read RDR, the RDRF flag is cleared
automatically.
Yes
No
Initialize
1
Read receive data
from RDR, and clear
RDRF flag to 0 in SSR
5
1.
Finished
receiving?
Yes
Clear RE bit to 0 in SCR
End
Figure 13.18 Sample Flowchart for Serial Receiving (1)
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Section 13 Serial Communication Interface
3
Error handling
Overrun error handling
Clear ORER flag to 0 in SSR
End
Figure 13.18 Sample Flowchart for Serial Receiving (2)
In receiving, the SCI operates as follows.
1. The SCI synchronizes with serial clock input or output and initializes internally.
2. Receive data is stored in RSR in order from LSB to MSB.
After receiving the data, the SCI checks that the RDRF flag is 0 so that receive data can be
transferred from RSR to RDR. If this check passes, the RDRF flag is set to 1 and the
received data is stored in RDR. If the check does not pass (receive error), the SCI operates
as indicated in table 13.11.
3. After setting the RDRF flag to 1, if the RIE bit is set to 1 in SCR, the SCI requests a
receive-data-full interrupt (RXI). If the ORER flag is set to 1 and the RIE bit in SCR is also
set to 1, the SCI requests a receive-error interrupt (ERI).
Figure 13.19 shows an example of SCI receive operation.
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Section 13 Serial Communication Interface
Receive direction
Serial clock
Serial data
Bit 7
Bit 7
Bit 0
Bit 0
Bit 1
Bit 6
Bit 7
RDRF
ORER
RXI
request
RXI interrupt
handler reads
data in RDR
and clears
RDRF flag to 0
RXI
request
Overrun error,
ERI request
1 frame
Figure 13.19 Example of SCI Receive Operation
• Transmitting and Receiving Serial Data Simultaneously (Synchronous Mode)
Figure 13.20 shows a sample flowchart for transmitting and receiving serial data
simultaneously and indicates the procedure to follow.
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Section 13 Serial Communication Interface
Initialize
1
Start transmitting and receiving
Read TDRE flag in SSR
2
No
TDRE = 1?
Yes
Write transmit data in TDR and
clear TDRE flag to 0 in SSR
Read ORER flag in SSR
Yes
ORER = 1?
3
No
Read RDRF flag in SSR
Error handling
4
No
RDRF = 1?
Yes
Read receive data from RDR
and clear RDRF flag to 0 in SSR
No
End of transmitting and
receiving?
5
Yes
Clear TE and RE bits to 0 in SCR
1. SCI initialization: the transmit data
output function of the TxD pin and
receive data input function of the
RxD pin are selected, enabling
simultaneous transmitting and
receiving.
2. SCI status check and transmit
data write: read SSR, check that
the TDRE flag is 1, then write
transmit data in TDR and clear
the TDRE flag to 0.
Notification that the TDRE flag has
changed from 0 to 1 can also be
given by the TXI interrupt.
3. Receive error handling: if a receive
error occurs, read the ORER flag in
SSR, then after executing the necessary error handling, clear the ORER
flag to 0.
Neither transmitting nor receiving
can resume while the ORER flag
remains set to 1.
4. SCI status check and receive
data read: read SSR, check that
the RDRF flag is 1, then read
receive data from RDR and clear
the RDRF flag to 0. Notification
that the RDRF flag has changed
from 0 to 1 can also be given
by the RXI interrupt.
5. To continue transmitting and
receiving serial data: check the
RDRF flag, read RDR, and clear
the RDRF flag to 0 before the
MSB (bit 7) of the current frame
is received. Also check that
the TDRE flag is set to 1, indicating that data can be written, write
data in TDR, then clear the TDRE
flag to 0 before the MSB (bit 7) of
the current frame is transmitted.
When the DMAC is activated by
a transmit-data-empty interrupt
request (TXI) to write data in TDR,
the TDRE flag is checked and
cleared automatically. When the
DMAC is activated by a receivedata-full interrupt request (RXI) to
read RDR, the RDRF flag is
cleared automatically.
End
Note: When switching from transmitting or receiving to simultaneous
transmitting and receiving, clear both the TE bit and the RE bit
to 0, then set both bits to 1.
Figure 13.20 Sample Flowchart for Serial Transmitting
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Section 13 Serial Communication Interface
13.4
SCI Interrupts
The SCI has four interrupt request sources: TEI (transmit-end interrupt), ERI (receive-error
interrupt), RXI (receive-data-full interrupt), and TXI (transmit-data-empty interrupt). Table 13.12
lists the interrupt sources and indicates their priority. These interrupts can be enabled and disabled
by the TIE, TEIE, and RIE bits in SCR. Each interrupt request is sent separately to the interrupt
controller.
The TXI interrupt is requested when the TDRE flag is set to 1 in SSR. The TEI interrupt is
requested when the TEND flag is set to 1 in SSR. The TXI interrupt request can activate the
DMAC to transfer data. Data transfer by the DMAC automatically clears the TDRE flag to 0. The
TEI interrupt request cannot activate the DMAC.
The RXI interrupt is requested when the RDRF flag is set to 1 in SSR. The ERI interrupt is
requested when the ORER, PER, or FER flag is set to 1 in SSR. The RXI interrupt request can
activate the DMAC to transfer data. Data transfer by the DMAC automatically clears the RDRF
flag to 0. The ERI interrupt request cannot activate the DMAC.
The DMAC can be activated by interrupts from SCI channel 0.
Table 13.12 SCI Interrupt Sources
Interrupt
Description
Priority
ERI
Receive error (ORER, FER, or PER)
High
RXI
Receive data register full (RDRF)
↑
TXI
Transmit data register empty (TDRE)
TEI
Transmit end (TEND)
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Low
Section 13 Serial Communication Interface
13.5
Usage Notes
Note the following points when using the SCI.
TDR Write and TDRE Flag: The TDRE flag in SSR is a status flag indicating the loading of
transmit data from TDR into TSR. The SCI sets the TDRE flag to 1 when it transfers data from
TDR to TSR.
Data can be written into TDR regardless of the state of the TDRE flag. If new data is written in
TDR when the TDRE flag is 0, the old data stored in TDR will be lost because this data has not
yet been transferred to TSR. Before writing transmit data in TDR, be sure to check that the TDRE
flag is set to 1.
Simultaneous Multiple Receive Errors: Table 13.13 indicates the state of SSR status flags when
multiple receive errors occur simultaneously. When an overrun error occurs the RSR contents are
not transferred to RDR, so receive data is lost.
Table 13.13 SSR Status Flags and Transfer of Receive Data
RDRF
ORER
FER
PER
Receive Data
Transfer
RSR → RDR
1
1
0
0
×
Overrun error
0
0
1
0
O
Framing error
0
0
0
1
O
Parity error
1
1
1
0
×
Overrun error + framing error
1
1
0
1
×
Overrun error + parity error
0
0
1
1
O
Framing error + parity error
1
1
1
1
×
Overrun error + framing error + parity error
Receive Errors
Notes: O: Receive data is transferred from RSR to RDR.
× : Receive data is not transferred from RSR to RDR.
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Section 13 Serial Communication Interface
Break Detection and Processing: Break signals can be detected by reading the RxD pin directly
when a framing error (FER) is detected. In the break state the input from the RxD pin consists of
all 0s, so the FER flag is set and the parity error flag (PER) may also be set. In the break state the
SCI receiver continues to operate, so if the FER flag is cleared to 0 it will be set to 1 again.
Sending a Break Signal: When the TE bit is cleared to 0 the TxD pin becomes an I/O port, the
level and direction (input or output) of which are determined by DR and DDR bits. This feature
can be used to send a break signal.
After the serial transmitter is initialized, the DR value substitutes for the mark state until the TE
bit is set to 1 (the TxD pin function is not selected until the TE bit is set to 1). The DDR and DR
bits should therefore both be set to 1 beforehand.
To send a break signal during serial transmission, clear the DR bit to 0, then clear the TE bit to 0.
When the TE bit is cleared to 0 the transmitter is initialized, regardless of its current state, so the
TxD pin becomes an output port outputting the value 0.
Receive Error Flags and Transmitter Operation (Synchronous Mode Only): When a receive
error flag (ORER, PER, or FER) is set to 1 the SCI will not start transmitting, even if the TDRE
flag is cleared to 0. Be sure to clear the receive error flags to 0 when starting to transmit. Note that
clearing the RE bit to 0 does not clear the receive error flags to 0.
Receive Data Sampling Timing in Asynchronous Mode and Receive Margin: In asynchronous
mode the SCI operates on a base clock with 16 times the bit rate frequency. In receiving, the SCI
synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive
data is latched at the rising edge of the eighth base clock pulse. See figure 13.21.
16 clocks
8 clocks
0
7
15 0
7
15 0
Internal
base clock
Receive data
(RxD)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 13.21 Receive Data Sampling Timing in Asynchronous Mode
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Section 13 Serial Communication Interface
The receive margin in asynchronous mode can therefore be expressed as in equation (1).
M = (0.5 –
1
) – (L – 0.5) F –
D – 0.5
2N
M:
N:
D:
L:
F:
N
(1 + F) × 100% ................... (1)
Receive margin (%)
Ratio of clock frequency to bit rate (N = 16)
Clock duty cycle (D = 0 to 1.0)
Frame length (L = 9 to 12)
Absolute deviation of clock frequency
From equation (1), if F = 0 and D = 0.5 the receive margin is 46.875%, as given by equation (2).
D = 0.5, F = 0
M = {0.5 – 1/(2 × 16)} × 100%
= 46.875% ............................................................................................. (2)
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Restrictions on Usage of DMAC: To have the DMAC read RDR, be sure to select the SCI
receive-data-full interrupt (RXI) as the activation source with bits DTS2 to DTS0 in DTCR.
Restrictions on Usage of the Serial Clock: When transmitting data using an external clock as the
serial clock, an interval of at least 5 states is necessary between clearing the TDRE bit in SSR and
the start (falling edge) of the first transmit clock pulse corresponding to each frame (see figure
13.22). This condition is also needed for continuous transmission. If it is not fulfilled, operational
error will occur.
SCK
t*
t*
TDRE
TXD
X0
X1
X2
X3
X4
X5
X6
X7
Y0
Y1
Y2
Y3
Continuous transmission
Note: * Ensure that t ≥ 5 states.
Figure 13.22 Serial Clock Transmission (Example)
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Section 13 Serial Communication Interface
Switching SCK Pin to Port Output Pin Function in Synchronous Mode: When the SCK pin is
used as the serial clock output in synchronous mode, and is then switched to its output port
function at the end of transmission, a low level may be output for one half-cycle. Half-cycle lowlevel output occurs when SCK is switched to its port function with the following settings when
DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1.
1. End of serial data transmission
2. TE bit = 0
3. C/A bit = 0 ... switchover to port output
4. Occurrence of low-level output (see figure 13.23)
Half-cycle low-level output
SCK/port
1. End of transmission
Data
Bit 6
4. Low-level output
Bit 7
2. TE = 0
TE
C/A
3. C/A = 0
CKE1
CKE0
Figure 13.23 Operation when Switching from SCK Pin Function to Port Pin Function
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Section 13 Serial Communication Interface
Sample Procedure for Preventing Low-Level Output
As this sample procedure temporarily places the SCK pin in the input state, the SCK/port pin
should be pulled up beforehand with an external circuit.
With DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following settings
in the order shown.
1. End of serial data transmission
2. TE bit = 0
3. CKE1 bit = 1
4. C/A bit = 0 ... switchover to port output
5. CKE1 bit = 0
High-level output
SCK/port
1. End of transmission
Data
Bit 6
Bit 7
2. TE = 0
TE
4. C/A = 0
C/A
3. CKE1 = 1
CKE1
5. CKE1 = 0
CKE0
Figure 13.24 Operation when Switching from SCK Pin Function to Port Pin Function
(Example of Preventing Low-Level Output)
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Section 13 Serial Communication Interface
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Section 14 Smart Card Interface
Section 14 Smart Card Interface
14.1
Overview
As an extension of its serial communication interface functions, SCI0 supports a smart card (IC
card) interface conforming to the ISO/IEC7816-3 (Identification Card) standard. Switchover
between normal serial communication and the smart card interface is controlled by a register
setting.
14.1.1
Features
Features of the smart-card interface supported by the H8/3048 Group are listed below.
• Asynchronous communication
Data length: 8 bits
Parity bits generated and checked
Error signal output in receive mode (parity error)
Error signal detect and automatic data retransmit in transmit mode
Supports both direct convention and inverse convention
• Built-in baud rate generator with selectable bit rates
• Three types of interrupts
Transmit-data-empty, receive-data-full, and receive-error interrupts are requested
independently. The transmit-data-empty and receive-data-full interrupts can activate the DMA
controller (DMAC) to transfer data.
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Section 14 Smart Card Interface
14.1.2
Block Diagram
Bus interface
Figure 14.1 shows a block diagram of the smart card interface.
Module data bus
RxD0
RDR
TDR
RSR
TSR
SCMR
SSR
SCR
SMR
Transmit/receive
control
TxD0
Parity generate
Parity check
BRR
φ
φ/4
Baud rate
generator
φ/16
φ/64
Clock
SCK0
TXI
RXI
ERI
Legend
SCMR:
RSR:
RDR:
TSR:
TDR:
SMR:
SCR:
SSR:
BRR:
Smart card mode register
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
Serial control register
Serial status register
Bit rate register
Figure 14.1 Smart Card Interface Block Diagram
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Internal
data
bus
Section 14 Smart Card Interface
14.1.3
Input/Output Pins
Table 14.1 lists the smart card interface pins.
Table 14.1 Smart Card Interface Pins
Name
Abbreviation
I/O
Function
Serial clock pin
SCK0
Output
Clock output
Receive data pin
RxD0
Input
Receive data input
Transmit data pin
TxD0
Output
Transmit data output
14.1.4
Register Configuration
The smart card interface has the internal registers listed in table 14.2. BRR, TDR, and RDR have
their normal serial communication interface functions, as described in section 13, Serial
Communication Interface.
Table 14.2 Registers
Address*
1
Name
Abbreviation
R/W
Initial Value
H'FFB0
Serial mode register
SMR
R/W
H'00
H'FFB1
Bit rate register
BRR
R/W
H'FF
H'FFB2
Serial control register
SCR
R/W
H'00
H'FFB3
Transmit data register
TDR
R/W
H'FF
2
H'FFB4
Serial status register
SSR
R/(W)*
F'84
H'FFB5
Receive data register
RDR
R
H'00
H'FFB6
Smart card mode register
SCMR
R/W
H'F2
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written, to clear flags.
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Section 14 Smart Card Interface
14.2
Register Descriptions
This section describes the new or modified registers and bit functions in the smart card interface.
14.2.1
Smart Card Mode Register (SCMR)
SCMR is an 8-bit readable/writable register that selects smart card interface functions.
Bit
7
6
5
4
3
2
1
0
—
—
—
—
SDIR
SINV
—
SMIF
Initial value
1
1
1
1
0
0
1
0
Read/Write
—
—
—
—
R/W
R/W
—
R/W
Reserved bits
Reserved bits
Smart card interface
mode select
Enables or disables
the smart card
interface function
Smart card data invert
Inverts data logic levels
Smart card data transfer direction
Selects the serial/parallel conversion format
SCMR is initialized to H'F2 by a reset and in standby mode.
Bits 7 to 4—Reserved: Read-only bits, always read as 1.
Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion
format.
Bit 3: SDIR
Description
0
TDR contents are transmitted LSB-first
1
TDR contents are transmitted MSB-first
Received data is stored LSB-first in RDR
Received data is stored MSB-first in RDR
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(Initial value)
Section 14 Smart Card Interface
Bit 2—Smart Card Data Inverter (SINV): Inverts data logic levels. This function is used in
combination with bit 3 to communicate with inverse-convention cards. SINV does not affect the
logic level of the parity bit. For parity settings, see section 14.3.4, Register Settings.
Bit 2: SINV
Description
0
Unmodified TDR contents are transmitted
(Initial value)
Received data is stored unmodified in RDR
1
Inverted TDR contents are transmitted
Received data is inverted before storage in RDR
Bit 1—Reserved: Read-only bit, always read as 1.
Bit 0—Smart Card Interface Mode Select (SMIF): Enables the smart card interface function.
Bit 0: SMIF
Description
0
Smart card interface function is disabled
1
Smart card interface function is enabled
14.2.2
(Initial value)
Serial Status Register (SSR)
The function of SSR bit 4 is modified in the smart card interface. This change also causes a
modification to the setting conditions for bit 2 (TEND).
Bit
7
6
5
4
3
2
1
0
TDRE
RDRF
ORER
ERS
PER
TEND
MPB
MPBT
Initial value
1
0
0
0
0
1
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R
R
R/W
Transmit end
Status flag indicating
end of transmission
Error signal status (ERS)
Status flag indicating that an
error signal has been received
Note: * Only 0 can be written, to clear the flag.
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Section 14 Smart Card Interface
Bits 7 to 5: These bits operate as in normal serial communication. For details see section 13,
Serial Communication Interface.
Bit 4—Error Signal Status (ERS): In smart card interface mode, this flag indicates the status of
the error signal sent from the receiving device to the transmitting device. The smart card interface
does not detect framing errors.
Bit 4: ERS
Description
0
Indicates normal data transmission, with no error signal returned (Initial value)
[Clearing conditions]
The chip is reset or enters standby mode.
Software reads ERS while it is set to 1, then writes 0.
1
Indicates that the receiving device sent an error signal reporting a parity error
[Setting condition]
A low error signal was sampled.
Note: Clearing the TE bit to 0 in SCR does not affect the ERS flag, which retains its previous
value.
Bits 3 to 0: These bits operate as in normal serial communication. For details see section 13,
Serial Communication Interface. The setting conditions for transmit end (TEND, bit 2), however,
are modified as follows.
Bit 2: TEND
Description
0
Transmission is in progress
[Clearing conditions]
Software reads TDRE while it is set to 1, then writes 0 in the TDRE flag.
The DMAC writes data in TDR.
1
End of transmission
(Initial value)
[Setting conditions]
The chip is reset or enters standby mode.
The TE bit and FER/ERS bit are both cleared to 0 in SCR.
TDRE is 1 and FER/ERS is 0 at a time 2.5 etu after the last bit of a 1-byte
serial character is transmitted (normal transmission)
Note: An etu (elementary time unit) is the time needed to transmit one bit.
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Section 14 Smart Card Interface
14.2.3
Serial Mode Register (SMR)
Bit 7 of SMR has a different function in smart card interface mode. The related serial control
register (SCR) changes from bit 1 to bit 0. However, this function does not exist in the flash
memory version.
Bit
7
6
5
4
3
2
1
0
GM
CHR
PR
O/E
STOP
MP
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7-GSM Mode (GM): Set at 0 when using the regular smart card interface. In GSM mode, set
to 1. When transmission is complete, initially the TEND flag set timing appears followed by clock
output restriction mode. Clock output restriction mode comprises serial control register bit 1 and
bit 0.
Bit 7: GM
Description
0
Using the regular smart card interface mode
1
•
The TEND flag is set 12.5 etu after the beginning of the start bit
•
Clock output on/off control only
(Initial value)
Using the GSM mode smart card interface mode
•
The TEND flag is set 11.0 etu after the beginning of the start bit
•
Clock output on/off and fixed-high/fixed-low control
Bits 6 to 0—Operate in the same way as for the normal SCI.
For details, see section 13.2.5, Serial Mode Register (SMR).
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Section 14 Smart Card Interface
14.2.4
Serial Control Register (SCR)
Bits 1 and 0 have different functions in smart card interface mode. However, this function does not
exist in the flash memory version.
Bit
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
0
0
0
0
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
Bits 7 to 2—Operate in the same way as for the normal SCI.
For details, see section 13.2.6, Serial Control Register (SCR).
Bits 1 and 0—Clock Enable (CKE1, CKE0): Setting enable or disable for the SCI clock
selection and clock output from the SCK pin. In smart card interface mode, it is possible to switch
between enabling and disabling of the normal clock output, and specify a fixed high level or fixed
low level for the clock output.
SMR
SCR
Bit 7:
GM
Bit 1:
CKE1
Bit 0:
CKE0
Description
0
0
0
The internal clock/SCK0 pin functions as an I/O port
0
0
1
The internal clock/SCK0 pin functions as the clock output
1
0
0
The internal clock/SCK0 pin is fixed at low-level output
1
0
1
The internal clock/SCK0 pin functions as the clock output
1
1
0
The internal clock/SCK0 pin is fixed at high-level output
1
1
1
The internal clock/SCK0 pin functions as the clock output
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(Initial value)
Section 14 Smart Card Interface
14.3
Operation
14.3.1
Overview
The main features of the smart-card interface are as follows.
• One frame consists of eight data bits and a parity bit.
• In transmitting, a guard time of at least two elementary time units (2 etu) is provided between
the end of the parity bit and the start of the next frame. (An elementary time unit is the time
required to transmit one bit.)
• In receiving, if a parity error is detected, a low error signal is output for 1 etu, beginning 10.5
etu after the start bit.
• In transmitting, if an error signal is received, after at least 2 etu, the same data is automatically
transmitted again.
• Only asynchronous communication is supported. There is no synchronous communication
function.
14.3.2
Pin Connections
Figure 14.2 shows a pin connection diagram for the smart card interface.
In communication with a smart card, data is transmitted and received over the same signal line.
The TxD0 and RxD0 pins should both be connected to this line. The data transmission line should
be pulled up to VCC through a resistor.
If the smart card uses the clock generated by the smart card interface, connect the SCK0 output pin
to the card’s CLK input. If the card uses its own internal clock, this connection is unnecessary.
The reset signal should be output from one of the H8/3048 Group’s generic ports.
In addition to these pin connections, power and ground connections will normally also be
necessary.
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Section 14 Smart Card Interface
VCC
TxD0
RxD0
Data line
SCK0
Clock line
Px (port)
H8/3048 Group
Chip
Reset line
I/O
CLK
RST
Smart card
Card-processing device
Figure 14.2 Smart Card Interface Connection Diagram
Note: A loop-back test can be performed by setting both RE and TE to 1 without connecting a
smart card.
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Section 14 Smart Card Interface
14.3.3
Data Format
Figure 14.3 shows the data format of the smart card interface. In receive mode, parity is checked
once per frame. If a parity error is detected, an error signal is returned to the transmitting device to
request retransmission. In transmit mode, the error signal is sampled and the same data is
retransmitted if the error signal is low.
No parity error
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
D6
D7
Dp
Output from transmitting device
Parity error
Ds
D0
D1
D2
D3
D4
D5
DE
Output from transmitting device
Output from
receiving device
Ds:
D0 to D7:
Dp:
DE:
Start bit
Data bits
Parity bit
Error signal
Figure 14.3 Smart Card Interface Data Format
The operating sequence is as follows.
1. When not in use, the data line is in the high-impedance state, and is pulled up to the high level
through a resistor.
2. To start transmitting a frame of data, the transmitting device transmits a low start bit (Ds),
followed by eight data bits (D0 to D7) and a parity bit (Dp).
3. Next, in the smart card interface, the transmitting device returns the data line to the highimpedance state. The data line is pulled up to the high level through a resistor.
4. The receiving device performs a parity check. If there is no parity error, the receiving device
waits to receive the next data. If a parity error is present, the receiving device outputs a low
error signal (DE) to request retransmission of the data. After outputting the error signal for a
designated interval, the receiving device returns the signal line to the high-impedance state.
The signal line is pulled back up to the high level through the pull-up resistor.
5. If the transmitting device does not receive an error signal, it proceeds to transmit the next data.
If it receives an error signal, it returns to step 2 and transmits the same data again.
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Section 14 Smart Card Interface
14.3.4
Register Settings
Table 14.3 shows a bit map of the registers used in the smart card interface. Bits indicated as 0 or
1 should always be set to the indicated value. The settings of the other bits will be described in this
section.
Table 14.3 Register Settings in Smart Card Interface
Register
Address*
SMR
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
H'FFB0
GM
0
1
O/E
1
0
CKS1
CKS0
BRR
H'FFB1
BRR7
BRR6
BRR5
BRR4
BRR3
BRR2
BRR1
SCR
H'FFB2
TIE
RIE
TE
RE
0
0
CKE1* CKE0
TDR
H'FFB3
TDR7
TDR6
TDR5
TDR4
TDR3
TDR2
TDR1
TDR0
SSR
H'FFB4
TDRE
RDRF
ORER
ERS
PER
TEND
0
0
RDR
H'FFB5
RDR7
RDR6
RDR5
RDR4
RDR3
RDR2
RDR1
RDR0
SCMR
H'FFB6
—
—
—
—
SDIR
SINV
—
SMIF
BRR0
2
Notes: — Unused bit.
1. Lower 16 bits of the address.
2. When the GM of the SMR is set at 0, be sure the CKE1 bit is 0.
Serial Mode Register (SMR) Settings: In regular smart card interface mode, set the GM bit at 0.
In regular smart card mode, clear the GM bit to 0. In GSM mode, set the GM bit to 1. Clear the
O/E bit to 0 if the smart card uses the direct convention. Set the O/E bit to 1 if the smart card uses
the inverse convention. Bits CKS1 and CKS0 select the clock source of the built-in baud rate
generator. See section 14.3.5, Clock.
Bit Rate Register (BRR) Settings: This register sets the bit rate. Equations for calculating the
setting are given in section 14.3.5, Clock.
Serial Control Register (SCR): The TIE, RIE, TE, and RE bits have their normal serial
communication functions. For details, see section 13, Serial Communication Interface. The CKE1
and CKE0 bits select clock output. When the GM bit of the SMR is cleared to 0, to disable clock
output, clear this bit to 00. To enable clock output, set this bit to 01. When the GM bit of the SMR
is set to 1, clock output is enabled. Clock output is fixed at high or low.
Smart Card Mode Register (SCMR): If the smart card follows the direct convention, clear the
SDIR and SINV bits to 0. If the smart card follows the indirect convention, set the SDIR and
SINV bits to 1. To use the smart card interface, set the SMIF bit to 1.
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Section 14 Smart Card Interface
The register settings and examples of starting character waveforms are shown below for two smart
cards, one following the direct convention and one the inverse convention.
• Direct convention (SDIR = SINV = O/E = 0)
(Z)
A
Z
Z
A
Z
Z
Z
A
A
Z
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
(Z)
State
In the direct convention, state Z corresponds to logic level 1, and state A to logic level 0.
Characters are transmitted and received LSB-first. In the example above the first character data
is H'3B. The parity bit is 1, following the even parity rule designated for smart cards.
• Inverse convention (SDIR = SINV = O/E = 1)
(Z)
A
Z
Z
A
A
A
A
A
A
Z
Ds
D7
D6
D5
D4
D3
D2
D1
D0
Dp
(Z)
State
In the inverse convention, state A corresponds to the logic level 1, and state Z to the logic level
0. Characters are transmitted and received MSB-first. In the example above the first character
data is H'3F. Following the even parity rule designated for smart cards, the parity bit logic
level is 0, corresponding to state Z.
In the H8/3048 Group, the SINV bit inverts only the data bits D7 to D0. The parity bit is not
inverted, so the O/E bit in SMR must be set to odd parity mode. This applies in both transmitting
and receiving.
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Section 14 Smart Card Interface
14.3.5
Clock
As its serial communication clock, the smart card interface can use only the internal clock
generated by the on-chip baud rate generator. The bit rate can be selected by setting the bit rate
register (BRR) and bits CKS1 and CKS0 in the serial mode register (SMR). The bit rate can be
calculated from the equation given below. Table 14.5 lists some examples of bit rate settings.
If bit CKE0 is set to 1, a clock signal with a frequency equal to 372 times the bit rate is output
from the SCK0 pin.
B=
where, N:
B:
φ:
n:
φ
1488 × 22n–1 × (N + 1)
× 106
BRR setting (0 ≤ N ≤ 255)
Bit rate (bits/s)
System clock frequency (MHz)*
See table 14.4
Table 14.4 n-Values of CKS1 and CKS0 Settings
n
CKS1
CKS0
0
0
0
1
0
1
2
1
0
3
1
1
Note: * If the gear function is used to divide the system clock frequency, use the divided
frequency to calculate the bit rate. The equation above applies directly to 1/1 frequency
division.
Table 14.5 Bit Rates (bits/s) for Different BRR Settings (when n = 0)
φ (MHz)
N
7.1424
10.00
10.7136
13.00
14.2848
16.00
18.00
0
9600.0
13440.9
14400.0
17473.1
19200.0
21505.4
24193.5
1
4800.0
6720.4
7200.0
8736.6
9600.0
10752.7
12096.8
2
3200.0
4480.3
4800.0
5824.4
6400.0
7168.5
8064.5
Note: Bit rates are rounded off to one decimal place.
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Section 14 Smart Card Interface
The following equation calculates the bit rate register (BRR) setting from the system clock
frequency and bit rate. N is an integer from 0 to 255, specifying the value with the smaller error.
N=
φ
1488 × 22n–1 × B
× 106 – 1
Table 14.6 BRR Settings for Typical Bit Rate (bits/s) (when n = 0)
φ (MHz)
7.1424
10.00
10.7136
13.00
14.2848
16.00
18.00
Bit/s
N
Error
N
Error
N
Error
N
Error
N
Error
N
Error
N
Error
9600
0
0.00
1
30.00
1
25.00
1
8.99
1
0.00
1
12.01
2
15.99
Table 14.7 Maximum Bit Rates for Various Frequencies (Smart Card Interface)
φ (MHz)
Maximum Bit Rate (bits/s)
N
n
7.1424
9600
0
0
10.00
13441
0
0
10.7136
14400
0
0
13.00
17473
0
0
14.2848
19200
0
0
16.00
21505
0
0
18.00
24194
0
0
The bit rate error is calculated from the following equation.
Error (%) =
φ
1488 ×
22n–1
× B × (N + 1)
× 106 – 1 × 100
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Section 14 Smart Card Interface
14.3.6
Transmitting and Receiving Data
Initialization: Before transmitting or receiving data, initialize the smart card interface by the
procedure below. Initialization is also necessary when switching from transmit mode to receive
mode or from receive mode to transmit mode.
1. Clear the TE and RE bits to 0 in the serial control register (SCR).
2. Clear the ERS, PER, and ORER error flags to 0 in the serial status register (SSR).
3. Set the parity mode bit (O/E) and baud rate generator clock source select bits (CKS1 and
CKS0) as required in the serial mode register (SMR). At the same time, clear the C/A, CHR,
and MP bits to 0, and set the STOP and PE bits to 1.
4. Set the SMIF, SDIR, and SINV bits as required in the smart card mode register (SMR). When
the SMIF bit is set to 1, the TxD0 and RxD0 pins switch from their I/O port functions to their
serial communication interface functions, and are placed in the high-impedance state.
5. Set a value corresponding to the desired bit rate in the bit rate register (BRR).
6. Set clock enable bit 0 (CKE0) as required in the serial control register (SCR). Write 0 in the
TIE, RIE, TE, RE, MPIE, TEIE, and CKE1 bits. If bit CKE0 is set to 1, a serial clock will be
output from the SCK0 pin.
7. Wait for at least the interval required to transmit or receive one bit, then set the TIE, RIE, TE,
and RE bits as necessary in SCR. Do not set TE and RE both to 1, except when performing a
loop-back test.
Transmitting Serial Data: The transmitting procedure in smart card mode is different from the
normal SCI procedure, because of the need to sample the error signal and retransmit. Figure 14.4
shows a flowchart for transmitting, and figure 14.5 shows the relation between a transmit
operation and the internal registers.
1. Initialize the smart card interface by the procedure given above in Initialization.
2. Check that the ERS error flag is cleared to 0 in SSR.
3. Check that the TEND flag is set to 1 in SSR. Repeat steps 2 and 3 until this check passes.
4. Write transmit data in TDR and clear the TDRE flag to 0. The data will be transmitted and the
TEND flag will be cleared to 0.
5. To continue transmitting data, return to step 2.
6. To terminate transmission, clear the TE bit to 0.
This procedure may include interrupt handling and DMA transfer.
If the TIE bit is set to 1 to enable interrupt requests, when transmission is completed and the
TEND flag is set to 1, a transmit-data-empty interrupt (TXI) is requested. If the RIE bit is set to 1
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Section 14 Smart Card Interface
to enable interrupt requests, when a transmit error occurs and the ERS flag is set to 1, a
transmit/receive-error interrupt (ERI) is requested.
The timing of TEND flag setting depends on the GM bit in SMR. The timing is shown in figure
14.6.
If the TXI interrupt activates the DMAC, the number of bytes designated in the DMAC can be
transmitted automatically, including automatic retransmit.
For details, see Interrupt Operations and Data Transfer by DMAC in this section.
Start
Initialize
Start transmitting
FER/ERS = 0 ?
No
Yes
Error handling
No
TEND = 1 ?
Yes
Write data in TDR and clear
TDRE flag to 0 in SSR
No
All data
transmitted ?
Yes
FER/ERS = 0 ?
No
Yes
Error handling
No
TEND = 1 ?
Yes
Clear TE bit to 0
End
Figure 14.4 Transmit Flowchart (Example)
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Section 14 Smart Card Interface
TDR
(1) Data write
Data 1
(2) Transfer from
TDR to TSR
Data 1
(3) Serial data output
Data 1
TSR
(shift register)
Data 1
; Data remains in TDR
Data 1
I/O signal line output
In case of normal transmission: TEND flag is set
In case of transmit error:
ERS flag is set
Steps (2) and (3) above are repeated until the TEND flag is set
Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first
transmission, D0 in MSB-first transmission) of the next transfer data to be transmitted has
been completed.
Figure 14.5 Relation Between Transmit Operation and Internal Registers
I/O data
DS
Da
Db
Dc
Dd
De
Df
Dg
Dh
Dp
DE
Guard
time
TXI
(TEND interrupt)
12.5 etu
When GM = 0
11.0 etu
When GM = 1
Figure 14.6 TEND Flag Occurrence Timing
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Section 14 Smart Card Interface
Receiving Serial Data: The receiving procedure in smart card mode is the same as the normal
SCI procedure. Figure 14.7 shows a flowchart for receiving.
1. Initialize the smart card interface by the procedure given in Initialization at the beginning of
this section.
2. Check that the ORER and PER error flags are cleared to 0 in SSR. If either flag is set, carry out
the necessary error handling, then clear both the ORER and PER flags to 0.
3. Check that the RDRF flag is set to 1. Repeat steps 2 and 3 until this check passes.
4. Read receive data from RDR.
5. To continue receiving data, clear the RDRF flag to 0 and return to step 2.
6. To terminate receiving, clear the RE bit to 0.
Start
Initialize
Start receiving
ORER = 0 and
PER = 0 ?
No
Yes
Error handling
No
RDRF = 1 ?
Yes
Read RDR and clear RDRF
flag to 0 in SSR
No
All data received ?
Yes
Clear RE bit to 0
Figure 14.7 Receive Flowchart (Example)
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Section 14 Smart Card Interface
This procedure may include interrupt handling and DMA transfer.
If the RIE bit is set to 1 to enable interrupt requests, when receiving is completed and the RDRF
flag is set to 1, a receive-data-full interrupt (RXI) is requested. If a receive error occurs, either the
ORER or PER flag is set to 1 and a transmit/receive-error interrupt (ERI) is requested.
If the RXI interrupt activates the DMAC, the number of bytes designated in the DMAC will be
transferred, skipping receive data in which an error occurred.
For details, see Interrupt Operations and Data Transfer by DMAC below.
When a parity error occurs and PER is set to 1, the receive data is transferred to RDR, so the
erroneous data can be read.
Switching Modes: To switch from receive mode to transmit mode, check that receiving
operations have completed, then initialize the smart card interface, clearing RE to 0 and setting TE
to 1. Completion of receive operations is indicated by the RDRF, PER, or ORER flag.
To switch from transmit mode to receive mode, check that transmitting operations have
completed, then initialize the smart card interface, clearing TE to 0 and setting RE to 1.
Completion of transmit operations can be verified from the TEND flag.
Fixing Clock Output: When the GM bit of the SMR is set to 1, clock output is fixed by CKE1
and CKE0 of SCR. In this case, the clock pulse can be set at minimum value.
Figure 14.8 shows clock output fixed timing: CKE0 is restricted with GM = 1 and CKE1 = 1.
Specified pulse width
Specified pulse width
CKE1 value
SCK
SCR write
(CKE0 = 0)
SCR write
(CKE0 = 1)
Figure 14.8 Clock Output Fixed Timing
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Section 14 Smart Card Interface
Interrupt Operations: The smart card interface has three interrupt sources: transmit-data-empty
(TXI), transmit/receive-error (ERI), and receive-data-full (RXI). The transmit-end interrupt
request (TEI) is not available in smart card mode.
A TXI interrupt is requested when the TEND flag is set to 1 in SSR. An RXI interrupt is requested
when the RDRF flag is set to 1 in SSR. An ERI interrupt is requested when the ORER, PER, or
ERS flag is set to 1 in SSR. These relationships are shown in table 14.8.
Table 14.8 Smart Card Mode Operating States and Interrupt Sources
Flag
Mask Bit
Interrupt
Source
DMAC
Activation
Normal operation
TEND
TIE
TXI
Available
Error
ERS
RIE
ERI
Not available
Normal operation
RDRF
RIE
RXI
Available
Error
PER, ORER
RIE
ERI
Not available
Operating State
Transmit mode
Receive mode
Data Transfer by DMAC: The DMAC can be used to transmit and receive in smart card mode,
as in normal SCI operations. In transmit mode, when the TEND flag is set to 1 in SSR, the TDRE
flag is set simultaneously, generating a TXI interrupt. If TXI is designated in advance as a DMAC
activation source, the DMAC will be activated by the TXI request and will transfer the next
transmit data. This data transfer by the DMAC automatically clears the TDRE and TEND flags to
0. When an error occurs, the SCI automatically retransmits the same data, keeping TEND cleared
to 0 so that the DMAC is not activated. The SCI and DMAC will therefore automatically transmit
the designated number of bytes, including retransmission when an error occurs. When an error
occurs the ERS flag is not cleared automatically, so the RIE bit should be set to 1 to enable the
error to generate an ERI request, and the ERI interrupt handler should clear ERS.
When using the DMAC to transmit or receive, first set up and enable the DMAC, then make SCI
settings. DMAC settings are described in section 8, DMA Controller.
In receive operations, when the RDRF flag is set to 1 in SSR, an RXI interrupt is requested. If RXI
is designated in advance as a DMAC activation source, the DMAC will be activated by the RXI
request and will transfer the received data. This data transfer by the DMAC automatically clears
the RDRF flag to 0. When an error occurs, the RDRF flag is not set and an error flag is set instead.
The DMAC is not activated. The ERI interrupt request is directed to the CPU. The ERI interrupt
handler should clear the error flags.
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Section 14 Smart Card Interface
Examples of Operation in GSM Mode: When switching between smart card interface mode and
software standby mode, use the following procedures to maintain the clock duty cycle.
• Switching from smart card interface mode to software standby mode
1. Set the P94 data register (DR) and data direction register (DDR) to the values for the fixed
output state in software standby mode.
2. Write 0 to the TE and RE bits in the serial control register (SCR) to stop transmit/receive
operations. At the same time, set the CKE1 bit to the value for the fixed output state in
software standby mode.
3. Write 0 to the CKE0 bit in SCR to stop the clock.
4. Wait for one serial clock cycle. During this period, the duty cycle is preserved and clock
output is fixed at the specified level.
5. Write H'00 to the serial mode register (SMR) and smart card mode register (SCMR).
6. Make the transition to the software standby state.
• Returning from software standby mode to smart card interface mode
1. Clear the software standby state.
2. Set the CKE1 bit in SCR to the value for the fixed output state at the start of software
standby (the current P94 pin state).
3. Set smart card interface mode and output the clock. Clock signal generation is started with
the normal duty cycle.
Normal operation
(1)(2)(3)
Software standby
mode
(4) (5)(6)
Normal operation
(1) (2)(3)
Figure 14.9 Procedure for Stopping and Restarting the Clock
Use the following procedure to secure the clock duty cycle after powering on.
1. The initial state is port input and high impedance. Use pull-up or pull-down resistors to fix the
potential.
2. Fix at the output specified by the CKE1 bit in SCR.
3. Set SMR and SCMR, and switch to smart card interface mode operation.
4. Set the CKE0 bit in SCR to 1 to start clock output.
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Section 14 Smart Card Interface
14.4
Usage Notes
When using the SCI as a smart card interface, note the following points.
Receive Data Sampling Timing in Smart Card Mode and Receive Margin: In smart card
mode the SCI operates on a base clock with 372 times the bit rate frequency. In receiving, the SCI
synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive
data is latched at the rising edge of the 186th base clock pulse. See figure 14.10.
372 clocks
186 clocks
0
185
371 0
185
371
0
Internal
base clock
Start
bit
Receive data
(RxD)
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 14.10 Receive Data Sampling Timing in Smart Card Mode
The receive margin can therefore be expressed as follows.
Receive margin in smart card mode:
M=
0.5 –
1
2N
– (L – 0.5) F –
D – 0.5
(1 + F) × 100%
N
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 372)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute deviation of clock frequency
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Section 14 Smart Card Interface
From this equation, if F = 0 and D = 0.5 the receive margin is as follows.
D = 0.5, F = 0
M = {0.5 – 1/(2 × 372)} × 100%
= 49.866%
Retransmission: Retransmission is described below for the separate cases of transmit mode and
receive mode.
• Retransmission when SCI is in Receive Mode (see figure 14.11)
(1) The SCI checks the received parity bit. If it detects an error, it automatically sets the PER flag
to 1. If the RIE bit in SCR is set to the enable state, an ERI interrupt is requested. The PER flag
should be cleared to 0 in SSR before the next parity bit sampling timing.
(2) The RDRF bit in SSR is not set to 1 for the error frame.
(3) If an error is not detected when the parity bit is checked, the PER flag is not set in SSR.
(4) If an error is not detected when the parity bit is checked, receiving operations are assumed to
have ended normally, and the RDRF bit is automatically set to 1 in SSR. If the RIE bit in SCR
is set to the enable state, an RXI interrupt is requested. If RXI is enabled as a DMA transfer
activation source, the RDR contents can be read automatically. When the DMAC reads the
RDR data, it automatically clears RDRF to 0.
(5) When a normal frame is received, at the error signal transmit timing, the data pin is held in the
high-impedance state.
Frame n
Retransmitted frame
Frame n + 1
(DE)
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
DE
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Ds D0 D1 D2 D3 D4
RDRF
(2)
(4)
(1)
(3)
PER
Figure 14.11 Retransmission in SCI Receive Mode
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Section 14 Smart Card Interface
• Retransmission when SCI is in Transmit Mode (see figure 14.12)
(6) After transmitting one frame, if the receiving device returns an error signal, the SCI sets the
ERS flag to 1 in SSR. If the RIE bit in SCR is set to the enable state, an ERI interrupt is
requested. The ERS flag should be cleared to 0 in SSR before the next parity bit sampling
timing.
(7) The TEND bit in SSR is not set for the frame in which the error signal was received, indicating
an error.
(8) If no error signal is returned from the receiving device, the ERS flag is not set in SSR.
(9) If no error signal is returned from the receiving device, transmission of the frame, including
retransmission, is assumed to be complete, and the TEND bit is set to 1 in SSR. If the TIE bit
in SCR is set to the enable state, a TXI interrupt is requested. If TXI is enabled as a DMA
transfer activation source, the next data can be written in TDR automatically. When the
DMAC writes data in TDR, it automatically clears the TDRE bit to 0.
Frame n
Retransmitted frame
Frame n + 1
(DE)
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
DE
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Ds D0 D1 D2 D3 D4
TDRE
Transfer from TDR to TSR
Transfer from
TDR to TSR
Transfer from TDR to TSR
TEND
(7)
(9)
ERS
(6)
(8)
Figure 14.12 Retransmission in SCI Transmit Mode
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Section 14 Smart Card Interface
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Section 15 A/D Converter
Section 15 A/D Converter
15.1
Overview
The H8/3048 Group includes a 10-bit successive-approximations A/D converter with a selection
of up to eight analog input channels.
When the A/D converter is not used, it can be halted independently to conserve power. For details
see section 21.6, Module Standby Function.
15.1.1
Features
A/D converter features are listed below.
• 10-bit resolution
• Eight input channels
• Selectable analog conversion voltage range
The analog voltage conversion range can be programmed by input of an analog reference
voltage at the VREF pin.
• High-speed conversion
Conversion time: Minimum 7.45 µs per channel (with 18 MHz system clock)
• Two conversion modes
Single mode: A/D conversion of one channel
Scan mode: continuous conversion on one to four channels
• Four 16-bit data registers
A/D conversion results are transferred for storage into data registers corresponding to the
channels.
• Sample-and-hold function
• A/D conversion can be externally triggered
• A/D interrupt requested at end of conversion
At the end of A/D conversion, an A/D end interrupt (ADI) can be requested.
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Section 15 A/D Converter
15.1.2
Block Diagram
Figure 15.1 shows a block diagram of the A/D converter.
Internal
data bus
AV SS
AN 0
AN 5
ADCR
ADCSR
ADDRD
–
AN 2
AN 4
ADDRC
+
AN 1
AN 3
ADDRB
10-bit D/A
ADDRA
V REF
Successiveapproximations register
AVCC
Bus interface
Module data bus
Analog
multiplexer
φ/8
Comparator
Control circuit
Sample-andhold circuit
φ/16
AN 6
AN 7
ADI
ADTRG
Legend
ADCR:
ADCSR:
ADDRA:
ADDRB:
ADDRC:
ADDRD:
A/D control register
A/D control/status register
A/D data register A
A/D data register B
A/D data register C
A/D data register D
Figure 15.1 A/D Converter Block Diagram
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Section 15 A/D Converter
15.1.3
Input Pins
Table 15.1 summarizes the A/D converter’s input pins. The eight analog input pins are divided
into two groups: group 0 (AN0 to AN3), and group 1 (AN4 to AN7). AVCC and AVSS are the power
supply for the analog circuits in the A/D converter. VREF is the A/D conversion reference voltage.
Table 15.1 A/D Converter Pins
Pin Name
Abbreviation
I/O
Function
Analog power supply pin
AVCC
Input
Analog power supply
Analog ground pin
AVSS
Input
Analog ground and reference voltage
Reference voltage pin
VREF
Input
Analog reference voltage
Analog input pin 0
AN0
Input
Group 0 analog inputs
Analog input pin 1
AN1
Input
Analog input pin 2
AN2
Input
Analog input pin 3
AN3
Input
Analog input pin 4
AN4
Input
Analog input pin 5
AN5
Input
Analog input pin 6
AN6
Input
Analog input pin 7
AN7
Input
A/D external trigger input pin
ADTRG
Input
Group 1 analog inputs
External trigger input for starting A/D
conversion
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Section 15 A/D Converter
15.1.4
Register Configuration
Table 15.2 summarizes the A/D converter’s registers.
Table 15.2 A/D Converter Registers
Address*
1
Name
Abbreviation
R/W
Initial Value
H'FFE0
A/D data register A (high)
ADDRAH
R
H'00
H'FFE1
A/D data register A (low)
ADDRAL
R
H'00
H'FFE2
A/D data register B (high)
ADDRBH
R
H'00
H'FFE3
A/D data register B (low)
ADDRBL
R
H'00
H'FFE4
A/D data register C (high)
ADDRCH
R
H'00
H'FFE5
A/D data register C (low)
ADDRCL
R
H'00
H'FFE6
A/D data register D (high)
ADDRDH
R
H'00
H'FFE7
A/D data register D (low)
ADDRDL
R
H'00
H'00
H'7F*
H'FFE8
A/D control/status register
ADCSR
2
R/(W)*
H'FFE9
A/D control register
ADCR
R/W
3
Notes: 1. Lower 16 bits of the address
2. Only 0 can be written in bit 7, to clear the flag.
3. H8/3048F, H8/3048ZTAT, H8/3048 mask-ROM, H8/3047 mask-ROM, H8/3045 maskROM, and H8/3044 mask-ROM versions
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Section 15 A/D Converter
15.2
Register Descriptions
15.2.1
A/D Data Registers A to D (ADDRA to ADDRD)
14
12
10
8
6
5
4
3
2
1
0
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 —
15
Bit
13
11
9
7
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
(n = A to D)
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
ADDRn
A/D conversion data
10-bit data giving an
A/D conversion result
Reserved bits
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the
results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data
register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper
byte of the A/D data register. The lower 2 bits are stored in the lower byte. Bits 5 to 0 of an A/D
data register are reserved bits that are always read as 0. Table 15.3 indicates the pairings of analog
input channels and A/D data registers.
The CPU can always read and write the A/D data registers. The upper byte can be read directly,
but the lower byte is read through a temporary register (TEMP). For details see section 15.3, CPU
Interface.
The A/D data registers are initialized to H'0000 by a reset and in standby mode.
Table 15.3 Analog Input Channels and A/D Data Registers
Analog Input Channel
Group 0
Group 1
A/D Data Register
AN0
AN4
ADDRA
AN1
AN5
ADDRB
AN2
AN6
ADDRC
AN3
AN7
ADDRD
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Section 15 A/D Converter
15.2.2
A/D Control/Status Register (ADCSR)
Bit
7
6
5
4
3
2
1
0
ADF
ADIE
ADST
SCAN
CKS
CH2
CH1
CH0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Channel select 2 to 0
These bits select analog
input channels
Clock select
Selects the A/D conversion time
Scan mode
Selects single mode or scan mode
A/D start
Starts or stops A/D conversion
A/D interrupt enable
Enables and disables A/D end interrupts
A/D end flag
Indicates end of A/D conversion
Note: * Only 0 can be written, to clear the flag.
ADCSR is an 8-bit readable/writable register that selects the mode and controls the A/D converter.
ADCSR is initialized to H'00 by a reset and in standby mode.
Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion.
Bit 7: ADF
Description
0
[Clearing condition]
Cleared by reading ADF while ADF = 1, then writing 0 in ADF
1
[Setting conditions]
Single mode: A/D conversion ends
Scan mode: A/D conversion ends in all selected channels
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(Initial value)
Section 15 A/D Converter
Bit 6—A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the
end of A/D conversion.
Bit 6: ADIE
Description
0
A/D end interrupt request (ADI) is disabled
1
A/D end interrupt request (ADI) is enabled
(Initial value)
Bit 5—A/D Start (ADST): Starts or stops A/D conversion. The ADST bit remains set to 1 during
A/D conversion. It can also be set to 1 by external trigger input at the ADTRG pin.
Bit 5: ADST
Description
0
A/D conversion is stopped
1
Single mode: A/D conversion starts; ADST is automatically cleared to 0 when
conversion ends.
(Initial value)
Scan mode: A/D conversion starts and continues, cycling among the selected
channels, until ADST is cleared to 0 by software, by a reset, or by a transition
to standby mode.
Bit 4—Scan Mode (SCAN): Selects single mode or scan mode. For further information on
operation in these modes, see section 15.4, Operation. Clear the ADST bit to 0 before switching
the conversion mode.
Bit 4: SCAN
Description
0
Single mode
1
Scan mode
(Initial value)
Bit 3—Clock Select (CKS): Selects the A/D conversion time. Clear the ADST bit to 0 before
switching the conversion time.
Bit 3: CKS
Description
0
Conversion time = 266 states (maximum)
1
Conversion time = 134 states (maximum)
(Initial value)
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Section 15 A/D Converter
Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit select the analog
input channels. Clear the ADST bit to 0 before changing the channel selection.
Group
Selection
Channel Selection
Description
CH2
CH1
CH0
Single Mode
Scan Mode
0
0
0
AN0 (Initial value)
AN0
1
AN1
AN0, AN1
0
AN2
AN0 to AN2
1
AN3
AN0 to AN3
0
AN4
AN4
1
AN5
AN4, AN5
0
AN6
AN4 to AN6
1
AN7
AN4 to AN7
1
1
0
1
15.2.3
A/D Control Register (ADCR)
Bit
7
6
5
4
3
2
1
0
TRGE
—
—
—
—
—
—
—
Initial value
0
1
1
1
1
1
1
1
Read/Write
R/W
—
—
—
—
—
—
—
Reserved bits
Trigger enable
Enables or disables external triggering of A/D conversion
ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D
conversion. ADCR is initialized to H'7F by a reset and in standby mode.
Bit 7—Trigger Enable (TRGE): Enables or disables external triggering of A/D conversion.
Bit 7: TRGE
Description
0
A/D conversion cannot be externally triggered
1
A/D conversion starts at the falling edge of the external trigger signal (ADTRG)
Bits 6 to 0—Reserved: Read-only bits, always read as 1.
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(Initial value)
Section 15 A/D Converter
15.3
CPU Interface
ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus.
Therefore, although the upper byte can be be accessed directly by the CPU, the lower byte is read
through an 8-bit temporary register (TEMP).
An A/D data register is read as follows. When the upper byte is read, the upper-byte value is
transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next, when the
lower byte is read, the TEMP contents are transferred to the CPU.
When reading an A/D data register, always read the upper byte before the lower byte. It is possible
to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained.
Figure 15.2 shows the data flow for access to an A/D data register.
Upper-byte read
CPU
(H'AA)
Module data bus
Bus interface
TEMP
(H'40)
ADDRnH
(H'AA)
ADDRnL
(H'40)
(n = A to D)
Lower-byte read
CPU
(H'40)
Module data bus
Bus interface
TEMP
(H'40)
ADDRnH
(H'AA)
ADDRnL
(H'40)
(n = A to D)
Figure 15.2 A/D Data Register Access Operation (Reading H'AA40)
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Section 15 A/D Converter
15.4
Operation
The A/D converter operates by successive approximations with 10-bit resolution. It has two
operating modes: single mode and scan mode.
15.4.1
Single Mode (SCAN = 0)
Single mode should be selected when only one A/D conversion on one channel is required. A/D
conversion starts when the ADST bit is set to 1 by software, or by external trigger input. The
ADST bit remains set to 1 during A/D conversion and is automatically cleared to 0 when
conversion ends.
When conversion ends the ADF bit is set to 1. If the ADIE bit is also set to 1, an ADI interrupt is
requested at this time. To clear the ADF flag to 0, first read ADCSR, then write 0 in ADF.
When the mode or analog input channel must be switched during analog conversion, to prevent
incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making
the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be
set at the same time as the mode or channel is changed.
Typical operations when channel 1 (AN1) is selected in single mode are described next.
Figure 15.3 shows a timing diagram for this example.
1. Single mode is selected (SCAN = 0), input channel AN1 is selected (CH2 = CH1 = 0,
CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1).
2. When A/D conversion is completed, the result is transferred into ADDRB. At the same time
the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle.
3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested.
4. The A/D interrupt handling routine starts.
5. The routine reads ADCSR, then writes 0 in the ADF flag.
6. The routine reads and processes the conversion result (ADDRB).
7. Execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1,
A/D conversion starts again and steps 2 to 7 are repeated.
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Note: * Vertical arrows ( ) indicate instructions executed by software.
ADDRD
ADDRC
ADDRB
Read conversion result
A/D conversion result (2)
Idle
Clear *
A/D conversion result (1)
A/D conversion (2)
Set *
Read conversion result
Idle
State of channel 3
(AN 3)
ADDRA
Idle
State of channel 2
(AN 2)
Idle
Clear *
State of channel 1
(AN 1)
A/D conversion (1)
Set *
Idle
Idle
A/D conversion
starts
State of channel 0
(AN 0)
ADF
ADST
ADIE
Set *
Section 15 A/D Converter
Figure 15.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
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Section 15 A/D Converter
15.4.2
Scan Mode (SCAN = 1)
Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the
ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first
channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1). When two or more channels are
selected, after conversion of the first channel ends, conversion of the second channel (AN1 or
AN5) starts immediately. A/D conversion continues cyclically on the selected channels until the
ADST bit is cleared to 0. The conversion results are transferred for storage into the A/D data
registers corresponding to the channels.
When the mode or analog input channel selection must be changed during analog conversion, to
prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After
making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the
first channel in the group. The ADST bit can be set at the same time as the mode or channel
selection is changed.
Typical operations when three channels in group 0 (AN0 to AN2) are selected in scan mode are
described next. Figure 15.4 shows a timing diagram for this example.
1. Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels
AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1).
2. When A/D conversion of the first channel (AN0) is completed, the result is transferred into
ADDRA. Next, conversion of the second channel (AN1) starts automatically.
3. Conversion proceeds in the same way through the third channel (AN2).
4. When conversion of all selected channels (AN0 to AN2) is completed, the ADF flag is set to 1
and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1, an ADI
interrupt is requested at this time.
5. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is
cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion
starts again from the first channel (AN0).
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Idle
Idle
Idle
A/D conversion (1)
Transfer
Idle
A/D conversion (3)
Idle
Idle
Clear*1
Idle
A/D conversion result (3)
A/D conversion result (2)
A/D conversion result (4)
Idle
A/D conversion (5)*2
A/D conversion time
A/D conversion (4)
A/D conversion result (1)
A/D conversion (2)
Idle
Notes: 1. Vertical arrows ( ) indicate instructions executed by software.
2. Data currently being converted is ignored.
ADDRD
ADDRC
ADDRB
ADDRA
State of channel 3
(AN 3)
State of channel 2
(AN 2)
State of channel 1
(AN 1)
State of channel 0
(AN 0)
ADF
ADST
Set *1
Continuous A/D conversion
Clear* 1
Section 15 A/D Converter
Figure 15.4 Example of A/D Converter Operation
(Scan Mode, Channels AN0 to AN2 Selected)
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Section 15 A/D Converter
15.4.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 15.5 shows the A/D
conversion timing. Table 15.4 indicates the A/D conversion time.
As indicated in figure 15.5, the A/D conversion time includes tD and the input sampling time. The
length of tD varies depending on the timing of the write access to ADCSR. The total conversion
time therefore varies within the ranges indicated in table 15.4.
In scan mode, the values given in table 15.4 apply to the first conversion. In the second and
subsequent conversions the conversion time is fixed at 256 states when CKS = 0 or 128 states
when CKS = 1.
(1)
φ
Address bus
(2)
Write signal
Input sampling
timing
ADF
t SPL
tD
t CONV
Legend
(1):
ADCSR write cycle
(2):
ADCSR address
tD :
Synchronization delay
t SPL : Input sampling time
t CONV: A/D conversion time
Figure 15.5 A/D Conversion Timing
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Section 15 A/D Converter
Table 15.4 A/D Conversion Time (Single Mode)
CKS = 0
CKS = 1
Symbol
Min
Typ
Max
Min
Typ
Max
Synchronization delay
tD
10
—
17
6
—
9
Input sampling time
tSPL
—
63
—
—
31
—
A/D conversion time
tCONV
259
—
266
131
—
134
Note: Values in the table are numbers of states.
15.4.4
External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGE bit is set to 1 in ADCR, external
trigger input is enabled at the ADTRG pin. A high-to-low transition at the ADTRG pin sets the
ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan
modes, are the same as if the ADST bit had been set to 1 by software. Figure 15.6 shows the
timing.
φ
ADTRG
Internal trigger
signal
ADST
A/D conversion
Figure 15.6 External Trigger Input Timing
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Section 15 A/D Converter
15.5
Interrupts
The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt
request can be enabled or disabled by the ADIE bit in ADCSR.
15.6
Usage Notes
When using the A/D converter, note the following points:
1. Analog Input Voltage Range: During A/D conversion, the voltages input to the analog input
pins should be in the range AVSS ≤ ANn ≤ VREF.
2. Relationships of AVCC and AVSS to VCC and VSS: AVCC, AVSS, VCC, and VSS should be related
as follows: AVSS = VSS. AVCC and AVSS must not be left open, even if the A/D converter is not
used.
3. VREF Programming Range: The reference voltage input at the VREF pin should be in the range
VREF ≤ AVCC.
4. Analog Voltage: When using an A/D converter, make the following voltage settings.
a. VCC ≥ AVCC – 0.3V
b. AVCC ≥ VREF ≥ ANn ≥ AVSS = VSS
(N = 0 to 7)
Note: Restriction for the ZTAT version only; The S-mask version of ZTAT, the Flash
Memory version and Mask ROM version can be used regularly without restriction.
Failure to observe points 1, 2, 3, and 4 above may degrade chip reliability.
5. Note on Board Design: In board layout, separate the digital circuits from the analog circuits as
much as possible. Particularly avoid layouts in which the signal lines of digital circuits cross or
closely approach the signal lines of analog circuits. Induction and other effects may cause the
analog circuits to operate incorrectly, or may adversely affect the accuracy of A/D conversion.
The analog input signals (AN0 to AN7), analog reference voltage (VREF), and analog supply
voltage (AVCC) must be separated from digital circuits by the analog ground (AVSS). The
analog ground (AVSS) should be connected to a stable digital ground (VSS) at one point on the
board.
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Section 15 A/D Converter
6. Note on Noise: To prevent damage from surges and other abnormal voltages at the analog
input pins (AN0 to AN7) and analog reference voltage pin (VREF), connect a protection circuit
like the one in figure 15.7 between AVCC and AVSS. The bypass capacitors connected to AVCC
and VREF and the filter capacitors connected to AN0 to AN7 must be connected to AVSS. If
filter capacitors like the ones in figure 15.7 are connected, the voltage values input to the
analog input pins (AN0 to AN7) will be smoothed, which may give rise to error. Error can also
occur if A/D conversion is frequently performed in scan mode so that the current that charges
and discharges the capacitor in the sample-and-hold circuit of the A/D converter becomes
greater than that input to the analog input pins via input impedance Rin. The circuit constants
should therefore be selected carefully.
AVCC
VREF
Rin*2
*1
100 Ω
AN0 to AN7
*1
0.1 µF
AVSS
Notes: 1. Numeric values are approximate.
10 µF
0.01 µF
2. Rin: input impedance
Figure 15.7 Example of Analog Input Protection Circuit
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Section 15 A/D Converter
10 kΩ
AN0 to AN7
To A/D converter
20 pF
Note: Numeric values are approximate.
Figure 15.8 Analog Input Pin Equivalent Circuit
Table 15.5 Analog Input Pin Ratings
Item
Min
Max
Unit
Analog input capacitance
—
20
pF
Allowable signal-source impedance
—
10*
kΩ
Note: * When VCC = 4.0 V to 5.5 V and φ ≤ 12 MHz.
7. A/D Conversion Accuracy Definitions: A/D conversion accuracy in the H8/3048 Group is
defined as follows:
•
Resolution
•
Offset error
Digital output code length of A/D converter
Deviation from ideal A/D conversion characteristic of analog input voltage required to
raise digital output from minimum voltage value B'0000000000 to B'0000000001 (figure
15.10)
•
Full-scale error
Deviation from ideal A/D conversion characteristic of analog input voltage required to
raise digital output from B'1111111110 to B'1111111111 (figure 15.10)
•
Quantization error
Intrinsic error of the A/D converter; 1/2 LSB (figure 15.9)
•
Nonlinearity error
Deviation from ideal A/D conversion characteristic in range from zero volts to full scale,
exclusive of offset error, full-scale error, and quantization error.
•
Absolute accuracy
Deviation of digital value from analog input value, including offset error, full-scale error,
quantization error, and nonlinearity error.
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Section 15 A/D Converter
Digital
output
111
Ideal A/D conversion
characteristic
110
101
100
011
010
Quantization error
001
000
1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS
Analog input
voltage
Figure 15.9 A/D Converter Accuracy Definitions (1)
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Section 15 A/D Converter
Full-scale
error
Digital
output
Ideal A/D
conversion
characteristic
Nonlinearity
error
Actual A/D conversion
characteristic
FS
Offset error
Analog input
voltage
Figure 15.10 A/D Converter Accuracy Definitions (2)
8. Allowable Signal-Source Impedance: The analog inputs of the H8/3048 Group are designed to
assure accurate conversion of input signals with a signal-source impedance not exceeding 10
kΩ. The reason for this rating is that it enables the input capacitor in the sample-and-hold
circuit in the A/D converter to charge within the sampling time. If the sensor output impedance
exceeds 10 kΩ, charging may be inadequate and the accuracy of A/D conversion cannot be
guaranteed.
If a large external capacitor is provided in scan mode, then the internal 10-kΩ input resistance
becomes the only significant load on the input. In this case the impedance of the signal source
is not a problem.
A large external capacitor, however, acts as a low-pass filter. This may make it impossible to
track analog signals with high dv/dt (e.g. a variation of 5 mV/µs) (figure 15.11). To convert
high-speed analog signals or to use scan mode, insert a low-impedance buffer.
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Section 15 A/D Converter
9. Effect on Absolute Accuracy: Attaching an external capacitor creates a coupling with ground,
so if there is noise on the ground line, it may degrade absolute accuracy. The capacitor must be
connected to an electrically stable ground, such as AVSS.
If a filter circuit is used, be careful of interference with digital signals on the same board, and
make sure the circuit does not act as an antenna.
H8/3048 Group
Sensor output impedance
Sensor
input
10 kΩ
Up to 10 kΩ
Low-pass
filter
Up to 0.1 µF
Equivalent circuit of
A/D converter
Cin =
15 pF
20 pF
Figure 15.11 Analog Input Circuit (Example)
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Section 15 A/D Converter
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Section 16 D/A Converter
Section 16 D/A Converter
16.1
Overview
The H8/3048 Group includes a D/A converter with two channels.
16.1.1
Features
D/A converter features are listed below.
• Eight-bit resolution
• Two output channels
• Conversion time: maximum 10 µs (with 20-pF capacitive load)
• Output voltage: 0 V to 255/256 * VREF
• D/A outputs can be sustained in software standby mode
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Section 16 D/A Converter
16.1.2
Block Diagram
Bus interface
Figure 16.1 shows a block diagram of the D/A converter.
Module data bus
DACR
8-bit D/A
DADR1
DA 0
DADR0
AVCC
DASTCR
VREF
DA 1
AVSS
Legend
DACR: D/A control register
DADR0: D/A data register 0
DADR1: D/A data register 1
DASTCR: D/A standby control register
Control circuit
Figure 16.1 D/A Converter Block Diagram
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Internal
data bus
Section 16 D/A Converter
16.1.3
Input/Output Pins
Table 16.1 summarizes the D/A converter’s input and output pins.
Table 16.1 D/A Converter Pins
Pin Name
Abbreviation
I/O
Function
Analog power supply pin
AVCC
Input
Analog power supply
Analog ground pin
AVSS
Input
Analog ground and reference voltage
Analog output pin 0
DA0
Output
Analog output, channel 0
Analog output pin 1
DA1
Output
Analog output, channel 1
Reference voltage input pin
VREF
Input
Analog reference voltage
16.1.4
Register Configuration
Table 16.2 summarizes the D/A converter’s registers.
Table 16.2 D/A Converter Registers
Address*
Name
Abbreviation
R/W
Initial Value
H'FFDC
D/A data register 0
DADR0
R/W
H'00
H'FFDD
D/A data register 1
DADR1
R/W
H'00
H'FFDE
D/A control register
DACR
R/W
H'1F
H'FF5C
D/A standby control register
DASTCR
R/W
H'FE
Note: * Lower 16 bits of the address
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Section 16 D/A Converter
16.2
Register Descriptions
16.2.1
D/A Data Registers 0 and 1 (DADR0/1)
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The D/A data registers (DADR0 and DADR1) are 8-bit readable/writable registers that store the
data to be converted. When analog output is enabled, the D/A data register values are constantly
converted and output at the analog output pins.
The D/A data registers are initialized to H'00 by a reset and in standby mode.
16.2.2
D/A Control Register (DACR)
Bit
7
6
5
4
3
2
1
0
DAOE1
DAOE0
DAE
—
—
—
—
—
Initial value
0
0
0
1
1
1
1
1
Read/Write
R/W
R/W
R/W
—
—
—
—
—
D/A enable
Controls D/A conversion
D/A output enable 0
Controls D/A conversion and analog output
D/A output enable 1
Controls D/A conversion and analog output
DACR is an 8-bit readable/writable register that controls the operation of the D/A converter.
DACR is initialized to H'1F by a reset and in standby mode.
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Section 16 D/A Converter
Bit 7—D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output.
Bit 7: DAOE1
Description
0
DA1 analog output is disabled
1
Channel-1 D/A conversion and DA1 analog output are enabled
(Initial value)
Bit 6—D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output.
Bit 6: DAOE0
Description
0
DA0 analog output is disabled
1
Channel-0 D/A conversion and DA0 analog output are enabled
(Initial value)
Bit 5—D/A Enable (DAE): Controls D/A conversion, together with bits DAOE0 and DAOE1.
When the DAE bit is cleared to 0, analog conversion is controlled independently in channels 0 and
1. When the DAE bit is set to 1, analog conversion is controlled together in channels 0 and 1.
Output of the conversion results is always controlled independently by DAOE0 and DAOE1.
Bit 7:
DAOE1
Bit 6:
DAOE0
Bit 5:
DAE
0
0
—
D/A conversion is disabled in channels 0 and 1
1
0
D/A conversion is enabled in channel 0
Description
D/A conversion is disabled in channel 1
1
0
1
D/A conversion is enabled in channels 0 and 1
0
D/A conversion is disabled in channel 0
1
D/A conversion is enabled in channels 0 and 1
—
D/A conversion is enabled in channels 0 and 1
D/A conversion is enabled in channel 1
1
When the DAE bit is set to 1, even if bits DAOE0 and DAOE1 in DACR and the ADST bit in
ADCSR are cleared to 0, the same current is drawn from the analog power supply as during A/D
and D/A conversion.
Bits 4 to 0—Reserved: Read-only bits, always read as 1.
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Section 16 D/A Converter
16.2.3
D/A Standby Control Register (DASTCR)
DASTCR is an 8-bit readable/writable register that enables or disables D/A output in software
standby mode.
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
DASTE
Initial value
1
1
1
1
1
1
1
0
Read/Write
—
—
—
—
—
—
—
R/W
Reserved bits
D/A standby enable
Enables or disables D/A output
in software standby mode
DASTCR is initialized to H'FE by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 1—Reserved: Read-only bits, always read as 1.
Bit 0—D/A Standby Enable (DASTE): Enables or disables D/A output in software standby
mode.
Bit 0: DASTE
Description
0
D/A output is disabled in software standby mode
1
D/A output is enabled in software standby mode
Rev. 7.00 Sep 21, 2005 page 562 of 878
REJ09B0259-0700
(Initial value)
Section 16 D/A Converter
16.3
Operation
The D/A converter has two built-in D/A conversion circuits that can perform conversion
independently.
D/A conversion is performed constantly while enabled in DACR. If the DADR0 or DADR1 value
is modified, conversion of the new data begins immediately. The conversion results are output
when bits DAOE0 and DAOE1 are set to 1.
An example of D/A conversion on channel 0 is given next. Timing is indicated in figure 16.2.
1. Data to be converted is written in DADR0.
2. Bit DAOE0 is set to 1 in DACR. D/A conversion starts and DA0 becomes an output pin. The
converted result is output after the conversion time. The output value is (DADR0 contents/256)
× VREF. Output of this conversion result continues until the value in DADR0 is modified or the
DAOE0 bit is cleared to 0.
3. If the DADR0 value is modified, conversion starts immediately, and the result is output after
the conversion time.
4. When the DAOE0 bit is cleared to 0, DA0 becomes an input pin.
DADR0
write cycle
DACR
write cycle
DADR0
write cycle
DACR
write cycle
φ
Address
bus
Conversion data 1
DADR0
Conversion data 2
DAOE0
DA 0
Conversion
result 2
Conversion
result 1
High-impedance state
t DCONV
t DCONV
Legend
t DCONV : D/A conversion time
Figure 16.2 Example of D/A Converter Operation
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Section 16 D/A Converter
16.4
D/A Output Control
In the H8/3048 Group, D/A converter output can be enabled or disabled in software standby mode.
When the DASTE bit is set to 1 in DASTCR, D/A converter output is enabled in software standby
mode. The D/A converter registers retain the values they held prior to the transition to software
standby mode.
When D/A output is enabled in software standby mode, the reference supply current is the same as
during normal operation.
16.5
Usage Notes
When using an D/A converter, note the following.
1. VCC ≥ AVCC – 0.3V
2. AVCC ≥ VREF ≥ ANn ≥ AVSS = VSS
(N = 0 to 7)
Note: Restriction for the ZTATTM version only; The S Mask version of ZTATTM, the Flash
Memory version and Mask ROM version can be used regularly without restriction.
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Section 17 RAM
Section 17 RAM
17.1
Overview
The H8/3048 and H8/3047 have 4 kbytes of high-speed static RAM on-chip. The H8/3045 and
H8/3044 have 2 kbytes. The RAM is connected to the CPU by a 16-bit data bus. The CPU
accesses both byte data and word data in two states, making the RAM useful for rapid data
transfer.
The on-chip RAM of the H8/3048 and H8/3047 is assigned to addresses H'FEF10 to H'FFF0F in
modes 1, 2, 5, and 7, and to addresses H'FFEF10 to H'FFFF0F in modes 3, 4, and 6. The on-chip
RAM of the H8/3045 and H8/3044 are assigned to addresses H'FF710 to H'FFF0F in modes 1, 2,
5, and 7, and to addresses H'FFF710 to H'FFFF0F in modes 3, 4, and 6. The RAM enable bit
(RAME) in the system control register (SYSCR) can enable or disable the on-chip RAM.
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Section 17 RAM
17.1.1
Block Diagram
Figure 17.1 shows a block diagram of the on-chip RAM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
Bus interface
H'FEF10*
H'FEF11*
H'FEF12*
H'FEF13*
SYSCR
On-chip RAM
H'FFF0E*
Even addresses
Legend
SYSCR: System control register
H'FFF0F*
Odd addresses
Note: * This example is of the H8/3048 operating in mode 7. The lower 20 bits of the address
are shown.
Figure 17.1 RAM Block Diagram
17.1.2
Register Configuration
The on-chip RAM is controlled by SYSCR. Table 17.1 gives the address and initial value of
SYSCR.
Table 17.1 System Control Register
Address*
Name
Abbreviation
R/W
Initial Value
H'FFF2
System control register
SYSCR
R/W
H'0B
Note: * Lower 16 bits of the address.
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Section 17 RAM
17.2
System Control Register (SYSCR)
Bit
7
6
5
4
3
2
1
0
SSBY
STS2
STS1
STS0
UE
NMIEG
—
RAME
Initial value
0
0
0
0
1
0
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
RAM enable
Enables or
disables
on-chip RAM
Reserved bit
NMI edge select
User bit enable
Standby timer select 2 to 0
Software standby
One function of SYSCR is to enable or disable access to the on-chip RAM. The on-chip RAM is
enabled or disabled by the RAME bit in SYSCR. For details about the other bits, see section 3.3,
System Control Register (SYSCR).
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized at the rising edge of the input at the RES pin. It is not initialized in software standby
mode.
Bit 0: RAME
Description
0
On-chip RAM is disabled
1
On-chip RAM is enabled
(Initial value)
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Section 17 RAM
17.3
Operation
When the RAME bit is set to 1, the on-chip RAM is enabled. Accesses to addresses H'FEF10 to
H'FFF0F in the H8/3048 and H8/3047 in modes 1, 2, 5, and 7, addresses H'FFEF10 to H'FFFF0F
in the H8/3048 and H8/3047 in modes 3, 4, and 6, addresses H'FF710 to H'FFF0F in the H8/3045
and H8/3044 in modes 1, 2, 5, and 7, and addresses H'FFF710 to H'FFFF0F in the H8/3045 and
H8/3044 in modes 3, 4, and 6 are directed to the on-chip RAM. In modes 1 to 6 (expanded
modes), when the RAME bit is cleared to 0, the off-chip address space is accessed. In mode 7
(single-chip mode), when the RAME bit is cleared to 0, the on-chip RAM is not accessed: read
access always results in H'FF data, and write access is ignored.
Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written
and read by word access. It can also be written and read by byte access. Byte data is accessed in
two states using the upper 8 bits of the data bus. Word data starting at an even address is accessed
in two states using all 16 bits of the data bus.
Rev. 7.00 Sep 21, 2005 page 568 of 878
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Section 18 ROM
Section 18 ROM
(H8/3048ZTAT and Mask-ROM Versions)
18.1
Overview
The H8/3048 has 128 kbytes of on-chip ROM, the H8/3047 has 96 kbytes, the H8/3045 has
64 kbytes and the H8/3044 has 32 kbytes. The ROM is connected to the CPU by a 16-bit data bus.
The CPU accesses both byte data and word data in two states, enabling rapid data transfer.
The mode pins (MD2 to MD0) can be set to enable or disable the on-chip ROM as indicated in
table 18.1.
Table 18.1 Operating Mode and ROM
Mode Pins
Mode
MD2
MD1
MD0
On-Chip ROM
Mode 1
(1-Mbyte expanded mode with on-chip ROM disabled)
0
0
1
Mode 2
(1-Mbyte expanded mode with on-chip ROM disabled)
0
1
0
Disabled
(external
address area)
Mode 3
(16-Mbyte expanded mode with on-chip ROM disabled)
0
1
1
Mode 4
(16-Mbyte expanded mode with on-chip ROM disabled)
1
0
0
Mode 5
(1-Mbyte expanded mode with on-chip ROM enabled)
1
0
1
Mode 6
(16-Mbyte expanded mode with on-chip ROM enabled)
1
1
0
Mode 7 (single-chip mode)
1
1
1
Enabled
The PROM version (H8/3048ZTAT) can be set to PROM mode and programmed with a generalpurpose PROM programmer.
Note: Care is required when changing from the H8/3048F-ONE to a model with on-chip mask
ROM (H8/3048, H8/3047, H8/3045, or H8/3044).
For details, refer to the H8/3048F-ONE Hardware Manual (Rev. 1.0) 1.4.5, Note on
Changeover to Mask ROM Version.
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Section 18 ROM
18.1.1
Block Diagram
Figure 18.1 shows a block diagram of the ROM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
Bus interface
H'0000
H'0001
H'0002
H'0003
On-chip ROM
H'1FFFE
H'1FFFF
Even addresses
Odd addresses
Figure 18.1 ROM Block Diagram (H8/3048, Mode 7)
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Section 18 ROM
18.2
PROM Mode
18.2.1
PROM Mode Setting
In PROM mode, the H8/3048 (H8/3048ZTAT) version with on-chip PROM suspends its
microcontroller functions, enabling the on-chip PROM to be programmed. The programming
method is the same as for the HN27C101, except that page programming is not supported. Table
18.2 indicates how to select PROM mode.
Table 18.2 Selecting PROM Mode
Pins
Setting
Three mode pins (MD2, MD1, MD0)
Low
STBY pin
P51 and P50
18.2.2
High
Socket Adapter and Memory Map
The PROM is programmed using a general-purpose PROM programmer with a socket adapter to
convert to 32 pins. Table 18.3 lists the socket adapter for each package option. Figure 18.2 shows
the pin assignments of the socket adapter. Figure 18.3 shows a memory map in PROM mode.
Table 18.3 Socket Adapter
Microcontroller
Package
Socket Adapter
H8/3048
100-pin QFP (FP-100B)
HS3042ESHS1H
100-pin TQFP (TFP-100B)
HS3042ESNS1H
The size of the H8/3048 PROM is 128 kbytes. Figure 18.3 shows a memory map in PROM mode.
H'FF data should be specified for unused address areas in the on-chip PROM.
When programming the H8/3048 with a PROM programmer, set the address range to H'00000 to
H'1FFFF.
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Section 18 ROM
H8/3048
FP-100B, TFP-100B
10
64
58
87
88
27
28
29
30
31
32
33
34
36
37
38
39
40
41
42
43
45
46
47
48
49
50
51
52
53
54
77
76
1
35
68
73
74
75
62
86
11
22
44
57
65
92
Pin
RESO
NMI
P6 0
P8 0
P8 1
P3 0
P3 1
P3 2
P3 3
P3 4
P3 5
P3 6
P3 7
P1 0
P1 1
P1 2
P1 3
P1 4
P1 5
P1 6
P1 7
P2 0
P2 1
P2 2
P2 3
P2 4
P2 5
P2 6
P2 7
P5 0
P5 1
VREF
AVCC
VCC
VCC
VCC
MD0
MD1
MD2
STBY
AVSS
VSS
VSS
VSS
VSS
VSS
VSS
Pin
VPP
EA 9
EA15
EA16
PGM
EO0
EO1
EO2
EO3
EO4
EO5
EO6
EO7
EA 0
EA 1
EA 2
EA 3
EA 4
EA 5
EA 6
EA 7
EA 8
OE
EA 10
EA 11
EA 12
EA 13
EA 14
CE
VCC
PROM Socket
HN27C101 (32 Pins)
1
26
3
2
31
13
14
15
17
18
19
20
21
12
11
10
9
8
7
6
5
27
24
23
25
4
28
29
22
32
VSS
Legend
V PP :
EO 7 to EO0 :
EA16 to EA 0 :
OE:
CE:
PGM:
16
Programming voltage (12.5 V)
Data input/output
Address input
Output enable
Chip enable
Program
Note: Pins not shown in this diagram should be left open.
This figure shows pin assignments, and does not show the entire socket adapter circuit. When undertaking a new design,
board design (power supply voltage stabilization, noise countermeasures, etc.) as a high-speed CMOS LSI is necessary.
Figure 18.2 Socket Adapter Pin Assignments
Rev. 7.00 Sep 21, 2005 page 572 of 878
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Section 18 ROM
Address in
MCU mode
Address in
PROM mode
H'00000
H'00000
On-chip PROM
H'1FFFF
H'1FFFF
Figure 18.3 H8/3048ZTAT Memory Map in PROM Mode
18.3
PROM Programming
Table 18.4 indicates how to select the program, verify, and other modes in PROM mode.
Table 18.4 Mode Selection in PROM Mode
Pins
Mode
CE
OE
PGM
VPP
VCC
EO7 to EO0
EA16 to EA0
Program
L
H
L
VPP
VCC
Data input
Address input
Verify
L
L
H
VPP
VCC
Data output
Address input
Program inhibited
L
L
L
VPP
VCC
High impedance
Address input
L
H
H
H
L
L
H
H
H
Legend
L: Low voltage level
H: High voltage level
VPP: VPP voltage level
VCC:VCC voltage level
Read/write specifications are the same as for the standard HN27C101 EPROM, except that page
programming is not supported. Do not select page programming mode. A PROM programmer that
supports only page-programming mode cannot be used. When selecting a PROM programmer,
check that it supports a byte-at-a-time high-speed programming mode. Be sure to set the address
range to H'00000 to H'1FFFF.
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Section 18 ROM
18.3.1
Programming and Verification
An efficient, high-speed programming procedure can be used to program and verify PROM data.
This procedure programs the chip quickly without subjecting it to voltage stress and without
sacrificing data reliability. Unused address areas contain H'FF data. Figure 18.4 shows the basic
high-speed programming flowchart. Tables 18.5 and 18.6 list the electrical characteristics of the
chip during programming. Figure 18.5 shows a timing chart.
Start
V
Set programming/verification mode
6.0 V ± 0.25 V, V PP = 12.5 V ± 0.3 V
CC=
Address = 0
n=0
n + 1→ n
No
Yes
n < 25
Program with t PW = 0.2 ms ± 5%
No
Address + 1 → address
Verification OK?
Yes
Program with t OPW = 0.2n ms
Last address?
No
Yes
Set read mode
V CC = 5.0 V ± 0.25 V, VPP = V CC
No
Fail
All addresses
read?
Yes
End
Figure 18.4 High-Speed Programming Flowchart
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Section 18 ROM
Table 18.5 DC Characteristics in PROM Mode
(Conditions: VCC = 6.0 V ± 0.25 V, VPP = 12.5 V ± 0.3 V, VSS = 0 V, Ta = 25°C ± 5°C)
Item
Symbol
Min
Typ
Max
Unit
Test Conditions
Input high
voltage
EO7 to EO0,
EA16 to EA0,
OE, CE, PGM
VIH
2.4
—
VCC + 0.3
V
Input low
voltage
EO7 to EO0,
EA16 to EA0,
OE, CE, PGM
VIL
–0.3
—
0.8
V
Output high
voltage
EO7 to EO0
VOH
2.4
—
—
V
IOH = –200 µA
Output low
voltage
EO7 to EO0
VOL
—
—
0.45
V
IOL = 1.6 mA
Input leakage
current
EO7 to EO0,
EA16 to EA0,
OE, CE, PGM
|ILI|
—
—
2
µA
Vin = 5.25 V/0.5 V
VCC current
ICC
—
—
40
mA
VPP current
IPP
—
—
40
mA
Note: For details on absolute maximum ratings, see section 22.1.1, Absolute Maximum Ratings.
Using an LSI in excess of absolute maximum ratings may result in permanent damage.
VPP peak overshoot should not exceed 13 V.
Rev. 7.00 Sep 21, 2005 page 575 of 878
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Section 18 ROM
Table 18.6 AC Characteristics in PROM Mode
(Conditions: VCC = 6.0 V ± 0.25 V, VPP = 12.5 V ± 0.3 V, Ta = 25°C ± 5°C)
Item
Symbol
Min
Typ
Max
Unit
Test Conditions
Address setup time
tAS
2
—
—
µs
Figure 18.5*
OE setup time
tOES
2
—
—
µs
Data setup time
tDS
2
—
—
µs
Address hold time
tAH
0
—
—
µs
Data hold time
tDH
2
—
—
µs
2
Data output disable time
tDF*
—
—
130
ns
VPP setup time
tVPS
2
—
—
µs
Programming pulse width
tPW
0.19
0.20
0.21
ms
PGM pulse width for overwrite
programming
tOPW *
0.19
—
5.25
ms
VCC setup time
tVCS
2
—
—
µs
CE setup time
tCES
2
—
—
µs
Data output delay time
tOE
0
—
150
ns
3
Notes: 1. Input pulse level: 0.8 V to 2.2 V
Input rise time and fall time ≤ 20 ns
Timing reference levels: 1.0 V and 2.0 V for input; 0.8 V and 2.0 V for output
2. tDF is defined at the point where the output is in the open state and the output level
cannot be read.
3. tOPW is defined by the value given in the flowchart.
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1
Section 18 ROM
Program
Verify
Address
tAH
tAS
Data
Input data
tDS
VPP
VCC
Output data
tDH
tDF
VPP
VCC
tVPS
VCC+1
VCC
tVCS
CE
tCES
PGM
tPW
OE
tOES
tOE
tOPW*
Note: * t OPW is defined by the value given in the flowchart.
Figure 18.5 PROM Program/Verify Timing
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Section 18 ROM
18.3.2
Programming Precautions
• Program with the specified voltages and timing.
The programming voltage (VPP) in PROM mode is 12.5 V.
Applied voltages in excess of the rated values can permanently destroy the chip. Be
particularly careful about the PROM programmer’s overshoot characteristics.
If the PROM programmer is set to Renesas Technology HN27C101 specifications, VPP will be
12.5 V.
• Before programming, check that the chip is correctly mounted in the PROM programmer.
Overcurrent damage to the chip can result if the index marks on the PROM programmer,
socket adapter, and chip are not correctly aligned.
• Don’t touch the socket adapter or chip while programming. Touching either of these can cause
contact faults and write errors.
• Select the programming mode carefully. The chip cannot be programmed in page
programming mode.
• The H8/3048 PROM size is 128 kbytes. Set the address range to H'00000 to H'1FFFF.
Rev. 7.00 Sep 21, 2005 page 578 of 878
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Section 18 ROM
18.3.3
Reliability of Programmed Data
A highly effective way to improve data retention characteristics is to bake the programmed chips
at 150°C, then screen them for data errors. This procedure quickly eliminates chips with PROM
memory cells prone to early failure.
Figure 18.6 shows the recommended screening procedure.
Program chip and verify programmed data
Bake chip for 24 to 48 hours at
125 C to 150 C with power off
Read and check program
Install
Figure 18.6 Recommended Screening Procedure
If a series of programming errors occurs while the same PROM programmer is in use, stop
programming and check the PROM programmer and socket adapter for defects. Please inform
Renesas Technology of any abnormal conditions noted during or after programming or in
screening of program data after high-temperature baking.
Rev. 7.00 Sep 21, 2005 page 579 of 878
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Section 18 ROM
18.4
Notes on Ordering Mask ROM Version Chip
When ordering the H8/3048 Group chips with a mask ROM, note the following.
• When ordering through an EPROM, use a 128-kbyte one.
• Fill all the unused addresses with H'FF as shown in figure 18.7 to make the ROM data size 128
kbytes for all H8/3048 Group chips, which incorporate different sizes of ROM. This applies to
ordering through an EPROM and through electrical data transfer.
HD6433048
(ROM: 128 kbytes)
Address:
H'00000–H'1FFFF
HD6433047
(ROM: 96 kbytes)
Address:
H'00000–H'17FFF
H'00000
HD6433045
(ROM: 64 kbytes)
Address:
H'00000–H'0FFFF
H'00000
HD6433044
(ROM: 32 kbytes)
Address:
H'00000–H'07FFF
H'00000
H'00000
H'07FFF
H'08000
H'0FFFF
H'10000
Not used*
H'17FFF
H'18000
Not used*
Not used*
H'1FFFF
H'1FFFF
H'1FFFF
Note: * Program H'FF to all addresses in these areas.
Figure 18.7 Masked ROM Addresses and Data
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H'1FFFF
Section 18 ROM
• The flash memory control registers (FLMCR, EBR1, EBR2, and RAMCR)* for use only by
the on-chip flash memory version (H8/3048F (dual-power-supply model)) are not provided in
the mask ROM version. Reading a corresponding address will always return a value of 1, and
writes to the corresponding addresses are invalid. This point must be noted when switching
from a flash memory model to a mask ROM version.
• In the case of the H8/3048F-ONE (single-power-supply model) on-chip flash memory version,
the 5 V version has a VCL pin and requires connection of an external capacitor. Care is
therefore required with the board design when switching to a mask ROM version. (For details,
see section 1.4.5, Notes on Switching to Mask ROM Version, in the H8/3048F-ONE Hardware
Manual (First Edition).
Note: * In the H8/3048F-ONE with on-chip flash memory, the flash memory control registers are
FLMCR1, FLMCR2, EBR, and RAMCR. (For details, see appendix B, Internal I/O
Registers, in the H8/3048F-ONE Hardware Manual (First Edition)).
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Section 18 ROM
Rev. 7.00 Sep 21, 2005 page 582 of 878
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
Section 19 Flash Memory
(H8/3048F: Dual Power Supply (VPP = 12 V))
19.1
Overview
The H8/3048F has 128 kbytes of on-chip flash memory. The flash memory is connected to the
CPU by a 16-bit data bus. The CPU accesses both byte data and word data in two states, enabling
rapid data transfer.
The mode pins (MD2 to MD0) can be set to enable or disable the on-chip ROM as indicated in
table 19.1.
Table 19.1 Operating Mode and ROM
Mode Pins
Mode
MD2
MD1
MD0
On-Chip ROM
Mode 1
(1-Mbyte expanded mode with on-chip ROM disabled)
0
0
1
Mode 2
(1-Mbyte expanded mode with on-chip ROM disabled)
0
1
0
Disabled
(external
address area)
Mode 3
(16-Mbyte expanded mode with on-chip ROM disabled)
0
1
1
Mode 4
(16-Mbyte expanded mode with on-chip ROM disabled)
1
0
0
Mode 5
(1-Mbyte expanded mode with on-chip ROM enabled)
1
0
1
Mode 6
(16-Mbyte expanded mode with on-chip ROM enabled)
1
1
0
Mode 7 (single-chip mode)
1
1
1
Enabled
The H8/3048F (dual-power supply flash memory version) can be set to PROM mode and
programmed with a general-purpose PROM programmer.
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
19.2
Flash Memory Overview
19.2.1
Flash Memory Operation
Table 19.2 illustrates the principle of operation of the on-chip flash memory of the H8/3048F
(dual-power supply).
Like EPROM, flash memory is programmed by applying a high gate-to-drain voltage that draws
hot electrons generated in the vicinity of the drain into a floating gate. The threshold voltage of a
programmed memory cell is therefore higher than that of an erased cell. Cells are erased by
grounding the gate and applying a high voltage to the source, causing the electrons stored in the
floating gate to tunnel out. After erasure, the threshold voltage drops. A memory cell is read like
an EPROM cell, by driving the gate to the high level and detecting the drain current, which
depends on the threshold voltage. Erasing must be done carefully, because if a memory cell is
overerased, its threshold voltage may become negative, causing the cell to operate incorrectly.
Section 19.5.6, Erasing Flowchart and Sample Program shows an optimal erase control flowchart
and sample program.
Table 19.2 Principle of Memory Cell Operation
Erase
Program
Memory
cell
Memory
array
Read
Vg = VPP
Vg = VCC
Vs = VPP
Vd
Vd
0V
Open
Open
Open
Vd
Vd
0V
VPP
0V
VCC
0V
VPP
0V
0V
0V
0V
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
19.2.2
Mode Programming and Flash Memory Address Space
As its on-chip ROM, the H8/3048F has 128 kbytes of flash memory. The flash memory is
connected to the CPU by a 16-bit data bus. The CPU accesses both byte data and word data in two
states.
The flash memory is assigned to addresses H'00000 to H'1FFFF on the memory map. The mode
pins enable either on-chip flash memory or external memory to be selected for this area. Table
19.3 summarizes the mode pin settings and usage of the flash memory area.
Table 19.3 Mode Pin Settings and Flash Memory Area
Mode Pin Setting
Mode
MD2
MD1
MD0
Flash Memory Area Usage
Mode 0
0
0
0
Illegal setting
Mode 1
0
0
1
External memory area
Mode 2
0
1
0
External memory area
Mode 3
0
1
1
External memory area
Mode 4
1
0
0
External memory area
Mode 5
1
0
1
On-chip flash memory area
Mode 6
1
1
0
On-chip flash memory area
Mode 7
1
1
1
On-chip flash memory area
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
19.2.3
Features
Features of the flash memory are listed below.
• Five flash memory operating modes
The flash memory has five operating modes: program mode, program-verify mode, erase
mode, erase-verify mode, and prewrite-verify mode.
• Block erase designation
Blocks to be erased in the flash memory address space can be selected by bit settings. The
address space includes a large-block area (eight blocks with sizes from 12 kbytes to 16 kbytes)
and a small-block area (eight 512-byte blocks).
• Program and erase time
Programming one byte of flash memory typically takes 50 µs. Erasing all blocks (128 kbytes)
typically takes 1 s.
• Erase-program cycles
Flash memory contents can be erased and reprogrammed up to 100 times.
• On-board programming modes
These modes can be used to program, erase, and verify flash memory contents. There are two
modes: boot mode, and user programming mode.
• Automatic bit-rate alignment
In boot-mode data transfer, the H8/3048F aligns its bit rate automatically to the host bit rate
(9600 bps, 4800 bps and 2400 bps).
• Flash memory emulation by RAM
Part of the RAM area can be overlapped onto flash memory, to emulate flash memory updates
in real time.
• PROM mode
As an alternative to on-board programming, the flash memory can be programmed and erased
in PROM mode, using a general-purpose PROM programmer.
• Protect modes
Flash memory can be program-, erase-, and/or verify-protected in hardware and software
protect modes.
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
19.2.4
Block Diagram
Figure 19.1 shows a block diagram of the flash memory.
8
Internal data bus (upper)
8
Internal data bus (lower)
FLMCR
Bus interface and control section
EBR1
H'00000
H'00001
H'00002
H'00003
H'00004
H'00005
On-chip flash memory
(128 kbytes)
H'1FFFC
H'1FFFD
H'1FFFE
H'1FFFF
EBR2
Upper byte
(even address)
Operating
mode
MD2
MD1
MD0
Lower byte
(odd address)
Legend
FLMCR: Flash memory control register*
EBR1: Erase block register 1*
EBR2: Erase block register 2*
Note: * The flash memory control registers (FLMCR, EBR1, and EBR2) and RAMCR are
used only by the flash memory version, and must not be accessed in the mask
ROM (ZTAT) version.
Figure 19.1 Flash Memory Block Diagram
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
19.2.5
Input/Output Pins
Flash memory is controlled by the pins listed in table 19.4.
Table 19.4 Flash Memory Pins
Pin Name
Abbreviation
Input/Output
Function
Programming power
VPP
Power supply
Apply 12.0 V
Mode 2
MD2
Input
H8/3048F operating mode
programming
Mode 1
MD1
Input
H8/3048F operating mode
programming
Mode 0
MD0
Input
H8/3048F operating mode
programming
Transmit data
TXD1
Output
Serial transmit data output
Receive data
RXD1
Input
Serial receive data input
The transmit data and receive data pins are used in boot mode.
19.2.6
Register Configuration
The flash memory is controlled by the registers listed in table 19.5.
Table 19.5 Flash Memory Registers
Address
Name
H'FF40
3
Flash memory control register*
Abbreviation
R/W
Initial Value
FLMCR
2
R/W *
H'00*
H'FF42
Erase block register 1*
3
EBR1
R/W *
2
H'00*
H'FF43
Erase block register 2*
3
EBR2
R/W *
2
H'00*
H'FF48
RAM control register
RAMCR
R/W
H'70
1
1
1
Notes: 1. The initial value is H'00 in modes 5, 6, and 7 (on-chip flash memory enabled).
2. In modes 1, 2, 3, and 4 (on-chip flash memory disabled), this register cannot be
modified and is always read as H'FF.
3. Dedicated registers for controlling flash memory, which are not provided by the maskROM and ZTAT versions. Therefore, these registers must not be accessed in the maskROM and ZTAT versions. These registers cannot be modified in the mask-ROM and
ZTAT versions.
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
19.3
Flash Memory Register Descriptions
19.3.1
Flash Memory Control Register
The flash memory control register (FLMCR) is an eight-bit register that controls the flash memory
operating modes. Transitions to program mode, erase mode, program-verify mode, and eraseverify mode are made by setting bits in this register. FLMCR is initialized to H'00 by a reset, in
the standby modes, and when 12 V is not applied to VPP. When 12 V is applied to VPP, a reset or
entry to a standby mode initializes FLMCR to H'80.
Bit
Initial value*
R/W
7
6
5
4
3
2
1
0
VPP
VPP E
—
—
EV
PV
E
P
0
0
0
0
0
0
0
0
—
R/W*
R/W*
R/W *
R/W *
R
R/W
—
Program mode
Designates
transition to
or exit from
program mode
Erase mode
Designates transition
to or exit from erase
mode
Program-verify mode
Designates transition to
or exit from program-verify
mode
Erase-verify mode
Designates transition to
or exit from erase-verify
mode
Reserved bits
VPP enable
Disables or enables 12-V
application to VPP pin
Programming power
Status flag indicating the
power to VPP
Note: * The initial value is H'00 in modes 5, 6, and 7 (on-chip flash memory enabled). In modes
1, 2, 3, and 4 (on-chip flash memory disabled), this register cannot be modified and is
always read as H'FF.
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
Bit 7—Programming Power (VPP): Programming power bit (VPP) detects VPP, and level is
displayed as “1” or “0.” The permissible output currents for impressed high voltage VH are given
in 22.2.2, “DC Characteristics.” The value of VH ranges from VCC + 2 V to 11.4 V. If a voltage in
excess of VH is applied, “1” is displayed; otherwise “0” is displayed.
This bit restricts the hardware protect functions during write and erase operations for the flash
memory. For details on hardware protect, see section 19.5.8, “Protect Modes.” For notes on VPP
usage, see section 19.8, “Flash Memory Programming and Erasing Precautions (Dual-Power
Supply).”
Bit 7: VPP
Description
0
[Clear condition]
(Initial value)
This is the regular operational mode when a voltage exceeding VH is not
applied to the VPP pin. The flash memory cannot be written or erased.
“Hardware Protect” is displayed.
1
[Set condition]
This is the operational mode when a voltage exceeding VH is applied to the
VPP pin. The flash memory can be written and erased. “Hardware Protect
Disabled” is displayed*.
Note: * For correct write and erase functions, the setting should be VPP = 12.0 V to 0.6 V (11.4 V to
12.6 V).
Bit 6—VPP Enable (VPPE): Disables or enables 12-V application to the VPP pin. After this bit is
set, it is necessary to wait for at least 5 µs for the internal power supply to stabilize; programming
and erasing cannot be performed until stabilization is complete. After this bit is cleared, it is
necessary to wait for the flash memory read setup time (tFRS) in order to read flash memory.
Bit 6: VPPE
Description
0
VPP pin 12-V power supply is disabled
1
VPP pin 12-V supply is enabled
(Initial value)
Note: The power supply system used for the flash memory is switched by means of the VppE bit.
After switching, operation is not guaranteed during the period before the power supply
system stabilizes. It is therefore prohibited to fetch from flash memory and execute an
instruction that sets or resets the VppE bit.
Bits 5 and 4—Reserved: Read-only bits, always read as 0.
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
Bit 3—Erase-Verify Mode (EV)*1: Selects transition to or exit from erase-verify mode.
Bit 3: EV
Description
0
Exit from erase-verify mode
1
Transition to erase-verify mode
(Initial value)
Bit 2—Erase-Verify Mode (PV)*1: Selects transition to or exit from program-verify mode.
Bit 2: PV
Description
0
Exit from program-verify mode
1
Transition to program-verify mode
(Initial value)
Bit 1—Erase Mode (E)*1 *2: Selects transition to or exit from erase mode.
Bit 1: E
Description
0
Exit from erase mode
1
Transition to erase mode
(Initial value)
Bit 0—Program Mode (P)*1 *2: Selects transition to or exit from program mode.
Bit 0: P
Description
0
Exit from program mode
1
Transition to program mode
(Initial value)
Notes: 1. Do not set two or more of these bits simultaneously. Do not turn off power supply
(VCC–VPP) while a bit is set.
2. For each bit setting procedure, follow the algorithm described in section 19.5,
Programming and Erasing Flash Memory. For the notes on programming and erasing,
refer to section 19.8, Flash Memory Programming and Erasing Precautions (DualPower Supply). Particularly, be sure to set the watchdog timer beforehand to prevent
program runaway, when the E or P bit is set.
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
19.3.2
Erase Block Register 1
Erase block register 1 (EBR1) is an eight-bit register that designates large flash-memory blocks for
programming and erasure. EBR1 is initialized to H'00 by a reset, in the standby modes, when 12 V
is applied to VPP while the VPPE bit is 0, and when 12 V is not applied to VPP. When a bit in EBR1
is set to 1, the corresponding block is selected and can be programmed and erased. Figure 19.2
shows a block map.
Bit
7
6
5
4
3
2
1
0
LB7
LB6
LB5
LB4
LB3
LB2
LB1
LB0
Initial value*
0
0
0
0
0
0
0
0
Read/Write
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
Note: * The initial value is H'00 in modes 5, 6, and 7 (on-chip flash memory enabled). In modes 1,
2, 3, and 4 (on-chip flash memory disabled), this register cannot be modified and is always
read as H'FF.
Bits 7 to 0—Large Block 7 to 0 (LB7 to LB0): These bits select large blocks (LB7 to LB0) to be
programmed and erased.
Bits 7 to 0:
LB7 to LB0
Description
0
Block LB7 to LB0 is not selected
1
Block LB7 to LB0 is selected
Rev. 7.00 Sep 21, 2005 page 592 of 878
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(Initial value)
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
19.3.3
Erase Block Register 2
Erase block register 2 (EBR2) is an eight-bit register that designates small flash-memory blocks
for programming and erasure. EBR2 is initialized to H'00 by a reset, in the standby modes, when
12 V is applied to VPP while the VPPE bit is 0, and when 12 V is not applied to VPP. When a bit in
EBR2 is set to 1, the corresponding block is selected and can be programmed and erased. Figure
19.2 shows a block map.
Bit
7
6
5
4
3
2
1
0
SB7
SB6
SB5
SB4
SB3
SB2
SB1
SB0
Initial value*
0
0
0
0
0
0
0
0
Read/Write
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
Note: * The initial value is H'00 in modes 5, 6, and 7 (on-chip flash memory enabled). In modes 1,
2, 3, and 4 (on-chip flash memory disabled), this register cannot be modified and is always
read as H'FF.
Bits 7 to 0—Small Block 7 to 0 (SB7 to SB0): These bits select small blocks (SB7 to SB0) to be
programmed and erased.
Bits 7 to 0:
SB7 to SB0
Description
0
Block SB7 to SB0 is not selected
1
Block SB7 to SB0 is selected
(Initial value)
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
Bit
Addresses
LB0
H'00000–H'03FFF
LB1
H'04000–H'07FFF
LB2
H'08000–H'0BFFF
LB3
H'0C000–H'0FFFF
LB4
H'10000–H'13FFF
LB5
H'14000–H'17FFF
LB6
H'18000–H'1BFFF
LB7
H'1C000-H'1EFFF
SB0
H'1F000–H'1F1FF
SB1
H'1F200–H'1F3FF
SB2
H'1F400–H'1F5FF
SB3
H'1F600–H'1F7FF
SB4
H'1F800–H'1F9FF
SB5
H'1FA00–H'1FBFF
SB6
H'1FC00–H'1FDFF
SB7
H'1FE00–H'1FFFF
H'00000
Large block
area
(124 kbytes)
Small block
area
(4 kbytes)
H'03FFF
H'04000
H'07FFF
H'08000
H'0BFFF
H'0C000
H'0FFFF
H'10000
H'13FFF
H'14000
H'17FFF
H'18000
H'1BFFF
H'1C000
H'1EFFF
H'1F000
H'1F1FF
H'1F200
H'1F3FF
H'1F400
H'1F5FF
H'1F600
H'1F7FF
H'1F800
H'1F9FF
H'1FA00
H'1FBFF
H'1FC00
H'1FDFF
H'1FE00
H'1FFFF
Figure 19.2 Erase Block Map
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16 kbytes
16 kbytes
16 kbytes
16 kbytes
16 kbytes
16 kbytes
16 kbytes
12 kbytes
512 bytes
512 bytes
512 bytes
512 bytes
512 bytes
512 bytes
512 bytes
512 bytes
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
19.3.4
RAM Control Register (RAMCR)
The RAM control register (RAMCR) enables flash-memory updates to be emulated in RAM, and
indicates flash memory errors.
Bit
7
6
5
4
3
2
1
0
FLER
—
—
—
RAMS
RAM2
RAM1
RAM0
Initial value
0
1
1
1
0
0
0
0
Read/Write
R
—
—
—
R/W
R/W
R/W
R/W
Bit 7—Flash Memory Error (FLER): Indicates that an error occurred while flash memory was
being programmed or erased. When bit 7 is set, flash memory is placed in an error-protect mode.*1
Bit 7: FLER
Description
0
Flash memory is not write/erase-protected (is not in error protect mode* )
(Initial value)
1
[Clearing condition]
Reset or hardware standby mode
1
Indicates that an error occurred while flash memory was being programmed or
1
erased, and error protection* is in effect
[Setting conditions]
2
Flash memory was read* while being programmed or erased (including vector
or instruction fetch, but not including reading of a RAM area overlapped onto
flash memory).
A hardware exception-handling sequence (other than a reset, trace exception,
invalid instruction, trap instruction, or zero-divide exception) was executed just
before programming or erasing.
The SLEEP instruction (for transition to sleep mode or software standby mode)
was executed during programming or erasing.
A bus was released during programming or erasing.
Notes: 1. For details, see section 19.5.8, Protect Modes.
2. The read data has undetermined values.
Bits 6 to 4—Reserved: Read-only bits, always read as 1.
Bit 3—RAM Select (RAMS)*: Is used with bits 2 to 0 to reassign an area to RAM (see table
19.6). When bit 3 is set, all flash-memory blocks are protected from programming and erasing,
regardless of the values of bits 2 to 0.
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
It is initialized by a reset and in hardware standby mode. It is not initialized in software standby
mode.
Bits 2 to 0—RAM2 to RAM0*: These bits are used with bit 3 to reassign an area to RAM (see
table 19.6). They are initialized by a reset and in hardware standby mode. They are not initialized
in software standby mode.
Note: * These bits can be written to in modes 5, 6, and 7 (on-chip flash memory enabled). In other
modes, they are always read as 0 and cannot be modified.
Table 19.6 RAM Area Reassignment
Bit 3
Bit 2
Bit 1
Bit 0
RAM Area
RAMS
RAM2
RAM1
RAM0
H'FFF000 to H'FFF1FF
0
0/1
0/1
0/1
H'01F000 to H'01F1FF
1
0
0
0
H'01F200 to H'01F3FF
1
0
0
1
H'01F400 to H'01F5FF
1
0
1
0
H'01F600 to H'01F7FF
1
0
1
1
H'01F800 to H'01F9FF
1
1
0
0
H'01FA00 to H'01FBFF
1
1
0
1
H'01FC00 to H'01FDFF
1
1
1
0
H'01FE00 to H'01FFFF
1
1
1
1
19.4
On-Board Programming Modes
When an on-board programming mode is selected, the on-chip flash memory can be programmed,
erased, and verified. There are two on-board programming modes: boot mode, and user program
mode. These modes are selected by inputs at the mode pins (MD2 to MD0) and VPP pin. Table 19.7
indicates how to select the on-board programming modes. For information about turning VPP on
and off, see note (4) in section 19.8, Flash Memory Programming and Erasing Precautions (DualPower Supply).
Rev. 7.00 Sep 21, 2005 page 596 of 878
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
Table 19.7 On-Board Programming Mode Selection
Mode Selections
Boot mode
User program
mode
19.4.1
VPP
MD2
MD1
MD0
Notes
12 V
12 V
0
1
0: VIL
Mode 6
12 V
1
0
1: VIH
Mode 7
12 V
1
1
Mode 5
1
0
1
Mode 6
1
1
0
Mode 7
1
1
1
Mode 5
Boot Mode
To use boot mode, a user program for programming and erasing the flash memory must be
provided in advance on the host machine (which may be a personal computer). Serial
communication interface 1 (SCI1) is used in asynchronous mode (see figure 19.3). If the
H8/3048F is placed in boot mode, after it comes out of reset, a built-in boot program is activated.
This program starts by measuring the low period of data transmitted from the host and setting the
bit rate register (BRR) accordingly. The H8/3048F’s built-in serial communication interface (SCI)
can then be used to download the user program from the host machine. The user program is stored
in on-chip RAM.
After the program has been stored, execution branches to address H'FF300 in modes 5 and 6 and
H'FFF300 in mode 7 in the on-chip RAM, and the program stored on RAM is executed to program
and erase the flash memory. Figure 19.4 shows the boot-mode execution procedure.
H8/3048F
Receive data to be programmed
HOST
Transmit verification data
RXD1
SCI1
TXD1
Figure 19.3 Boot-Mode System Configuration
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
Boot-Mode Execution Procedure: Figure 19.4 shows the boot-mode execution procedure.
Start
1. Program the H8/3048F pins for boot mode, and start the
H8/3048F from a reset.
1
Program H8/3048F pins for
boot mode, and resets.
2
Host transmits H'00 data
continuously at desired bit rate.
2. Set the host's data format to 8 bits + 1 stop bit, select the
desired bit rate (2400, 4800 or 9600), and transmit H'00
data continuously.
H8/3048F measures H'00 low period
for data transmitted from the host.
3. H8/3048F measures the duration of repeat when the RDX
pin is "Low," then computes the bit rate of the serial
transmission from the host.
H8/3048F computes the bit rate, then
sets the value in the bit rate register.
4. After H8/3048F completes SCI bit rate adjustment, one byte
of H'00 data is transmitted to indicate completion.
4
After completing bit rate adjustment,
H8/3048F transmits one H'00 byte to the
host to indicate completion.
5. On receiving one byte from H8/3048F to indicate completion
of bit rate adjustment, the host confirms regular reception
then transmits one byte of H'55. H8/3048F transmits H'AA to
indicate regular reception.
5
The host confirms that bit rate
adjustment was completed successfully,
then transmits one H'55 byte.
6
H8/3048F receives, as 2 bytes,
number of program bytes (N) to be
transferred to on-chip RAM*1
3
6. The host transmits the number of user program bytes to be
transferred to the H8/3048F. The number of bytes should
be sent as two bytes, upper byte followed by lower byte.
The host should then sequentially transmit the program set
by the user.
The H8/3048F transmits the received byte count and user
program sequentially to the host, one byte at a time, as
verify data (echo-back).
H8/3048F transfers user
program to RAM*2
7. The H8/3048F sequentially writes the received user
program to on-chip RAM area H'FFF300 to H'FFFEFF.
8. The H8/3048F transfers part of the boot program to on-chip
RAM area H'FFEF10 to H'FFF2FF.
H8/3048F calculates remaining
bytes to be transferred (N = N–1)
No
7
Transfer end byte
count N = 0?
8
H8/3048F transfers part of
boot program to RAM
Yes
9. The H8/3048F branches to the RAM boot program area
(H'FFEF10 to H'FFF2FF) and checks for the presence of
data written in the flash memory. If data has been written in
the flash memory, the H8/3048F erases all blocks. When
erasing ends normally, the H8/3048F transmits one H'AA
byte.
10. The H8/3048F branches to on-chip RAM address H'FFF300
and executes the user program written in that area.
H8/3048F branches to RAM
boot area, then checks flash
memory user area data
9
10
Notes: 1. The user can use 3072 bytes of RAM. The number of
bytes transferred must not exceed 3072 bytes. Be
sure to transmit the byte length in two bytes, most
No
significant byte first and least significant byte second.
All data = H'FF?
For example, if the byte length of the program to be
transferred is 256 bytes, (H'0100), transmit H'01 as
Yes
Delete all flash memory
the most significant byte, followed by H'00 as the
blocks*3,*4
least significant byte.
2. The part of the user program that controls the flash
memory should be coded according to the flash
H8/3048F confirms that all flash
memory program/erase algorithms given later.
memory data is H'FF, then
3. If a memory cell malfunctions and cannot be erased,
transmits one H'AA byte to host
the H8/3048F transmits one H'FF byte to report an
erase error, halts erasing, and halts further
H8/3048F branches to RAM area
operations.
address H'FFF300 and executes
4. The allotted boot program area is H'FFF300 to
user program transferred to RAM
H'FFFEFF.
Figure 19.4 Boot Mode Flowchart
Rev. 7.00 Sep 21, 2005 page 598 of 878
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
Automatic Alignment of SCI Bit Rate
Start
bit
D0
D1
D2
D3
D4
D5
D6
D7
Stop
bit
This low period (9 bits) is measured (H'00 data)
High for at
least 1 bit
Figure 19.5 Measurement of Low Period in Data Transmitted from Host
When started in boot mode, the H8/3048F measures the low period in asynchronous SCI data
transmitted from the host (figure 19.5). The data format is eight data bits, one stop bit, and no
parity bit. From the measured low period (nine bits), the H8/3048F computes the host’s
transmission bit rate. After aligning its own bit rate, the H8/3048F sends the host one byte of H'00
data to indicate that bit-rate alignment is completed. The host should check that this alignmentcompleted indication is received normally, then transmit one H'55 byte. If the host does not
receive a normal alignment-completed indication, the H8/3048F should be reset, then restarted in
boot mode to measure the low period again. There may be some alignment error between the
host’s and H8/3048F’s bit rates, depending on the host’s bit rate and the H8/3048F’s system clock
frequency. To have the SCI operate normally, set the host’s bit rate to a value 2400, 4800, or 9600
bps*1. Table 19.8 lists typical host bit rates and indicates the clock-frequency ranges over which
the H8/3048F can align its bit rate automatically. Boot mode should be used within these
frequency ranges.*2
Table 19.8 System Clock Frequencies Permitting Automatic Bit-Rate Alignment by
H8/3048F
Host Bit Rate*
1
System Clock Frequencies Permitting
Automatic Bit-Rate Alignment by H8/3048F
9600 bps
8 MHz to 16 MHz
4800 bps
4 MHz to 16 MHz
2400 bps
2 MHz to 16 MHz
Notes: 1. Host bit rate settings are 2400, 4800, and 9600 bps; no other settings should be used.
2. Although the H8/3048F may perform automatic bit-rate alignment with combinations
of bit rate and system clock other than those shown in table 19.8, there may be a
discrepancy between the bit rates of the host and the H8/3048F, preventing subsequent
transfer from being performed normally. Boot mode execution should therefore be
confined to the range of combinations shown in table 19.8.
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
RAM Area Allocation in Boot Mode: In boot mode, the H'3F0 bytes from H'FEF10 to H'FF2FF
in modes 5 and 7, and from H'FFEF10 to H'FFF2FF in mode 6 are reserved for use by the boot
program. The user program is transferred into the area from H'FF300 to H'FFEFF, in modes 5 and
7, and from H'FFF300 to H'FFFEFF in mode 6 (H'C00 bytes). The boot program area is used
during the transition to execution of the user program transferred into RAM.
H'FEF10
H'FFEF10
Boot
program
area*1
H'FF300
Boot
program
area*1
H'FFF300
User program
transfer area
(H'C00 bytes)
H'FFEFF
H'FFF00
H'FFF0F
User program
transfer area
(H'C00 bytes)
H'FFFEFF
Reserved*2
H'FFFF00
H'FFFF0F
Modes 5 and 7
Reserved*2
Mode 6
Notes: 1. This area is unavailable until the user program transferred into RAM enters execution state (branch
to H'FF300 in modes 5 and 7, and H'FFF300 in mode 6). After branching to the user program area,
the boot program is retained in the boot program area (H'FEF10 to H'FF2FF in modes 5 and 7, and
H'FFEF10 to H'FFF2FF in mode 6).
2. Do not use reversed areas.
Figure 19.6 RAM Areas in Boot Mode
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
Notes on Use of Boot Mode
1. When the H8/3048F comes out of reset in boot mode, it measures the low period of the input at
the SCI1’s RXD1 pin. The reset should end with RXD1 high. After the reset ends, it takes about
100 states for the H8/3048F to get ready to measure the low period of the RXD1 input.
2. In boot mode, if any data has been programmed into the flash memory (if all data are not
H'FF), all flash memory blocks are erased. Boot mode is for use when user program mode is
unavailable, e.g. the first time on-board programming is performed, or if the update program
activated in user program mode is accidentally erased.
3. Interrupts cannot be used while the flash memory is being programmed or erased.
4. The RXD1 and TXD1 lines should be pulled up on-board.
5. Before branching to the user program (at address H'F300 in the RAM area), the H8/3048F
terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE
and TE bits in serial control register (SCR) to 0 in channel 1), but the auto-aligned bit rate
remains set in bit rate register BRR1. The transmit data pin (TXD1) is in the high output state
(in port 9, the P91DDR bit in port 9 data direction register P9DDR and P91DR bit in port 9 data
register are set to 1).
When the branch to the user program occurs, the contents of general registers in the CPU are
undetermined. After the branch, the user program should begin by initializing general registers,
especially the stack pointer (SP), which is used implicitly in subroutine calls and at other
times. The stack pointer must be set to provide a stack area for use by the user program. The
other on-chip registers do not have specific initialization requirements.
6. Transition to boot mode are shown in figure 19.7, User Program Mode Operation (Example).
This is possible after applying 12 V to pins MD2 and VPP and restarting. In this case, H8/3048F
reset is erased (startup with Low → High) timing*1, mode pin status latches the personal
computer internally to maintain boot mode. Boot mode can be erased if the 12 V applied to the
MD2 pin and the VPP pin is erased, then reset is erased*1. However, please note the following.
a. When transferring from boot mode to regular mode (VPP ≠ 12 V, MD2 ≠ 12 V), before
transfer the erase must be carried out by the reset input personal computer internal boot
mode RES pin. After VPP interrupt, erase reset. The time needed until reset vector lead is
flash memory read setup (tFRS)*2.
b. While in boot mode, if the 12 V applied to the MD2 pin is erased, as long as reset input
from the RES pin does not occur, the personal computer internal boot mode status will be
maintained and boot mode will continue. In boot mode, if watchdog timer reset occur, the
personal computer internal boot mode is not erased, and despite mode pin status the
internal boot program restarts.
c. When transferring to boot mode (reset erase timing) or during boot mode operation,
program voltage VPP should be within the range 12 V to 0.6 V. If this range is exceeded,
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
boot mode will not operate correctly. In addition, during boot program operation or writing
and erasing the flash memory, do not interrupt VPP*2.
7. During reset (when RES pin input is Low), if MD2 pin input changes from 0 V to 12 V or vice
versa, by instantaneous transfer to 5 V input, the personal computer switches to operation
mode. As a result, the address port or bus control output signal (AS, RD, HWR, LWR) status
changes, so do not these pins as output signals during reset, as the personal computer internal
section needs to be shut down.
8. Regarding 12 V application to the VPP and MD2 pins, insure that peak overshoot does not
exceed the maximum rating of 13 V. Also, be sure to connect bypass capacitors to the Vpp and
MD2 pins*1.
Notes: 1. Mode pin input must satisfy the mode programming setup time (tMDS) with respect to
the reset release timing. When 12 V is applied to or disconnected from the MD2 pin, a
delay occurs in the fall and rise waveforms due to the influence of the pull-up/pulldown resistor connected to the MD2 pin, etc. For reset release timing, therefore, this
delay must be confirmed with the actual waveform on the board.
2. For notes on applying and cutting VPP, refer to 19.8, note (4) of “Flash Memory
Programming and Erasing Precautions (Dual-Power Supply).”
19.4.2
User Program Mode
When set to user program mode, the H8/3048F can erase and program its flash memory by
executing a user program. On-board updates of the on-chip flash memory can be carried out by
providing on-board circuits for supplying VPP and data, and storing an update program in part of
the program area.
To select user program mode, select a mode that enables the on-chip ROM (mode 5, 6, or 7) and
apply 12 V to the VPP pin. In this mode, the on-chip peripheral modules operate as they normally
would in mode 5, 6, or 7, except for the flash memory. A watchdog timer overflow, however,
cannot output a reset signal while 12 V is applied to VPP. The watchdog timer’s reset output enable
bit (RSTOE) should not be set to 1.
The flash memory cannot be read while being programmed or erased, so the update program must
either be stored in external memory, or transferred temporarily to the RAM area and executed in
RAM.
Rev. 7.00 Sep 21, 2005 page 602 of 878
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
User Program Mode Execution Procedure: Figure 19.7 shows the procedure for user program
mode execution in RAM.
Procedure
1
Store user application programs
Set MD2 to MD0 to 101, 110, or 111
Apply 0 to 5 V to MD2
2
VPP = 12 V
(user program mode)
3
Transfer on-board update
program into RAM
Execute on-board update
program in RAM
Set VPPE bit
4
Wait 5 to 10 µs
1. The user stores application programs in flash
memory. One of these is an on-board
update program that will execute steps 3 to 5
below.
2. Pin inputs are set up for user program mode.
3. A reset starts the CPU, which transfers the
on-board update program into RAM.
4. Following a branch to the program in RAM,
the on-board update program is executed.
VPPE bit in FLMCR is set to update flash
memory.
Wait 5 to 10 µs to stabilize internal power
supply.
Update program is executed.
5. After the on-board update ends, clear the
VPPE bit then a branch is made to the
updated user application program and this
program is executed.
After clearing the VPPE bit, before the flash
memory program executes, flash memory
read setup time (tFRS) is needed.
Update flash memory
5
Execute user application program
Note: To prevent microcontroller errors caused by accidental programming or erasing, apply 12 V to
VPP only when the flash memory is programmed or erased, or when flash memory is emulated
by RAM; do not apply 12 V to the VPP pin during normal operation. While 12 V is applied, the
watchdog timer should be running and enabled to halt runaway program execution, so that
program runaway will not lead to overprogramming or overerasing. For further information
about turning VPP on and off, see section 19.8, Flash Memory Programming and Erasing
Precautions (Dual-Power Supply).
Figure 19.7 User Program Mode Operation (Example)
Rev. 7.00 Sep 21, 2005 page 603 of 878
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
19.5
Programming and Erasing Flash Memory
The H8/3048F’s on-chip flash memory is programmed and erased by software, using the CPU.
The flash memory operating modes and state transition diagram are shown in figure 19.8.
Program/erase modes comprise program mode, erase mode, program-verify mode, erase-verify
mode, and prewrite-verify mode. Transitions to these modes can be made by setting the P, E, PV,
and EV bits in the flash memory control register (FLMCR). Transition to the prewrite-verify mode
can also be made by clearing all the bits in FLMCR.
The flash memory cannot be read while being programmed or erased. The program that controls
the programming and erasing of the flash memory must be stored and executed in on-chip RAM or
in external memory. A description of each mode is given below, with recommended flowcharts
and sample programs for programming and erasing. High-reliability programming and erasing
algorithms are used, which double the programming or erase processing time for each step.
Section 19.8, Flash Memory Programming and Erasing Precautions (Dual-Power Supply), gives
further notes on programming and erasing.
Normal ROM access mode
VPPE= 0
VPP off
VPP= 12 V and
VPPE= 1
Prewrite-verify mode
P= 1
P= 0
Program mode
E= 1
Erase mode
EV= 0
PV= 0
E= 0
PV= 1
Flash memory
program/erase
operations
EV= 1
Program-verify
mode
Erase-verify
mode
Note: Do not perform simultaneous setting/clearing of the P, E, PV, and EV bits.
Figure 19.8 Flash Memory Program/Erase Operating Mode State Transition Diagram
Rev. 7.00 Sep 21, 2005 page 604 of 878
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
19.5.1
Program Mode
To write data into the flash memory, follow the programming algorithm shown in figure 19.9.
This programming algorithm can write data without subjecting the device to voltage stress or
impairing the reliability of programmed data.
To program data, first set the VPPE bit in FLMCR, wait 5 to 10 µs, then designate the blocks to be
programmed by erase block registers 1 and 2 (EBR1, EBR2), and write the data to the address to
be programmed, as in writing to RAM. The flash memory latches the address and data in an
address latch and data latch. Next set the P bit in FLMCR, selecting program mode. The
programming duration is the time during which the P bit is set. A software timer should be used to
provide an initial programming duration of 15.8 µs or less. Programming for too long a time, due
to program runaway for example, can cause device damage. Before selecting program mode, set
up the watchdog timer so as to prevent overprogramming.
19.5.2
Program-Verify Mode
In program-verify mode, after data has been programmed in program mode, the data is read to
check that it has been programmed correctly.
After the programming time has elapsed, exit programming mode (clear the P bit to 0) and select
program-verify mode (set the PV bit to 1). In program-verify mode, a program-verify voltage is
applied to the memory cells at the latched address. If the flash memory is read in this state, the
data at the latched address will be read. After selecting program-verify mode, wait 4 µs before
reading, then compare the programmed data with the verify data. If they agree, exit programverify mode and program the next address. If they do not agree, select program mode again and
repeat the same program and program-verify sequence. Do not repeat the program and programverify sequence more than 6 times for the same bit. (When a bit is programmed repeatedly, set a
loop counter so that the total programming time will not exceed 1 ms.)
Rev. 7.00 Sep 21, 2005 page 605 of 878
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
19.5.3
Programming Flowchart and Sample Program
Flowchart for Programming One Byte
Start
n=1
Set VPP E bit
(VPP E bit = 1 in FLMCR)
Wait (z) µs
Set erase block register
(set bit of block to be programmed to 1)
Write data to flash memory (flash
memory latches write address
and data)*1
Wait initial value setting x = 15 µs
Enable watchdog timer*2
Select program mode
(P bit = 1 in FLMCR)
Wait (x) µs
Clear P bit
Disable watchdog timer
Select program-verify mode
(PV bit = 1 in FLMCR)
Wait (tVS1) µs *4
Verify (read memory)*3
Notes: 1. Write the data to be programmed using a
byte transfer instruction.
2. Set the watchdog timer overflow interval
by setting CKS2 and CKS1 to 0 and
CKS0 to 1.
3. Read to verify data from the memory
using a byte transfer instruction.
Programming ends
4. tVS1: 4 µs
z:
5 to 10 µs
N: 6 (set N so that total programming
time does not exceed 1 ms)
5. Programming time x, which is determined
by the initial time × 2n–1 (n = 1 to 6),
increases in proportion to n. Thus, set the
initial time to 15.8 µs or less to make total
programming time 1 ms or less.
No good
OK
Clear PV bit
Clear PV bit
n ≥ N?
Clear erase block register
(clear bit of programmed block to 0)
No
n+1→n
Yes
Clear erase block register
(clear bit of block to be
programmed to 0)
Clear VPP E bit
Verify ends
Double the programming
time (x × 2 → x)*5
End (1-byte data programmed)
Clear VPP E bit
Programming error
Figure 19.9 Programming Flowchart
Rev. 7.00 Sep 21, 2005 page 606 of 878
REJ09B0259-0700
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
Sample Program for Programming One Byte: This program uses the following registers.
R0: Program-verify fail counter
R1: Program-verify timing loop counter
ER2: Stores the address to be programmed as long word data. Valid addresses are H'00000000 to
H'0001FFFF.
R3H: Stores data to be programmed as byte data
R4: Sets and clears TCSR and FLMCR
E4: Stores the initial program loop counter value
R5: Clears FLMCR
E5: Stores the program loop counter value
Arbitrary data can be programmed at an arbitrary address by setting the address in ER2 and the
data in R3H.
The values of #a, #b, and #g depend on the clock frequency. They can be calculated as indicated
under table 19.9.
FLMCR:
.EQU
FFFF40
EBR1:
.EQU
FFFF42
EBR2:
.EQU
FFFF43
TCSR:
.EQU
FFFFA8
PRGM:
MOV.W
#0001,
R0
; Program-verify fail count
MOV.W
#g,
R1
; Set program loop counter
MOV.W
#4140,
R4
;
MOV.B
R4L,
@FLMCR:8 ; Set VPPE bit
DEC.W
#1,
R1
;
BPL
LOOP0
MOV.B
#**,
R0H
;
MOV.B
R0H,
@EBR*:8
; Set EBR*
MOV.B
R3H,
@ER2
; Dummy write
MOV.W
#a,
E4
; Set initial program loop counter value
MOV.W
#A579,
R4
; Start watchdog timer
MOV.W
R4,
@TCSR:16 ;
MOV:W
E4,
E5
; Set program loop counter
MOV.W
#4140,
R4
;
MOV.B
R4H,
@FLMCR:8 ; Set P bit
DEC.W
#1,
E5
BPL
LOOP1
LOOP0:
PRGMS:
LOOP1:
; Program
;
Rev. 7.00 Sep 21, 2005 page 607 of 878
REJ09B0259-0700
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
LOOP2:
PVNG:
MOV.B
R4L,
@FLMCR:8 ; Clear P bit
MOV.W
#A500,
R4
MOV.W
R4,
@TCSR:16 ; Stop watchdog timer
MOV:W
#b ,
R1
; Set program-verify loop counter
MOV.B
#44,
R4H
;
MOV.B
R4H,
@FLMCR:8 ; Set PV bit
DEC.W
#1,
R1
BPL
LOOP2
MOV.B
@ER2,
R1H
; Read programmed address
CMP.B
R3H,
R1H
; Compare programmed data with read data
BEQ
PVOK
MOV.B
#40,
R5H
MOV.B
R5H,
@FLMCR:8 ; Clear PV bit
CMP.B
#06,
R0L
BEQ
NGEND
; If program-verify executed 6 times, branch to
INC.B
R0L
; Program-verify fail count + 1 → R0L
SHLL.W
E4
; Double program loop counter value
BRA
PRGMS
; Program again
MOV.W
#4000,
R5
MOV.B
R5H,
@FLMCR:8 ; Clear PV bit
MOV.B
R5L,
@EBR*:8
MOV.B
R5L,
@FLMCR:8 ; Clear VPPE bit
;
; Wait
;
; Program-verify decision
;
; Program-verify executed 6 times?
NGEND
PVOK:
;
; Clear EBR*
............................ One byte programmed
NGEND:
MOV.W
#4000,
R5
;
MOV.B
R5L,
@EBR*:8
; Clear EBR*
MOV.B
R5L,
@FLMCR:8 ; Clear VPPE bit
Programming error
Rev. 7.00 Sep 21, 2005 page 608 of 878
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
19.5.4
Erase Mode
To erase the flash memory, follow the erasing algorithm shown in figure 19.10. This erasing
algorithm can erase data without subjecting the device to voltage stress or impairing the reliability
of programmed data.
To erase flash memory, before starting to erase, first place all memory data in all blocks to be
erased in the programmed state (program all memory data to H'00). If all memory data is not in the
programmed state, follow the sequence described later to program the memory data to zero. To
select the flash memory areas to be erased, first set the VPPE bit in the flash memory control
register (FLMCR), wait 5 to 10 µs, and set up erase block registers 1 and 2 (EBR1 and EBR2).
Next set the E bit in FLMCR, selecting erase mode. The erase time is the time during which the
E bit is set. To prevent overerasing, use a software timer to divide the erase time. Overerasing, due
to program runaway for example, can give memory cells a negative threshold voltage and cause
them to operate incorrectly. Before selecting erase mode, set up the watchdog timer so as to
prevent overerasing.
19.5.5
Erase-Verify Mode
In program-verify mode, after data has been erased, it is read to check that it has been erased
correctly. After the erase time has elapsed, exit erase mode (clear the E bit to 0), select eraseverify mode (set the EV bit to 1), and wait 4 µs. Before reading data in erase-verify mode, write
H'FF dummy data to the address to be read. This dummy write applies an erase-verify voltage to
the memory cells at the latched address. If the flash memory is read in this state, the data at the
latched address will be read. After the dummy write, wait 2 µs before reading. If the read data has
been successfully erased, perform the dummy write, wait 2 µs, and erase-verify for the next
address. If the read data has not been erased, select erase mode again and repeat the same erase
and erase-verify sequence through the last address, until all memory data has been erased to 1. Do
not repeat the erase and erase-verify sequence more than 602 times, however.
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
19.5.6
Erasing Flowchart and Sample Program
Flowchart for Erasing One Block
Start
Notes: 1. Program all addresses to be
erased by following the prewrite
flowchart.
2. Set the watchdog timer overflow
interval to the value indicated in
table 19.10.
3. For the erase-verify dummy
write, write H'FF using a byte
transfer instruction.
4. Read to verify data from the
memory using a byte transfer
instruction.
5. tVS1: 4 µs
z:
5 to 10 µs
tVS2: 2 µs
N: 602
Write 0 data in all addresses
to be erased (prewrite)*1
n=1
Set VPP E bit
( VPP E bit = 1 in FLMCR)
Wait (z) µs
Set erase block register
(set bit of block to be erased to 1)
Set top address in block
as verify address
Wait initial value setting x = 6.25 ms
6. The erase time x is successively
incremented by the initial set
value × 2n–1 (n = 1, 2, 3, 4). An
initial value of 6.25 ms or less
should be set, and the time for
one erasure should be 50 ms or
less.
Enable watchdog timer*2
Select erase mode
(E bit = 1 in FLMCR)
Wait (x) ms
Clear E bit
Erasing ends
Disable watchdog timer
Select erase-verify mode
(EV bit = 1)
Wait (tVS1) µs*5
Dummy write to verify address*3
(flash memory latches address)
Wait (tVS2) µs*5
Verify (read memory)*4
Clear EV bit
OK
No
Address + 1 → address
No good
Last address?
n ≥ N?
Yes
Clear EV bit
Yes
Clear erase block register
(clear bit of erased block to 0)
Clear erase block register
(clear bit of block to be
erased to 0)
Clear VPP E bit
Clear VPP E bit
End of block erase
Erase error
Erase-verify ends
No
n+1→n
n ≥ 5?
No
Figure 19.10 Erasing Flowchart
Rev. 7.00 Sep 21, 2005 page 610 of 878
REJ09B0259-0700
Double the erase time*6
(x × 2 → x)
Yes
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
Prewrite Flowchart
Start
Address = top address
Set VPP E bit
( VPP E bit = 1 in FLMCR)
Wait (z) µs
Set erase block register
(set bit of block to be erased to 1)
n=1
Address + 1 → address
Wait initial value setting x = 15 µs
Notes: 1. Use a byte transfer instruction.
2. Set the watchdog timer overflow
interval by setting CKS2 = 0,
CKS1 = 0 and CKS0 = 1.
3. In prewrite-verify mode P, E, PV,
and EV are all cleared to 0 and
12 V is applied to VPP. Use a
byte transfer instruction.
4. tVS1: 4 µs
z:
5 to 10 µs
N: 6 (set N so that total
Programming ends
programming time does not
exceed 1 ms)
Write H'00 to flash memory
(flash memory latches
write address and write data)*1
Enable watchdog timer*2
Select program mode
(set P bit to 1 in FLMCR)
Wait (x) µs
Clear P bit
Disable watchdog timer
Wait (tVS1) µs*4
No good
Prewrite verify*3
(read data = H'00?)
No
n ≥ N?
OK
n+1→n
Yes
Clear erase block register
(clear bit of block to be erased to 0)
Double
the programming
time (x × 2 → x)
Clear VPPE bit
Programming error
No
Last address?
Yes
Clear erase block register
(clear bit of block to be erased to 0)
Clear VPP E bit
End of prewrite
Figure 19.11 Prewrite Flowchart
Rev. 7.00 Sep 21, 2005 page 611 of 878
REJ09B0259-0700
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
Sample Program for Erasing One Block: This program uses the following registers.
R0:
ER1:
ER2:
ER3:
ER4:
R5:
R6:
Prewrite-verify and erase-verify fail counter
Stores address used in prewrite
Stores address used in prewrite and erase-verify
Stores address used in erase-verify
Timing loop counter
Sets appropriate registers
Sets appropriate registers
The values of #a, #c, #d, #e, #f, #g, and #h, in the program depend on the clock frequency. They
can be calculated as indicated in tables 19.9 and 19.10.
FLMCR: .EQU
FFFF40
EBR1:
.EQU
FFFF42
EBR2:
.EQU
FFFF43
TCSR:
.EQU
FFFFA8
; #BLKSTR is top address of block to be erased
; #BLKEND is last address of block to be erased
MOV.L
#BLKSTR:32, ER1
; ER1: top address of block to be erased
MOV.L
#BLKEND:32, ER2
; ER2: last address of block to be erased
#g,
R4
; Set wait counter
MOV.W
#4140,
R6
;
MOV.B
R6L,
@FLMCR:8 ; Set VPPE bit
#1,
R4
; Execute prewrite
PREWRT: MOV.W
LOOPR0: DEC.W
BPL
LOOPR0
;
;
;SET EBR1 or EBR2 bit of block to be erased
MOV.B
#**,
R5H
;
MOV.B
R5H,
@EBR*
; Set EBR*
PREWRN: SUB.B
R0H,
R0H
; R0: prewrite-verify fail count
#a,
E4
; Set initial prewrite loop counter value
PREWRS: MOV.B
#00,
R5H
; Write #00 data
MOV.B
R5H,
@ER1
;
MOV.W
#A579,
R5
; Start watchdog timer
MOV.W
R5,
@TCSR:16 ;
MOV.W
E4,
R4
; Set prewrite loop counter
MOV.W
#4140,
R6
;
MOV.W
Rev. 7.00 Sep 21, 2005 page 612 of 878
REJ09B0259-0700
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
MOV.B
LOOPR1: DEC.W
R6H,
@FLMCR:8 ; Set P bit
#1,
R4
; Prewrite
BPL
LOOPR1
MOV.B
R6L,
@FLMCR:8 ; Clear P bit
MOV.W
#A500,
R5
MOV.W
R5,
@TCSR:16 ;
MOV.W
#c ,
R5
; Set prewrite-verify loop counter
#1,
R5
; Wait
LOOPR2: DEC.W
;
; Stop watchdog timer
BPL
LOOPR2
;
MOV.B
@ER1,
BEQ
PWVFOK
CMP.B
#05,
BEQ
ABEND1
; If prewrite-verify executed 6 times, branch to
SHLL.W
E4
; Double prewrite loop counter value
INC.B
R0H
; Prewrite-verify fail count + 1 → R0H
BRA
PREWRS
; Prewrite again
R5H
; Read data = H'00?
; If read data = H'00, branch to PWVFOK
R0H
; Prewrite-verify executed 6 times?
ABEND1
PWVFOK: CMP.L
ER2,
BEQ
ERASES
INC.L
#1,
BRA
PREWRN
ER1
; Last address?
;
ER1
; Address + 1 → R1
; If not last address, prewrite next address
;Execute erase
ERASES: SUB.W
ERASE:
LOOPE:
R0,
R0
; R0: erase-verify fail count
MOV.L
#BLKSTR:32,ER3
; ER3: top address of block to be erased
MOV.W
#d,
E4
; Set initial erase loop counter value
CMP.W
#025A,
R0
; R0 = H'025A? (erase-verify fail count = 603?)
BEQ
ABEND2
INC.W
#1,
R0
; Erase-verify fail count + 1 → R0
MOV.W
E4,
R4
;
MOV.W
#f,
R5
; Start watchdog timer
MOV.W
R5,
@TCSR:16 ;
MOV.B
#42,
R5H
MOV.B
R5H,
@FLMCR:8 ;
PUSH.L
ER5
POP.L
ER5
; If R0 = H'025A, branch to ABEND2
; Set E bit
Rev. 7.00 Sep 21, 2005 page 613 of 878
REJ09B0259-0700
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
PUSH.L
ER5
POP.L
ER5
PUSH.L
ER5
POP.L
ER5
DEC.W
#1,
BPL
LOOPE
MOV.B
#40,
R5H
MOV.B
R5H,
@FLMCR:8 ; Clear E bit
MOV.W
#A500,
R5
MOV.W
R5,
@TCSR:16 ; Stop watchdog timer
MOV.B
#48,
R5H
MOV.B
R5H,
@FLMCR:8 ; Set EV bit
MOV.W
#e ,
R4
; R4: erase-verify loop counter
#1,
R4
;
R4
; Erase
;
;
;
; Execute erase-verify
LOOPEV: DEC.W
;
; Wait
BPL
LOOPEV
MOV.B
#FF,
@ER3
; Dummy write
MOV.W
#h,
R4
; R4: erase-verify loop counter
LOOPDW: DEC.W
#1,
R4
;
EVR2:
; Wait
BPL
LOOPDW
MOV.B
@ER3+,
R4H
; Read
CMP.B
#FF,
R4H
; Read data = H'FF?
BNE
RERASE
CMP.L
ER2,
BGT
EVR2
; If not last address in block, erase-verify next
BRA
OKEND,
; Branch to OKEND
; If read data ≠ H'FF, branch to RERASE
ER3
; Last address in block?
address
RERASE: MOV.W
#4000,
R5
;
MOV.B
R5H,
@FLMCR:8 ; Clear EV bit
DEC.L
#1,
ER3
; Erase-verify address – 1 → R3
CMP.W
#0004,
R0
;
BGE
KEEP
; Erase executed 4 times?
SHLL.W
E4
; Double erase loop counter value
KEEP:
BRA
ERASE
OKEND:
MOV.W
#4000,
; Erase again
R5
Rev. 7.00 Sep 21, 2005 page 614 of 878
REJ09B0259-0700
;
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
MOV.B
R5H,
@FLMCR:8 ; Clear EV bit
MOV.W
#0000,
R5
MOV.W
R5,
@EBR1:16 ; Clear EBR1 and EBR2
MOV.B
R5L,
@FLMCR:8 ; Clear VPPE bit
;
............................. One block erased
ABEND1: MOV.W
#0000,
R5
MOV.W
R5,
@EBR1:16 ; Clear EBR1 and EBR2
;
MOV.B
R5L,
@FLMCR:8 ; Clear VPPE bit
Programming error
ABEND2: MOV.W
#0000,
R5
MOV.W
R5,
@EBR1:16 ; Clear EBR1 and EBR2
;
MOV.B
R5L,
@FLMCR:8 ; Clear VPPE bit
Erase error
Rev. 7.00 Sep 21, 2005 page 615 of 878
REJ09B0259-0700
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
Flowchart for Erasing Multiple Blocks
Notes: 1. Program all addresses to be erased by
following the prewrite flowchart.
2. Set the watchdog timer overflow interval to
the value indicated in table 19.10.
3. For the erase-verify dummy write, write H'FF
with a byte transfer instruction.
4. When erasing two or more blocks, clear the
bits of erased blocks in the erase block
register, so that only unerased blocks will be
erased again.
5. tVS1: 4 µs
z:
5 to 10 µs
Start
Write 0 data to all addresses to be
erased (prewrite)*1
n=1
Set VPP E bit
(VPP E bit = 1 in FLMCR)
Wait (z) µs
Set erase block registers
(set bits of blocks to be erased to 1)
Wait initial value setting x = 6.25 ms
Enable watchdog timer*2
Select erase mode (E bit = 1 in FLMCR)
Wait (x) ms
Erasing ends
Clear E bit
Disable watchdog timer
tVS2: 2 µs
N: 602
6. The erase time x is successively
incremented by the initial set value
× 2n–1 (n = 1, 2, 3, 4). An initial
value of 10 ms or less should be
set, and the time for one erasure
should be 50 ms or less.
Select erase-verify mode
(EV bit = 1 in FLMCR)
Wait (tVS1) µs *5
Set top address of block as
verify address
Erase-verify
next block
Dummy write to verify address*3
(flash memory latches address)
Wait (tVS2) µs *5
Verify
(read memory)
Erase-verify next block
No good
OK
Address + 1 → address
No
Last
address in block?
All erased blocks
verified?
Yes
No
Yes
Clear EBR bit of erase-verified block *4
No
All erased blocks
verified?
Yes
Clear EV bit
All blocks erased?
(EBR1 = EBR2 = 0?)
Yes
Clear VPP E bit
End of erase
No
n ≥ 4?
Yes
No
Double the erase time (x × 2 → x)*6
n ≥ N?
No
Yes
Clear erase block registers
(clear bits of blocks to be erased to 0)
Clear VPP E bit
Erase error
Figure 19.12 Multiple-Block Erase Flowchart
Rev. 7.00 Sep 21, 2005 page 616 of 878
REJ09B0259-0700
n+1→n
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
Sample Program for Erasing Multiple Blocks: This program uses the following registers.
R0, R6: Specifies blocks to be erased (set as explained below)
R1H: Prewrite-verify fail counter
R1L: Used to test bits 0 to 15 of R0
ER2: Specifies address where address used in prewrite and erase-verify is stored
ER3: Stores address used in prewrite and erase-verify
ER4: Stores address used in prewrite and erase-verify
ER5: Sets appropriate registers
E0, E1: Timing loop counter
E6:
Erase-verify fail counter
Arbitrary blocks can be erased by setting bits in R6.
A bit map of R6 and an example setting for erasing specific blocks are shown next.
Bit
15
14
13
R6
LB7
LB6
LB5
12
11
10
LB4 LB3 LB2
9
LB1
8
7
6
5
4
3
2
1
0
LB0 SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0
Corresponds to EBR1
Corresponds to EBR2
Example: to erase blocks LB2, SB7, and SB0
Bit
15
14
13
R6
LB7
LB6
LB5
12
11
10
LB4 LB3 LB2
9
LB1
8
7
6
0
0
0
0
0
1
4
3
2
1
0
LB0 SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0
Corresponds to EBR1
Setting
5
Corresponds to EBR2
0
0
1
0
0
0
0
0
0
1
R6 is set as follows:
MOV.W
#0481,
R6
MOV.W
R6,
@EBR1
The values of #a, #c, #d, #e, #f, #g, and #h in the program depend on the clock frequency. They
can be calculated as indicated in tables 19.9 and 19.10.
For #RAMSTR in the program, substitute the starting destination address in RAM, to be used
when this program is moved from flash memory into RAM.
Rev. 7.00 Sep 21, 2005 page 617 of 878
REJ09B0259-0700
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
FLMCR:
.EQU
FFFF40
EBR1:
.EQU
FFFF42
EBR2:
.EQU
FFFF43
TCSR:
.EQU
FFFFA8
; Set R0 value
START:
MOV.W
#FFFF,
R6
; Select blocks to be erased (R6: EBR1/EBR2)
MOV.W
R6,
R0
; R0: EBR1/EBR2
SUB.W
R1,
R1
; R1L: used to test R1-th bit in R0
; #RAMSTR is starting destination address to which program is transferred in RAM
; Set #RAMSTR to even number
MOV.L
#RAMSTR:32, ER2
; Starting transfer destination address
ADD.L
#ERVADR:32, ER2
; #RAMSTR + #ERVADR → ER2
SUB.L
#START:32,
; ER2: address of data area used in RAM
PRETST: CMP.B
BC0:
#10,
ER2
R1L
; R1L = #10?
; If finished checking all R0 bits, branch to ERASES
BEQ
ERASES
CMP.B
#08,
BCC
BC0
BTST
R1L,
BNE
PREWRT
;
BRA
PWADD1
;
BTST
R1L,
BNE
PREWRT
; If R1-th bit in R0 is 1, branch to PREWRT
R1L
; R1L + 1 → R1L
PWADD1: INC.B
R1L
;
;
R0H
R0L
;
; Test R1-th bit in R0
ER3
; Dummy-increment ER2
@ER2+,
ER3
; ER3: prewrite starting address
MOV.L
@ER2,
ER4
; ER4: top address of next block
MOV.W
#g,
E5
; Wait counter
MOV.W
#4140,
R5
;
MOV.B
R5L,
@FLMCR:8 ; Set VPPE bit
DEC.W
#1,
E5
BPL
LOOPR0
MOV.W
R6,
@EBR1:16 ; Set EBR (R6: EBR1/EBR2)
MOV.B
#01,
R1H
MOV.L
@ER2+,
BRA
PRETST
; Execute prewrite
PREWRT: MOV.L
LOOPR0
PREW:
;
;
Rev. 7.00 Sep 21, 2005 page 618 of 878
REJ09B0259-0700
; Prewrite-verify fail count
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
#a,
E0
; Set initial prewrite loop counter value
PREWRS: MOV.B
#00,
R5H
; Write #00 data
MOV.B
R5H,
@ER3
;
MOV.W
#A579,
E5
;
MOV.W
E5,
@TCSR:16 ; Start watchdog timer
MOV.W
E0,
E1
; Set program loop counter
MOV.W
#4140,
R5
;
MOV.B
R5H,
@FLMCR:8 ; Set P bit
#1,
E1
MOV.W
LOOPR1: DEC.W
; Program
BPL
LOOPR1
MOV.B
R5L,
@FLMCR:8 ; Clear P bit
MOV.W
#A500,
R5
MOV.W
R5,
@TCSR:16 ; Stop watchdog timer
MOV.W
#c,
R5
; Prewrite-verify loop counter
LOOPR2: DEC.W
#1,
R5
;
BPL
LOOPR2
MOV.B
@ER3,
BEQ
PWVFOK
PWVFNG: CMP.B
#06,
;
;
;
R5H
; Read data = #'00?
; If read data = #'00, branch to PWVFOK
R1H
; Prewrite-verify executed 6 times?
BEQ
ABEND1
; If prewrite-verify executed 6 times, branch to
INC.B
R1H
; Prewrite-verify fail count + 1 → R1H
SHLL.W
E0
; Double prewrite loop counter value
BRA
PREWRS
; Prewrite again
ABEND1
#1,
ER3
; Address + 1 → ER3
CMP.L
ER4,
ER3
; Last address?
BEQ
PWADD2
;
BRA
PREW
;
R1L
; Used to test (R1L + 1)–th bit in R0
PRETST
; Branch to PRETST
PWVFOK: INC.L
PWADD2: INC.B
BRA
; Execute erase
ERASES: MOV.W
R6,
@EBR1:16 ; Set EBR1/EBR2
SUB.W
E6,
E6
; E6: erase-verify fail count
MOV.W
#d,
E0
; Set initial erase loop counter value
MOV.W
#f ,
R5
;
ERASE:
Rev. 7.00 Sep 21, 2005 page 619 of 878
REJ09B0259-0700
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
LOOPE:
MOV.W
R5,
@TCSR:16 ; Start watchdog timer
MOV.W
E0,
E1
; Set erase-loop counter
MOV.W
#4240,
R5
;
MOV.B
R5H,
@FLMCR:8 ; Set E bit
PUSH.L
ER5
POP.L
ER5
PUSH.L
ER5
POP.L
ER5
PUSH.L
ER5
POP.L
ER5
DEC.W
#1,
BPL
LOOPE
MOV.B
R5L,
@FLMCR:8 ; Clear E bit
MOV.W
#A500,
R5
MOV.W
R5,
@TCSR:16 ; Stop watchdog timer
MOV.W
R6,
R0
; R0: EBR1/EBR2
SUB.W
R1,
R1
; R1: used to test R1-th bit in R0
; Erase
E1
;
; Execute erase-verify
EVR:
; #RAMSTR is starting destination address to which program is transferred in RAM
MOV.L
#RAMSTR:32, ER2
; Starting transfer destination address (RAM)
ADD.L
#ERVADR:32, ER2
; #RAMSTR + #ERVADR → ER2
SUB.L
#START:32,
; ER2: address of data area used in RAM
MOV.B
#48,
R5H
MOV.B
R5H,
@FLMCR:8 ; Set EV bit
MOV.W
#e ,
R5
; R5: set erase-verify loop counter
#1,
R5
; Program
LOOPEV: DEC.W
BPL
EBRTST: CMP.B
ER2
; Wait
LOOPEV
#10,
;
R1L
; R1L = #10?
; If finished checking all R0 bits, branch to HANTEI
BEQ
HANTEI
CMP.B
#08,
BCC
BC1
BTST
R1L,
BNE
ERSEVF
;
BRA
ADD01
;
R1L
;
;
R0H
Rev. 7.00 Sep 21, 2005 page 620 of 878
REJ09B0259-0700
; Test R1-th bit in R0H (EBR1)
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
BC1:
ADD01:
R1L,
BNE
ERSEVF
; If R1-th bit in R0 is 1, branch to ERSEVF
INC.B
R1L
; R1L + 1 → R1L
MOV.L
@ER2+,
BRA
EBRTST
ER3
; Dummy-increment R2
;
@ER2+,
ER3
; ER3: top address of block to be erase-verified
MOV.L
@ER2,
ER4
; ER4: top address of next block
MOV.B
#FF,
R5H
;
MOV.B
R5H,
@ER3
; Dummy write
MOV.W
#h ,
R5
; R5: erase-verify loop counter
#1,
R5
;
ERSEVF: MOV.L
EVR2:
R0L
; Test R1-th bit in R0L (EBR2)
BTST
LOOPDW: DEC.W
; Wait
BPL
LOOPDW
MOV.B
@ER3+,
R5L
; Read
CMP.B
#FF,
R5L
; Read data = #FF?
BNE
ADD02
CMP.L
ER4,
BNE
EVR2
CMP.B
#08,
BCC
BC2
BCLR
R1L,
BRA
ADD02
BC2:
BCLR
R1L,
ADD02:
INC.B
R1L
; R1L + 1 → R1L
BRA
EBRTST
; Erase-verify next erased block
HANTEI: MOV.W
KEEP:
; If read data ≠ #FF, branch to ADD02
ER3
; Last address in block?
; If not last address in block, branch to EVR2
R1L
;
;
R0H
; Clear R1L-th bit in R0H (EBR1)
;
R0L
; Clear R1L-th bit in R0L (EBR2)
#4000,
R5
;
MOV.B
R5H,
@FLMCR:8 ; Clear EV bit
MOV.W
R0,
@EBR1:16 ; Clear bit of erased block to 0
BEQ
EOWARI
CMP.W
#025A,
BEQ
ABEND2
INC.W
#1,
E6
; Erase-verify fail count + 1 → E6
CMP.W
#0004,
E6
;
BGE
KEEP
; Erase executed 4-times?
SHLL.W
E0
; Double erase loop counter value
BRA
ERASE
; Erase again
; If EBR1/EBR2 is all 0, erasing ended normally
E6
; E6 = 025A? (erase-verify fail count = 602?)
; If E6 = 025A, branch to ABEND2
Rev. 7.00 Sep 21, 2005 page 621 of 878
REJ09B0259-0700
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
;————<Block address table used in erase-verify>——————————————————
.ALIGN2
ERVADR: .DATA.L
00000000
; #0000
LB0
.DATA.L
00004000
; #4000
LB1
.DATA.L
00008000
; #8000
LB2
.DATA.L
0000C000
; #C000
LB3
.DATA.L
00010000
; #10000
LB4
.DATA.L
00014000
; #14000
LB5
.DATA.L
00018000
; #18000
LB6
.DATA.L
0001C000
; #1C000
LB7
.DATA.L
0001F000
; #1F000
SB0
.DATA.L
0001F200
; #1F200
SB1
.DATA.L
0001F400
; #1F400
SB2
.DATA.L
0001F600
; #1F600
SB3
.DATA.L
0001F800
; #1F800
SB4
.DATA.L
0001FA00
; #1FA00
SB5
.DATA.L
0001FC00
; #1FC00
SB6
.DATA.L
0001FE00
; #1FE00
SB7
.DATA.L
00020000
; #20000
FLASH AREA END ADDRESS
EOWARI: MOV.B
#00,
R5L
;
MOV.B
R5L,
@FLMCR:8 ; Clear VPPE bit
#0000,
R5
MOV.W
R5,
@EBR1:16 ; Clear EBR1 and EBR2
MOV.B
R5L,
@FLMCR:8 ; Clear VPPE bit
Erase end
ABEND1: MOV.W
;
Programming error
ABEND2: MOV.W
#0000,
R5
MOV.W
R5,
@EBR1:16 ; Clear EBR1 and EBR2
MOV.B
R5L,
@FLMCR:8 ; Clear VPPE bit
Erase error
Rev. 7.00 Sep 21, 2005 page 622 of 878
REJ09B0259-0700
;
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
Loop Counter Values in Programs and Watchdog Timer Overflow Interval Settings: The
values of a to h in the programs depend on the clock frequency. Table 19.9 indicates the values for
10 MHz. Values for other frequencies can be calculated as shown below, but use the settings in
table 19.10 for the value off.
Table 19.9 Loop Counter Values in Program (10 MHz)
Variable
Clock Frequency
a (f)
b (f)
c (f)
d (f)
f = 10 MHz
Hexadecimal
H'0019
H'0007
H'0007
H'03B3 H'0007
H'0009 H'0004
Decimal
25
7
7
947
9
Comments
Program tVS1
tVS2
Erase
at write at pre-write
e (f)
7
g (f)
tVS1
z
at erase
h (f)
4
tVS2
Formula:
Clock frequency f [MHz]
× {a (f = 10) to h (f = 10)}
10
a (f) to h (f) =
Examples for 16 MHz:
a (f) =
b (f) =
c (f) =
d (f) =
e (f) =
g (f) =
h (f) =
16
10
16
10
16
10
16
10
16
10
16
10
16
10
×
25 =
40 ≈ H'0028
×
7 =
11.2 ≈ H'000C
×
7 =
11.2 ≈ H'000C
× 947 = 1515.2 ≈ H'05EC
×
7 =
11.2 ≈ H'000C
×
9 =
14.4 ≈ H'000F
×
4 =
6.4 ≈ H'0007
Rev. 7.00 Sep 21, 2005 page 623 of 878
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
Table 19.10 Watchdog Timer Overflow Interval Settings
Variable
Clock Frequency
f
10 MHz ≤ frequency ≤ 16 MHz
H'A57F
2 MHz ≤ frequency < 10 MHz
H'A57E
1 MHz ≤ frequency < 2 MHz
H'A57D
Note: The watchdog timer (WDT) set value is calculated based on the number of instructions
including write time and erase time from start to stop of WDT operation. In this program
example, therefore, no more instructions should be added between the start and stop of
WDT operation.
19.5.7
Prewrite-Verify Mode
Prewrite-verify mode is a verify mode used after writing 0 to all bits to equalize their threshold
voltages before erasure.
To program all bits, write H'00 in accordance with the algorithm shown in figure 19.11. Use this
procedure to set all data in the flash memory to H'00 after programming. After the necessary
programming time has elapsed, exit program mode (by clearing the P bit to 0) and select prewriteverify mode (leave the P, E, PV, and EV bits all cleared to 0). In prewrite-verify mode, a prewriteverify voltage is applied to the memory cells at the read address. If the flash memory is read in this
state, the data at the read address will be read. After selecting prewrite-verify mode, wait 4 µs
before reading.
Note: For a sample prewriting program, see the sample erasing program.
Rev. 7.00 Sep 21, 2005 page 624 of 878
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
19.5.8
Protect Modes
Flash memory can be protected from programming and erasing by software or hardware methods.
These two protection modes are described below.
Software Protection: Prevents transitions to program mode and erase mode even if the P or E bit
is set in the flash memory control register (FLMCR). Details are as follows.
Function
Protection
Description
Program
Erase
1
Verify*
Block
protect
Individual blocks can be erase and
program-protected by the erase block
registers (EBR1 and EBR2). If EBR1 and
EBR2 are both set to H'00, all blocks are
erase- and program-protected.
Disabled
Disabled
Enabled
Emulation
protect
When the RAMS bit is set in the RAM
control register (RAMCR), all blocks are
protected from both programming and
erasing.
Disabled*
2
3
Disabled*
Enabled
Notes: 1. Three modes: program-verify, erase-verify, and prewrite-verify.
2. Except in RAM areas overlapped onto flash memory.
3. All blocks are erase-disabled. It is not possible to specify individual blocks.
Rev. 7.00 Sep 21, 2005 page 625 of 878
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
Hardware Protection: Suspends or disables the programming and erasing of flash memory, and
resets the flash memory control register (FLMCR) and erase block registers (EBR1 and EBR2).
The error-protect function permits the P and E bits to be set, but prevents transitions to program
mode and erase mode. Details of hardware protection are as follows.
Function
1
Verify*
Protection
Description
Program
Erase
Programing
voltage (VPP)
protect
When VPP is not applied, FLMCR, EBR1,
and EBR2 are initialized, disabling
programming and erasing. To obtain this
3
protection, VPP should not exceed VCC.*
Disabled
Disabled*
Reset and
standby
protect
When a reset occurs (including a
watchdog timer reset) or standby mode is
entered, FLMCR, EBR1, and EBR2 are
initialized, disabling programming and
erasing. Note that RES input does not
ensure a reset unless the RES pin is held
low for at least 20 ms at power-up (to
enable the oscillator to settle), or at least
10 system clock cycles (φ) during
operation.
Disabled
Disabled*
Error protect
If an operational error is detected during
Disabled
programming or erasing of flash memory
(FLER = 1), the FLMCR, EBR1, and EBR2
settings are preserved, but programming
or erasing is aborted immediately. This
type of protection can be cleared only by a
reset or hardware standby.
Disabled*
2
Disabled
2
Disabled
2
Enabled
Notes: 1. Program-verify, erase-verify, and prewrite-verify modes.
2. All blocks are erase-disabled. It is not possible to specify individual blocks.
3. For details, see section 19.8, Flash Memory Programming and Erasing Precautions
(Dual-Power Supply).
Error Protect: This protection mode is entered if one of the error conditions that set the FLER bit
in RAMCR is detected while flash memory is being programmed or erased (while the P bit or E
bit is set in FLMCR). These conditions can occur if microcontroller operations do not follow the
programming or erasing algorithm. Error protect is a flash-memory state. It does not affect other
microcontroller operations.
In this state the settings of the flash memory control register (FLMCR) and erase block registers
(EBR1 and EBR2) are preserved*, but program mode or erase mode is terminated as soon as the
error is detected. While the FLER bit is set, it is not possible to enter program mode or erase
Rev. 7.00 Sep 21, 2005 page 626 of 878
REJ09B0259-0700
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
mode, even by setting the P bit or E bit in FLMCR again. The PV and EV bits in FLMCR remain
valid, however. Transitions to verify modes are possible in the error-protect state.
The error-protect state can be cleared only by a reset or entry to hardware standby mode.
Note: * It is possible to write to these registers. Note that a transition to software standby mode
initializes these registers.
Memory read
or verify mode
RES = 0 or STBY = 0
or software standby
RD VF PR ER
FLER = 0
RES = 1 and STBY = 1
and not software standby
P = 1 or E = 1
P = 0 and E = 0
Error occurs
(software standby)
RES = 0 or
STBY = 0
Error occurs
RD:
VF:
PR:
ER:
RD:
VF:
PR:
ER:
INIT.:
RD VF PR ER
INIT.
FLER = 0
RES = 0 or
STBY = 0
Program mode
or erase mode
RD VF PR ER
FLER = 0
Reset or standby
(hardware protect)
Memory read enabled
Verify read enabled
Error-protect mode
Programming enabled
Erase enabled
Memory read disabled
RD VF PR ER
Verify read disabled
FLER = 1
Programming disabled
Erase disabled
Initialized state of registers (FLMCR, EBR1, EBR2)
Software
standby
RES = 0 or
STBY = 0
Error-protect mode
(software standby)
RD VF PR ER
INIT.
FLER = 1
Software standby
cleared
Figure 19.13 Flash Memory State Transitions in Modes 5, 6, and 7 (On-Chip ROM
Enabled) when Programming Voltage (VPP) is Applied
The purpose of error-protect mode is to prevent overprogramming or overerasing damage to flash
memory by detecting abnormal conditions that occur if the programming or erasing algorithm is
not followed, or if a program crashes while the flash memory is being programmed or erased.
This protection function does not cover abnormal conditions other than the setting conditions of
the flash memory error bit (FLER), however. Also, if too much time elapses before the errorprotect state is reached, the flash memory may already have been damaged. This function
accordingly does not offer foolproof protection from damage to flash memory.
To prevent abnormal operations, when programming voltage (VPP) is applied, follow the
programming and erasing algorithms correctly, and keep microcontroller operations under
Rev. 7.00 Sep 21, 2005 page 627 of 878
REJ09B0259-0700
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
constant internal and external supervision, using the watchdog timer for example. If a transition to
error-protect mode occurs, the flash memory may contain incorrect data due to errors in
programming or erasing, or it may contain data that has been insufficiently programmed or erased
because of the suspension of these operations. Boot mode should be used to recover to a normal
state.
If the memory contains overerased memory cells, boot mode may not operate correctly. This is
because the H8/3048F’s built-in boot program is located in part of flash memory, and will not read
correctly if memory cells have been overerased.
19.5.9
NMI Input Masking
NMI input is disabled when flash memory is being programmed or erased (when the P or E bit is
set in FLMCR). NMI input is also disabled while the boot program is executing in boot mode,
until the branch to the on-chip RAM area takes place*1. There are three reasons for this.
• NMI input during programming or erasing might cause a violation of the programming or
erasing algorithm. Normal operation could not be assured.
• In the NMI exception-handling sequence during programming or erasing, the vector would not
be read correctly*2. The result might be a program runaway.
• If NMI input occurred during boot program execution, the normal boot-mode sequence could
not be executed.
NMI input is also disabled in the error-protect state while the P or E bit remains set in the flash
memory control register (FLMCR).
NMI requests should be disabled externally whenever VPP is applied.
Notes: 1. The disabled state lasts until the branch to the boot program area in on-chip RAM
(addresses H'FFEF10 to H'FFF2FF) that takes place as soon as the transfer of the user
program is completed. After the branch to the RAM area, NMI input is enabled except
during programming or erasing. NMI interrupt requests must therefore be disabled
externally until the user program has completed initial programming (including the
vector table and the NMI interrupt-handling program).
2. The vector may not be read correctly for the following two reasons.
• If flash memory is read while being programmed or erased (while the P or E bit is
set in FLMCR), correct read data will not be obtained. Undetermined values are
returned.
• If the NMI entry in the vector table has not been programmed yet, NMI exception
handling will not be executed correctly.
Rev. 7.00 Sep 21, 2005 page 628 of 878
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
19.6
Flash Memory Emulation by RAM
Erasing and programming flash memory takes time, which can make it difficult to tune parameters
and other data in real time. If necessary, real-time updates of flash memory can be emulated by
overlapping the small-block flash-memory area with part of the RAM (H'FFF000 to H'FFF1FF).
This RAM reassignment is performed using bits 3 to 0 of the RAM control register (RAMCR).
After a flash memory area has been overlapped by RAM, it can be accessed from two address
areas: the overlapped flash memory area, and the original RAM area (H'FFF000 to H'FFF1FF).
Table 19.11 indicates how to reassign RAM.
RAM Control Register (RAMCR)
Bit
7
6
5
4
3
2
1
0
FLER
—
—
—
RAMS
RAM2
RAM1
RAM0
Initial value*
0
1
1
1
0
0
0
0
Read/Write
R
—
—
—
R/W
R/W
R/W
R/W
Note: * Bit 7 and bits 3 to 0 are initialized by a reset and in hardware standby mode. They are not
initialized in software standby mode. Bits 3 to 0 can be written to in modes 5, 6, and 7 (onchip flash memory enabled). In other modes, they are always read as 0 and cannot be
modified.
Table 19.11 RAM Area Reassignment
Bit 3
Bit 2
Bit 1
Bit 0
RAM Area
RAMS
RAM2
RAM1
RAM0
H'FFF000 to H'FFF1FF
0
0/1
0/1
0/1
H'01F000 to H'01F1FF
1
0
0
0
H'01F200 to H'01F3FF
1
0
0
1
H'01F400 to H'01F5FF
1
0
1
0
H'01F600 to H'01F7FF
1
0
1
1
H'01F800 to H'01F9FF
1
1
0
0
H'01FA00 to H'01FBFF
1
1
0
1
H'01FC00 to H'01FDFF
1
1
1
0
H'01FE00 to H'01FFFF
1
1
1
1
Rev. 7.00 Sep 21, 2005 page 629 of 878
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
Example of Emulation of Real-Time Flash-Memory Update
Procedure
H'01F000
1. Set the RAME bit to 1 in SYSCR
to enable the on-chip RAM.
2. Overlap part of RAM (H'FFF000
to H'FFF1FF) onto the area
requiring real-time update (SB5).
Flash memory
address space
(Set RAMCR bits 3 to 0 to
1101.)
Overlapped by RAM
H'01F9FF
H'01FA00
Small-block
area (SB5)
H'01FBFF
3. Perform real-time updates in the
overlapping RAM.
4. After finalization of the update
data, clear the RAM overlap (by
clearing the RAMS bit).
H'01FDFF
H'01FE00
5. Program the data written in RAM
addresses H'FFF000 to
H'FFF1FF into the flash memory
area.
H'01FFFF
H'FFEF10
H'FFF000
H'FFF1FF
H'FFF200
On-chip RAM
area
H'FFFF0F
Notes: 1. When part of RAM (H'FFF000 to H'FFF1FF) is overlapped onto a small-block area in flash
memory, the overlapped flash memory area cannot be accessed. Access is enabled when the
overlap is cleared.
2. When the RAMS bit is set to 1, all flash memory blocks are write-protected and erase-protected,
regardless of the values of bits RAM2 to RAM0. In this state, no transition to program or erase
mode will take place if the P or E bit is set in the flash memory control register (FLMCR). To
actually program or erase a flash memory area, the RAMS bit must be cleared to 0.
Figure 19.14 Example of RAM Overlap
Rev. 7.00 Sep 21, 2005 page 630 of 878
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
19.7
Flash Memory PROM Mode
19.7.1
PROM Mode Setting
The on-chip flash memory of the H8/3048F can be programmed and erased not only in the onboard programming modes but also in PROM mode, using a general-purpose PROM programmer.
Table 19.12 indicates how to select PROM mode. Be sure to use the indicated table 19.13 socket
adapter in PROM mode.
Table 19.12 Selecting PROM Mode
Pins
Setting
Mode pins: MD2, MD1, MD0
Low
P80, P81, and P92
STBY and HWR
High
P50, P51, and P82
RES
Power on reset circuit
XTAL and EXTAL
Oscillator circuit
Rev. 7.00 Sep 21, 2005 page 631 of 878
REJ09B0259-0700
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
19.7.2
Socket Adapter and Memory Map
Programs can be written and verified by attaching a special 100-pin/32-pin socket adapter to the
PROM programmer. Table 19.13 gives ordering information for the socket adapter. Figure 19.15
shows a memory map in PROM mode. Figure 19.16 shows the socket adapter pin
interconnections.
Table 19.13 Socket Adapter
Microcontroller
Package
Socket Adapter
HD64F3048F
100-pin plastic QFP (FP-100B)
HS3048ESHF1H
100-pin plastic TQFP (TFP-100B)
HS3048ESNF1H
HD64F3048VF
HD64F3048TF
HD64F3048VTF
H8/3048F
MCU mode
H'000000
PROM mode
H'00000
On-chip ROM area
H'01FFFF
H'1FFFF
Figure 19.15 Memory Map in PROM Mode
Note: The FP-100B and TFP-100B pin pitch is only 0.5 mm. Use an appropriate tool when
inserting the device in the IC socket and removing it. For example, the tool listed in table
19.14 can be used.
Table 19.14
Manufacturer
Part Number
ENPLAS CORPORATION
HP-100 (vacuum pen)
Rev. 7.00 Sep 21, 2005 page 632 of 878
REJ09B0259-0700
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
H8/3048F
Pin No.
Pin Name
Socket Adapter
FP-100B, TFP-100B
Pin No.
10
RESO
VPP
1
64
NMI
A9
26
69
P63
A 16
2
58
P6 0
A 15
3
90
P83
WE
31
27
P30
I/O 0
13
28
P31
I/O 1
14
29
P32
I/O 2
15
30
P33
I/O 3
17
31
P34
I/O 4
18
32
P35
I/O 5
19
33
P36
I/O 6
20
34
P37
I/O 7
21
36
P1 0
A0
12
37
P1 1
A1
11
38
P1 2
A2
10
39
P1 3
A3
9
40
P1 4
A4
8
41
P1 5
A5
7
42
P1 6
A6
6
43
P1 7
A7
5
45
P2 0
A8
27
46
P2 1
OE
24
47
P2 2
A 10
23
48
P2 3
A 11
25
49
P2 4
A 12
4
50
P2 5
A 13
28
51
P2 6
A 14
29
52
P2 7
CE
22
P5 0, P5 1, P82
VCC
32
STBY, HWR
VSS
16
53, 54, 89
62, 71
73 to 75
87, 88, 14
76, 77
MD0, MD1, MD2,
AVCC, VREF
VCC
86
AVSS
VSS
57, 65, 92
63
66, 67
Other pins
Legend
VPP:
P80, P81, P92
1, 35, 68
11, 22, 44
Note:
HN28F101 (32 Pins)
Pin Name
RES
EXTAL, XTAL
Power-on
reset circuit
Programming
power supply
I/O 7 to I/O0 : Data input/output
A 16 to A 0 : Address input
Output enable
OE:
Chip enable
CE:
WE:
Write enable
Oscillator circuit
NC (OPEN)
This figure shows pin assignments, and does not show the entire socket adapter circuit. When undertaking a new
design, board design (power supply voltage stabilization, noise countermeasures, etc.) and operating timing design
as a high-speed CMOS LSI are necessary.
Figure 19.16 Wiring of Socket Adapter
Rev. 7.00 Sep 21, 2005 page 633 of 878
REJ09B0259-0700
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
19.7.3
Operation in PROM Mode
The program/erase/verify specifications in PROM mode are the same as for the standard
HN28F101 flash memory. Table 19.15 indicates how to select the various operating modes. The
H8/3048F does not have a device recognition code, so the programmer cannot read the device
name automatically.
Table 19.15 Operating Mode Selection in PROM Mode
Pins
VPP
VCC
CE
OE
WE
I/O7 to I/O0
A16 to A0
Read
VCC
VCC
L
L
H
Data output
Address input
Output
disable
VCC
VCC
L
H
H
High
impedance
Standby
VCC
VCC
H
X
X
High
impedance
Read
VPP
VCC
L
L
H
Data output
Output
disable
VPP
VCC
L
H
H
High
impedance
Standby
VPP
VCC
H
X
X
High
impedance
Write
VPP
VCC
L
H
L
Data input
Mode
Read
Command
write
Legend
L: Low level
H: High level
VPP: VPP level
VCC:VCC level
X: Don’t care
Rev. 7.00 Sep 21, 2005 page 634 of 878
REJ09B0259-0700
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
Table 19.16 PROM Mode Commands
1st Cycle
2nd Cycle
Command
Cycles
Mode
Address
Data
Mode
Address
Data
Memory read
1
Write
X
H'00
Read
RA
Dout
Erase setup/erase
2
Write
X
H'20
Write
X
H'20
Erase-verify
2
Write
EA
H'A0
Read
X
EVD
Auto-erase setup/
auto-erase
2
Write
X
H'30
Write
X
H'30
Program setup/
program
2
Write
X
H'40
Write
PA
PD
Program-verify
2
Write
X
H'C0
Read
X
PVD
Reset
2
Write
X
H'FF
Write
X
H'FF
PA:
EA:
RA:
PD:
PVD:
EVD:
Program address
Erase-verify address
Read address
Program data
Program-verify output data
Erase-verify output data
Rev. 7.00 Sep 21, 2005 page 635 of 878
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
High-Speed, High-Reliability Programming: Unused areas of the H8/3048F flash memory
contain H'FF data (initial value). The H8/3048F flash memory uses a high-speed, high-reliability
programming procedure. This procedure provides enhanced programming speed without
subjecting the device to voltage stress and without sacrificing the reliability of programmed data.
Figure 19.17 shows the basic high-speed, high-reliability programming flowchart. Tables 19.17
and 19.18 list the electrical characteristics during programming.
Start
Set VPP = 12.0 V ±0.6 V
Address = 0
n=0
n+1→n
Program setup command
Program command
Wait (25 µs)
Program-verify command
Wait (6 µs)
Address + 1 → address
Verification?
No good
OK
No
n = 20?
No
Last address?
Yes
Yes
Set VPP = VCC
End
Fail
Figure 19.17 High-Speed, High-Reliability Programming
Rev. 7.00 Sep 21, 2005 page 636 of 878
REJ09B0259-0700
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
High-Speed, High-Reliability Erasing: The H8/3048F flash memory uses a high-speed, highreliability erasing procedure. This procedure provides enhanced erasing speed without subjecting
the device to voltage stress and without sacrificing data reliability. Figure 19.18 shows the basic
high-speed, high-reliability erasing flowchart. Tables 19.17 and 19.18 list the electrical
characteristics during programming.
Start
Program 0 to all bits *
Address = 0
n=0
n+1→n
Erase setup/erase command
Wait (10 ms)
Erase-verify command
Wait (6 µs)
Address + 1 → address
Verification?
No good
OK
No
n = 3000?
No
Last address?
Yes
Yes
End
Fail
Note: * Follow the high-speed, high-reliability flowchart in programming all bits.
Figure 19.18 High-Speed, High-Reliability Erasing
Rev. 7.00 Sep 21, 2005 page 637 of 878
REJ09B0259-0700
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
Table 19.17 DC Characteristics in PROM Mode
(Conditions: VCC = 5.0 V ±10%, VPP = 12.0 V ±0.6 V, VSS = 0 V, Ta = 25°C ±5°C)
Item
Symbol
Min
Typ
Max
Unit
Test Conditions
Input high
voltage
I/O7 to I/O0,
A16 to A0,
OE, CE, WE
VIH
2.2
—
VCC + 0.3
V
Input low
voltage
I/O7 to I/O0,
A16 to A0,
OE, CE, WE
VIL
–0.3
—
0.8
V
Output high
voltage
I/O7 to I/O0
VOH
2.4
—
—
V
IOH = –200 µA
Output low
voltage
I/O7 to I/O0
VOL
—
—
0.45
V
IOL = 1.6 mA
Input leakage
current
I/O7 to I/O0,
A16 to A0,
OE, CE, WE
ILI
—
—
2
µA
VIN = 0 to VCC V
VCC current
Read
ICC
—
40
80
mA
Program
ICC
—
40
80
mA
Erase
ICC
—
40
80
mA
Read
IPP
—
—
200
µA
VPP = 5.0 V
—
10
20
mA
VPP = 12.6 V
VPP current
Program
IPP
—
20
40
mA
Erase
IPP
—
20
40
mA
Note: For details on absolute maximum ratings, see section 22.2.1. Using an LSI in excess of
absolute maximum ratings may result in permanent damage*.
* VPP peak overshoot should not exceed 13 V.
Rev. 7.00 Sep 21, 2005 page 638 of 878
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
Table 19.18 AC Characteristics in PROM Mode
(Conditions: VCC = 5.0 V ± 10%, VPP = 12.0 V ± 0.6 V, VSS = 0 V, Ta = 25°C ± 5°C)
Item
Symbol
Min
Typ
Max
Unit
Test Conditions
Command write cycle
tCWC
120
—
—
ns
Address setup time
tAS
0
—
—
ns
Address hold time
tAH
60
—
—
ns
Figure 19.19
Figure 19.20*
Figure 19.21
Data setup time
tDS
50
—
—
ns
Data hold time
tDH
10
—
—
ns
CE setup time
tCES
0
—
—
ns
CE hold time
tCEH
0
—
—
ns
VPP setup time
tVPS
100
—
—
ns
VPP hold time
tVPH
100
—
—
ns
WE programming pulse
width
tWEP
70
—
—
ns
WE programming pulse
high time
tWEH
20
—
—
ns
OE setup time before
command write
tOEWS
0
—
—
ns
OE setup time before verify
tOERS
6
—
—
µs
Verify access time
tVA
—
—
500
ns
OE setup time before
status polling
tOEPS
120
—
—
ns
Status polling access time
tSPA
—
—
120
ns
Program wait time
tPPW
25
—
—
ns
Erase wait time
tET
9
—
11
ms
Output disable time
tDF
0
—
40
ns
Total auto-erase time
tAET
0.5
—
30
s
Note: CE, OE, and WE should be high during transitions of VPP from 5 V to 12 V and from 12 V to
5 V.
* Input pulse level: 0.45 V to 2.4 V
Input rise time and fall time ≤ 10 ns
Timing reference levels: 0.8 V and 2.0 V for input; 0.8 V and 2.0 V for output
Rev. 7.00 Sep 21, 2005 page 639 of 878
REJ09B0259-0700
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
Auto-erase setup
VCC
VPP
Auto-erase and status polling
5.0 V
12 V
5.0 V
tVPS
tVPH
Address
CE
tCEH
OE
tCES
tOEWS
tWEP
WE
tDS
I/O 7
tOEPS
tCWC
tCES
tCEH
tWEH
tDH
Command
in
tCES
tAET
tWEP
tDH
tDS
tSPA
Command
in
Status polling
I/O 0 to I/O 6
Command
in
Command
in
Figure 19.19 Auto-Erase Timing
Rev. 7.00 Sep 21, 2005 page 640 of 878
REJ09B0259-0700
tDF
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
Program setup
VCC
Program
Program-verify
5.0 V
12 V
VPP
5.0 V
tVPS
tVPH
Address
Valid address
tAH
tAS
CE
tCEH
tCES
OE
tOEWS
tWEP
tCWC
tCEH
tWEH
tDH
WE
tDS
tCES
tCES
tPPW
tWEP
tDH
tDS
tCEH
tWEP
tOERS
tDH
tDS
tVA
tDF
I/O 7
Command
in
Data
in
Command
in
Valid data
out
I/O 0 to I/O 6
Command
in
Data
in
Command
in
Valid data
out
Note: Program-verify data output values may be intermediate between 1 and 0 if programming is insufficient.
Figure 19.20 High-Speed, High-Reliability Programming Timing
Rev. 7.00 Sep 21, 2005 page 641 of 878
REJ09B0259-0700
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
Erase setup
VCC
Erase
Erase-verify
5.0 V
12 V
VPP
5.0 V
tVPS
tVPH
Address
Valid address
tAS
tAH
CE
OE
tOEWS
tCES
WE
tCES
tCEH
tDS
I/O0 to I/O7
tCEH
tCES
tCEH
tCWC
tWEP
tET
tWEP
tOERS
tWEP
tVA
tWEH
tDH
tDS
Command
in
Command
in
tDH
tDS
Command
in
tDH
tDF
Valid data
out
Note: Erase-verify data output values may be intermediate between 1 and 0 if erasing is insufficient.
Figure 19.21 Erase Timing
Rev. 7.00 Sep 21, 2005 page 642 of 878
REJ09B0259-0700
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
19.8
Flash Memory Programming and Erasing Precautions (Dual-Power
Supply)
(1) Program with the specified voltages and timing.
The rated programming voltage (VPP) of the flash memory is 12.0 V.
If the PROM programmer is set to Renesas Technology HN28F101 specifications, VPP will be
12.0 V. Applied voltages in excess of the rating can permanently damage the device. Insure, in
particular, that peak overshoot at the Vpp and MD2 pins does not exceed the maximum rating of
13 V. Also, be very careful about PROM programmer overshoot.
(2) Before programming, check that the chip is correctly mounted in the PROM
programmer. Overcurrent damage to the device can result if the index marks on the PROM
programmer socket, socket adapter, and chip are not correctly aligned.
(3) Don’t touch the socket adapter or chip while programming. Touching either of these can
cause contact faults and write errors.
(4) Precautions in turning the programming voltage (VPP) on and off (see figures 19.22 to
19.24):
• Apply the programming voltage (VPP) after the rise of VCC, when the microcontroller is in a
stable condition. Shut off VPP before VCC, again while the microcontroller is in a stable
condition. If VPP is turned on or off while VCC is not within its rated voltage range (VCC = 2.7
to 5.5 V), since microcontroller operation is unstable and flash memory protection is not
functioning, the flash memory may be programmed or erased by mistake. This can occur even
if VCC = 0 V. The same danger of incorrect programming or erasing exists when VCC is within
its rated voltage range (VCC = 2.7 to 5.5 V) if the clock oscillator has not stabilized, if the clock
oscillator has stopped (except in standby), or if a program runaway has occurred. After VCC
power-up, do not apply VPP until the clock oscillator has had time to settle (tOSC1 = 20 ms min)
and the microcontroller is safely in the reset state, or the reset has been cleared.
These power-on and power-off timing requirements should also be satisfied in the event of a
power failure and recovery from a power failure. If these requirements are not satisfied, the
flash memory may not only be unintentionally programmed or erased; it may be permanently
damaged.
• The VPP bit in the flash memory control register (FLMCR) is set or cleared when the VPPE bit
in FLMCR is set or cleared while a voltage of 12.0 ± 0.6 V is being applied to the VPP pin.
After the VPPE bit is set, it becomes possible to write the erase block registers (EBR1 and
EBR2) and the EV, PV, E, and P bits in FLMCR. Accordingly, program or erase flash memory
Rev. 7.00 Sep 21, 2005 page 643 of 878
REJ09B0259-0700
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
5 to 10 µs after the VPPE bit is set. VPP should be turned off only when the P, E and VPPE bits
in FLMCR are cleared. Be sure that these bits are not set by mistaken access to FLMCR.
tVPS*
Programming/
erasing
tFRS
possible
φ
min 0 µs
tosc1
2.7 to 5.5 V
VCC
12±0.6 V
VPP
min 0 µs
0 to Vcc V
min 10 φ
0 to Vcc V
12±0.6 V
0 to Vcc V
0 to Vcc V
tMDS
MD2
min 0µs
RES
VppE
set
VppE
cleared
VPPE bit
Period during which flash memory access is prohibited
Period during which flash memory can be rewritten
(Execution of program in flash memory prohibited, and data reads other than verify
operations prohibited)
Note: * tVPS: 5 to 10µs
Figure 19.22 Power-On and Power-Off Timing (Boot Mode)
Rev. 7.00 Sep 21, 2005 page 644 of 878
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
tVPS*
1
Programming/
erasing
possible
t
FRS
φ
min 0 µs
tosc1
VCC
2.7 to
5.5 V
12±0.6 V
VPP
MD2
to 0
0 to
Vcc V
*2
*2
0 to
Vcc V
0 to
Vcc V
0 to
Vcc V
tMDS
RES
VppE
set
VppE
cleared
VPPE bit
Period during which flash memory access is prohibited
Period during which flash memory can be rewritten
(Execution of program in flash memory prohibited, and data reads other than verify
operations prohibited)
Notes: 1. tVPS: 5 to 10 µs
2. The level of the mode pins (MD2 to MD0) must be fixed from power-on to power-off
by pulling the pins up or down.
Figure 19.23 Power-On and Power-Off Timing (User Program Mode)
Rev. 7.00 Sep 21, 2005 page 645 of 878
REJ09B0259-0700
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
tVPS
tVPS
Programming/
erasing
possible
tFRS
tVPS
Programming/
erasing
possible tFRS
tVPS
Programming/
erasing
possible tFRS
Programming/
erasing
possible
φ
tosc1
VCC
VPP
2.7 to
5.5 V
0 to
Vcc V
12±0.6 V
min 0 µs
min 10 φ
12±0.6 V
MD2
to 0
0 to
Vcc V
tMDS*2
min 0µs
tMDS
RES
VppE
set
VppE
cleared
tFRS*2
Clear
VppE
VPPE bit
Mode
switching*1
Boot mode
Mode
switching*1
User
mode
User program mode
User
mode
User program
mode
Period during which flash memory access is prohibited
Period during which flash memory can be rewritten
(Execution of program in flash memory prohibited, and data reads other than verify operations prohibited)
Notes: 1. When entering boot mode or making a transition from boot mode to another mode, mode switching must be carried
out by means of RES input. The pin output states change during this switchover interval (the interval during which
the RES pin is low), and therefore these pins should not be used as output signals during this time.
2. When making a transition from boot mode to another mode, the flash memory read setup time tFRS and
mode programming setup time tMDS must be satisfied with respect to RES clearance timing.
Figure 19.24 Mode Transition Timing
(Example: Boot Mode → User Mode ↔ User Program Mode)
Rev. 7.00 Sep 21, 2005 page 646 of 878
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
(5) Do not apply 12 V to the VPP pin during normal operation. To prevent microcontroller
errors caused by accidental programming or erasing, apply 12 V to VPP only when the flash
memory is programmed or erased, or when flash memory is emulated by RAM. While 12 V is
applied, the watchdog timer should be running and enabled to halt runaway program execution, so
that program runaway will not lead to overprogramming or overerasing.
(6) Disable watchdog-timer reset output (RESO
RESO)
RESO while the programming voltage (VPP) is
turned on. If 12 V is applied during watchdog timer reset output (while the RESO pin is low),
overcurrent flow will permanently destroy the reset output circuit. The watchdog timers reset
output enable bit (RSTOE) should not be set to 1.
If a pull-up resistor is externally attached to the VPP/RESO pin, a diode is necessary to prevent
reverse current from flowing to VCC when VPP is applied (figure 19.25).
(7) If the watchdog timer generates a reset output signal when 12 V is not applied, the rise
and fall of the reset output waveform will be delayed by any decoupling capacitors
connected to the VPP pin.
+5 V
Pull-up resistor and
a diode
VPP /
RESO
+12 V
H8/3048F
(dual-power supply)
1.0 µF
0.01 µF
Figure 19.25 VPP Power Supply Circuit Design (Example)
Rev. 7.00 Sep 21, 2005 page 647 of 878
REJ09B0259-0700
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
(8) Notes concerning mounting board development—handling of VPP and mode MD2 pins
1. The standard 12 V high voltage is applied to the VPP and mode MD2 pins when erasing or
programming flash memory. The voltage at these pins also includes overshoot and noise, and
the following points should be noted to ensure that the 13 V maximum rated voltage is not
exceeded.
a. Bypass capacitors should be inserted to eliminate overshoot and noise. These should be
positioned as close as possible to the chip’s VPP and mode MD2 pins.
1.0 µF:
Stabilizes fluctuations in the low-frequency components, such as power supply
ripple.
0.01 µF: Bypasses high-frequency components such as induction noise.
b. The VPP and mode MD2 pin wiring should be kept as short as possible to suppress
induction noise. When designing a new board, in particular, noise may be increased by
jumper wires, etc. In this case too, the power supply waveform should be monitored and
measures taken to prevent the maximum rating from being exceeded.
c. The maximum rated voltage is based on the potential of the VSS pin. If the potential of this
pin oscillates due to current fluctuations, etc., the voltage of the VPP and mode MD2 pins
may reciprocally exceed the maximum rated voltage. Careful attention must therefore be
paid to stabilizing the reference potential.
Note: When the user system’s 12 V power supply is connected, attention must be paid to the
current capacity. A power supply with a small current capacity will not be able to
handle fluctuations in the chip’s operating voltage, resulting in voltage drops and rises
or oscillation that may make it impossible to obtain the rated operating voltage. If the
power supply has a large current capacity, or if the 12 V voltage is turned on abruptly
by means of a switch, etc., caution is required since a voltage exceeding the maximum
rating may be generated due to the inductance component of the power supply wiring
or the power supply characteristics.
Before using the power supply, check the power supply waveform to ensure that the
above problems will not arise.
2. 12 V is applied to the VPP and mode MD2 pins when programming or erasing flash memory.
When these pins are pulled up to the VCC line in normal operation, diodes should be inserted to
prevent reverse current from flowing to the VCC line when 12 V is applied.
Note: In normal operation, if the mode MD2 pin to which 12 V is applied is to be set to 0, it
should be pulled down with a resistor.
Rev. 7.00 Sep 21, 2005 page 648 of 878
REJ09B0259-0700
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
A sample circuit is shown figure 19.26.
VCC
VPP pin
12 V
VPP
H8/3048F
(dualpower
supply)
VCC
0.01 µF 1.0 µF
12 V
MD2
mode
pin
Mode pin
0.01 µF 1.0 µF
Adapter board
User system
Figure 19.26 Example of Mounting Board Design for the H8/3048F-ZTAT with the DualPower Supply
(Connection to Adapter Board—When VPP Pin and Mode Pin Settings Are 1)
(9) Do not set or clear the VppE bit during execution of a program in flash memory.
Flash memory data cannot be read normally when the VppE bit is set or cleared. After the VppE
bit is cleared, flash memory data can be rewritten after waiting for the elapse of the Vpp enable
setup time (tVPS: 5 10 µs), but flash memory cannot be accessed for purposes other than
verification (verification during programming, erasing, or prewriting). After the VppE is cleared,
wait for the elapse of the flash memory read setup time before performing program execution and
data reading in flash memory.
(10) Do not use interrupts while programming or erasing flash memory.
When Vpp is applied, disable all interrupt requests, including NMI, to give the programming or
erase operation (including RAM emulation) the highest priority.
(11) The Vpp flag is set and cleared by a threshold decision on the voltage applied to the
Vpp pin. The threshold level is approximately in the range from Vcc +2 V to 11.4 V.
When this flag is set, it becomes possible to write to the flash memory control register (FLMCR)
and the erase block registers (EBR1 and EBR2), even though the Vpp voltage may not yet have
Rev. 7.00 Sep 21, 2005 page 649 of 878
REJ09B0259-0700
Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
reached the programming voltage range of 12.0 V ±0.6 V. Do not actually program or erase the
flash memory until Vpp has reached the programming voltage range.
The programming voltage range for programming and erasing flash memory is 12.0 V ±0.6 V
(11.4 V to 12.6 V). Programming and erasing cannot be performed correctly outside this range.
When not programming or erasing the flash memory, ensure that the Vpp voltage does not exceed
the Vcc voltage. This will prevent unintentional programming and erasing.
(12) After the Vpp enable bit (VppE) is cleared, the flash memory read setup time (tFRS)*
must elapse before the flash memory is read.
When switching from boot mode or user program mode to normal mode (Vpp ≠ 12 V, MD2 ≠ 12
V), this setup time is required as the period from VppE bit clearance until the flash memory is
read.
When switching from boot mode to another mode, a mode programming setup time (tMDS) is
required with respect to the RES release timing.
Note: * The flash memory read setup time stipulates the interval before flash memory is read after
the VppE bit is cleared (figure 19.24). Also, when using an external clock (EXTAL input),
after powering on and when returning from standby mode, the flash memory read setup
time must elapse before the flash memory is read.
Rev. 7.00 Sep 21, 2005 page 650 of 878
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
19.9
Notes when Converting the F-ZTAT (Dual-Power Supply)
Application Software to the Mask-ROM Versions
Please note the following when converting the F-ZTAT (dual-power supply) application software
to the mask-ROM versions.
The values read from the internal registers (refer to appendix B, Internal I/O Register, Table B.1)
for the flash ROM of the mask-ROM version and F-ZTAT (dual-power supply) version differ as
follows.
Status
Register
Bit
FLMCR
VPP
F-ZTAT (Dual-Power Supply)
Version
Mask-ROM Version
0: Application software running
1: Programming
0: Not read out
1: Application software running
Note: This difference applies to all the F-ZTAT (dual-power supply) versions and all the maskROM versions that have different ROM size.
Rev. 7.00 Sep 21, 2005 page 651 of 878
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Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V))
Rev. 7.00 Sep 21, 2005 page 652 of 878
REJ09B0259-0700
Section 20 Clock Pulse Generator
Section 20 Clock Pulse Generator
20.1
Overview
The H8/3048 Group has a built-in clock pulse generator (CPG) that generates the system clock (φ)
and other internal clock signals (φ/2 to φ/4096). After duty adjustment, a frequency divider divides
the clock frequency to generate the system clock (φ). The system clock is output at the φ pin*1 and
furnished as a master clock to prescalers that supply clock signals to the on-chip supporting
modules. Frequency division ratios of 1/1, 1/2, 1/4, and 1/8 can be selected for the frequency
divider by settings in a division control register (DIVCR). Power consumption in the chip is
reduced in almost direct proportion to the frequency division ratio*2.
Notes: 1. Usage of the φ pin differs depending on the chip operating mode and the PSTOP bit
setting in the module standby control register (MSTCR). For details, see section 21.7,
System Clock Output Disabling Function.
2. The division ratio of the frequency divider can be changed dynamically during
operation. The clock output at the φ pin also changes when the division ratio is
changed. The frequency output at the φ pin is shown below.
φ = EXTAL × n
where,
EXTAL: Frequency of crystal resonator or external clock signal
n:
Frequency division ratio (n = 1/1, 1/2, 1/4, or 1/8)
Rev. 7.00 Sep 21, 2005 page 653 of 878
REJ09B0259-0700
Section 20 Clock Pulse Generator
20.1.1
Block Diagram
Figure 20.1 shows a block diagram of the clock pulse generator.
CPG
XTAL
Oscillator
EXTAL
Duty
adjustment
circuit
Frequency
divider
Prescalers
Division
control
register
Data bus
φ
Figure 20.1 Block Diagram of Clock Pulse Generator
Rev. 7.00 Sep 21, 2005 page 654 of 878
REJ09B0259-0700
φ/2 to φ/4096
Section 20 Clock Pulse Generator
20.2
Oscillator Circuit
Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock
signal.
20.2.1
Connecting a Crystal Resonator
Circuit Configuration: A crystal resonator can be connected as in the example in figure 20.2.
The damping resistance Rd should be selected according to table 20.1. An AT-cut parallelresonance crystal should be used.
C L1
EXTAL
XTAL
Rd
C L2
CL1 = CL2 = 10 pF to 22 pF
Figure 20.2 Connection of Crystal Resonator (Example)
In order to improve the accuracy of the oscillation frequency, a thorough study of oscillation
matching evaluation, etc., should be carried out when deciding the circuit constants.
Table 20.1 Damping Resistance Value
Damping Resistance
Value
Rd
(Ω)
Frequency f (MHz)
2
2<f≤4
4<f≤8
8 < f ≤ 10
10 < f ≤ 13 13 < f ≤ 16 16 < f ≤ 18
For products
listed below*
1k
500
200
0
0
0
0
H8/3048F
1k
1k
500
200
100
0
—
Note: A crystal resonator between 2 MHz and 18 MHz can be used. If the chip is to be operated
at less than 2 MHz, the on-chip frequency divider should be used. (A crystal resonator of
less than 2 MHz cannot be used.)
* H8/3048ZTAT, H8/3048 mask-ROM, H8/3047 mask-ROM, H8/3045 mask-ROM,
H8/3044 mask-ROM
Rev. 7.00 Sep 21, 2005 page 655 of 878
REJ09B0259-0700
Section 20 Clock Pulse Generator
Crystal Resonator: Figure 20.3 shows an equivalent circuit of the crystal resonator. The crystal
resonator should have the characteristics listed in table 20.2.
CL
L
Rs
XTAL
EXTAL
AT-cut parallel-resonance type
C0
Figure 20.3 Crystal Resonator Equivalent Circuit
Table 20.2 Crystal Resonator Parameters
Frequency (MHz)
Rs max (Ω
Ω)
2
4
8
10
12
16
18
500
120
80
70
60
50
40
C0 max (pF)
7
Use a crystal resonator with a frequency equal to the system clock frequency (φ).
Notes on Board Design: When a crystal resonator is connected, the following points should be
noted:
Other signal lines should be routed away from the oscillator circuit to prevent induction from
interfering with correct oscillation. See figure 20.4.
When the board is designed, the crystal resonator and its load capacitors should be placed as close
as possible to the XTAL and EXTAL pins.
Rev. 7.00 Sep 21, 2005 page 656 of 878
REJ09B0259-0700
Section 20 Clock Pulse Generator
Avoid
Signal A
Signal B
C L2
H8/3048 Group
XTAL
EXTAL
C L1
Figure 20.4 Example of Incorrect Board Design
20.2.2
External Clock Input
Circuit Configuration: An external clock signal can be input as shown in the examples in figure
20.5. The external clock is input from the EXTAL pin. If the XTAL pin is left open, the stray
capacitance should not exceed 10 pF. If the stray capacitance at the XTAL pin exceeds 10 pF in
configuration a, use configuration b instead and hold the clock high in standby mode.
External clock input
EXTAL
Open
XTAL
a. XTAL pin left open
External clock input
EXTAL
74HC04
XTAL
b. Complementary clock input at XTAL pin
Figure 20.5 External Clock Input (Examples)
Rev. 7.00 Sep 21, 2005 page 657 of 878
REJ09B0259-0700
Section 20 Clock Pulse Generator
External Clock: The external clock frequency should be equal to the system clock frequency (φ)
when not divided by the on-chip frequency divider. Table 20.3, figures 20.6 and 20.7 indicate the
clock timing.
When the appropriate external clock is input via the EXTAL pin, its waveform is corrected by the
on-chip oscillator and duty adjustment circuit. The resulting stable clock is output to external
devices after the external clock settling time (tDEXT) has passed after the clock input. The system
must remain reset with the reset signal low during tDEXT, while the clock output is unstable.
Table 20.3 Clock Timing
VCC =
2.7 V to 5.5 V
VCC =
5.0 V ± 10%
Item
Symbol
Min
Max
Min
Max
Unit
Test Conditions
External clock
input low pulse
width
tEXL
40
—
20
—
ns
Figure 20.6
External clock
input high pulse
width
tEXH
40
—
20
—
ns
External clock
rise time
tEXr
—
10
—
5
ns
External clock
fall time
tEXf
—
10
—
5
ns
Clock low pulse
width
tCL
0.4
0.6
0.4
0.6
tcyc
φ ≥ 5 MHz
80
—
80
—
ns
φ < 5 MHz
Clock high pulse
width
tCH
0.4
0.6
0.4
0.6
tcyc
φ ≥ 5 MHz
80
—
80
—
ns
φ < 5 MHz
External clock
output settling
delay time
tDEXT*
500
—
500
—
µs
Figure 20.7
Note: * tDEXT includes 10 tcyc of RES (tRESW).
Rev. 7.00 Sep 21, 2005 page 658 of 878
REJ09B0259-0700
Figure
22.7
Section 20 Clock Pulse Generator
tEXH
tEXL
VCC × 0.7
EXTAL
VCC × 0.5
0.3 V
tEXf
tEXr
Figure 20.6 External Clock Input Timing
VCC
STBY
VIH
EXTAL
φ (internal or
external)
RES
tDEXT
Figure 20.7 External Clock Output Settling Delay Timing
20.3
Duty Adjustment Circuit
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate the signal that becomes the system clock.
20.4
Prescalers
The prescalers divide the system clock (φ) to generate internal clocks (φ/2 to φ/4096).
Rev. 7.00 Sep 21, 2005 page 659 of 878
REJ09B0259-0700
Section 20 Clock Pulse Generator
20.5
Frequency Divider
The frequency divider divides the duty-adjusted clock signal to generate the system clock (φ). The
frequency division ratio can be changed dynamically by modifying the value in DIVCR, as
described below. Power consumption in the chip is reduced in almost direct proportion to the
frequency division ratio. The system clock generated by the frequency divider can be output at the
φ pin.
20.5.1
Register Configuration
Table 20.4 summarizes the frequency division register.
Table 20.4 Frequency Division Register
Address*
Name
Abbreviation
R/W
Initial Value
H'FF5D
Division control register
DIVCR
R/W
H'FC
Note: * The lower 16 bits of the address are shown.
20.5.2
Division Control Register (DIVCR)
DIVCR is an 8-bit readable/writable register that selects the division ratio of the frequency
divider.
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
—
DIV1
DIV0
Initial value
1
1
1
1
1
1
0
0
Read/Write
—
—
—
—
—
—
R/W
R/W
Reserved bits
Divide bits 1 and 0
These bits select the
frequency division ratio
DIVCR is initialized to H'FC by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 2—Reserved: Read-only bits, always read as 1.
Rev. 7.00 Sep 21, 2005 page 660 of 878
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Section 20 Clock Pulse Generator
Bits 1 and 0—Divide (DIV1 and DIV0): These bits select the frequency division ratio, as
follows.
Bit 1: DIV1
Bit 0: DIV0
Frequency Division Ratio
0
0
1/1
1
1/2
0
1/4
1
1/8
1
20.5.3
(Initial value)
Usage Notes
The DIVCR setting changes the φ frequency, so note the following points.
• Select a frequency division ratio that stays within the assured operation range specified for the
clock cycle time tcyc in the AC electrical characteristics. Note that φMIN must be in the lower
limit of the clock frequency range. Avoid settings that give system clock frequencies less than
the lower limit.
Table 20.5 shows the comparison with the clock frequency range for each version.
Table 20.5 Comparison with the Clock Frequency Ranges in the H8/3048 Group
F-ZTAT
ZTAT
Product type
H8/3048F
H8/3048
Guaranteed 4.5–5.5 V
clock
3.15–5.5 V
frequency
2.7–5.5 V
range
1–16 MHz
1–18 MHz
1–18 MHz
—
1–13 MHz
1–13 MHz
1–8 MHz
1–8 MHz
1–8 MHz
Crystal oscillation range
2–16 MHz
2–18 MHz
2–18 MHz
ROM type
Mask ROM
H8/3048
Mask ROM
Version
H8/3047
Mask ROM
Version
H8/3045
Mask ROM
Version
H8/3044
Mask ROM
Version
• All on-chip module operations are based on φ. Note that the timing of timer operations, serial
communication, and other time-dependent processing differs before and after any change in
the division ratio. The waiting time for exit from software standby mode also changes when
the division ratio is changed. For details, see section 21.4.3, Selection of Waiting Time for Exit
from Software Standby Mode.
Rev. 7.00 Sep 21, 2005 page 661 of 878
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Section 20 Clock Pulse Generator
Rev. 7.00 Sep 21, 2005 page 662 of 878
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Section 21 Power-Down State
Section 21 Power-Down State
21.1
Overview
The H8/3048 Group has a power-down state that greatly reduces power consumption by halting
the CPU, and a module standby function that reduces power consumption by selectively halting
on-chip modules.
The power-down state includes the following three modes:
• Sleep mode
• Software standby mode
• Hardware standby mode
The module standby function can halt on-chip supporting modules independently of the powerdown state. The modules that can be halted are the ITU, SCI0, SCI1, DMAC, refresh controller,
and A/D converter.
Table 21.1 indicates the methods of entering and exiting the power-down modes and module
standby mode, and gives the status of the CPU and on-chip supporting modules in each mode.
Rev. 7.00 Sep 21, 2005 page 663 of 878
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Halted*2 Halted*2
and
and
reset
held*1
Halted
and
reset
Halted
and
reset
Active
Halted
and
reset
Halted
and
reset
Active
A/D
Halted
and
reset
Halted
and
reset
Active
—
• NMI
• IRQ0 to IRQ2
• RES
• STBY
• Interrupt
• RES
• STBY
Exiting
Conditions
High
—
impedance*2
• STBY
• RES
• Clear MSTCR
bit to 0*4
High
• STBY
impedance • RES
Held
Held
φ output
High
output
I/O Ports
φ Clock
Output
Held*3 High
impedance
Held
Held
Other
Modules RAM
Halted*2 Halted*2 Halted*2 Halted*2 Active
and
and
and
and
reset
reset
reset
reset
Halted
and
reset
Halted
and
reset
Halted
and
reset
Halted
and
reset
Active
Active
SCI1
Rev. 7.00 Sep 21, 2005 page 664 of 878
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Legend
SYSCR: System control register
SSBY: Software standby bit
MSTCR: Module standby control register
RTCNT and bits 7 and 6 of RTMCSR are initialized. Other bits and registers hold their previous states.
State in which the corresponding MSTCR bit was set to 1. For details see section 21.2.2, Module Standby Control Register (MSTCR).
The RAME bit must be cleared to 0 in SYSCR before the transition from the program execution state to hardware standby mode.
When a MSTCR bit is set to 1, the registers of the corresponding on-chip supporting module are initialized. To restart the module, first clear the MSTCR bit to 0, then set
up the module registers again.
—
Halted
and
reset
Halted
and
held*1
Active
SCI0
Notes: 1.
2.
3.
4.
Active
Halted
and
reset
Halted
and
reset
Active
Refresh
Controller ITU
Corresponding Active
bit set to 1 in
MSTCR
Undetermined
Held
Held
CPU
Registers DMAC
Module
standby
Halted Halted
Halted
CPU
Hardware Low input at
standby STBY pin
mode
Active
Clock
Halted Halted
SLEEP
instruction
executed
while
SSBY = 0
in SYSCR
Entering
Conditions
Software SLEEP
standby instruction
mode
executed
while
SSBY = 1
in SYSCR
Sleep
mode
Mode
State
Section 21 Power-Down State
Table 21.1 Power-Down State and Module Standby Function
Section 21 Power-Down State
21.2
Register Configuration
The H8/3048 Group has a system control register (SYSCR) that controls the power-down state,
and a module standby control register (MSTCR) that controls the module standby function. Table
21.2 summarizes these registers.
Table 21.2 Control Register
Address*
Name
Abbreviation
R/W
Initial Value
H'FFF2
System control register
SYSCR
R/W
H'0B
H'FF5E
Module standby control register
MSTCR
R/W
H'40
Note: * Lower 16 bits of the address.
21.2.1
System Control Register (SYSCR)
Bit
7
6
5
4
3
2
1
0
SSBY
STS2
STS1
STS0
UE
NMIEG
—
RAME
Initial value
0
0
0
0
1
0
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
RAM enable
Reserved bit
NMI edge select
User bit enable
Standby timer select 2 to 0
These bits select the
waiting time at exit from
software standby mode
Software standby
Enables transition to
software standby mode
SYSCR is an 8-bit readable/writable register. Bit 7 (SSBY) and bits 6 to 4 (STS2 to STS0) control
the power-down state. For information on the other SYSCR bits, see section 3.3, System Control
Register (SYSCR).
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Section 21 Power-Down State
Bit 7—Software Standby (SSBY): Enables transition to software standby mode. When software
standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal
operation. To clear this bit, write 0.
Bit 7: SSBY
Description
0
SLEEP instruction causes transition to sleep mode
1
SLEEP instruction causes transition to software standby mode
(Initial value)
Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU
and on-chip supporting modules wait for the clock to settle when software standby mode is exited
by an external interrupt. If the clock is generated by a crystal resonator, set these bits according to
the clock frequency so that the waiting time will be at least 7 ms. See table 21.3. If an external
clock is used, any value may be selected.
Bit 6: STS2
Bit 5: STS1
Bit 4: STS0
Description
0
0
0
Waiting time = 8,192 states
1
Waiting time = 16,384 states
0
Waiting time = 32,768 states
1
Waiting time = 65,536 states
0
Waiting time = 131,072 states
1
Waiting time = 1,024 states
—
Illegal setting
1
1
0
1
Rev. 7.00 Sep 21, 2005 page 666 of 878
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(Initial value)
Section 21 Power-Down State
21.2.2
Module Standby Control Register (MSTCR)
MSTCR is an 8-bit readable/writable register that controls output of the system clock (φ). It also
controls the module standby function, which places individual on-chip supporting modules in the
standby state. Module standby can be designated for the ITU, SCI0, SCI1, DMAC, refresh
controller, and A/D converter modules.
Bit
7
6
PSTOP
—
Initial value
0
1
0
0
0
0
0
0
Read/Write
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
4
5
3
2
1
0
MSTOP5 MSTOP4 MSTOP3 MSTOP2 MSTOP1 MSTOP0
Reserved bit
Module standby 5 to 0
These bits select modules
to be placed in standby
ø clock stop
Enables or disables
output of the system clock
MSTCR is initialized to H'40 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—φ
φ Clock Stop (PSTOP): Enables or disables output of the system clock (φ).
Bit 1: PSTOP
Description
0
System clock output is enabled
1
System clock output is disabled
(Initial value)
Bit 6—Reserved: Read-only bit, always read as 1.
Bit 5—Module Standby 5 (MSTOP5): Selects whether to place the ITU in standby.
Bit 5: MSTOP5
Description
0
ITU operates normally
1
ITU is in standby state
(Initial value)
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Section 21 Power-Down State
Bit 4—Module Standby 4 (MSTOP4): Selects whether to place SCI0 in standby.
Bit 4: MSTOP4
Description
0
SCI0 operates normally
1
SCI0 is in standby state
(Initial value)
Bit 3—Module Standby 3 (MSTOP3): Selects whether to place SCI1 in standby.
Bit 3: MSTOP3
Description
0
SCI1 operates normally
1
SCI1 is in standby state
(Initial value)
Bit 2—Module Standby 2 (MSTOP2): Selects whether to place the DMAC in standby.
Bit 2: MSTOP2
Description
0
DMAC operates normally
1
DMAC is in standby state
(Initial value)
Bit 1—Module Standby 1 (MSTOP1): Selects whether to place the refresh controller in standby.
Bit 1: MSTOP1
Description
0
Refresh controller operates normally
1
Refresh controller is in standby state
(Initial value)
Bit 0—Module Standby 0 (MSTOP0): Selects whether to place the A/D converter in standby.
Bit 0: MSTOP0
Description
0
A/D converter operates normally
1
A/D converter is in standby state
Rev. 7.00 Sep 21, 2005 page 668 of 878
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(Initial value)
Section 21 Power-Down State
21.3
Sleep Mode
21.3.1
Transition to Sleep Mode
When the SSBY bit is cleared to 0 in SYSCR, execution of the SLEEP instruction causes a
transition from the program execution state to sleep mode. Immediately after executing the SLEEP
instruction the CPU halts, but the contents of its internal registers are retained. The DMA
controller (DMAC), refresh controller, and on-chip supporting modules do not halt in sleep mode.
Modules which have been placed in standby by the module standby function, however, remain
halted.
21.3.2
Exit from Sleep Mode
Sleep mode is exited by an interrupt, or by input at the RES or STBY pin.
Exit by Interrupt: An interrupt terminates sleep mode and causes a transition to the interrupt
exception handling state. Sleep mode is not exited by an interrupt source in an on-chip supporting
module if the interrupt is disabled in the on-chip supporting module. Sleep mode is not exited by
an interrupt other than NMI if the interrupt is masked by the I and UI bits in CCR and IPR.
Exit by RES Input: Low input at the RES pin exits from sleep mode to the reset state.
Exit by STBY Input: Low input at the STBY pin exits from sleep mode to hardware standby
mode.
21.4
Software Standby Mode
21.4.1
Transition to Software Standby Mode
To enter software standby mode, execute the SLEEP instruction while the SSBY bit is set to 1 in
SYSCR.
In software standby mode, current dissipation is reduced to an extremely low level because the
CPU, clock, and on-chip supporting modules all halt. The DMAC and on-chip supporting modules
are reset. As long as the specified voltage is supplied, however, CPU register contents and on-chip
RAM data are retained. The settings of the I/O ports and refresh controller* are also held.
Note: * RTCNT and bits 7 and 6 of RTMCSR are initialized. Other bits and registers hold their
previous states.
Rev. 7.00 Sep 21, 2005 page 669 of 878
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Section 21 Power-Down State
When the WDT is used as a watchdog timer (WT/IT = 1), the TME bit must be cleared to 0 before
setting SSBY. Also, when setting TME to 1, SSBY should be cleared to 0.
Clear the BRLE bit in BRCR (inhibiting bus release) before making a transition to software
standby mode.
21.4.2
Exit from Software Standby Mode
Software standby mode can be exited by input of an external interrupt at the NMI, IRQ0, IRQ1, or
IRQ2 pin, or by input at the RES or STBY pin.
Exit by Interrupt: When an NMI, IRQ0, IRQ1, or IRQ2 interrupt request signal is received, the
clock oscillator begins operating. After the oscillator settling time selected by bits STS2 to STS0
in SYSCR, stable clock signals are supplied to the entire chip, software standby mode ends, and
interrupt exception handling begins. Software standby mode is not exited if the interrupt enable
bits of interrupts IRQ0, IRQ1, and IRQ2 are cleared to 0, or if these interrupts are masked in the
CPU.
Exit by RES Input: When the RES input goes low, the clock oscillator starts and clock pulses are
supplied immediately to the entire chip. The RES signal must be held low long enough for the
clock oscillator to stabilize. When RES goes high, the CPU starts reset exception handling.
Exit by STBY Input: Low input at the STBY pin causes a transition to hardware standby mode.
21.4.3
Selection of Waiting Time for Exit from Software Standby Mode
Bits STS2 to STS0 in SYSCR and bits DIV1 and DIV0 in DIVCR should be set as follows.
Crystal Resonator: Set STS2 to STS0, DIV1, and DIV0 so that the waiting time (for the clock to
stabilize) is at least 7 ms. Table 21.3 indicates the waiting times that are selected by STS2 to
STS0, DIV1, and DIV0 settings at various system clock frequencies. Refer to table 21.3 for the
operating frequency and the waiting time needed for the oscillator to settle.
External Clock: Any values may be set.
Rev. 7.00 Sep 21, 2005 page 670 of 878
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Section 21 Power-Down State
Table 21.3 Clock Frequency and Waiting Time for Clock to Settle
DIV1 DIV0 STS2 STS1 STS0 Waiting Time 18 MHz 16 MHz 12 MHz 10 MHz 8 MHz 6 MHz 4 MHz 2 MHz 1 MHz Unit
0
0
1
1
0
1
0
1
0
0
0
8192 states
0.46
0.51
0.65
0.8
0
0
1
16384 states
0.91
0
1
0
32768 states
1.8
1.0
1.3
2.0
2.7
0
1
1
65536 states
3.6
4.1
1
0
0
1
0
1
131072 states 7.3*
1024 states
1
1
—
0
0
0
8192 states
0.91
1.02
1.4
1.6
2.0
2.7
4.0
8.2*
16.4* ms
0
0
1
16384 states
1.8
2.0
2.7
3.3
4.1
5.5
8.2*
16.4
32.8
0
1
0
32768 states
3.6
4.1
5.5
6.6
8.2*
10.9* 16.4
32.8
65.5
0
1
1
65536 states
7.3*
8.2*
10.9*
13.1*
16.4
21.8
32.8
65.5
131.1
1
0
0
131072 states 14.6
16.4
21.8
26.2
32.8
43.7
65.5
131.1 262.1
1
0
1
1024 states
0.11
0.13
0.17
0.20
0.26
0.34
0.51
1.0
0.057
1.0
1.3
2.0
4.1
1.6
2.0
3.3
4.1
5.5
6.6
8.2*
10.9*
0.064
0.085
8.2*
2.7
4.1
8.2*
16.4
5.5
8.2*
16.4
32.8
8.2*
10.9* 16.4
32.8
65.5
13.1*
16.4
21.8
32.8
65.5
131.1
0.10
0.13
0.17
0.26
0.51
1.0
Illegal setting
1
1
—
0
0
0
8192 states
1.8
2.0
2.7
3.3
4.1
5.5
0
0
1
16384 states
3.6
4.1
5.5
6.6
8.2*
10.9* 16.4
2.0
Illegal setting
8.2*
16.4* 32.8* ms
32.8
65.5
131.1
0
1
0
32768 states
7.3*
8.2*
10.9*
13.1*
16.4
21.8
32.8
65.5
0
1
1
65536 states
14.6
16.4
21.8
26.2
32.8
43.7
65.5
131.1 262.1
1
0
0
131072 states 29.1
32.8
43.7
52.4
65.5
87.4
131.1 262.1 524.3
1
0
1
1024 states
0.23
0.26
0.34
0.41
0.51
0.68
1.02
2.0
4.1
1
1
—
0
0
0
8192 states
3.6
4.1
5.5
6.6
8.2*
10.9* 16.4* 32.8* 65.5
0
0
1
16384 states
7.3*
8.2*
10.9*
13.1*
16.4
21.8
32.8
65.5
0
1
0
32768 states
14.6
16.4
21.8
26.2
32.8
43.7
65.5
131.1 262.1
0
1
1
65536 states
29.1
32.8
43.7
52.4
65.5
87.4
131.1 262.1 524.3
1
0
0
131072 states 58.3
65.5
87.4
104.9
131.1 174.8 262.1 524.3 1048.6
1024 states
0.51
0.68
0.82
1.0
1
0
1
1
1
—
ms
Illegal setting
0.46
1.4
2.0
4.1
ms
131.1
8.2
Illegal setting
*: Recommended setting
Rev. 7.00 Sep 21, 2005 page 671 of 878
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Section 21 Power-Down State
21.4.4
Sample Application of Software Standby Mode
Figure 21.1 shows an example in which software standby mode is entered at the fall of NMI and
exited at the rise of NMI.
With the NMI edge select bit (NMIEG) cleared to 0 in SYSCR (selecting the falling edge), an
NMI interrupt occurs. Next the NMIEG bit is set to 1 (selecting the rising edge) and the SSBY bit
is set to 1; then the SLEEP instruction is executed to enter software standby mode.
Software standby mode is exited at the next rising edge of the NMI signal.
Clock
oscillator
φ
NMI
NMIEG
SSBY
NMI interrupt
handler
NMIEG = 1
SSBY = 1
Software standby
mode (powerdown state)
Oscillator
settling time
(tosc2)
NMI exception
handling
SLEEP
instruction
Figure 21.1 NMI Timing for Software Standby Mode (Example)
21.4.5
Note
The I/O ports retain their existing states in software standby mode. If a port is in the high output
state, its output current is not reduced.
Rev. 7.00 Sep 21, 2005 page 672 of 878
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Section 21 Power-Down State
21.5
Hardware Standby Mode
21.5.1
Transition to Hardware Standby Mode
Regardless of its current state, the chip enters hardware standby mode whenever the STBY pin
goes low. Hardware standby mode reduces power consumption drastically by halting all functions
of the CPU, DMAC, refresh controller, and on-chip supporting modules. All modules are reset
except the on-chip RAM. As long as the specified voltage is supplied, on-chip RAM data is
retained. I/O ports are placed in the high-impedance state.
Clear the RAME bit to 0 in SYSCR before STBY goes low to retain on-chip RAM data.
The inputs at the mode pins (MD2 to MD0) should not be changed during hardware standby
mode.
21.5.2
Exit from Hardware Standby Mode
Hardware standby mode is exited by inputs at the STBY and RES pins. While RES is low, when
STBY goes high, the clock oscillator starts running. RES should be held low long enough for the
clock oscillator to settle. When RES goes high, reset exception handling begins, followed by a
transition to the program execution state.
21.5.3
Timing for Hardware Standby Mode
Figure 21.2 shows the timing relationships for hardware standby mode. To enter hardware standby
mode, first drive RES low, then drive STBY low. To exit hardware standby mode, first drive
STBY high, wait for the clock to settle, then bring RES from low to high.
Rev. 7.00 Sep 21, 2005 page 673 of 878
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Section 21 Power-Down State
Clock
oscillator
RES
STBY
Oscillator
settling time
Reset
exception
handling
Figure 21.2 Hardware Standby Mode Timing
21.6
Module Standby Function
21.6.1
Module Standby Timing
The module standby function can halt several of the on-chip supporting modules (the ITU, SCI0,
SCI1, DMAC, refresh controller, and A/D converter) independently of the power-down state. This
standby function is controlled by bits MSTOP5 to MSTOP0 in MSTCR. When one of these bits is
set to 1, the corresponding on-chip supporting module is placed in standby and halts at the
beginning of the next bus cycle after the MSTCR write cycle.
21.6.2
Read/Write in Module Standby
When an on-chip supporting module is in module standby, read/write access to its registers is
disabled. Read access always results in H'FF data. Write access is ignored.
Rev. 7.00 Sep 21, 2005 page 674 of 878
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Section 21 Power-Down State
21.6.3
Usage Notes
When using the module standby function, note the following points.
DMAC and Refresh Controller: When setting bit MSTOP2 or MSTOP1 to 1 to place the
DMAC or refresh controller in module standby, make sure that the DMAC or refresh controller is
not currently requesting the bus right. If bit MSTOP2 or MSTOP1 is set to 1 when a bus request is
present, operation of the bus arbiter becomes ambiguous and a malfunction may occur.
Internal Peripheral Module Interrupt: When MSTCR is set to “1”, prevent module interrupt in
advance. When an on-chip supporting module is placed in standby by the module standby
function, its registers, including the interrupt flag, are initialized.
Pin States: Pins used by an on-chip supporting module lose their module functions when the
module is placed in module standby. What happens after that depends on the particular pin. For
details, see section 9, I/O Ports. Pins that change from the input to the output state require special
care. For example, if SCI1 is placed in module standby, the receive data pin loses its receive data
function and becomes a generic I/O pin. If its data direction bit is set to 1, the pin becomes a data
output pin, and its output may collide with external serial data. Data collisions should be prevented
by clearing the data direction bit to 0 or taking other appropriate action.
Register Resetting: When an on-chip supporting module is halted by the module standby
function, all its registers are initialized. To restart the module, after its MSTCR bit is cleared to 0,
its registers must be set up again. It is not possible to write to the registers while the MSTCR bit is
set to 1.
MSTCR Access from DMAC Disabled: To prevent malfunctions, MSTCR can only be accessed
from the CPU. It can be read by the DMAC, but it cannot be written by the DMAC.
Rev. 7.00 Sep 21, 2005 page 675 of 878
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Section 21 Power-Down State
21.7
System Clock Output Disabling Function
Output of the system clock (φ) can be controlled by the PSTOP bit in MSTCR. When the PSTOP
bit is set to 1, output of the system clock halts and the φ pin is placed in the high-impedance state.
Figure 21.3 shows the timing of the stopping and starting of system clock output. When the
PSTOP bit is cleared to 0, output of the system clock is enabled. Table 21.4 indicates the state of
the φ pin in various operating states.
MSTCR write cycle
MSTCR write cycle
(PSTOP = 1)
(PSTOP = 0)
T1
T2
T3
T1
T2
T3
φ pin
High impedance
Figure 21.3 Starting and Stopping of System Clock Output
Table 21.4
φ Pin State in Various Operating States
Operating State
PSTOP = 0
PSTOP = 1
Hardware standby
High impedance
High impedance
Software standby
Always high
High impedance
Sleep mode
System clock output
High impedance
Normal operation
System clock output
High impedance
Rev. 7.00 Sep 21, 2005 page 676 of 878
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Section 22 Electrical Characteristics
Section 22 Electrical Characteristics
Table 22.1 shows the electrical characteristics of the various products in the H8/3048 Group.
Table 22.1 Electrical Characteristics of H8/3048 Group Products
Unit
H8/3048
F-ZTAT
(Dual Power
Supply)
H8/3048
H8/3047
H8/3045
H8/3044
MHz
1 to 16
1 to 18
1 to 18
2 to 25
VCC = 3.15 to 5.5 V
—
1 to 13
1 to 13
—
VCC = 2.7 to 5.5 V
1 to 8
1 to 8
1 to 8
VCC = 3.0 to 3.6 V
—
—
—
2 to 25
–20 to +75
–20 to +75
–20 to +75
–20 to +75*1
–40 to +85
–40 to +85
–40 to +85
–40 to +85*1
Item
Operating
range
Symbol
VCC = 4.5 to 5.5 V
Operating
Regular
temperature specifications
range
Wide-range
specifications
Topr
Absolute
maximum
ratings
Vin
VPP pin rating
°C
H8/3048
ZTAT
H8/3048
F-ONE
(Single Power
Supply)*5
—
Yes
—
Yes
—
FWE pin rating
—
—
—
Yes
VCL pin
—
—
—
Cannot be
connected
to power
supply*2
(5 V operation
model only)
–0.3 to +7.0
–0.3 to +7.0
Power supply
voltage
Vin
V
–0.3 to +7.0 –0.3 to +7.0
(5 V operation
model)
–0.3 to +4.6
(3 V operation
model)
DC characteristics
RESO pin
specification
Yes
Yes
Yes
—
FWE pin
specification
—
—
—
Yes
Yes
—
—
—
Determination
level for applying
high voltage (12 V)
Standby current
(Ta ≤ 50°C)
Standby current
(50°C < Ta)
ICC*3
µA
Max 5
Max 5
Max 5
Max 10
Max 20
Max 20
Max 20
Max 80
Rev. 7.00 Sep 21, 2005 page 677 of 878
REJ09B0259-0700
Section 22 Electrical Characteristics
Symbol
Unit
H8/3048
F-ZTAT
(Dual Power
Supply)
Clock cycle time
tcyc
ns
Max 1000
RES pulse width
tRESW
tcyc
Min 10
Min 10
Min 10
RESO output
delay time
tRESD
ns
Max 100
Max 100
Max 100
—
RESO output
pulse width
tRESOW
tcyc
Min 132
Min 132
Min 132
—
Item
AC characteristics
Flash
memory
characteristics*4
Notes: 1.
2.
3.
4.
5.
Other wait times
See table
22.20
H8/3048
H8/3047
H8/3045
H8/3044
H8/3048
ZTAT
Max 1000
Max 1000
Max 500
Min 20
—
—
H8/3048
F-ONE
(Single Power
Supply)*5
See table
21.11
The operating temperature range for flash memory programming/erasing is 0°C to +75°.
Connect an external capacitor between the VCL pin and GND.
See the DC Characteristics table for current dissipation during operation.
Refer to the program/erase algorithms for details of flash memory characteristics.
Refer to the H8/3048F-ONE Hardware Manual (Rev. 1.0) for details.
Rev. 7.00 Sep 21, 2005 page 678 of 878
REJ09B0259-0700
Section 22 Electrical Characteristics
22.1
Electrical Characteristics for H8/3048 ZTAT (PROM) and On-Chip
Mask ROM Versions
Target product types: H8/3048 ZTAT, H8/3048 mask-ROM, H8/3047 mask-ROM,
H8/3045 mask-ROM, H8/3044 mask-ROM
22.1.1
Absolute Maximum Ratings
Table 22.2 lists the absolute maximum ratings.
Table 22.2 Absolute Maximum Ratings
Item
Symbol
Value
Unit
Power supply voltage
VCC
–0.3 to +7.0
V
Programming voltage (H8/3048 ZTAT)
VPP
–0.3 to +13.5
V
Input voltage (except for port 7)
Vin
–0.3 to VCC + 0.3
V
Input voltage (port 7)
Vin
–0.3 to AVCC + 0.3
V
Reference voltage
VREF
–0.3 to AVCC + 0.3
V
Analog power supply voltage
AVCC
–0.3 to +7.0
V
Analog input voltage
VAN
–0.3 to AVCC + 0.3
V
Operating temperature
Topr
Regular specifications: –20 to +75
°C
Wide-range specifications: –40 to +85
°C
–55 to +125
°C
Storage temperature
Tstg
Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded.
Particularly, insure that peak overshoot at the VPP pin does not exceed 13 V.
Rev. 7.00 Sep 21, 2005 page 679 of 878
REJ09B0259-0700
Section 22 Electrical Characteristics
22.1.2
DC Characteristics
Table 22.3 lists the DC characteristics. Table 22.4 lists the permissible output currents.
Table 22.3 DC Characteristics (1)
Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V*1, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Schmitt
trigger input
voltages
Port A,
P82 to P80,
PB3 to PB0
Symbol
Min
Typ
Max
Unit Test Conditions
VT–
1.0
—
—
V
VT+
—
—
VCC × 0.7 V
—
—
VT+ – VT– 0.4
Input high
voltage
Input low
voltage
Output high
voltage
Output low
voltage
Input
leakage
current
RES, STBY,
NMI,
EXTAL
VIH
V
VCC – 0.7 —
VCC + 0.3 V
VCC × 0.7 —
VCC + 0.3 V
Port 7
2.0
—
Ports 1 to 6, 9,
P83, P84, PB4
RES, STBY,
VIL
MD2 to MD0
NMI, EXTAL,
ports 1 to 7, 9,
All output pins VOH
(except RESO)
2.0
—
AVCC +
V
0.3
VCC + 0.3 V
–0.3
—
0.5
V
–0.3
—
0.8
V
VCC – 0.5 —
—
V
IOH = –200 µA
3.5
—
—
V
IOH = –1 mA
—
—
0.4
V
IOL = 1.6 mA
—
—
1.0
V
IOL = 10 mA
—
—
0.4
V
IOL = 2.6 mA
—
—
1.0
µA
—
—
1.0
µA
VIN = 0.5 to
VCC – 0.5 V
VIN = 0.5 to
AVCC – 0.5 V
All output pins VOL
(except RESO)
Ports 1, 2, 5,
and B
RESO
STBY, NMI,
RES,
Port 7
|IIN|
Rev. 7.00 Sep 21, 2005 page 680 of 878
REJ09B0259-0700
Section 22 Electrical Characteristics
Item
Three-state
leakage
current
(off state)
Ports 1 to 6,
8 to B
Symbol
Min
Typ
Max
Unit Test Conditions
|ITS1|
—
—
1.0
µA
—
—
10.0
µA
50
—
300
µA
VIN = 0 V
RESO
Input pull-up Ports 2, 4,
current
and 5
–IP
Input
NMI
capacitance All input pins
except NMI
CIN
Current
Normal
2
dissipation* operation
ICC
—
50
pF
VIN = 0 V
—
15
pF
f = 1 MHz
—
50
65
mA
f = 16 MHz
—
55
75
mA
f = 18 MHz
—
35
50
mA
f = 16 MHz
—
40
55
mA
f = 18 MHz
Module standby
4
mode*
—
20
25
mA
f = 16 MHz
—
25
27
mA
f = 18 MHz
Standby
3
mode*
—
0.01
5.0
µA
Ta ≤ 50°C
—
—
20.0
µA
50°C < Ta
—
1.2
2.0
mA
—
1.2
2.0
mA
—
0.01
5.0
µA
DASTE = 0
—
0.3
0.6
mA
VREF = 5.0 V
During A/D and
D/A conversion
—
1.3
3.0
mA
Idle
—
0.01
5.0
µA
2.0
—
—
V
During A/D
conversion
AICC
During A/D and
D/A conversion
Idle
Reference
current
—
—
Ta = 25°C
Sleep mode
Analog
power
supply
current
VIN = 0.5 to
VCC – 0.5 V
During A/D
conversion
RAM standby voltage
AICC
VRAM
DASTE = 0
Notes: 1. If the A/D and D/A converters are not used, do not leave the AVCC, AVSS, and VREF pins
open. Connect AVCC and VREF to VCC, and connect AVSS to VSS.
2. Current dissipation values are for VIHmin = VCC – 0.5 V and VILmax = 0.5 V with all output
pins unloaded and the on-chip pull-up transistors in the off state.
3. The values are for VRAM ≤ VCC < 4.5 V, VIHmin = VCC × 0.9, and VILmax = 0.3 V.
4. Module standby current values apply in sleep mode with all modules halted.
Rev. 7.00 Sep 21, 2005 page 681 of 878
REJ09B0259-0700
Section 22 Electrical Characteristics
Table 22.2 DC Characteristics (2)
Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V*1, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Symbol
Min
Max
Unit Test Conditions
Schmitt
trigger input
voltages
Port A,
P82 to P80,
PB3 to PB0
VT–
VCC × 0.2 —
—
V
VT+
—
—
VCC × 0.7 V
—
—
Input high
voltage
RES, STBY,
NMI,
MD2 to MD0
VIH
VT+ – VT– VCC ×
0.07
Typ
V
VCC × 0.9 —
VCC + 0.3 V
EXTAL
VCC × 0.7 —
VCC + 0.3 V
Port 7
VCC × 0.7 —
AVCC +
0.3
Ports 1 to 6, 9,
P84, P83, PB7 to
PB4
VCC × 0.7 —
VCC + 0.3 V
–0.3
—
VCC × 0.1 V
NMI, EXTAL,
ports 1 to 7, 9,
P83, P84 PB4 to
PB7
–0.3
—
VCC × 0.2 V
VCC < 4.0 V
0.8
V
VCC =
4.0 V to 5.5 V
Output high
voltage
All output pins VOH
(except RESO)
VCC – 0.5 —
—
V
IOH = –200 µA
VCC – 1.0 —
—
V
IOH = –1 mA
Output low
voltage
All output pins VOL
(except RESO)
—
—
0.4
V
IOL = 1.6 mA
Ports 1, 2, 5,
and B
—
—
1.0
V
VCC ≤ 4 V
IOL = 5 mA,
4 V < VCC ≤ 5.5 V
IOL = 10 mA
—
—
0.4
V
IOL = 1.6 mA
—
—
1.0
µA
VIN = 0.5 to
VCC – 0.5 V
—
—
1.0
µA
VIN = 0.5 to
AVCC – 0.5 V
Input low
voltage
RES, STBY,
MD2 to MD0
VIL
RESO
Input
leakage
current
STBY, NMI,
RES,
MD2 to MD0
|IIN|
Port 7
Rev. 7.00 Sep 21, 2005 page 682 of 878
REJ09B0259-0700
V
Section 22 Electrical Characteristics
Item
Three-state
leakage
current
(off state)
Ports 1 to 6,
8 to B
Symbol
Min
Typ
Max
Unit Test Conditions
|ITS1|
—
—
1.0
µA
—
—
10.0
µA
10
—
300
µA
VCC = 2.7 V to
5.5 V, VIN = 0 V
pF
VIN = 0 V
RESO
Input pull-up Ports 2, 4,
current
and 5
–IP
Input
NMI
capacitance All input pins
except NMI
CIN
Current
Normal
2
dissipation* operation
4
ICC*
50
15
f = 1 MHz
—
12
(3.0 V)
35
(5.5 V)
mA
f = 8 MHz
—
20
(3.3 V)
55
(5.5 V)
mA
f = 13 MHz
(VCC = 3.15 V to
5.5 V)
—
8
(3.0 V)
25
(5.5 V)
mA
f = 8 MHz
—
12
(3.3 V)
40
(5.5 V)
mA
f = 13 MHz
(VCC = 3.15 V to
5.5 V)
—
5
(3.0 V)
14
(5.5 V)
mA
f = 8 MHz
—
7
(3.3 V)
20
(5.5 V)
mA
13 MHz
(VCC = 3.15 V to
5.5 V)
—
0.01
5.0
µA
Ta ≤ 50°C
—
—
20.0
µA
50°C < Ta
—
0.4
1.0
mA
AVCC = 3.0 V
—
1.2
—
mA
AVCC = 5.0 V
During A/D and
D/A conversion
—
0.4
1.0
mA
AVCC = 3.0 V
—
1.2
—
mA
AVCC = 5.0 V
Idle
—
0.01
5.0
µA
DASTE = 0
—
0.2
0.4
mA
VREF = 3.0 V
—
0.3
—
mA
VREF = 5.0 V
During A/D and
D/A conversion
—
0.8
2.0
mA
VREF = 3.0 V
—
1.3
—
mA
VREF = 5.0 V
Idle
—
0.01
5.0
µA
DASTE = 0
2.0
—
—
V
Module standby
5
mode*
Standby
3
mode*
Reference
current
—
—
Ta = 25°C
Sleep mode
Analog
power
supply
current
—
—
VIN = 0.5 to
VCC – 0.5 V
During A/D
conversion
During A/D
conversion
RAM standby voltage
AICC
AICC
VRAM
Rev. 7.00 Sep 21, 2005 page 683 of 878
REJ09B0259-0700
Section 22 Electrical Characteristics
Notes: 1. If the A/D and D/A converters are not used, do not leave the AVCC, AVSS, and VREF pins
open. Connect AVCC and VREF to VCC, and connect AVSS to VSS.
2. Current dissipation values are for VIHmin = VCC – 0.5 V and VILmax = 0.5 V with all output
pins unloaded and the on-chip pull-up transistors in the off state.
3. The values are for VRAM ≤ VCC < 2.7 V, VIHmin = VCC × 0.9, and VILmax = 0.3 V.
4. ICC depends on VCC and f as follows:
ICCmax = 3.0 (mA) + 0.75 (mA/MHz · V) × VCC × f
[normal mode]
ICCmax = 3.0 (mA) + 0.55 (mA/MHz · V) × VCC × f
[sleep mode]
[module standby mode]
ICCmax = 3.0 (mA) + 0.25 (mA/MHz · V) × VCC × f
5. Module standby current values apply in sleep mode with all modules halted.
Table 22.4 Permissible Output Currents
Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Permissible output
low current (per pin)
Ports 1, 2, 5, and B
Permissible output
low current (total)
Total of 28 pins in
ports 1, 2, 5, and B
Symbol
Min
Typ
Max
Unit
IOL
—
—
10
mA
—
—
2.0
mA
—
—
80
mA
—
—
120
mA
Other output pins
ΣIOL
Total of all output pins,
including the above
Permissible output
high current (per pin)
All output pins
IOH
—
—
2.0
mA
Permissible output
high current (total)
Total of all output pins
ΣIOH
—
—
40
mA
Notes: 1. To protect chip reliability, do not exceed the output current values in table 22.4.
2. When driving a darlington pair or LED, always insert a current-limiting resistor in the
output line, as shown in figures 22.1 and 22.2.
Rev. 7.00 Sep 21, 2005 page 684 of 878
REJ09B0259-0700
Section 22 Electrical Characteristics
H8/3048
Group
2 kΩ
Port
Darlington pair
Figure 22.1 Darlington Pair Drive Circuit (Example)
H8/3048
Group
Ports 1, 2, 5,
and B
600 Ω
LED
Figure 22.2 LED Drive Circuit (Example)
Rev. 7.00 Sep 21, 2005 page 685 of 878
REJ09B0259-0700
Section 22 Electrical Characteristics
22.1.3
AC Characteristics
Bus timing parameters are listed in table 22.5. Refresh controller bus timing parameters are listed
in table 22.6. Control signal timing parameters are listed in table 22.7. Timing parameters of the
on-chip supporting modules are listed in table 22.8.
Table 22.5 Bus Timing
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V, φ = 1 MHz to 8 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition B: VCC = 3.15 V to 5.5 V, AVCC = 3.15 V to 5.5 V, VREF = 3.15 V to AVCC,
VSS = AVSS = 0 V, φ = 1 MHz to 13 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V, φ = 1 MHz to 18 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition
A
8 MHz
Item
Condition
B
13 MHz
16 MHz
Min
Max
18 MHz
Min
Test
Max Unit Conditions
Symbol
Min
Max
Min
Clock cycle time
tCYC
125
1000
76.9 1000
62.5 1000
55.5 1000 ns
Clock pulse low width
tCL
40
—
20
—
20
—
17
—
Clock pulse high width
tCH
40
—
20
—
20
—
17
—
Clock rise time
tCR
—
20
—
15
—
10
—
10
Clock fall time
tCF
—
20
—
15
—
10
—
10
Address delay time
tAD
—
60
—
50
—
30
—
25
Address hold time
tAH
25
—
20
—
10
—
10
—
Address strobe delay
time
tASD
—
60
—
50
—
30
—
25
Write strobe delay time
tWSD
—
60
—
50
—
30
—
25
Strobe delay time
tSD
—
60
—
50
—
30
—
25
Write data strobe pulse
width 1
tWSW1*
85
—
40
—
35
—
32
—
Write data strobe pulse
width 2
tWSW2*
150
—
90
—
65
—
62
—
Address setup time 1
tAS1
20
—
15
—
10
—
10
—
Address setup time 2
tAS2
80
—
45
—
40
—
38
—
Rev. 7.00 Sep 21, 2005 page 686 of 878
REJ09B0259-0700
Max
Condition
C
Figure 22.7,
Figure 22.8
Section 22 Electrical Characteristics
Condition
A
Condition
B
8 MHz
13 MHz
Condition
C
16 MHz
18 MHz
Item
Symbol
Min
Max
Min
Max
Min
Max
Min
Test
Max Unit Conditions
Read data setup time
tRDS
50
—
30
—
20
—
15
—
Read data hold time
tRDH
0
—
0
—
0
—
0
—
Write data delay time
tWDD
—
75
—
75
—
60
—
55
Write data setup time 1
tWDS1
60
—
20
—
15
—
10
—
Write data setup time 2
tWDS2
5
—
–10
—
–5
—
–10
—
Write data hold time
tWDH
25
—
15
—
20
—
20
—
Read data access time 1 tACC1*
—
120
—
60
—
60
—
50
Read data access time 2 tACC2*
—
240
—
140
—
120
—
105
Read data access time 3 tACC3*
—
70
—
30
—
30
—
20
Read data access time 4 tACC4*
—
180
—
100
—
95
—
80
Precharge time
tPCH*
85
—
55
—
45
—
40
—
Wait setup time
tWTS
40
—
40
—
25
—
25
—
Wait hold time
tWTH
10
—
10
—
5
—
5
—
Bus request setup ime
tBRQS
40
—
40
—
40
—
40
—
Bus acknowledge delay
time 1
tBACD1
—
60
—
50
—
30
—
30
Bus acknowledge delay
time 2
tBACD2
—
60
—
50
—
30
—
30
Bus-floating time
tBZD
—
70
—
70
—
40
—
40
ns
Figure 22.7,
Figure 22.8
ns
Figure 22.9
ns
Figure 22.21
Note: * At 8 MHz, the times below depend as indicated on the clock cycle time.
tACC1 = 1.5 × tCYC – 68 (ns)
tWSW1 = 1.0 × tCYC – 40 (ns)
tACC2 = 2.5 × tCYC – 73 (ns)
tWSW2 = 1.5 × tCYC – 38 (ns)
tACC3 = 1.0 × tCYC – 55 (ns)
tPCH = 1.0 × tCYC – 40 (ns)
tACC4 = 2.0 × tCYC – 70 (ns)
At 13 MHz, the times below depend as indicated on the clock cycle time.
tACC1 = 1.5 × tCYC – 56 (ns)
tWSW1 = 1.0 × tCYC – 37 (ns)
tWSW2 = 1.5 × tCYC – 26 (ns)
tACC2 = 2.5 × tCYC – 53 (ns)
tACC3 = 1.0 × tCYC – 47 (ns)
tPCH = 1.0 × tCYC – 32 (ns)
tACC4 = 2.0 × tCYC – 54 (ns)
At 16 MHz, the times below depend as indicated on the clock cycle time.
tACC1 = 1.5 × tCYC – 34 (ns)
tWSW1 = 1.0 × tCYC – 28 (ns)
tACC2 = 2.5 × tCYC – 37 (ns)
tWSW2 = 1.5 × tCYC – 29 (ns)
tPCH = 1.0 × tCYC – 28 (ns)
tACC3 = 1.0 × tCYC – 33 (ns)
tACC4 = 2.0 × tCYC – 30 (ns)
Rev. 7.00 Sep 21, 2005 page 687 of 878
REJ09B0259-0700
Section 22 Electrical Characteristics
At 18 MHz, the times below depend as indicated on the clock cycle time.
tWSW1 = 1.0 × tCYC – 24 (ns)
tACC1 = 1.5 × tCYC – 34 (ns)
tACC2 = 2.5 × tCYC – 34 (ns)
tWSW2 = 1.5 × tCYC – 22 (ns)
tPCH = 1.0 × tCYC – 21 (ns)
tACC3 = 1.0 × tCYC – 36 (ns)
tACC4 = 2.0 × tCYC – 31 (ns)
Table 22.6 Refresh Controller Bus Timing
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V, φ = 1 MHz to 8 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition B: VCC = 3.15 V to 5.5 V, AVCC = 3.15 V to 5.5 V, VREF = 3.15 V to AVCC,
VSS = AVSS = 0 V, φ = 1 MHz to 13 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V, φ = 1 MHz to 18 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition
A
Condition
B
Condition
C
8 MHz
13 MHz
16 MHz
18 MHz
Item
Symbol
Min
Max
Min
Max
Min
Max
Min
Test
Max Unit Conditions
RAS delay time 1
tRAD1
—
60
—
50
—
30
—
30
RAS delay time 2
tRAD2
—
60
—
50
—
30
—
30
RAS delay time 3
tRAD3
—
60
—
50
—
30
—
30
Row address hold time*
tRAH
25
—
20
—
15
—
15
—
RAS precharge time*
tRP
85
—
55
—
45
—
40
—
CAS to RAS precharge
time*
tCRP
85
—
55
—
45
—
40
—
CAS pulse width
tCAS
100
—
55
—
40
—
35
—
RAS access time*
tRAC
—
160
—
80
—
85
—
70
Address access time
tAA
—
105
—
45
—
55
—
45
CAS access time*
tCAC
—
50
—
30
—
30
—
25
Write data setup time 3
tWDS3
50
—
20
—
15
—
10
—
CAS setup time*
tCSR
20
—
10
—
15
—
10
—
Read strobe delay time
tRSD
—
60
—
50
—
30
—
30
Note: * At 8 MHz, the times below depend as indicated on the clock cycle time.
tRAH = 0.5 × tCYC – 38 (ns)
tCAC = 1.0 × tCYC – 75 (ns)
Rev. 7.00 Sep 21, 2005 page 688 of 878
REJ09B0259-0700
ns
Figure 22.10
to
Figure 22.16
Section 22 Electrical Characteristics
tRAC = 2.0 × tCYC – 90 (ns)
tCSR = 0.5 × tCYC – 43 (ns)
tRP = tCRP = 1.0 × tCYC – 40 (ns)
At 13 MHz, the times below depend as indicated on the clock cycle time.
tRAH = 0.5 × tCYC – 19 (ns)
tCAC = 1.0 × tCYC – 47 (ns)
tCSR = 0.5 × tCYC – 29 (ns)
tRAC = 2.0 × tCYC – 74 (ns)
tRP = tCRP = 1.0 × tCYC – 22 (ns)
At 16 MHz, the times below depend as indicated on the clock cycle time.
tRAH = 0.5 × tCYC – 17 (ns)
tCAC = 1.0 × tCYC – 33 (ns)
tRAC = 2.0 × tCYC – 40 (ns)
tCSR = 0.5 × tCYC – 17 (ns)
tRP = tCRP = 1.0 × tCYC – 18 (ns)
At 18 MHz, the times below depend as indicated on the clock cycle time.
tRAH = 0.5 × tCYC – 13 (ns)
tCAC = 1.0 × tCYC – 31 (ns)
tRAC = 2.0 × tCYC – 41 (ns)
tCSR = 0.5 × tCYC – 18 (ns)
tRP = tCRP = 1.0 × tCYC – 16 (ns)
Rev. 7.00 Sep 21, 2005 page 689 of 878
REJ09B0259-0700
Section 22 Electrical Characteristics
Table 22.7 Control Signal Timing
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V, φ = 1 MHz to 8 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition B: VCC = 3.15 V to 5.5 V, AVCC = 3.15 V to 5.5 V, VREF = 3.15 V to AVCC,
VSS = AVSS = 0 V, φ = 1 MHz to 13 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V, φ = 1 MHz to 18 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition
A
Condition
B
Condition
C
8 MHz
13 MHz
16 MHz
18 MHz
Item
Symbol
Min
Max
Min
Max
Min
Max
Min
Test
Max Unit Conditions
RES setup time
tRESS
200
—
200
—
200
—
200
—
ns
RES pulse width
tRESW
10
—
10
—
10
—
10
—
tCYC
Mode programming setup tMDS
time
200
—
200
—
200
—
200
—
ns
RESO output delay
time
—
100
—
100
—
100
—
100
ns
RESO output pulse width tRESOW
132
—
132
—
132
—
132
—
tCYC
NMI setup time
(NMI, IRQ5 to IRQ0)
tNMIS
200
—
200
—
150
—
150
—
ns
Figure 22.20
NMI hold time
(NMI, IRQ5 to IRQ0)
tNMIH
10
—
10
—
10
—
10
—
Interrupt pulse width
(NMI, IRQ2 to IRQ0
when exiting software
standby mode)
tNMIW
200
—
200
—
200
—
200
—
Clock oscillator settling
time at reset (crystal)
tOSC1
20
—
20
—
20
—
20
—
ms
Figure 22.22
Clock oscillator settling
time in software standby
(crystal)
tOSC2
7
—
7
—
7
—
7
—
ms
Figure 21.1
tRESD
Rev. 7.00 Sep 21, 2005 page 690 of 878
REJ09B0259-0700
Figure 22.18
Figure 22.19
Section 22 Electrical Characteristics
Table 22.8 Timing of On-Chip Supporting Modules
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V, φ = 1 MHz to 8 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition B: VCC = 3.15 V to 5.5 V, AVCC = 3.15 V to 5.5 V, VREF = 3.15 V to AVCC,
VSS = AVSS = 0 V, φ = 1 MHz to 13 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V, φ = 1 MHz to 18 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition
A
Condition
B
Condition
C
8 MHz
13 MHz
16 MHz
18 MHz
Item
Symbol
Min
Max
Min
Max
Min
Max
Min
Test
Max Unit Conditions
DMAC DREQ setup
time
tDRQS
40
—
40
—
30
—
30
—
DREQ hold
time
tDRQH
10
—
10
—
10
—
10
—
TEND delay
time 1
tTED1
—
100
—
100
—
50
—
50
TEND delay
time 2
tTED2
—
100
—
100
—
50
—
50
Timer output
delay time
tTOCD
—
100
—
100
—
100
—
100
Timer input
setup time
tTICS
50
—
50
—
50
—
50
—
Timer clock
input setup time
tTCKS
50
—
50
—
50
—
50
—
Timer Single
clock edge
pulse
Both
width
edges
tTCKWH
1.5
—
1.5
—
1.5
—
1.5
—
tTCKWL
2.5
—
2.5
—
2.5
—
2.5
—
tSCYC
Asynchronous
4
—
4
—
4
—
4
—
SyntSCYC
chronous
6
—
6
—
6
—
6
—
ITU
SCI
Input
clock
cycle
Input clock rise
time
tSCKr
—
1.5
—
1.5
—
1.5
—
1.5
Input clock fall
time
tSCKf
—
1.5
—
1.5
—
1.5
—
1.5
Input clock
pulse width
tSCKW
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
ns
Figure 22.30
Figure 22.28,
Figure 22.29
ns
Figure 22.24
Figure 22.25
tCYC
tCYC
Figure 22.26
tSCYC
Rev. 7.00 Sep 21, 2005 page 691 of 878
REJ09B0259-0700
Section 22 Electrical Characteristics
Condition
A
8 MHz
13 MHz
16 MHz
18 MHz
Min
Max
Min
Max
Min
Max
Min
Test
Max Unit Conditions
Transmit data
delay time
tTXD
—
100
—
100
—
100
—
100
Receive data
setup time
(synchronous)
tRXS
100
—
100
—
100
—
100
—
Clock tRXH
input
100
—
100
—
100
—
100
—
Clock
output
0
—
0
—
0
—
0
—
Receive
data
hold time
(synchronous)
Ports
and
TPC
Condition
C
Symbol
Item
SCI
Condition
B
Output data
delay time
tPWD
—
100
—
100
—
100
—
100
Input data
setup time
tPRS
50
—
50
—
50
—
50
—
Input data
hold time
tPRH
50
—
50
—
50
—
50
—
RL
ns
Figure 22.27
ns
Figure 22.23
C = 90 pF: ports 4, 5, 6, 8, A (19 to 0),
D (15 to 8), φ
C = 30 pF: ports 9, A, B, RESO
H8/3048 Group
output pin
R L = 2.4 k Ω
R H = 12 k Ω
C
RH
Input/output timing measurement levels
• Low: 0.8 V
• High: 2.0 V
Figure 22.3 Output Load Circuit
Rev. 7.00 Sep 21, 2005 page 692 of 878
REJ09B0259-0700
Section 22 Electrical Characteristics
22.1.4
A/D Conversion Characteristics
Table 22.9 lists the A/D conversion characteristics.
Table 22.9 A/D Converter Characteristics
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V, φ = 1 MHz to 8 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition B: VCC = 3.15 V to 5.5 V, AVCC = 3.15 V to 5.5 V, VREF = 3.15 V to AVCC,
VSS = AVSS = 0 V, φ = 1 MHz to 13 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V, φ = 1 MHz to 18 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition A
Condition B
8 MHz
Condition C
13 MHz
16 MHz
18 MHz
Item
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max Unit
Resolution
10
10
10
10
10
10
10
10
10
10
10
10
bits
Conversion time 16.75 —
—
10.31 —
—
8.375 —
—
7.45 —
—
µs
Analog input
capacitance
—
—
20
—
—
20
—
—
20
—
—
20
pF
Permissible
signal-source
impedance
—
—
10*1
—
—
10*1
—
—
10*3
—
—
10*3 kΩ
—
—
5*2
—
—
5*2
—
—
5*4
—
—
5*4
Nonlinearity
error
—
—
±6.0
—
—
±6.0
—
—
±3.0
—
—
±3.0 LSB
Offset error
—
—
±4.0
—
—
±4.0
—
—
±2.0
—
—
±2.0 LSB
Full-scale error
—
—
±4.0
—
—
±4.0
—
—
±2.0
—
—
±2.0 LSB
Quantization
error
—
—
±0.5
—
—
±0.5
—
—
±0.5
—
—
±0.5 LSB
Absolute
accuracy
—
—
±8.0
—
—
±8.0
—
—
±4.0
—
—
±4.0 LSB
Notes: 1.
2.
3.
4.
The value is for 4.0 ≤ AVCC ≤ 5.5.
The value is for 2.7 ≤ AVCC ≤ 4.0.
The value is for φ ≤ 12 MHz.
The value is for φ > 12 MHz.
Rev. 7.00 Sep 21, 2005 page 693 of 878
REJ09B0259-0700
Section 22 Electrical Characteristics
22.1.5
D/A Conversion Characteristics
Table 22.10 lists the D/A conversion characteristics.
Table 22.10 D/A Converter Characteristics
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V, φ = 1 MHz to 8 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition B: VCC = 3.15 V to 5.5 V, AVCC = 3.15 V to 5.5 V, VREF = 3.15 V to AVCC,
VSS = AVSS = 0 V, φ = 1 MHz to 13 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V, φ = 1 MHz to 18 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition A
Condition B
8 MHz
Condition C
13 MHz
16 MHz
18 MHz
Item
Min
Typ Max
Min
Typ Max
Min
Typ Max
Min
Test
Typ Max Unit Conditions
Resolution
8
8
8
8
8
8
8
8
8
8
8
8
Bits
Conversion
time
—
—
10
—
—
10
—
—
10
—
—
10
µs
Absolute
accuracy
—
±2.0 ±3.0
—
±2.0 ±3.0
—
±1.0 ±1.5
—
±1.0 ±1.5 LSB 2-MΩ
resistive
load
—
—
—
—
—
—
—
—
±2.0
±2.0
Rev. 7.00 Sep 21, 2005 page 694 of 878
REJ09B0259-0700
±1.0
20-pF
capacitive
load
±1.0 LSB 4-MΩ
resistive
load
Section 22 Electrical Characteristics
22.2
Electrical Characteristics of H8/3048F (Dual-Power Supply)
22.2.1
Absolute Maximum Ratings
Table 22.11 lists the absolute maximum ratings.
Table 22.11 Absolute Maximum Ratings
Item
Symbol
Value
Unit
Power supply voltage
VCC
–0.3 to +7.0
V
Programming voltage
VPP
–0.3 to +13.0
V
Input voltage
(except for MD2 and port 7
Vin
–0.3 to VCC + 0.3
V
Input voltage (MD2)
Vin
–0.3 to +13.0
V
Input voltage (port 7)
Vin
–0.3 to AVCC + 0.3
V
Reference voltage
VREF
–0.3 to AVCC + 0.3
V
Analog power supply voltage
AVCC
–0.3 to +7.0
V
Analog input voltage
VAN
–0.3 to AVCC + 0.3
V
Operating temperature
Topr
Regular specifications: –20 to +75
°C
Wide-range specifications: –40 to +85
°C
–55 to +125
°C
Storage temperature
Tstg
Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded.
Particularly, insure that peak overshoot at the VPP and MD2 pins does not exceed 13 V.
Rev. 7.00 Sep 21, 2005 page 695 of 878
REJ09B0259-0700
Section 22 Electrical Characteristics
22.2.2
DC Characteristics
Table 22.12 lists the DC characteristics. Table 22.13 lists the permissible output currents.
Table 22.12 DC Characteristics (1)
Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V*1, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Symbol
Min
Typ
Max
Unit Test Conditions
Schmitt
trigger input
voltages
Port A,
P82 to P80,
PB3 to PB0
VT–
1.0
—
—
V
VT+
—
—
VCC × 0.7 V
—
—
Input high
voltage
RES, STBY,
NMI,
MD2 to MD0
VIH
Input low
voltage
VT+ – VT– 0.4
V
VCC – 0.7 —
VCC + 0.3 V
EXTAL
VCC × 0.7 —
VCC + 0.3 V
Port 7
2.0
—
AVCC +
0.3
Ports 1 to 6, 9,
P84, P83, PB7 to
PB4
2.0
—
VCC + 0.3 V
–0.3
—
0.5
V
–0.3
—
0.8
V
RES, STBY,
MD2 to MD0
VIL
NMI, EXTAL,
ports 1 to 7, 9,
P84, P83, PB7 to
PB4
Output high
voltage
All output pins
Output low
voltage
VCC – 0.5 —
—
V
IOH = –200 µA
3.5
—
—
V
IOH = –1 mA
All output pins VOL
(except RESO)
—
—
0.4
V
IOL = 1.6 mA
Ports 1, 2, 5,
and B
—
—
1.0
V
IOL = 10 mA
RESO
—
—
0.4
V
IOL = 2.6 mA
11.4
V
VCC =
4.5 V to 5.5 V
High voltage RESO/VPP
(12 V)
MD2
application
criterion
5
level*
VOH
V
VH
Rev. 7.00 Sep 21, 2005 page 696 of 878
REJ09B0259-0700
VCC + 2.0 —
Section 22 Electrical Characteristics
Item
Input
leakage
current
Three-state
leakage
current
(off state)
Symbol
Min
Typ
Max
Unit Test Conditions
|Iin|
STBY, NMI,
RES, MD1, MD0
—
—
1.0
µA
Vin = 0.5 to
VCC – 0.5 V
MD2
—
—
10.0
µA
Vin = 0.5 to
VCC + 0.5 V
MD2
—
—
50.0
µA
Vin = VCC +
0.5 to 12.6 V
Port 7
—
—
1.0
µA
Vin = 0.5 to
AVCC – 0.5 V
—
—
1.0
µA
Vin = 0.5 to
VCC – 0.5 V
—
—
20.0
mA
VCC to 5 V <
Vin ≤ 12.6 V
—
—
10.0
µA
0.5 V ≤ Vin ≤
VCC to 0.5 V
Ports 1 to 6,
8 to B
|ITSI|
RESO/VPP
Input pull-up Ports 2, 4,
current
and 5
–IP
50
—
300
µA
Vin = 0 V
Input
NMI
capacitance All input pins
except NMI
Cin
—
—
50
pF
VIN = 0 V
—
—
15
pF
f = 1 MHz
Current
Normal
2
dissipation* operation
ICC
Analog
power
supply
current
Reference
current
Ta = 25°C
—
50
65
mA
f = 16 MHz
Sleep mode
—
35
50
mA
f = 16 MHz
Module standby
4
mode*
—
20
25
mA
f = 16 MHz
Standby
3
mode*
—
0.01
5.0
µA
Ta ≤ 50°C
—
—
20.0
µA
50°C < Ta
—
1.2
2.0
mA
During A/D and
D/A conversion
—
1.2
2.0
mA
Idle
—
0.01
5.0
µA
DASTE = 0
—
0.3
0.6
mA
VREF = 5.0 V
During A/D and
D/A conversion
—
1.3
3.0
mA
Idle
—
0.01
5.0
µA
During A/D
conversion
During A/D
conversion
AICC
AICC
DASTE = 0
Rev. 7.00 Sep 21, 2005 page 697 of 878
REJ09B0259-0700
Section 22 Electrical Characteristics
Item
VPP pin
current
Symbol
Min
Typ
Max
Unit Test Conditions
IPP
—
—
10
µA
VPP = 5.0 V
—
10
20
mA
VPP = 12.6 V
Program
execution
—
20
40
mA
Erase
—
20
40
mA
2.0
—
—
V
Read output
RAM standby voltage
VRAM
Notes: 1. If the A/D and D/A converters are not used, do not leave the AVCC, AVSS, and VREF pins
open. Connect AVCC and VREF to VCC, and connect AVSS to VSS.
2. Current dissipation values are for VIHmin = VCC – 0.5 V and VILmax = 0.5 V with all output
pins unloaded and the on-chip pull-up transistors in the off state.
3. The values are for VRAM ≤ VCC < 4.5 V, VIHmin = VCC × 0.9, and VILmax = 0.3 V.
4. Module standby current values apply in sleep mode with all modules halted.
5. The high-voltage application criterion level is as shown above. However, in boot mode
and during flash memory write and erase it should be set at 12.0 V ±0.6 V.
Rev. 7.00 Sep 21, 2005 page 698 of 878
REJ09B0259-0700
Section 22 Electrical Characteristics
Table 22.12 DC Characteristics (2)
Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V*1, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Symbol
Min
Max
Unit Test Conditions
Schmitt
trigger input
voltages
Port A,
P82 to P80,
PB3 to PB0
VT–
VCC × 0.2 —
—
V
VT+
—
—
VCC × 0.7 V
—
—
Input high
voltage
RES, STBY,
NMI,
MD2 to MD0
VIH
Input low
voltage
VT+ – VT– VCC ×
0.07
Typ
V
VCC × 0.9 —
VCC + 0.3 V
EXTAL
VCC × 0.7 —
VCC + 0.3 V
Port 7
VCC × 0.7 —
AVCC +
0.3
Ports 1 to 6, 9,
P84, P83, PB7 to
PB4
VCC × 0.7 —
VCC + 0.3 V
–0.3
—
VCC × 0.1 V
–0.3
—
VCC × 0.2 V
VCC < 4.0 V
0.8
V
VCC =
4.0 V to 5.5 V
VCC – 0.5 —
—
V
IOH = –200 µA
VCC – 1.0 —
—
V
IOH = –1 mA
RES, STBY,
MD2 to MD0
VIL
NMI, EXTAL,
ports 1 to 7, 9,
P84, P83, PB7 to
PB4
VOH
V
Output high
voltage
All output pins
Output low
voltage
All output pins VOL
(except RESO)
—
—
0.4
V
IOL = 1.6 mA
Ports 1, 2, 5,
and B
—
—
1.0
V
VCC ≤ 4 V
IOL = 5 mA,
4 V < VCC ≤ 5.5 V
IOL = 10 mA
—
—
0.4
V
IOL = 1.6 mA
11.4
V
VCC = 2.7 V
to 5.5 V
RESO
High voltage RESO/VPP
MD2
(12 V)
application
criterion
6
level*
VH
VCC + 2.0 —
Rev. 7.00 Sep 21, 2005 page 699 of 878
REJ09B0259-0700
Section 22 Electrical Characteristics
Item
Input
leakage
current
Three-state
leakage
current
(off state)
Symbol
Min
Typ
Max
Unit Test Conditions
STBY, NMI,
|Iin|
RES, MD1, MD0
—
—
1.0
µA
Vin = 0.5 to
VCC – 0.5 V
MD2
—
—
10.0
µA
Vin = 0.5 to
VCC + 0.5 V
MD2
—
—
50.0
µA
Vin = VCC +
0.5 to 12.6 V
Port 7
—
—
1.0
µA
Vin = 0.5 to
AVCC – 0.5 V
—
—
1.0
µA
Vin = 0.5 to
VCC – 0.5 V
—
—
20.0
mA
VCC + 0.5 < Vin
—
—
10.0
µA
≤ 12.6
0.5 ≤ Vin ≤ VCC
10
—
300
µA
+0.5V
VCC = 2.7 V to
5.5 V, Vin = 0 V
pF
Vin = 0 V
Ports 1 to 6,
8 to B
|ITSI|
RESO/VPP
Input pull-up Ports 2, 4,
current
and 5
–IP
Input
NMI
capacitance All input pins
except NMI
Cin
Current
Normal
2
dissipation* operation
4
ICC*
Analog
power
supply
current
—
50
—
15
f = 1 MHz
Ta = 25°C
—
12
(3.0 V)
35
(5.5 V)
mA
f = 8 MHz
Sleep mode
—
8
(3.0 V)
25
(5.5 V)
mA
f = 8 MHz
Module
5
standby mode*
—
5
(3.0 V)
14
(5.5 V)
mA
f = 8 MHz
Standby
3
mode*
—
0.01
5.0
µA
Ta ≤ 50°C
—
—
20.0
µA
50°C < Ta
—
0.4
1.0
mA
AVCC = 3.0 V
—
1.2
—
mA
AVCC = 5.0 V
—
0.4
1.0
mA
AVCC = 3.0 V
—
1.2
—
mA
AVCC = 5.0 V
—
0.01
5.0
µA
DASTE = 0
—
0.2
0.4
mA
VREF = 3.0 V
—
0.3
—
mA
VREF = 5.0 V
During A/D and
D/A conversion
—
0.8
2.0
mA
VREF = 3.0 V
—
1.3
—
mA
VREF = 5.0 V
Idle
—
0.01
5.0
µA
DASTE = 0
During A/D
conversion
AICC
During A/D and
D/A conversion
Idle
Reference
current
—
—
During A/D
conversion
AICC
Rev. 7.00 Sep 21, 2005 page 700 of 878
REJ09B0259-0700
Section 22 Electrical Characteristics
Item
VPP pin
current
Symbol
Min
Typ
Max
Unit Test Conditions
IPP
—
—
10
µA
—
10
20
mA
Program
execution
—
20
40
mA
Erase
—
20
40
mA
2.0
—
—
V
Read output
RAM standby voltage
VRAM
VPP = 5.0 V
VPP = 12.6 V
Notes: 1. If the A/D and D/A converters are not used, do not leave the AVCC, AVSS, and VREF pins
open. Connect AVCC and VREF to VCC, and connect AVSS to VSS.
2. Current dissipation values are for VIHmin = VCC – 0.5 V and VILmax = 0.5 V with all output
pins unloaded and the on-chip pull-up transistors in the off state.
3. The values are for VRAM ≤ VCC < 2.7 V, VIHmin = VCC × 0.9, and VILmax = 0.3 V.
4. ICC depends on VCC and f as follows:
ICCmax = 3.0 (mA) + 0.75 (mA/MHz · V) × VCC × f
[normal mode]
ICCmax = 3.0 (mA) + 0.55 (mA/MHz · V) × VCC × f
[sleep mode]
ICCmax = 3.0 (mA) + 0.25 (mA/MHz · V) × VCC × f
[module standby mode]
5. Module standby current values apply in sleep mode with all modules halted.
6. The high-voltage application criterion level is as shown above. However, in boot mode
and during flash memory write and erase it should be set at 12.0 V ±0.6 V.
Table 22.13 Permissible Output Currents
Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Symbol
Permissible output
low current (per pin)
Ports 1, 2, 5, and B
Permissible output
low current (total)
Total of 28 pins in
ports 1, 2, 5, and B
IOL
Other output pins
ΣIOL
Total of all output pins,
including the above
Min
Typ
Max
Unit
—
—
10
mA
—
—
2.0
mA
—
—
80
mA
—
—
120
mA
Permissible output
high current (per pin)
All output pins
IOH
—
—
2.0
mA
Permissible output
high current (total)
Total of all output pins
ΣIOH
—
—
40
mA
Notes: 1. To protect chip reliability, do not exceed the output current values in table 22.13.
2. When driving a darlington pair or LED, always insert a current-limiting resistor in the
output line, as shown in figures 22.4 and 22.5.
Rev. 7.00 Sep 21, 2005 page 701 of 878
REJ09B0259-0700
Section 22 Electrical Characteristics
H8/3048
Group
2 kΩ
Port
Darlington pair
Figure 22.4 Darlington Pair Drive Circuit (Example)
H8/3048
Group
Ports 1, 2, 5,
and B
600 Ω
LED
Figure 22.5 LED Drive Circuit (Example)
Rev. 7.00 Sep 21, 2005 page 702 of 878
REJ09B0259-0700
Section 22 Electrical Characteristics
22.2.3
AC Characteristics
Bus timing parameters are listed in table 22.14. Refresh controller bus timing parameters are listed
in table 22.15. Control signal timing parameters are listed in table 22.16. Timing parameters of the
on-chip supporting modules are listed in table 22.17.
Table 22.14 Bus Timing
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V, φ = 1 MHz to 8 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V, φ = 1 MHz to 16 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition A
Condition C
8 MHz
16 MHz
Item
Symbol
Min
Max
Min
Max
Unit
Test
Conditions
Clock cycle time
tCYC
125
1000
62.5
1000
ns
Figure 22.7,
Clock pulse low width
tCL
40
—
20
—
Clock pulse high width
tCH
40
—
20
—
Clock rise time
tCR
—
20
—
10
Clock fall time
tCF
—
20
—
10
Address delay time
tAD
—
60
—
30
Address hold time
tAH
25
—
10
—
Address strobe delay time
tASD
—
60
—
30
Write strobe delay time
tWSD
—
60
—
30
Strobe delay time
tSD
—
60
—
30
Write data strobe pulse width 1
tWSW1*
85
—
35
—
Write data strobe pulse width 2
tWSW2*
150
—
65
—
Address setup time 1
tAS1
20
—
10
—
Address setup time 2
tAS2
80
—
40
—
Read data setup time
tRDS
50
—
20
—
Read data hold time
tRDH
0
—
0
—
Figure 22.8
Rev. 7.00 Sep 21, 2005 page 703 of 878
REJ09B0259-0700
Section 22 Electrical Characteristics
Condition A
Condition C
8 MHz
16 MHz
Max
Unit
Test
Conditions
—
60
ns
Figure 22.7,
15
—
–5
—
—
20
—
120
—
60
—
240
—
120
—
70
—
30
—
180
—
95
85
—
45
—
tWTS
40
—
25
—
Wait hold time
tWTH
10
—
5
—
Bus request setup time
tBRQS
40
—
40
—
Bus acknowledge delay time 1
tBACD1
—
60
—
30
Bus acknowledge delay time 2
tBACD2
—
60
—
30
Bus-floating time
tBZD
—
70
—
40
Item
Symbol
Min
Max
Min
Write data delay time
tWDD
Write data setup time 1
tWDS1
—
75
60
—
Write data setup time 2
tWDS2
5
—
Write data hold time
Read data access time 1
tWDH
25
tACC1*
—
Read data access time 2
tACC2*
Read data access time 3
tACC3*
Read data access time 4
Precharge time
tACC4*
tPCH*
Wait setup time
Figure 22.8
ns
Figure 22.9
ns
Figure 22.21
Note: * At 8 MHz, the times below depend as indicated on the clock cycle time.
tACC1 = 1.5 × tCYC – 68 (ns)
tWSW1 = 1.0 × tCYC – 40 (ns)
tACC2 = 2.5 × tCYC – 73 (ns)
tWSW2 = 1.5 × tCYC – 38 (ns)
tACC3 = 1.0 × tCYC – 55 (ns)
tPCH = 1.0 × tCYC – 40 (ns)
tACC4 = 2.0 × tCYC – 70 (ns)
At 16 MHz, the times below depend as indicated on the clock cycle time.
tACC1 = 1.5 × tCYC – 34 (ns)
tWSW1 = 1.0 × tCYC – 28 (ns)
tACC2 = 2.5 × tCYC – 37 (ns)
tWSW2 = 1.5 × tCYC – 29 (ns)
tACC3 = 1.0 × tCYC – 33 (ns)
tPCH = 1.0 × tCYC – 28 (ns)
tACC4 = 2.0 × tCYC – 30 (ns)
Rev. 7.00 Sep 21, 2005 page 704 of 878
REJ09B0259-0700
Section 22 Electrical Characteristics
Table 22.15 Refresh Controller Bus Timing
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V, φ = 1 MHz to 8 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V, φ = 1 MHz to 16 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition A
Condition C
8 MHz
16 MHz
Item
Symbol
Min
Max
Min
Max
Unit
RAS delay time 1
tRAD1
—
60
RAS delay time 2
tRAD2
—
60
—
30
ns
—
30
RAS delay time 3
tRAD3
—
60
—
30
Row address hold time*
tRAH
25
—
15
—
RAS precharge time*
tRP
85
—
45
—
CAS to RAS precharge time*
tCRP
85
—
45
—
CAS pulse width
tCAS
100
—
40
—
RAS access time*
tRAC
—
160
—
85
Address access time
tAA
—
105
—
55
CAS access time*
tCAC
—
50
—
30
Write data setup time 3
tWDS3
50
—
15
—
CAS setup time*
tCSR
20
—
15
—
Read strobe delay time
tRSD
—
60
—
30
Test
Conditions
Figure 22.10
to
Figure 22.16
Note: * At 8 MHz, the times below depend as indicated on the clock cycle time.
tRAH = 0.5 × tCYC – 38 (ns)
tCAC = 1.0 × tCYC – 75 (ns)
tRAC = 2.0 × tCYC – 90 (ns)
tCSR = 0.5 × tCYC – 43 (ns)
tRP = tCRP = 1.0 × tCYC – 40 (ns)
At 16 MHz, the times below depend as indicated on the clock cycle time.
tRAH = 0.5 × tCYC – 17 (ns)
tCAC = 1.0 × tCYC – 33 (ns)
tRAC = 2.0 × tCYC – 40 (ns)
tCSR = 0.5 × tCYC – 17 (ns)
tRP = tCRP = 1.0 × tCYC – 18 (ns)
Rev. 7.00 Sep 21, 2005 page 705 of 878
REJ09B0259-0700
Section 22 Electrical Characteristics
Table 22.16 Control Signal Timing
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V, φ = 1 MHz to 8 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V, φ = 1 MHz to 16 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition A
Condition C
8 MHz
16 MHz
Item
Symbol
Min
Max
Min
Max
Unit
Test
Conditions
RES setup time
tRESS
200
—
200
—
ns
Figure 22.18
RES pulse width
tRESW
10
—
10
—
tCYC
Mode programming setup time
tMDS
200
—
200
—
ns
RESO output delay time
tRESD
—
100
—
100
ns
RESO output pulse width
tRESOW
132
—
132
—
tCYC
NMI setup time
(NMI, IRQ5 to IRQ0)
tNMIS
200
—
150
—
ns
Figure 22.20
NMI hold time
(NMI, IRQ5 to IRQ0)
tNMIH
10
—
10
—
Interrupt pulse width
(NMI, IRQ2 to IRQ0
when exiting software
standby mode)
tNMIW
200
—
200
—
Clock oscillator settling
time at reset (crystal)
tOSC1
20
—
20
—
ms
Figure 22.22
Clock oscillator settling
time in software standby
(crystal)
tOSC2
7
—
7
—
ms
Figure 21.1
Rev. 7.00 Sep 21, 2005 page 706 of 878
REJ09B0259-0700
Figure 22.19
Section 22 Electrical Characteristics
Table 22.17 Timing of On-Chip Supporting Modules
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V, φ = 1 MHz to 8 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V, φ = 1 MHz to 16 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Item
DMAC DREQ setup time
ITU
SCI
SCI
Ports
and
TPC
Condition A
Condition C
8 MHz
16 MHz
Symbol
Min
Max
Min
Max
Unit
Test
Conditions
ns
Figure 22.30
tDRQS
40
—
30
—
DREQ hold time
tDRQH
10
—
10
—
TEND delay time 1
tTED1
—
100
—
50
Figure 22.28
TEND delay time 2
tTED2
—
100
—
50
Figure 22.29
Timer output delay time
tTOCD
—
100
—
100
Timer input setup time
tTICS
50
—
50
—
Timer clock input setup time
tTCKS
50
—
50
—
Timer clock
pulse width
Single edge
tTCKWH
1.5
—
1.5
—
Both edges
tTCKWL
2.5
—
2.5
—
Input clock
cycle
Asynchronous
tSCYC
4
—
4
—
Synchronous
tSCYC
6
—
6
—
Input clock rise time
tSCKr
—
1.5
—
1.5
Input clock fall time
tSCKf
—
1.5
—
1.5
Input clock pulse width
tSCKW
0.4
0.6
0.4
0.6
tSCYC
Transmit data delay time
tTXD
—
100
—
100
ns
Figure 22.27
Receive data setup time
(synchronous)
tRXS
100
—
100
—
Receive
data hold
time (synchronous)
Clock input
tRXH
100
—
100
—
Clock output
tRXH
0
—
0
—
tPWD
—
100
—
100
ns
Figure 22.23
Input data setup time
tPRS
50
—
50
—
Input data hold time
tPRH
50
—
50
—
Output data delay time
ns
Figure 22.24
Figure 22.25
tCYC
tCYC
Figure 22.26
Rev. 7.00 Sep 21, 2005 page 707 of 878
REJ09B0259-0700
Section 22 Electrical Characteristics
RL
C = 90 pF: ports 4, 5, 6, 8, A (19 to 0),
D (15 to 8), φ
C = 30 pF: ports 9, A, B, RESO
H8/3048 Group
output pin
R L = 2.4 k Ω
R H = 12 k Ω
C
RH
Input/output timing measurement levels
• Low: 0.8 V
• High: 2.0 V
Figure 22.6 Output Load Circuit
Rev. 7.00 Sep 21, 2005 page 708 of 878
REJ09B0259-0700
Section 22 Electrical Characteristics
22.2.4
A/D Conversion Characteristics
Table 22.18 lists the A/D conversion characteristics.
Table 22.18 A/D Converter Characteristics
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V, φ = 1 MHz to 8 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V, φ = 1 MHz to 16 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition A
Condition C
8 MHz
16 MHz
Item
Min
Typ
Max
Min
Typ
Max
Unit
Resolution
10
10
10
10
10
10
bits
Conversion time
16.75
—
—
8.375
—
—
µs
Analog input capacitance
—
—
20
—
—
20
pF
Permissible signal-source
impedance
—
—
10*1
—
—
10*3
kΩ
—
—
5*2
—
—
5*4
Nonlinearity error
—
—
±6.0
—
—
±3.0
LSB
Offset error
—
—
±4.0
—
—
±2.0
LSB
Full-scale error
—
—
±4.0
—
—
±2.0
LSB
Quantization error
—
—
±0.5
—
—
±0.5
LSB
Absolute accuracy
—
—
±8.0
—
—
±4.0
LSB
Notes: 1.
2.
3.
4.
The value is for 4.0 ≤ AVCC ≤ 5.5.
The value is for 2.7 ≤ AVCC < 4.0.
The value is for φ ≤ 12 MHz.
The value is for φ > 12 MHz.
Rev. 7.00 Sep 21, 2005 page 709 of 878
REJ09B0259-0700
Section 22 Electrical Characteristics
22.2.5
D/A Conversion Characteristics
Table 22.19 lists the D/A conversion characteristics.
Table 22.19 D/A Converter Characteristics
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V, φ = 1 MHz to 8 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V, φ = 1 MHz to 16 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition A
Condition C
8 MHz
16 MHz
Item
Min
Typ
Max
Min
Typ
Max
Unit
Resolution
8
8
8
8
8
8
Bits
Conversion time
—
—
10
—
—
10
µs
20-pF capacitive
load
Absolute accuracy
—
±2.0
±3.0
—
±1.0
±1.5
LSB
2-MΩ resistive
load
—
—
±2.0
—
—
±1.0
LSB
4-MΩ resistive
load
Rev. 7.00 Sep 21, 2005 page 710 of 878
REJ09B0259-0700
Test Conditions
Section 22 Electrical Characteristics
22.2.6
Flash Memory Characteristics
Table 22.20 lists the flash memory characteristics.
Table 22.20 Flash Memory
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V, VPP = 12 V ± 0.6 V, φ = 1 MHz to 8 MHz, Ta = –20°C to +75°C
(regular specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V, VPP = 12 V ± 0.6 V, φ = 1 MHz to 16 MHz, Ta = –20°C to
+75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications)
Item
Symbol
Min
Typ
Max
Unit
Programming time*1
Test Conditions
tP
—
50
1000
µs
Erase time*1
tE
—
1
30
s
Erase-program cycle
NWEC
—
—
100
time
*1
tVS1
4
—
—
µs
Verify setup time 2*1
tVS2
2
—
—
µs
Flash memory read
setup time*2
tFRS
50
—
—
µs
VCC ≥ 4.5 V
100
—
—
µs
VCC < 4.5 V
Verify setup time 1
Notes: 1. To specify each time, follow the appropriate algorithm.
2. Before reading the flash memory, wait at least for the read setup time after clearing the
VPPE bit; lowering the voltage supplied to VPP from 12 V to 0–5 V; turning on the power
when the external clock is used; or returning from standby mode. When the VPP voltage
is cut off, tFRS indicates the time from when the VPP falls below VCC + 2 V to when the
flash memory is read.
Rev. 7.00 Sep 21, 2005 page 711 of 878
REJ09B0259-0700
Section 22 Electrical Characteristics
22.3
Operational Timing
This section shows timing diagrams.
22.3.1
Bus Timing
Bus timing is shown as follows:
• Basic bus cycle: two-state access
Figure 22.7 shows the timing of the external two-state access cycle.
• Basic bus cycle: three-state access
Figure 22.8 shows the timing of the external three-state access cycle.
• Basic bus cycle: three-state access with one wait state
Figure 22.9 shows the timing of the external three-state access cycle with one wait state
inserted.
Rev. 7.00 Sep 21, 2005 page 712 of 878
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Section 22 Electrical Characteristics
T1
T2
tCYC
tCH
tCL
φ
tCF
tcyc
tAD
tCR
A23 to A0,
CS 7 to CS 0
AS
tPCH
tASD
tACC3
tSD
tAH
tASD
tACC3
tSD
tAH
tAS1
tPCH
RD
(read)
tAS1
tACC1
tRDS
tRDH
D15 to D0
(read)
tPCH
tASD
HWR, LWR
(write)
tSD
tAH
tAS1
tWSW1
tWDD
tWDS1
tWDH
D15 to D0
(write)
Figure 22.7 Basic Bus Cycle: Two-State Access
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Section 22 Electrical Characteristics
T1
T2
T3
φ
A23 to A0
tACC4
AS
tACC4
RD (read)
tRDS
tACC2
D15 to D0
(read)
tWSD
HWR, LWR
(write)
tWSW2
tAS2
tWDS2
D15 to D0
(write)
Figure 22.8 Basic Bus Cycle: Three-State Access
Rev. 7.00 Sep 21, 2005 page 714 of 878
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Section 22 Electrical Characteristics
T1
T2
TW
T3
φ
A23 to A0
AS
RD (read)
D15 to D0
(read)
HWR, LWR
(write)
D15 to D0
(write)
tWTS
tWTH
tWTS
tWTH
WAIT
Figure 22.9 Basic Bus Cycle: Three-State Access with One Wait State
Rev. 7.00 Sep 21, 2005 page 715 of 878
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Section 22 Electrical Characteristics
22.3.2
Refresh Controller Bus Timing
Refresh controller bus timing is shown as follows:
• DRAM bus timing
Figures 22.10 to 22.15 show the DRAM bus timing in each operating mode.
• PSRAM bus timing
Figures 22.16 and 22.17 show the pseudo-static RAM bus timing in each operating mode.
T2
T1
φ
tAD
T3
tAD
A9 to A1
AS
tRAD1
CS 3 (RAS)
tRAD3
tRAH
tAS1
tRP
tASD
RD (CAS)
tAS1
HWR (UW),
LWR (LW )
(read)
HWR (UW),
LWR (LW )
(write)
tCAS
tRAC
tASD
tSD
tCRP
tSD
tAA
tCAC
RFSH
tWDH
tRDS
D15 to D0
(read)
tRDH
tWDS3
D15 to D0
(write)
Figure 22.10 DRAM Bus Timing (Read/Write): Three-State Access
— 2WE
WE Mode —
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Section 22 Electrical Characteristics
T1
T2
T3
φ
A9 to A1
tASD
tSD
AS
tCSR
tRAD3
CS3 (RAS)
tASD
tRAD2
tSD
tRAD2
tRAD3
RD (CAS)
HWR (UW),
LWR (LW)
RFSH
tCSR
Figure 22.11 DRAM Bus Timing (Refresh Cycle): Three-State Access
— 2WE
WE Mode —
φ
CS3 (RAS)
RD (CAS)
tCSR
tCSR
RFSH
Figure 22.12 DRAM Bus Timing (Self-Refresh Mode)
— 2WE
WE Mode —
Rev. 7.00 Sep 21, 2005 page 717 of 878
REJ09B0259-0700
Section 22 Electrical Characteristics
T1
φ
T2
tAD
T3
tAD
A9 to A1
AS
tAS1
CS 3 (RAS)
tRAD3
tRAD1
tRAH
tRP
tASD
HWR (UCAS),
LWR (LCAS)
tCAS
tAS1
RD (WE)
(read)
tRAC
tCAC
RD (WE)
(write)
RFSH
tCRP
tSD
tAA
tASD
tSD
tWDH
tRDS
tRDH
D15 to D0
(read)
tWDS3
D15 to D0
(write)
Figure 22.13 DRAM Bus Timing (Read/Write): Three-State Access
— 2CAS
CAS Mode —
Rev. 7.00 Sep 21, 2005 page 718 of 878
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Section 22 Electrical Characteristics
T1
T2
T3
φ
A9 to A1
tASD
tSD
AS
tCSR
tRAD3
CS 3 (RAS)
tASD
tRAD2
tSD
tRAD2
tRAD3
HWR (UCAS),
LWR (LCAS)
RD (WE)
RFSH
tCSR
Figure 22.14 DRAM Bus Timing (Refresh Cycle): Three-State Access
— 2CAS
CAS Mode —
φ
CS 3 (RAS)
tCSR
HWR (UCAS),
LWR (LCAS)
tCSR
RFSH
Figure 22.15 DRAM Bus Timing (Self-Refresh Mode)
— 2CAS
CAS Mode —
Rev. 7.00 Sep 21, 2005 page 719 of 878
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Section 22 Electrical Characteristics
T1
φ
T2
T3
tAD
A23 to A0
AS
tRAD1
tRAD3
tRP
CS3
tAS1
RD (read)
tSD
tRSD
tRDS
D15 to D0
(read)
tRDH
tWSD
tSD
HWR, LWR
(write)
tWDS2
D15 to D0
(write)
RFSH
Figure 22.16 PSRAM Bus Timing (Read/Write): Three-State Access
T1
T2
T3
φ
A23 to A0
AS
CS3, HWR,
LWR, RD
tRAD2
tRAD3
RFSH
Figure 22.17 PSRAM Bus Timing (Refresh Cycle): Three-State Access
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Section 22 Electrical Characteristics
22.3.3
Control Signal Timing
Control signal timing is shown as follows:
• Reset input timing
Figure 22.18 shows the reset input timing.
• Reset output timing
Figure 22.19 shows the reset output timing.
• Interrupt input timing
Figure 22.20 shows the input timing for NMI and IRQ5 to IRQ0.
• Bus-release mode timing
Figure 22.21 shows the bus-release mode timing.
φ
tRESS
tRESS
RES
tMDS
tRESW
MD2 to MD0
Figure 22.18 Reset Input Timing
φ
tRESD
tRESD
RESO
tRESOW
Figure 22.19 Reset Output Timing*
Note: * This is a function for models with on-chip mask ROM (H8/3048, H8/3047, H8/3045, and
H8/3044), PROM (H8/3048ZTAT), and on-chip flash memory with a dual power supply
(H8/3048F). The function does not exist in the product with on-chip flash memory with a
single power supply (H8/3048F-ONE).
Rev. 7.00 Sep 21, 2005 page 721 of 878
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Section 22 Electrical Characteristics
φ
tNMIS
tNMIH
tNMIS
tNMIH
NMI
IRQ E
tNMIS
IRQ L
IRQ E : Edge-sensitive IRQ i
IRQ L : Level-sensitive IRQ i (i = 0 to 5)
tNMIW
NMI
IRQ j
(j = 0 to 2)
Figure 22.20 Interrupt Input Timing
φ
tBRQS
tBRQS
BREQ
tBACD2
tBACD1
BACK
tBZD
A23 to A0,
AS, RD,
HWR, LWR
Figure 22.21 Bus-Release Mode Timing
Rev. 7.00 Sep 21, 2005 page 722 of 878
REJ09B0259-0700
tBZD
Section 22 Electrical Characteristics
22.3.4
Clock Timing
Clock timing is shown as follows:
• Oscillator settling timing
Figure 22.22 shows the oscillator settling timing.
φ
VCC
STBY
tOSC1
tOSC1
RES
Figure 22.22 Oscillator Settling Timing
22.3.5
TPC and I/O Port Timing
Figure 22.23 shows the TPC and I/O port timing.
T1
T2
T3
φ
tPRS
tPRH
Port 1 to B
(read)
tPWD
Port 1 to 6,
8 to B
(write)
Figure 22.23 TPC and I/O Port Input/Output Timing
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Section 22 Electrical Characteristics
22.3.6
ITU Timing
ITU timing is shown as follows:
• ITU input/output timing
Figure 22.24 shows the ITU input/output timing.
• ITU external clock input timing
Figure 22.25 shows the ITU external clock input timing.
φ
tTOCD
Output
compare*1
tTICS
Input
capture*2
Notes: 1. TIOCA0 to TIOCA4, TIOCB0 to TIOCB4, TOCXA4, TOCXB4
2. TIOCA0 to TIOCA4, TIOCB0 to TIOCB4
Figure 22.24 ITU Input/Output Timing
tTCKS
φ
tTCKS
TCLKA to
TCLKD
tTCKWL
tTCKWH
Figure 22.25 ITU External Clock Input Timing
Rev. 7.00 Sep 21, 2005 page 724 of 878
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Section 22 Electrical Characteristics
22.3.7
SCI Input/Output Timing
SCI timing is shown as follows:
• SCI input clock timing
Figure 22.26 shows the SCK input clock timing.
• SCI input/output timing (synchronous mode)
Figure 22.27 shows the SCI input/output timing in synchronous mode.
tSCKW
tSCKr
tSCKf
SCK0, SCK1
tScyc
Figure 22.26 SCK Input Clock Timing
tScyc
SCK0, SCK1
tTXD
TxD0, TxD1
(transmit
data)
tRXS
tRXH
RxD0, RxD1
(receive
data)
Figure 22.27 SCI Input/Output Timing in Synchronous Mode
Rev. 7.00 Sep 21, 2005 page 725 of 878
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Section 22 Electrical Characteristics
22.3.8
DMAC Timing
DMAC timing is shown as follows.
• DMAC TEND output timing for 2 state access
Figure 22.28 shows the DMAC TEND output timing for 2 state access.
• DMAC TEND output timing for 3 state access
Figure 22.29 shows the DMAC TEND output timing for 3 state access.
• DMAC DREQ input timing
Figure 22.30 shows DMAC DREQ input timing.
T1
T2
φ
tTED1
tTED2
TEND
Figure 22.28 DMAC TEND Output Timing for 2 State Access
T1
φ
T2
T3
tTED2
tTED1
TEND
Figure 22.29 DMAC TEND Output Timing for 3 State Access
φ
tDRQS
tDRQH
DREQ
Figure 22.30 DMAC DREQ Input Timing
Rev. 7.00 Sep 21, 2005 page 726 of 878
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Appendix A Instruction Set
Appendix A Instruction Set
A.1
Instruction List
Operand Notation
Symbol
Description
Rd
General destination register
Rs
General source register
Rn
General register
ERd
General destination register (address register or 32-bit register)
ERs
General source register (address register or 32-bit register)
ERn
General register (32-bit register)
(EAd)
Destination operand
(EAs)
Source operand
PC
Program counter
SP
Stack pointer
CCR
Condition code register
N
N (negative) flag in CCR
Z
Z (zero) flag in CCR
V
V (overflow) flag in CCR
C
C (carry) flag in CCR
disp
Displacement
→
Transfer from the operand on the left to the operand on the right, or transition from
the state on the left to the state on the right
+
Addition of the operands on both sides
–
Subtraction of the operand on the right from the operand on the left
×
Multiplication of the operands on both sides
÷
Division of the operand on the left by the operand on the right
∧
Logical AND of the operands on both sides
∨
Logical OR of the operands on both sides
⊕
Exclusive logical OR of the operands on both sides
¬
NOT (logical complement)
( ), < >
Contents of operand
Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers
(R0 to R7 and E0 to E7).
Rev. 7.00 Sep 21, 2005 page 727 of 878
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Appendix A Instruction Set
Symbol
Description
↔
Condition Code Notation
Changed according to execution result
*
Undetermined (no guaranteed value)
0
Cleared to 0
1
Set to 1
—
Not affected by execution of the instruction
∆
Varies depending on conditions, described in notes
Rev. 7.00 Sep 21, 2005 page 728 of 878
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Appendix A Instruction Set
Table A.1
Instruction Set
1. Data transfer instructions
No. of
States*1
MOV.B @(d:16, ERs), Rd
B @(d:16, ERs) → Rd8
4
— —
MOV.B @(d:24, ERs), Rd
B @(d:24, ERs) → Rd8
8
— —
MOV.B @ERs+, Rd
B @ERs → Rd8
ERs32+1 → ERs32
MOV.B @aa:8, Rd
B @aa:8 → Rd8
2
— —
MOV.B @aa:16, Rd
B @aa:16 → Rd8
4
— —
MOV.B @aa:24, Rd
B @aa:24 → Rd8
6
— —
MOV.B Rs, @ERd
B Rs8 → @ERd
MOV.B Rs, @(d:16, ERd)
B Rs8 → @(d:16, ERd)
4
— —
MOV.B Rs, @(d:24, ERd)
B Rs8 → @(d:24, ERd)
8
— —
MOV.B Rs, @–ERd
B ERd32–1 → ERd32
Rs8 → @ERd
MOV.B Rs, @aa:8
B Rs8 → @aa:8
2
— —
MOV.B Rs, @aa:16
B Rs8 → @aa:16
4
— —
MOV.B Rs, @aa:24
B Rs8 → @aa:24
6
— —
MOV.W #xx:16, Rd
W #xx:16 → Rd16
MOV.W Rs, Rd
W Rs16 → Rd16
MOV.W @ERs, Rd
W @ERs → Rd16
— —
2
— —
2
— —
2
— —
2
— —
4
— —
2
— —
2
MOV.W @(d:16, ERs), Rd W @(d:16, ERs) → Rd16
4
— —
MOV.W @(d:24, ERs), Rd W @(d:24, ERs) → Rd16
8
— —
MOV.W @ERs+, Rd
W @ERs → Rd16
ERs32+2 → @ERd32
MOV.W @aa:16, Rd
W @aa:16 → Rd16
4
— —
MOV.W @aa:24, Rd
W @aa:24 → Rd16
6
— —
MOV.W Rs, @ERd
W Rs16 → @ERd
— —
2
— —
2
MOV.W Rs, @(d:16, ERd) W Rs16 → @(d:16, ERd)
4
— —
MOV.W Rs, @(d:24, ERd) W Rs16 → @(d:24, ERd)
8
— —
↔ ↔ ↔ ↔ ↔ ↔
B @ERs → Rd8
↔ ↔ ↔ ↔ ↔ ↔
MOV.B @ERs, Rd
— —
2
0 —
0 —
0 —
Advanced
Normal
C
0 —
↔ ↔ ↔ ↔ ↔ ↔ ↔
B Rs8 → Rd8
V
↔ ↔ ↔ ↔ ↔ ↔ ↔
Z
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
N
MOV.B Rs, Rd
2
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
I
B #xx:8 → Rd8
↔ ↔ ↔ ↔ ↔
H
— —
MOV.B #xx:8, Rd
↔ ↔ ↔ ↔ ↔
—
@@aa
@(d, PC)
Condition Code
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
Operation
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
2
0 —
2
0 —
4
0 —
6
0 —
10
0 —
6
4
0 —
6
0 —
8
0 —
4
0 —
6
0 —
10
0 —
6
4
0 —
6
0 —
8
0 —
4
0 —
2
0 —
4
0 —
6
0 —
10
0 —
6
6
0 —
8
0 —
4
0 —
6
0 —
10
Rev. 7.00 Sep 21, 2005 page 729 of 878
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Appendix A Instruction Set
No. of
States*1
N
Z
4
— —
6
— —
V
L @(d:24, ERs) → ERd32
10
MOV.L @ERs+, ERd
L @ERs → ERd32
ERs32+4 → ERs32
MOV.L @aa:16, ERd
L @aa:16 → ERd32
MOV.L @aa:24, ERd
L @aa:24 → ERd32
MOV.L ERs, @ERd
L ERs32 → @ERd
MOV.L ERs, @(d:16, ERd)
L ERs32 → @(d:16, ERd)
6
MOV.L ERs, @(d:24, ERd)
L ERs32 → @(d:24, ERd)
10
MOV.L ERs, @–ERd
L ERd32–4 → ERd32
ERs32 → @ERd
MOV.L ERs, @aa:16
L ERs32 → @aa:16
MOV.L ERs, @aa:24
L ERs32 → @aa:24
6
— —
POP.W Rn
W @SP → Rn16
SP+2 → SP
8
2 — —
POP.L ERn
L @SP → ERn32
SP+4 → SP
4 — —
PUSH.W Rn
W SP–2 → SP
Rn16 → @SP
2 — —
PUSH.L ERn
L SP–4 → SP
ERn32 → @SP
4 — —
MOVFPE @aa:16, Rd
B Cannot be used in
the H8/3048 Group
4
Cannot be used in
the H8/3048 Group
B Cannot be used in
the H8/3048 Group
4
Cannot be used in
the H8/3048 Group
MOVTPE Rs, @aa:16
Rev. 7.00 Sep 21, 2005 page 730 of 878
REJ09B0259-0700
— —
— —
4
— —
4
6
— —
8
— —
— —
— —
— —
4
— —
↔
MOV.L @(d:24, ERs), ERd
— —
↔
6
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
L @(d:16, ERs) → ERd32
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
MOV.L @(d:16, ERs), ERd
— —
4
↔ ↔ ↔ ↔ ↔ ↔
L @ERs → ERd32
↔ ↔ ↔ ↔ ↔ ↔
MOV.L @ERs, ERd
— —
2
0 —
0 —
8
0 —
10
0 —
14
0 —
10
↔ ↔ ↔
L ERs32 → ERd32
↔ ↔ ↔
MOV.L ERs, ERd
— —
6
0 —
10
0 —
12
0 —
6
↔
L #xx:32 → Rd32
↔
MOV.L #xx:32, Rd
0 —
0 —
10
↔
W Rs16 → @aa:24
↔
W Rs16 → @aa:16
MOV.W Rs, @aa:24
C
0 —
0 —
6
↔
MOV.W Rs, @aa:16
2
Advanced
I
W ERd32–2 → ERd32
Rs16 → @ERd
↔
H
— —
MOV.W Rs, @–ERd
Normal
—
@@aa
@(d, PC)
Condition Code
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
Operation
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
0 —
10
6
6
0 —
8
0 —
6
0 —
2
0 —
8
0 —
10
0 —
14
0 —
10
10
0 —
12
Appendix A Instruction Set
2. Arithmetic instructions
No. of
States*1
Advanced
N
Z
V
C
↔ ↔
— (2)
↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
2
— (2)
↔
↔
↔
↔
2
↔ ↔
(3)
↔ ↔
↔ ↔
I
Normal
H
↔ ↔
—
@@aa
@(d, PC)
Condition Code
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
Operation
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
2
— — — — — —
2
B Rd8+#xx:8 → Rd8
ADD.B Rs, Rd
B Rd8+Rs8 → Rd8
ADD.W #xx:16, Rd
W Rd16+#xx:16 → Rd16
ADD.W Rs, Rd
W Rd16+Rs16 → Rd16
ADD.L #xx:32, ERd
L ERd32+#xx:32 →
ERd32
ADD.L ERs, ERd
L ERd32+ERs32 →
ERd32
ADDX.B #xx:8, Rd
B Rd8+#xx:8 +C → Rd8
ADDX.B Rs, Rd
B Rd8+Rs8 +C → Rd8
2
—
ADDS.L #1, ERd
L ERd32+1 → ERd32
2
ADDS.L #2, ERd
L ERd32+2 → ERd32
2
— — — — — —
2
ADDS.L #4, ERd
L ERd32+4 → ERd32
2
— — — — — —
2
INC.B Rd
B Rd8+1 → Rd8
2
— —
INC.W #1, Rd
W Rd16+1 → Rd16
2
— —
INC.W #2, Rd
W Rd16+2 → Rd16
2
— —
INC.L #1, ERd
L ERd32+1 → ERd32
2
— —
INC.L #2, ERd
L ERd32+2 → ERd32
2
— —
DAA Rd
B Rd8 decimal adjust
→ Rd8
2
— *
2
—
— (1)
2
6
2
2
— (1)
(3)
2
4
2
6
2
—
2
—
2
—
2
—
2
—
2
* —
2
SUB.W Rs, Rd
W Rd16–Rs16 → Rd16
SUB.L #xx:32, ERd
L ERd32–#xx:32 → ERd32
SUB.L ERs, ERd
L ERd32–ERs32 → ERd32
SUBX.B #xx:8, Rd
B Rd8–#xx:8–C → Rd8
SUBX.B Rs, Rd
B Rd8–Rs8–C → Rd8
2
—
SUBS.L #1, ERd
L ERd32–1 → ERd32
2
— — — — — —
2
SUBS.L #2, ERd
L ERd32–2 → ERd32
2
— — — — — —
2
SUBS.L #4, ERd
L ERd32–4 → ERd32
2
— — — — — —
2
DEC.B Rd
B Rd8–1 → Rd8
2
— —
DEC.W #1, Rd
W Rd16–1 → Rd16
2
— —
DEC.W #2, Rd
W Rd16–2 → Rd16
2
— —
2
6
— (1)
— (2)
2
— (2)
—
↔ ↔
2
(3)
(3)
↔ ↔ ↔
— (1)
↔ ↔ ↔
4
↔ ↔ ↔
2
W Rd16–#xx:16 → Rd16
↔
B Rd8–Rs8 → Rd8
SUB.W #xx:16, Rd
↔ ↔ ↔ ↔ ↔ ↔ ↔
SUB.B Rs, Rd
↔ ↔ ↔ ↔ ↔ ↔ ↔
—
↔ ↔ ↔ ↔ ↔
4
—
↔ ↔ ↔ ↔ ↔ ↔
2
↔ ↔ ↔ ↔ ↔
—
↔ ↔ ↔ ↔ ↔ ↔ ↔
2
↔ ↔ ↔ ↔ ↔ ↔
ADD.B #xx:8, Rd
4
2
6
2
2
2
—
2
—
2
—
2
Rev. 7.00 Sep 21, 2005 page 731 of 878
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Appendix A Instruction Set
No. of
States*1
Advanced
V
C
— —
L ERd32–2 → ERd32
2
— —
↔ ↔
—
2
DAS.Rd
B Rd8 decimal adjust
→ Rd8
2
— *
↔ ↔ ↔
2
DEC.L #2, ERd
↔ ↔ ↔
—
* —
2
MULXU. B Rs, Rd
B Rd8 × Rs8 → Rd16
(unsigned multiplication)
2
— — — — — —
14
MULXU. W Rs, ERd
W Rd16 × Rs16 → ERd32
(unsigned multiplication)
2
— — — — — —
22
MULXS. B Rs, Rd
B Rd8 × Rs8 → Rd16
(signed multiplication)
4
— —
↔
I
Normal
Z
2
MULXS. W Rs, ERd
W Rd16 × Rs16 → ERd32
(signed multiplication)
4
— —
DIVXU. B Rs, Rd
B Rd16 ÷ Rs8 → Rd16
(RdH: remainder,
RdL: quotient)
(unsigned division)
DIVXU. W Rs, ERd
2
— — (6) (7) — —
14
W ERd32 ÷ Rs16 → ERd32
(Ed: remainder,
Rd: quotient)
(unsigned division)
2
— — (6) (7) — —
22
DIVXS. B Rs, Rd
B Rd16 ÷ Rs8 → Rd16
(RdH: remainder,
RdL: quotient)
(signed division)
4
— — (8) (7) — —
16
DIVXS. W Rs, ERd
W ERd32 ÷ Rs16 → ERd32
(Ed: remainder,
Rd: quotient)
(signed division)
4
— — (8) (7) — —
24
CMP.B #xx:8, Rd
B Rd8–#xx:8
CMP.B Rs, Rd
B Rd8–Rs8
CMP.W #xx:16, Rd
W Rd16–#xx:16
CMP.W Rs, Rd
W Rd16–Rs16
CMP.L #xx:32, ERd
L ERd32–#xx:32
CMP.L ERs, ERd
L ERd32–ERs32
Rev. 7.00 Sep 21, 2005 page 732 of 878
REJ09B0259-0700
2
—
2
—
— (1)
4
2
— (1)
— (2)
6
2
— (2)
↔ ↔ ↔ ↔ ↔ ↔
24
↔ ↔ ↔ ↔ ↔ ↔
— —
↔ ↔ ↔ ↔ ↔ ↔
16
↔ ↔
— —
↔ ↔ ↔ ↔ ↔ ↔
↔
N
L ERd32–1 → ERd32
↔
H
DEC.L #1, ERd
↔
—
@@aa
@(d, PC)
Condition Code
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
Operation
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
2
2
4
2
4
2
Appendix A Instruction Set
No. of
States*1
↔ ↔ ↔
W 0–Rd16 → Rd16
2
—
NEG.L ERd
L 0–ERd32 → ERd32
2
—
EXTU.W Rd
W 0 → (<bits 15 to 8>
of Rd16)
2
— — 0
EXTU.L ERd
L 0 → (<bits 31 to 16>
of ERd32)
2
— — 0
EXTS.W Rd
W (<bit 7> of Rd16) →
(<bits 15 to 8> of Rd16)
2
— —
EXTS.L ERd
L (<bit 15> of ERd32) →
(<bits 31 to 16> of
ERd32)
2
— —
Advanced
↔ ↔ ↔
NEG.W Rd
Normal
C
↔ ↔ ↔
V
↔ ↔ ↔ ↔
—
2
0 —
2
↔
2
0 —
2
↔
H
B 0–Rd8 → Rd8
0 —
2
↔
Z
↔
I
NEG.B Rd
↔ ↔ ↔
N
↔
—
@@aa
@(d, PC)
Condition Code
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
Operation
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
0 —
2
2
2
Rev. 7.00 Sep 21, 2005 page 733 of 878
REJ09B0259-0700
Appendix A Instruction Set
3. Logic instructions
No. of
States*1
Z
B Rd8∧#xx:8 → Rd8
AND.B Rs, Rd
B Rd8∧Rs8 → Rd8
AND.W #xx:16, Rd
W Rd16∧#xx:16 → Rd16
AND.W Rs, Rd
W Rd16∧Rs16 → Rd16
AND.L #xx:32, ERd
L ERd32∧#xx:32 → ERd32
AND.L ERs, ERd
L ERd32∧ERs32 → ERd32
OR.B #xx:8, Rd
B Rd8∨#xx:8 → Rd8
OR.B Rs, Rd
B Rd8∨Rs8 → Rd8
OR.W #xx:16, Rd
W Rd16∨#xx:16 → Rd16
OR.W Rs, Rd
W Rd16∨Rs16 → Rd16
OR.L #xx:32, ERd
L ERd32∨#xx:32 → ERd32
OR.L ERs, ERd
L ERd32∨ERs32 → ERd32
XOR.B #xx:8, Rd
B Rd8⊕#xx:8 → Rd8
XOR.B Rs, Rd
B Rd8⊕Rs8 → Rd8
XOR.W #xx:16, Rd
W Rd16⊕#xx:16 → Rd16
XOR.W Rs, Rd
W Rd16⊕Rs16 → Rd16
XOR.L #xx:32, ERd
L ERd32⊕#xx:32 → ERd32 6
XOR.L ERs, ERd
L ERd32⊕ERs32 → ERd32
4
— —
NOT.B Rd
B ¬ Rd8 → Rd8
2
— —
NOT.W Rd
W ¬ Rd16 → Rd16
2
— —
NOT.L ERd
L ¬ Rd32 → Rd32
2
— —
Rev. 7.00 Sep 21, 2005 page 734 of 878
REJ09B0259-0700
2
2
— —
— —
4
2
— —
— —
6
4
— —
— —
2
2
— —
— —
4
2
— —
— —
6
4
— —
— —
2
2
— —
— —
4
2
— —
— —
V
C
Advanced
N
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
I
AND.B #xx:8, Rd
Normal
H
— —
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
—
@@aa
@(d, PC)
Condition Code
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
Operation
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
0 —
2
0 —
2
0 —
4
0 —
2
0 —
6
0 —
4
0 —
2
0 —
2
0 —
4
0 —
2
0 —
6
0 —
4
0 —
2
0 —
2
0 —
4
0 —
2
0 —
6
0 —
4
0 —
2
0 —
2
0 —
2
Appendix A Instruction Set
4. Shift instructions
SHAL.L ERd
L
SHAR.B Rd
B
SHAR.W Rd
W
SHAR.L ERd
L
SHLL.B Rd
B
SHLL.W Rd
W
SHLL.L ERd
L
SHLR.B Rd
B
SHLR.W Rd
W
SHLR.L ERd
L
ROTXL.B Rd
B
ROTXL.W Rd
W
ROTXL.L ERd
L
ROTXR.B Rd
B
ROTXR.W Rd
W
ROTXR.L ERd
L
ROTL.B Rd
B
ROTL.W Rd
W
ROTL.L ERd
L
ROTR.B Rd
B
ROTR.W Rd
W
ROTR.L ERd
L
C
0
MSB
LSB
C
MSB
LSB
C
0
MSB
LSB
0
C
MSB
LSB
C
MSB
LSB
C
MSB
LSB
C
MSB
LSB
C
MSB
LSB
Z
2
— —
2
— —
2
— —
2
— —
2
— —
2
— —
2
— —
2
— —
2
— —
2
— —
2
— —
2
— —
2
— —
2
— —
2
— —
2
— —
2
— —
2
— —
2
— —
2
— —
2
— —
2
— —
2
— —
V
C
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Advanced
I
Normal
—
@@aa
@(d, PC)
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
N
— —
↔ ↔ ↔
W
H
2
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
SHAL.W Rd
Condition Code
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
B
No. of
States*1
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
SHAL.B Rd
Operation
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Rev. 7.00 Sep 21, 2005 page 735 of 878
REJ09B0259-0700
Appendix A Instruction Set
5. Bit manipulation instructions
BSET #xx:3, @ERd
B (#xx:3 of @ERd) ← 1
BSET #xx:3, @aa:8
B (#xx:3 of @aa:8) ← 1
BSET Rn, Rd
B (Rn8 of Rd8) ← 1
BSET Rn, @ERd
B (Rn8 of @ERd) ← 1
BSET Rn, @aa:8
B (Rn8 of @aa:8) ← 1
BCLR #xx:3, Rd
B (#xx:3 of Rd8) ← 0
BCLR #xx:3, @ERd
B (#xx:3 of @ERd) ← 0
BCLR #xx:3, @aa:8
B (#xx:3 of @aa:8) ← 0
BCLR Rn, Rd
B (Rn8 of Rd8) ← 0
BCLR Rn, @ERd
B (Rn8 of @ERd) ← 0
BCLR Rn, @aa:8
B (Rn8 of @aa:8) ← 0
BNOT #xx:3, Rd
B (#xx:3 of Rd8) ←
¬ (#xx:3 of Rd8)
BNOT #xx:3, @ERd
B (#xx:3 of @ERd) ←
¬ (#xx:3 of @ERd)
BNOT #xx:3, @aa:8
B (#xx:3 of @aa:8) ←
¬ (#xx:3 of @aa:8)
BNOT Rn, Rd
B (Rn8 of Rd8) ←
¬ (Rn8 of Rd8)
BNOT Rn, @ERd
B (Rn8 of @ERd) ←
¬ (Rn8 of @ERd)
BNOT Rn, @aa:8
B (Rn8 of @aa:8) ←
¬ (Rn8 of @aa:8)
BTST #xx:3, Rd
B ¬ (#xx:3 of Rd8) → Z
BTST #xx:3, @ERd
B ¬ (#xx:3 of @ERd) → Z
BTST #xx:3, @aa:8
B ¬ (#xx:3 of @aa:8) → Z
BTST Rn, Rd
B ¬ (Rn8 of @Rd8) → Z
BTST Rn, @ERd
B ¬ (Rn8 of @ERd) → Z
BTST Rn, @aa:8
B ¬ (Rn8 of @aa:8) → Z
BLD #xx:3, Rd
B (#xx:3 of Rd8) → C
Rev. 7.00 Sep 21, 2005 page 736 of 878
REJ09B0259-0700
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
N
4
8
— — — — — —
8
— — — — — —
2
— — — — — —
8
— — — — — —
8
— — — — — —
2
— — — — — —
8
— — — — — —
8
— — — — — —
2
— — — — — —
8
— — — — — —
8
— — — — — —
2
— — — — — —
8
— — — — — —
8
— — — — — —
2
— — — — — —
8
— — — — — —
8
— — —
— — —
4
4
C
2
— — —
2
V
— — — — — —
— — —
4
Z
Advanced
H
Normal
—
@@aa
I
— — — — — —
— — —
2
2
@(d, PC)
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Condition Code
— — —
— —
2
— —
6
— —
6
— —
2
— —
6
— —
6
↔
B (#xx:3 of Rd8) ← 1
No. of
States*1
↔ ↔ ↔ ↔ ↔ ↔
BSET #xx:3, Rd
Rn
Operation
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
2
— — — — —
Appendix A Instruction Set
BLD #xx:3, @aa:8
B (#xx:3 of @aa:8) → C
BILD #xx:3, Rd
B ¬ (#xx:3 of Rd8) → C
BILD #xx:3, @ERd
B ¬ (#xx:3 of @ERd) → C
BILD #xx:3, @aa:8
B ¬ (#xx:3 of @aa:8) → C
BST #xx:3, Rd
B C → (#xx:3 of Rd8)
BST #xx:3, @ERd
B C → (#xx:3 of @ERd24)
BST #xx:3, @aa:8
B C → (#xx:3 of @aa:8)
BIST #xx:3, Rd
B ¬ C → (#xx:3 of Rd8)
BIST #xx:3, @ERd
B ¬ C → (#xx:3 of @ERd24)
BIST #xx:3, @aa:8
B ¬ C → (#xx:3 of @aa:8)
BAND #xx:3, Rd
B C∧(#xx:3 of Rd8) → C
BAND #xx:3, @ERd
B C∧(#xx:3 of @ERd24) → C
BAND #xx:3, @aa:8
B C∧(#xx:3 of @aa:8) → C
BIAND #xx:3, Rd
B C∧ ¬ (#xx:3 of Rd8) → C
BIAND #xx:3, @ERd
B C∧ ¬ (#xx:3 of @ERd24) → C
BIAND #xx:3, @aa:8
B C∧ ¬ (#xx:3 of @aa:8) → C
BOR #xx:3, Rd
B C∨(#xx:3 of Rd8) → C
BOR #xx:3, @ERd
B C∨(#xx:3 of @ERd24) → C
BOR #xx:3, @aa:8
B C∨(#xx:3 of @aa:8) → C
BIOR #xx:3, Rd
B C∨ ¬ (#xx:3 of Rd8) → C
BIOR #xx:3, @ERd
B C∨ ¬ (#xx:3 of @ERd24) → C
BIOR #xx:3, @aa:8
B C∨ ¬ (#xx:3 of @aa:8) → C
BXOR #xx:3, Rd
B C⊕(#xx:3 of Rd8) → C
BXOR #xx:3, @ERd
B C⊕(#xx:3 of @ERd24) → C
BXOR #xx:3, @aa:8
B C⊕(#xx:3 of @aa:8) → C
BIXOR #xx:3, Rd
B C⊕ ¬ (#xx:3 of Rd8) → C
BIXOR #xx:3, @ERd
B C⊕ ¬ (#xx:3 of @ERd24) → C
BIXOR #xx:3, @aa:8
B C⊕ ¬ (#xx:3 of @aa:8) → C
4
4
I
H
N
Z
C
6
— — — — — —
2
— — — — — —
8
— — — — — —
8
— — — — — —
2
— — — — — —
8
— — — — — —
8
2
— — — — —
— — — — —
2
— — — — —
4
4
2
4
4
2
4
4
— — — — —
— — — — —
2
— — — — —
4
4
— — — — —
— — — — —
2
— — — — —
4
4
— — — — —
— — — — —
2
— — — — —
4
4
— — — — —
— — — — —
2
— — — — —
4
4
— — — — —
— — — — —
2
— — — — —
4
4
— — — — —
— — — — —
2
— — — — —
4
4
Advanced
V
— — — — —
Normal
—
@@aa
@(d, PC)
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Condition Code
↔ ↔ ↔ ↔ ↔
B (#xx:3 of @ERd) → C
No. of
States*1
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
BLD #xx:3, @ERd
Rn
Operation
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
— — — — —
6
2
6
6
6
6
2
6
6
2
6
6
2
6
6
2
6
6
2
6
6
Rev. 7.00 Sep 21, 2005 page 737 of 878
REJ09B0259-0700
Appendix A Instruction Set
6. Branching instructions
BRA d:8 (BT d:8)
BRN d:16 (BF d:16)
— If condition Always
— is true then
PC ← PC+d
Never
—
else next;
—
BHI d:8
—
BHI d:16
—
BLS d:8
—
BLS d:16
—
BCC d:8 (BHS d:8)
—
BCC d:16 (BHS d:16)
—
BCS d:8 (BLO d:8)
—
BCS d:16 (BLO d:16)
—
BNE d:8
—
BNE d:16
—
BEQ d:8
—
BEQ d:16
—
BVC d:8
—
BVC d:16
—
BVS d:8
—
BVS d:16
—
BPL d:8
—
BPL d:16
—
BMI d:8
—
BMI d:16
—
BGE d:8
—
BGE d:16
—
BLT d:8
—
BLT d:16
—
BGT d:8
—
BGT d:16
—
BLE d:8
—
BLE d:16
—
BRA d:16 (BT d:16)
BRN d:8 (BF d:8)
C∨Z=0
C∨Z=1
C=0
C=1
Z=0
Z=1
V=0
V=1
N=0
N=1
N⊕V = 0
N⊕V = 1
Z ∨ (N⊕V) = 0
Z ∨ (N⊕V) = 1
Rev. 7.00 Sep 21, 2005 page 738 of 878
REJ09B0259-0700
No. of
States*1
H
N
Z
V
C
Advanced
I
Normal
—
@@aa
@(d, PC)
Condition Code
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Branch
Condition
Rn
Operation
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
2
— — — — — —
4
4
— — — — — —
6
2
— — — — — —
4
4
— — — — — —
6
2
— — — — — —
4
4
— — — — — —
6
2
— — — — — —
4
4
— — — — — —
6
2
— — — — — —
4
4
— — — — — —
6
2
— — — — — —
4
4
— — — — — —
6
2
— — — — — —
4
4
— — — — — —
6
2
— — — — — —
4
4
— — — — — —
6
2
— — — — — —
4
4
— — — — — —
6
2
— — — — — —
4
4
— — — — — —
6
2
— — — — — —
4
4
— — — — — —
6
2
— — — — — —
4
4
— — — — — —
6
2
— — — — — —
4
4
— — — — — —
6
2
— — — — — —
4
4
— — — — — —
6
2
— — — — — —
4
4
— — — — — —
6
2
— — — — — —
4
4
— — — — — —
6
Appendix A Instruction Set
JMP @ERn
— PC ← ERn
JMP @aa:24
— PC ← aa:24
JMP @@aa:8
— PC ← @aa:8
BSR d:8
— PC → @–SP
PC ← PC+d:8
BSR d:16
— PC → @–SP
PC ← PC+d:16
JSR @ERn
— PC → @–SP
PC ← @ERn
JSR @aa:24
— PC → @–SP
PC ← @aa:24
JSR @@aa:8
— PC → @–SP
PC ← @aa:8
RTS
— PC ← @SP+
No. of
States*1
H
N
Z
V
C
— — — — — —
2
4
— — — — — —
4
Advanced
I
Normal
—
@@aa
@(d, PC)
Condition Code
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
Operation
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
6
— — — — — —
8
10
2
— — — — — —
6
8
4
— — — — — —
8
10
— — — — — —
6
8
— — — — — —
8
10
— — — — — —
8
12
2 — — — — — —
8
10
2
2
4
2
Rev. 7.00 Sep 21, 2005 page 739 of 878
REJ09B0259-0700
Appendix A Instruction Set
7. System control instructions
No. of
States*1
6
LDC @(d:24, ERs), CCR
W @(d:24, ERs) → CCR
10
LDC @ERs+, CCR
W @ERs → CCR
ERs32+2 → ERs32
LDC @aa:16, CCR
W @aa:16 → CCR
6
LDC @aa:24, CCR
W @aa:24 → CCR
8
@@aa
Advanced
W @(d:16, ERs) → CCR
Normal
LDC @(d:16, ERs), CCR
— — — — — —
2
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
4
10
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
4
C
↔
W @ERs → CCR
2
V
↔
LDC @ERs, CCR
2
↔
B Rs8 → CCR
Z
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
B #xx:8 → CCR
LDC Rs, CCR
↔
LDC #xx:8, CCR
N
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
— Transition to powerdown state
16
H
↔
SLEEP
1 — — — — — 14
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
— CCR ← @SP+
PC ← @SP+
I
2
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
RTE
—
— PC → @–SP
CCR → @–SP
<vector> → PC
↔
TRAPA #x:2
@(d, PC)
Condition Code
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
Operation
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
12
— — — — — —
2
— — — — — —
6
2
2
6
8
8
8
10
6
— — — — — —
8
STC CCR, @(d:24, ERd)
W CCR → @(d:24, ERd)
10
— — — — — —
12
STC CCR, @–ERd
W ERd32–2 → ERd32
CCR → @ERd
— — — — — —
8
STC CCR, @aa:16
W CCR → @aa:16
6
— — — — — —
8
STC CCR, @aa:24
W CCR → @aa:24
8
— — — — — —
10
ANDC #xx:8, CCR
B CCR∧#xx:8 → CCR
2
ORC #xx:8, CCR
B CCR∨#xx:8 → CCR
2
XORC #xx:8, CCR
B CCR⊕#xx:8 → CCR
2
NOP
— PC ← PC+2
Rev. 7.00 Sep 21, 2005 page 740 of 878
REJ09B0259-0700
↔ ↔ ↔
4
↔ ↔ ↔
W CCR → @(d:16, ERd)
4
↔ ↔ ↔
STC CCR, @(d:16, ERd)
2
↔ ↔ ↔
W CCR → @ERd
↔ ↔ ↔
B CCR → Rd8
STC CCR, @ERd
↔ ↔ ↔
STC CCR, Rd
2
2 — — — — — —
2
2
2
Appendix A Instruction Set
8. Block transfer instructions
No. of
States*1
H
N
Z
V
C
EEPMOV. B
— if R4L ≠ 0 then
repeat @R5 → @R6
R5+1 → R5
R6+1 → R6
R4L–1 → R4L
until
R4L=0
else next
4 — — — — — — 8+
4n*2
EEPMOV. W
— if R4 ≠ 0 then
repeat @R5 → @R6
R5+1 → R5
R6+1 → R6
R4–1 → R4
until
R4=0
else next
4 — — — — — — 8+
4n*2
Advanced
I
Normal
—
@@aa
@(d, PC)
Condition Code
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
Operation
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
Notes: 1. The number of states is the number of states required for execution when the
instruction and its operands are located in on-chip memory. For other cases see
section A.3, Number of States Required for Execution.
2. n is the value set in register R4L or R4.
(1) Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0.
(2) Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0.
(3) Retains its previous value when the result is zero; otherwise cleared to 0.
(4) Set to 1 when the adjustment produces a carry; otherwise retains its previous value.
(5) The number of states required for execution of an instruction that transfers data in
synchronization with the E clock is variable.
(6) Set to 1 when the divisor is negative; otherwise cleared to 0.
(7) Set to 1 when the divisor is zero; otherwise cleared to 0.
(8) Set to 1 when the quotient is negative; otherwise cleared to 0.
Rev. 7.00 Sep 21, 2005 page 741 of 878
REJ09B0259-0700
Rev. 7.00 Sep 21, 2005 page 742 of 878
REJ09B0259-0700
MULXU
5
STC
Table A-2
(2)
LDC
3
SUBX
OR
XOR
AND
MOV
C
D
E
F
BILD
BIST
BLD
BST
TRAPA
BEQ
B
BIAND
BAND
AND
RTE
BNE
CMP
BIXOR
BXOR
XOR
BSR
BCS
A
BIOR
BOR
OR
RTS
BCC
MOV.B
Table A-2
(2)
LDC
7
ADDX
BTST
DIVXU
BLS
AND.B
ANDC
6
9
BCLR
MULXU
BHI
XOR.B
XORC
5
ADD
BNOT
DIVXU
BRN
OR.B
ORC
4
8
7
BSET
BRA
6
2
1
Table A-2 Table A-2 Table A-2 Table A-2
(2)
(2)
(2)
(2)
NOP
4
3
2
1
0
0
MOV
BVS
9
B
JMP
BPL
BMI
MOV
Table A-2 Table A-2
(2)
(2)
Table A-2 Table A-2
(2)
(2)
A
Table A-2 Table A-2
EEPMOV
(2)
(2)
SUB
ADD
Table A-2
(2)
BVC
8
BSR
BGE
C
CMP
MOV
Instruction when most significant bit of BH is 1.
Instruction when most significant bit of BH is 0.
JSR
BGT
SUBX
ADDX
E
Table A-2
(3)
BLT
D
BLE
Table A-2
(2)
Table A-2
(2)
F
Table A.2
AL
1st byte 2nd byte
AH AL BH BL
A.2
AH
Instruction code:
Appendix A Instruction Set
Operation Code Map
Operation Code Map
SUBS
DAS
BRA
MOV
MOV
1B
1F
58
79
7A
CMP
CMP
ADD
ADD
2
BHI
1
SUB
SUB
BLS
OR
OR
XOR
XOR
BCS
AND
AND
BEQ
BVC
SUB
9
BVS
NEG
NOT
DEC
ROTR
ROTXR
DEC
ROTL
ADDS
SLEEP
8
ROTXL
EXTU
INC
7
SHAR
BNE
6
SHLR
EXTU
INC
5
SHAL
BCC
LDC/STC
4
SHLL
3
1st byte 2nd byte
AH AL BH BL
BRN
NOT
17
DEC
ROTXR
13
1A
ROTXL
12
DAA
0F
SHLR
ADDS
0B
11
INC
0A
SHLL
MOV
01
10
0
BH
AH AL
Instruction code:
BPL
A
MOV
BMI
NEG
CMP
SUB
ROTR
ROTL
SHAR
C
D
BGE
BLT
DEC
EXTS
INC
Table A-2 Table A-2
(3)
(3)
ADD
SHAL
B
BGT
E
BLE
DEC
EXTS
INC
Table A-2
(3)
F
Appendix A Instruction Set
Rev. 7.00 Sep 21, 2005 page 743 of 878
REJ09B0259-0700
CL
Rev. 7.00 Sep 21, 2005 page 744 of 878
REJ09B0259-0700
DIVXS
3
BSET
7Faa7 * 2
BNOT
BNOT
BCLR
BCLR
Notes: 1. r is the register designation field.
2. aa is the absolute address field.
BSET
7Faa6 * 2
BTST
BCLR
7Eaa7 * 2
BNOT
BTST
BSET
7Dr07 * 1
7Eaa6 * 2
BSET
7Dr06 * 1
BTST
BCLR
MULXS
2
7Cr07 * 1
BNOT
DIVXS
1
BTST
MULXS
0
BIOR
BOR
BIOR
BOR
OR
4
BIXOR
BXOR
BIXOR
BXOR
XOR
5
BIAND
BAND
BIAND
BAND
AND
6
7
BIST
BILD
BST
BLD
BIST
BILD
BST
BLD
1st byte 2nd byte 3rd byte 4th byte
AH AL BH BL CH CL DH DL
7Cr06 * 1
01F06
01D05
01C05
01406
AH
ALBH
BLCH
Instruction code:
8
LDC
STC
9
A
LDC
STC
B
C
LDC
STC
D
E
LDC
STC
F
Instruction when most significant bit of DH is 1.
Instruction when most significant bit of DH is 0.
Appendix A Instruction Set
Appendix A Instruction Set
A.3
Number of States Required for Execution
The tables in this section can be used to calculate the number of states required for instruction
execution by the H8/300H CPU. Table A.4 indicates the number of instruction fetch, data
read/write, and other cycles occurring in each instruction. Table A.3 indicates the number of states
required per cycle according to the bus size. The number of states required for execution of an
instruction can be calculated from these two tables as follows:
Number of states = I × SI + J × SJ + K × SK + L × SL + M × SM + N × SN
Examples of Calculation of Number of States Required for Execution
Examples: Advanced mode, stack located in external address space, on-chip supporting modules
accessed with 8-bit bus width, external devices accessed in three states with one wait state and
16-bit bus width.
BSET #0, @FFFFC7:8
From table A.4, I = L = 2 and J = K = M = N = 0
From table A.3, SI = 4 and SL = 3
Number of states = 2 × 4 + 2 × 3 = 14
JSR @@30
From table A.4, I = J = K = 2 and L = M = N = 0
From table A.3, SI = SJ = SK = 4
Number of states = 2 × 4 + 2 × 4 + 2 × 4 = 24
Rev. 7.00 Sep 21, 2005 page 745 of 878
REJ09B0259-0700
Appendix A Instruction Set
Table A.3
Number of States per Cycle
Access Conditions
On-Chip
Supporting
Module
Cycle
Instruction fetch
SI
Branch address read
SJ
Stack operation
SK
Byte data access
SL
Word data access
SM
Internal operation
SN
External Device
8-Bit Bus
16-Bit Bus
On-Chip
Memory
8-Bit
Bus
16-Bit
Bus
2-State
Access
3-State
Access
2-State
Access
3-State
Access
2
6
3
4
6 + 2m
2
3+m
2
3+m
1
1
3
6
1
1
1
4
6 + 2m
1
1
Legend
m: Number of wait states inserted into external device access
Rev. 7.00 Sep 21, 2005 page 746 of 878
REJ09B0259-0700
Appendix A Instruction Set
Table A.4
Number of Cycles per Instruction
Instruction Mnemonic
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access
Access
Operation
I
J
K
L
M
N
ADD
ADD.B #xx:8, Rd
1
ADD.B Rs, Rd
1
ADD.W #xx:16, Rd
2
ADD.W Rs, Rd
1
ADD.L #xx:32, ERd
3
ADD.L ERs, ERd
1
ADDS
ADDS #1/2/4, ERd
1
ADDX
ADDX #xx:8, Rd
1
ADDX Rs, Rd
1
AND
AND.B #xx:8, Rd
1
AND.B Rs, Rd
1
AND.W #xx:16, Rd
2
AND.W Rs, Rd
1
AND.L #xx:32, ERd
3
AND.L ERs, ERd
2
ANDC
ANDC #xx:8, CCR
1
BAND
BAND #xx:3, Rd
1
Bcc
BAND #xx:3, @ERd
2
1
BAND #xx:3, @aa:8
2
1
BRA d:8 (BT d:8)
2
BRN d:8 (BF d:8)
2
BHI d:8
2
BLS d:8
2
BCC d:8 (BHS d:8)
2
BCS d:8 (BLO d:8)
2
BNE d:8
2
BEQ d:8
2
BVC d:8
2
BVS d:8
2
BPL d:8
2
BMI d:8
2
BGE d:8
2
BLT d:8
2
Rev. 7.00 Sep 21, 2005 page 747 of 878
REJ09B0259-0700
Appendix A Instruction Set
Instruction Mnemonic
Bcc
BCLR
BIAND
BILD
BIOR
BIST
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access
Access
Operation
I
J
K
L
M
N
BGT d:8
2
BLE d:8
2
BRA d:16 (BT d:16)
2
2
BRN d:16 (BF d:16)
2
2
BHI d:16
2
2
BLS d:16
2
2
BCC d:16 (BHS d:16)
2
2
BCS d:16 (BLO d:16)
2
2
BNE d:16
2
2
BEQ d:16
2
2
BVC d:16
2
2
BVS d:16
2
2
BPL d:16
2
2
BMI d:16
2
2
BGE d:16
2
2
BLT d:16
2
2
BGT d:16
2
2
2
BLE d:16
2
BCLR #xx:3, Rd
1
BCLR #xx:3, @ERd
2
2
BCLR #xx:3, @aa:8
2
2
BCLR Rn, Rd
1
BCLR Rn, @ERd
2
2
BCLR Rn, @aa:8
2
2
BIAND #xx:3, Rd
1
BIAND #xx:3, @ERd
2
1
BIAND #xx:3, @aa:8
2
1
BILD #xx:3, Rd
1
BILD #xx:3, @ERd
2
1
BILD #xx:3, @aa:8
2
1
BIOR #xx:8, Rd
1
BIOR #xx:8, @ERd
2
1
BIOR #xx:8, @aa:8
2
1
BIST #xx:3, Rd
1
BIST #xx:3, @ERd
2
2
BIST #xx:3, @aa:8
2
2
Rev. 7.00 Sep 21, 2005 page 748 of 878
REJ09B0259-0700
Appendix A Instruction Set
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access
Access
Operation
I
J
K
L
M
N
Instruction Mnemonic
BIXOR
BLD
BNOT
BOR
BSET
BIXOR #xx:3, Rd
1
BIXOR #xx:3, @ERd
2
1
BIXOR #xx:3, @aa:8
2
1
BLD #xx:3, Rd
1
BLD #xx:3, @ERd
2
1
BLD #xx:3, @aa:8
2
1
BNOT #xx:3, Rd
1
BNOT #xx:3, @ERd
2
2
BNOT #xx:3, @aa:8
2
2
BNOT Rn, Rd
1
BNOT Rn, @ERd
2
2
BNOT Rn, @aa:8
2
2
BOR #xx:3, Rd
1
BOR #xx:3, @ERd
2
1
1
BOR #xx:3, @aa:8
2
BSET #xx:3, Rd
1
BSET #xx:3, @ERd
2
2
BSET #xx:3, @aa:8
2
2
BSET Rn, Rd
1
BSET Rn, @ERd
2
BSET Rn, @aa:8
BSR
BST
BTST
2
2
2
BSR d:8
Normal*1
2
1
Advanced
2
2
BSR d:16
Normal*1
2
1
2
Advanced
2
2
2
BST #xx:3, Rd
1
BST #xx:3, @ERd
2
2
BST #xx:3, @aa:8
2
2
BTST #xx:3, Rd
1
BTST #xx:3, @ERd
2
1
BTST #xx:3, @aa:8
2
1
BTST Rn, Rd
1
BTST Rn, @ERd
2
1
BTST Rn, @aa:8
2
1
Rev. 7.00 Sep 21, 2005 page 749 of 878
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Appendix A Instruction Set
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access
Access
Operation
I
J
K
L
M
N
Instruction Mnemonic
BXOR
CMP
DAA
BXOR #xx:3, Rd
1
BXOR #xx:3, @ERd
2
1
BXOR #xx:3, @aa:8
2
1
CMP.B #xx:8, Rd
1
CMP.B Rs, Rd
1
CMP.W #xx:16, Rd
2
CMP.W Rs, Rd
1
CMP.L #xx:32, ERd
3
CMP.L ERs, ERd
1
DAA Rd
1
DAS
DAS Rd
1
DEC
DEC.B Rd
1
DIVXS
DIVXU
EEPMOV
EXTS
DEC.W #1/2, Rd
1
DEC.L #1/2, ERd
1
DIVXS.B Rs, Rd
2
12
DIVXS.W Rs, ERd
2
20
DIVXU.B Rs, Rd
1
12
DIVXU.W Rs, ERd
1
EEPMOV.B
2
EEPMOV.W
2
2n + 2*2
EXTS.W Rd
1
EXTS.L ERd
1
EXTU
EXTU.W Rd
1
EXTU.L ERd
1
INC
INC.B Rd
1
JMP
20
2n + 2*2
INC.W #1/2, Rd
1
INC.L #1/2, ERd
1
JMP @ERn
2
JMP @aa:24
2
JMP @@aa:8 Normal*1
Advanced
2
2
1
2
2
2
2
Rev. 7.00 Sep 21, 2005 page 750 of 878
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Appendix A Instruction Set
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access
Access
Operation
I
J
K
L
M
N
Instruction Mnemonic
JSR
JSR @ERn
JSR @aa:24
Normal*1
2
1
Advanced
2
2
Normal*1
2
1
2
Advanced
2
2
2
JSR @@aa:8 Normal*1
Advanced
LDC
MOV
2
1
1
2
2
2
LDC #xx:8, CCR
1
LDC Rs, CCR
1
LDC @ERs, CCR
2
1
LDC @(d:16, ERs), CCR
3
1
LDC @(d:24, ERs), CCR
5
1
LDC @ERs+, CCR
2
1
LDC @aa:16, CCR
3
1
LDC @aa:24, CCR
4
1
MOV.B #xx:8, Rd
1
MOV.B Rs, Rd
1
MOV.B @ERs, Rd
1
1
MOV.B @(d:16, ERs), Rd
2
1
MOV.B @(d:24, ERs), Rd
4
1
MOV.B @ERs+, Rd
1
1
MOV.B @aa:8, Rd
1
1
MOV.B @aa:16, Rd
2
1
MOV.B @aa:24, Rd
3
1
MOV.B Rs, @ERd
1
1
MOV.B Rs, @(d:16, ERd)
2
1
MOV.B Rs, @(d:24, ERd)
4
1
MOV.B Rs, @–ERd
1
1
MOV.B Rs, @aa:8
1
1
MOV.B Rs, @aa:16
2
1
MOV.B Rs, @aa:24
3
1
2
2
2
MOV.W #xx:16, Rd
2
MOV.W Rs, Rd
1
MOV.W @ERs, Rd
1
1
MOV.W @(d:16, ERs), Rd 2
1
Rev. 7.00 Sep 21, 2005 page 751 of 878
REJ09B0259-0700
Appendix A Instruction Set
Instruction Mnemonic
MOV
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access
Access
Operation
I
J
K
L
M
N
MOV.W @(d:24, ERs), Rd 4
1
MOV.W @ERs+, Rd
1
1
MOV.W @aa:16, Rd
2
1
MOV.W @aa:24, Rd
3
1
MOV.W Rs, @ERd
1
1
MOV.W Rs, @(d:16, ERd) 2
1
MOV.W Rs, @(d:24, ERd) 4
1
MOV.W Rs, @–ERd
1
1
MOV.W Rs, @aa:16
2
1
MOV.W Rs, @aa:24
3
1
MOV.L #xx:32, ERd
3
MOV.L ERs, ERd
1
MOV.L @ERs, ERd
2
2
MOV.L @(d:16, ERs), ERd 3
2
MOV.L @(d:24, ERs), ERd 5
2
MOV.L @ERs+, ERd
2
2
MOV.L @aa:16, ERd
3
2
MOV.L @aa:24, ERd
4
2
MOV.L ERs, @ERd
2
2
2
2
2
MOV.L ERs, @(d:16, ERd) 3
2
MOV.L ERs, @(d:24, ERd) 5
2
MOV.L ERs, @–ERd
2
2
MOV.L ERs, @aa:16
3
2
MOV.L ERs, @aa:24
4
2
MOVFPE
MOVFPE @aa:16, Rd*1
2
1
MOVTPE
MOVTPE Rs, @aa:16*1
2
1
MULXS
MULXS.B Rs, Rd
2
12
MULXS.W Rs, ERd
2
20
MULXU.B Rs, Rd
1
12
MULXU.W Rs, ERd
1
20
NEG.B Rd
1
NEG.W Rd
1
MULXU
NEG
NOP
NEG.L ERd
1
NOP
1
Rev. 7.00 Sep 21, 2005 page 752 of 878
REJ09B0259-0700
2
Appendix A Instruction Set
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access
Access
Operation
I
J
K
L
M
N
Instruction Mnemonic
NOT
OR
ORC
POP
PUSH
ROTL
ROTR
ROTXL
ROTXR
RTE
RTS
SHAL
SHAR
NOT.B Rd
1
NOT.W Rd
1
NOT.L ERd
1
OR.B #xx:8, Rd
1
OR.B Rs, Rd
1
OR.W #xx:16, Rd
2
OR.W Rs, Rd
1
OR.L #xx:32, ERd
3
OR.L ERs, ERd
2
ORC #xx:8, CCR
1
POP.W Rn
1
1
2
POP.L ERn
2
2
2
PUSH.W Rn
1
1
2
PUSH.L ERn
2
2
2
ROTL.B Rd
1
ROTL.W Rd
1
ROTL.L ERd
1
ROTR.B Rd
1
ROTR.W Rd
1
ROTR.L ERd
1
ROTXL.B Rd
1
ROTXL.W Rd
1
ROTXL.L ERd
1
ROTXR.B Rd
1
ROTXR.W Rd
1
ROTXR.L ERd
1
RTE
2
RTS
2
2
Normal*1
2
1
2
Advanced
2
2
2
SHAL.B Rd
1
SHAL.W Rd
1
SHAL.L ERd
1
SHAR.B Rd
1
SHAR.W Rd
1
SHAR.L ERd
1
Rev. 7.00 Sep 21, 2005 page 753 of 878
REJ09B0259-0700
Appendix A Instruction Set
Instruction Mnemonic
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access
Access
Operation
I
J
K
L
M
N
SHLL
SHLL.B Rd
1
SHLL.W Rd
1
SHLR
SHLL.L ERd
1
SHLR.B Rd
1
SHLR.W Rd
1
SHLR.L ERd
1
SLEEP
SLEEP
1
STC
STC CCR, Rd
1
STC CCR, @ERd
2
1
STC CCR, @(d:16, ERd)
3
1
SUB
STC CCR, @(d:24, ERd)
5
1
STC CCR, @–ERd
2
1
STC CCR, @aa:16
3
1
STC CCR, @aa:24
4
1
SUB.B Rs, Rd
1
SUB.W #xx:16, Rd
2
SUB.W Rs, Rd
1
SUB.L #xx:32, ERd
3
2
SUB.L ERs, ERd
1
SUBS
SUBS #1/2/4, ERd
1
SUBX
SUBX #xx:8, Rd
1
SUBX Rs, Rd
1
TRAPA
TRAPA #x:2 Normal*1
2
1
2
4
2
2
2
4
XOR
XOR.B #xx:8, Rd
1
XOR.B Rs, Rd
1
XOR.W #xx:16, Rd
2
Advanced
XORC
XOR.W Rs, Rd
1
XOR.L #xx:32, ERd
3
XOR.L ERs, ERd
2
XORC #xx:8, CCR
1
Notes: 1. Not available in the H8/3048 Group.
2. n is the value set in register R4L or R4. The source and destination are accessed n + 1
times each.
Rev. 7.00 Sep 21, 2005 page 754 of 878
REJ09B0259-0700
Appendix B Internal I/O Register
Appendix B Internal I/O Register
Table B.1
Comparison of H8/3048 Group Internal I/O Register Specifications
Address
(Low)
H8/3048
ZTAT
H8/3048 Mask ROM Version,
H8/3047 Mask ROM Version,
H8/3045 Mask ROM Version,
H8/3044 Mask ROM Version
H8/3048F
H'FF40
—
—
FLMCR
H'FF41
—
—
—
H'FF42
—
—
EBR1
H'FF43
—
—
EBR2
H'FF47
—
—
—
H'FF48
—
—
RAMCR
Module
Flash memory
Note: A dash (“—”) indicates that access is prohibited. Normal operation is not guaranteed if
these addresses are accessed.
Rev. 7.00 Sep 21, 2005 page 755 of 878
REJ09B0259-0700
Appendix B Internal I/O Register
B.1
Addresses
Address Register
(low)
Name
Data
Bus
Width Bit 7
Bit Names
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
Name
H'1C
H'1D
H'1E
H'1F
H'20
MAR0AR
8
H'21
MAR0AE
8
H'22
MAR0AH
8
H'23
MAR0AL
8
H'24
ETCR0AH
8
H'25
ETCR0AL
8
H'26
IOAR0A
8
H'27
DTCR0A
8
H'28
MAR0BR
8
H'29
MAR0BE
8
H'2A
MAR0BH
8
H'2B
MAR0BL
8
H'2C
ETCR0BH
8
H'2D
ETCR0BL
8
H'2E
IOAR0B
8
H'2F
DTCR0B
8
DMAC
channel 0A
DTE
DTSZ
DTID
RPE
DTIE
DTS2
DTS1
DTS0
Short
address
mode
DTE
DTSZ
SAID
SAIDE
DTIE
DTS2A
DTS1A
DTS0A
Full
address
mode
DMAC
channel 0B
DTE
DTSZ
DTID
RPE
DTIE
DTS2
DTS1
DTS0
Short
address
mode
DTME
—
DAID
DAIDE
TMS
DTS2B
DTS1B
DTS0B
Full
address
mode
Rev. 7.00 Sep 21, 2005 page 756 of 878
REJ09B0259-0700
Appendix B Internal I/O Register
Address Register
(low)
Name
Data
Bus
Width Bit 7
H'30
MAR1AR
8
H'31
MAR1AE
8
H'32
MAR1AH
8
H'33
MAR1AL
8
H'34
ETCR1AH
8
H'35
ETCR1AL
8
H'36
IOAR1A
8
H'37
DTCR1A
8
H'38
MAR1BR
8
H'39
MAR1BE
8
H'3A
MAR1BH
8
H'3B
MAR1BL
8
H'3C
ETCR1BH
8
H'3D
ETCR1BL
8
H'3E
IOAR1B
8
H'3F
DTCR1B
8
Bit Names
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
Name
DMAC
channel 1A
DTE
DTSZ
DTID
RPE
DTIE
DTS2
DTS1
DTS0
Short
address
mode
DTE
DTSZ
SAID
SAIDE
DTIE
DTS2A
DTS1A
DTS0A
Full
address
mode
DMAC
channel 1B
DTE
DTSZ
DTID
RPE
DTIE
DTS2
DTS1
DTS0
Short
address
mode
DTME
—
DAID
DAIDE
TMS
DTS2B
DTS1B
DTS0B
Full
address
mode
E
P
Flash
memory
H'40
FLMCR
8
VPP
VPPE
—
—
EV
PV
H'41
—
—
—
—
—
—
—
—
—
—
H'42
EBR1
8
LB7
LB6
LB5
LB4
LB3
LB2
LB1
LB0
H'43
EBR2
8
SB7
SB6
SB5
SB4
SB3
SB2
SB1
SB0
H'44
—
—
—
—
—
—
—
—
—
—
H'45
—
—
—
—
—
—
—
—
—
—
H'46
—
—
—
—
—
—
—
—
—
—
H'47
—
—
—
—
—
—
—
—
—
—
H'48
RAMCR
8
FLER
—
—
—
RAMS
RAM2
RAM1
RAM0
H'49
—
—
—
—
—
—
—
—
—
—
H'4A
—
—
—
—
—
—
—
—
—
—
H'4B
—
—
—
—
—
—
—
—
—
—
H'4C
—
—
—
—
—
—
—
—
—
—
H'4D
—
—
—
—
—
—
—
—
—
—
Rev. 7.00 Sep 21, 2005 page 757 of 878
REJ09B0259-0700
Appendix B Internal I/O Register
Address Register
(low)
Name
Data
Bus
Width Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
H'4E
—
—
—
—
—
—
—
—
—
—
H'4F
—
—
—
—
—
—
—
—
—
—
H'50
—
—
—
—
—
—
—
—
—
—
H'51
—
—
—
—
—
—
—
—
—
—
H'52
—
—
—
—
—
—
—
—
—
—
H'53
—
—
—
—
—
—
—
—
—
—
H'54
—
—
—
—
—
—
—
—
—
—
H'55
—
—
—
—
—
—
—
—
—
—
H'56
—
—
—
—
—
—
—
—
—
—
H'57
—
—
—
—
—
—
—
—
—
—
H'58
—
—
—
—
—
—
—
—
—
—
H'59
—
—
—
—
—
—
—
—
—
—
H'5A
—
—
—
—
—
—
—
—
—
—
H'5B
—
—
—
—
—
—
—
—
—
—
H'5C
DASTCR
8
—
—
—
—
—
—
—
DASTE
D/A converter
H'5D
DIVCR
8
—
—
—
—
—
—
DIV1
DIV0
H'5E
MSTCR
8
PSTOP
—
MSTOP5 MSTOP4 MSTOP3 MSTOP2 MSTOP1 MSTOP0
System
control
H'5F
CSCR
8
CS7E
CS6E
CS5E
CS4E
—
—
—
—
Bus controller
H'60
TSTR
8
—
—
—
STR4
STR3
STR2
STR1
STR0
—
ITU
(all channels)
H'61
TSNC
8
H'62
TMDR
8
H'63
TFCR
8
—
Bit Names
—
—
SYNC4
SYNC3
SYNC2
SYNC1
SYNC0
MDF
FDIR
PWM4
PWM3
PWM2
PWM1
PWM0
—
CMD1
CMD0
BFB4
BFA4
BFB3
BFA3
H'64
TCR0
8
—
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
H'65
TIOR0
8
—
IOB2
IOB1
IOB0
—
IOA2
IOA1
IOA0
H'66
TIER0
8
—
—
—
—
—
OVIE
IMIEB
IMIEA
H'67
TSR0
8
—
—
—
—
—
OVF
IMFB
IMFA
H'68
TCNT0H
16
H'69
TCNT0L
H'6A
GRA0H
H'6B
GRA0L
H'6C
GRB0H
H'6D
GRB0L
Module
Name
ITU
channel 0
16
16
H'6E
TCR1
8
—
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
H'6F
TIOR1
8
—
IOB2
IOB1
IOB0
—
IOA2
IOA1
IOA0
Rev. 7.00 Sep 21, 2005 page 758 of 878
REJ09B0259-0700
ITU
channel 1
Appendix B Internal I/O Register
Address Register
(low)
Name
Data
Bus
Width Bit 7
Bit Names
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
Name
H'70
TIER1
8
—
—
—
—
—
OVIE
IMIEB
IMIEA
ITU channel 1
H'71
TSR1
8
—
—
—
—
—
OVF
IMFB
IMFA
H'72
TCNT1H
16
H'73
TCNT1L
H'74
GRA1H
H'75
GRA1L
H'76
GRB1H
H'77
GRB1L
16
16
H'78
TCR2
8
—
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
H'79
TIOR2
8
—
IOB2
IOB1
IOB0
—
IOA2
IOA1
IOA0
H'7A
TIER2
8
—
—
—
—
—
OVIE
IMIEB
IMIEA
H'7B
TSR2
8
—
—
—
—
—
OVF
IMFB
IMFA
H'7C
TCNT2H
16
H'7D
TCNT2L
H'7E
GRA2H
H'7F
GRA2L
H'80
GRB2H
H'81
GRB2L
H'82
TCR3
8
—
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
H'83
TIOR3
8
—
IOB2
IOB1
IOB0
—
IOA2
IOA1
IOA0
H'84
TIER3
8
—
—
—
—
—
OVIE
IMIEB
IMIEA
H'85
TSR3
8
—
—
—
—
—
OVF
IMFB
IMFA
H'86
TCNT3H
16
H'87
TCNT3L
H'88
GRA3H
H'89
GRA3L
H'8A
GRB3H
H'8B
GRB3L
H'8C
BRA3H
H'8D
BRA3L
H'8E
BRB3H
H'8F
BRB3L
ITU channel 2
16
16
ITU channel 3
16
16
16
16
Rev. 7.00 Sep 21, 2005 page 759 of 878
REJ09B0259-0700
Appendix B Internal I/O Register
Address Register
(low)
Name
Data
Bus
Width Bit 7
Bit Names
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
H'90
TOER
8
—
—
EXB4
EXA4
EB3
EB4
EA4
EA3
H'91
TOCR
8
—
—
—
XTGD
—
—
OLS4
OLS3
H'92
TCR4
8
—
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
H'93
TIOR4
8
—
IOB2
IOB1
IOB0
—
IOA2
IOA1
IOA0
H'94
TIER4
8
—
—
—
—
—
OVIE
IMIEB
IMIEA
H'95
TSR4
8
—
—
—
—
—
OVF
IMFB
IMFA
H'96
TCNT4H
16
H'97
TCNT4L
H'98
GRA4H
H'99
GRA4L
H'9A
GRB4H
H'9B
GRB4L
H'9C
BRA4H
H'9D
BRA4L
H'9E
BRB4H
H'9F
BRB4L
H'A0
TPMR
8
—
—
—
—
G3NOV
G2NOV
G1NOV
G0NOV
H'A1
TPCR
8
G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0
H'A2
NDERB
8
NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9
NDER8
16
16
NDERA
8
NDER7
NDER6
NDER5
NDER4
NDER3
NDER2
NDER1
NDER0
NDRB*1
8
NDR15
NDR14
NDR13
NDR12
NDR11
NDR10
NDR9
NDR8
8
NDR15
NDR14
NDR13
NDR12
—
—
—
—
8
NDR7
NDR6
NDR5
NDR4
NDR3
NDR2
NDR1
NDR0
8
NDR7
NDR6
NDR5
NDR4
—
—
—
—
8
—
—
—
—
—
—
—
—
8
—
—
—
—
NDR11
NDR10
NDR9
NDR8
8
—
—
—
—
—
—
—
—
8
—
—
—
—
NDR3
NDR2
NDR1
NDR0
OVF
WT/IT
TME
—
—
CKS2
CKS1
CKS0
H'A6
H'A7
NDRB*1
NDRA*1
ITU channel 4
16
H'A4
H'A5
ITU (all
channels)
16
H'A3
NDRA*1
Module
Name
H'A8
TCSR*2
8
H'A9
2
TCNT*
8
H'AA
—
—
—
—
—
—
—
—
—
H'AB
RSTCSR*3 8
WRST
RSTOE
—
—
—
—
—
—
H'AC
RFSHCR
8
SRFMD
PSRAME DRAME CAS/WE M9/M8
RFSHE
—
RCYCE
H'AD
RTMCSR
8
CMF
CMIE
—
—
—
H'AE
RTCNT
8
H'AF
RTCOR
8
CKS2
Rev. 7.00 Sep 21, 2005 page 760 of 878
REJ09B0259-0700
CKS1
CKS0
TPC
WDT
Refresh
controller
Appendix B Internal I/O Register
Address Register
(low)
Name
Data
Bus
Width Bit 7
H'B0
SMR
8
H'B1
BRR
8
Bit Names
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
Name
C/A GM CHR
PE
O/E
STOP
MP
CKS1
CKS0
SCI channel 0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
TDRE
RDRF
ORER
FER/
ERS
PER
TEND
MPB
MPBT
Bit 6
/
H'B2
SCR
8
H'B3
TDR
8
H'B4
SSR
8
H'B5
RDR
8
H'B6
SCMR
8
—
—
—
—
SDIR
SINV
—
SMIF
H'B8
SMR
8
C/A
CHR
PE
O/E
STOP
MP
CKS1
CKS0
H'B9
BRR
8
H'BA
SCR
8
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
H'BB
TDR
8
H'BC
SSR
8
TDRE
RDRF
ORER
FER
PER
TEND
MPB
MPBT
H'BD
RDR
8
H'BE
—
—
—
—
—
—
—
—
—
H'B7
SCI channel 1
H'BF
H'C0
P1DDR
8
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Port 1
H'C1
P2DDR
8
P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Port 2
H'C2
P1DR
8
P17
P16
P15
P14
P13
P12
P11
P10
Port 1
H'C3
P2DR
8
P27
P26
P25
P24
P23
P22
P21
P20
Port 2
H'C4
P3DDR
8
P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Port 3
H'C5
P4DDR
8
P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Port 4
H'C6
P3DR
8
P37
P36
P35
P34
P33
P32
P31
P30
Port 3
H'C7
P4DR
8
P47
P46
P45
P44
P43
P42
P41
P40
Port 4
H'C8
P5DDR
8
—
—
—
—
P53DDR P52DDR P51DDR P50DDR Port 5
H'C9
P6DDR
8
—
P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Port 6
H'CA
P5DR
8
—
—
—
—
P53
P52
P51
P50
Port 5
H'CB
P6DR
8
—
P66
P65
P64
P63
P62
P61
P60
Port 6
H'CC
—
—
—
—
—
—
—
—
—
H'CD
P8DDR
8
—
—
—
P84DDR P83DDR P82DDR P81DDR P80DDR Port 8
H'CE
P7DR
8
P77
P76
P75
P74
P73
P72
P71
P70
Port 7
H'CF
P8DR
8
—
—
—
P84
P83
P82
P81
P80
Port 8
Rev. 7.00 Sep 21, 2005 page 761 of 878
REJ09B0259-0700
Appendix B Internal I/O Register
Address Register
(low)
Name
Data
Bus
Width Bit 7
Bit Names
Bit 6
Bit 5
—
P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR Port 9
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
Name
H'D0
P9DDR
8
—
H'D1
PADDR
8
PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR Port A
H'D2
P9DR
8
—
—
P95
P94
P93
P92
P91
P90
Port 9
H'D3
PADR
8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Port A
H'D4
PBDDR
8
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Port B
H'D5
—
—
—
—
—
—
—
—
—
—
—
H'D6
PBDR
8
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Port B
H'D7
—
—
—
—
—
—
—
—
—
—
—
H'D8
P2PCR
P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR Port 2
H'D9
—
—
H'DA
P4PCR
8
P47PCR P46PCR P45PCR P44PCR P43PCR P42PCR P41PCR P40PCR Port 4
H'DB
P5PCR
8
—
H'DC
DADR0
8
H'DD
DADR1
8
H'DE
DACR
8
H'DF
—
H'E0
ADDRAH
H'E1
ADDRAL
H'E2
—
—
—
—
—
—
—
—
—
—
P53PCR P52PCR P51PCR P50PCR Port 5
D/A converter
DAOE1
DAOE0
DAE
—
—
—
—
—
—
—
—
—
—
—
—
—
8
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
8
AD1
AD0
—
—
—
—
—
—
ADDRBH
8
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
H'E3
ADDRBL
8
AD1
AD0
—
—
—
—
—
—
H'E4
ADDRCH
8
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
H'E5
ADDRCL
8
AD1
AD0
—
—
—
—
—
—
H'E6
ADDRDH
8
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
H'E7
ADDRDL
8
AD1
AD0
—
—
—
—
—
—
H'E8
ADCSR
8
ADF
ADIE
ADST
SCAN
CKS
CH2
CH1
CH0
H'E9
ADCR
8
TRGE
—
—
—
—
—
—
—
H'EA
—
—
—
—
—
—
—
—
—
H'EB
—
—
—
—
—
—
—
—
—
H'EC
ABWCR
ABW7
ABW6
ABW5
ABW4
ABW3
ABW2
ABW1
ABW0
8
H'ED
ASTCR
8
AST7
AST6
AST5
AST4
AST3
AST2
AST1
AST0
H'EE
WCR
8
—
—
—
—
WMS1
WMS0
WC1
WC0
H'EF
WCER
8
WCE7
WCE6
WCE5
WCE4
WCE3
WCE2
WCE1
WCE0
Rev. 7.00 Sep 21, 2005 page 762 of 878
REJ09B0259-0700
A/D converter
Bus controller
Appendix B Internal I/O Register
Address Register
(low)
Name
Data
Bus
Width Bit 7
Bit Names
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
Name
H'F0
—
—
—
—
—
—
—
—
—
H'F1
MDCR
8
—
—
—
—
—
MDS2
MDS1
MDS0
H'F2
SYSCR
8
SSBY
STS2
STS1
STS0
UE
NMIEG
—
RAME
H'F3
BRCR
8
A23E
A22E
A21E
—
—
—
—
BRLE
H'F4
ISCR
8
—
—
H'F5
IER
8
—
—
IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC Interrupt
controller
IRQ5E
IRQ4E
IRQ3E
IRQ2E
IRQ1E
IRQ0E
H'F6
ISR
8
—
—
IRQ5F
IRQ4F
IRQ3F
H'F7
—
—
—
—
—
—
—
—
—
H'F8
IPRA
8
IPRA7
IPRA6
IPRA5
IPRA4
IPRA3
IPRA2
IPRA1
IPRA0
H'F9
IPRB
8
IPRB7
IPRB6
IPRB5
—
IPRB3
IPRB2
IPRB1
—
H'FA
—
—
—
—
—
—
—
—
—
H'FB
—
—
—
—
—
—
—
—
—
H'FD
—
—
—
—
—
—
—
—
—
H'FE
—
—
—
—
—
—
—
—
—
H'FF
—
—
—
—
—
—
—
—
—
IRQ2F
IRQ1F
System
control
Bus controller
IRQ0F
H'FC
Notes: 1. The address depends on the output trigger setting.
2. For write access to TCSR and TCNT, see section 12.2.4, Notes on Register Access.
3. For write access to RSTCSR, see section 12.2.4, Notes on Register Access.
Legend
DMAC: DMA controller
ITU:
16-bit integrated timer unit
TPC: Programmable timing pattern controller
SCI:
Serial communication interface
WDT: Watchdog timer
Rev. 7.00 Sep 21, 2005 page 763 of 878
REJ09B0259-0700
Appendix B Internal I/O Register
B.2
Function
Register
acronym
Register
name
TSTR Timer Start Register
Address to which
the register is mapped
H'60
Name of on-chip
supporting
module
ITU (all channels)
Bit
numbers
Bit
Initial bit
values
7
6
5
4
3
2
1
0
—
—
—
STR4
STR3
STR2
STR1
STR0
Initial value
1
1
1
0
0
0
0
0
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
Names of the
bits. Dashes
(—) indicate
reserved bits.
Possible types of access
R
Read only
W
Write only
R/W Read and write
Counter start 0
0 TCNT0 is halted
1 TCNT0 is counting
Counter start 1
0 TCNT1 is halted
1 TCNT1 is counting
Full name
of bit
Counter start 2
0 TCNT2 is halted
1 TCNT2 is counting
Counter start 3
0 TCNT3 is halted
1 TCNT3 is counting
Counter start 4
0 TCNT4 is halted
1 TCNT4 is counting
Rev. 7.00 Sep 21, 2005 page 764 of 878
REJ09B0259-0700
Descriptions
of bit settings
Appendix B Internal I/O Register
MAR0A R/E/H/L—Memory Address Register 0A R/E/H/L
23
H'20, H'21,
H'22, H'23
22
21
Bit
31
30
29
28
27
26
25
24
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
—
—
—
—
— R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
Read/Write
15
14
13
12
11
19
18
17
16
Undetermined
MAR0AR
Bit
20
DMAC0
MAR0AE
10
Undetermined
9
8
7
6
5
4
3
2
1
0
Undetermined
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MAR0AH
MAR0AL
Source or destination address
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Appendix B Internal I/O Register
ETCR0A H/L—Execute Transfer Count Register 0A H/L
H'24, H'25
DMAC0
• Short address mode
I/O mode and idle mode
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
Undetermined
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Transfer counter
Repeat mode
Bit
7
6
5
R/W
R/W
R/W
Initial value
Read/Write
4
3
2
1
0
R/W
R/W
R/W
2
1
0
R/W
R/W
R/W
Undetermined
R/W
R/W
ETCR0AH
Transfer counter
Bit
7
6
5
Initial value
Read/Write
4
3
Undetermined
R/W
R/W
R/W
R/W
R/W
ETCR0AL
Initial count
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Appendix B Internal I/O Register
ETCR0A H/L—Execute Transfer Count Register 0A H/L
(cont)
H'24, H'25
DMAC0
• Full address mode
Normal mode
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
Undetermined
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Transfer counter
Block transfer mode
Bit
7
6
5
Initial value
Read/Write
4
3
2
1
0
R/W
R/W
R/W
2
1
0
R/W
R/W
R/W
Undetermined
R/W
R/W
R/W
R/W
R/W
ETCR0AH
Block size counter
Bit
7
6
5
Initial value
Read/Write
4
3
Undetermined
R/W
R/W
R/W
R/W
R/W
ETCR0AL
Initial block size
Rev. 7.00 Sep 21, 2005 page 767 of 878
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Appendix B Internal I/O Register
IOAR0A—I/O Address Register 0A
Bit
7
6
H'26
5
Initial value
Read/Write
4
3
DMAC0
2
1
0
R/W
R/W
R/W
Undetermined
R/W
R/W
R/W
R/W
R/W
Short address mode: source or destination address
Full address mode: not used
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Appendix B Internal I/O Register
DTCR0A—Data Transfer Control Register 0A
H'27
DMAC0
• Short address mode
Bit
7
6
5
4
3
2
1
0
DTE
DTSZ
DTID
RPE
DTIE
DTS2
DTS1
DTS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data transfer select
Bit 2 Bit 1 Bit 0
DTS2 DTS1 DTS0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Data Transfer Activation Source
Compare match/input capture A interrupt from ITU channel 0
Compare match/input capture A interrupt from ITU channel 1
Compare match/input capture A interrupt from ITU channel 2
Compare match/input capture A interrupt from ITU channel 3
SCI0 transmit-data-empty interrupt
SCI0 receive-data-full interrupt
Transfer in full address mode (channel A)
Transfer in full address mode (channel A)
Data transfer interrupt enable
0 Interrupt requested by DTE bit is disabled
1 Interrupt requested by DTE bit is enabled
Repeat enable
RPE
0
1
DTIE
0
1
0
1
Description
I/O mode
Repeat mode
Idle mode
Data transfer increment/decrement
0 Incremented: If DTSZ = 0, MAR is incremented by 1 after each transfer
If DTSZ = 1, MAR is incremented by 2 after each transfer
1 Decremented: If DTSZ = 0, MAR is decremented by 1 after each transfer
If DTSZ = 1, MAR is decremented by 2 after each transfer
Data transfer size
0 Byte-size transfer
1 Word-size transfer
Data transfer enable
0 Data transfer is disabled
1 Data transfer is enabled
Rev. 7.00 Sep 21, 2005 page 769 of 878
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Appendix B Internal I/O Register
DTCR0A—Data Transfer Control Register 0A (cont)
H'27
DMAC0
• Full address mode
Bit
7
6
5
4
3
2
1
0
DTE
DTSZ
SAID
SAIDE
DTIE
DTS2A
DTS1A
DTS0A
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data transfer select 0A
0 Normal mode
1 Block transfer mode
Data transfer select 2A and 1A
Set both bits to 1
Data transfer interrupt enable
0 Interrupt request by DTE bit is disabled
1 Interrupt request by DTE bit is enabled
Source address increment/decrement (bit 5)
Source address increment/decrement enable (bit 4)
Bit 5 Bit 4
SAID SAIDE Increment/Decrement Enable
0
0
MARA is held fixed
1
Incremented: If DTSZ = 0, MARA is incremented by 1 after each transfer
If DTSZ = 1, MARA is incremented by 2 after each transfer
1
0
MARA is held fixed
1
Decremented: If DTSZ = 0, MARA is decremented by 1 after each transfer
If DTSZ = 1, MARA is decremented by 2 after each transfer
Data transfer size
0 Byte-size transfer
1 Word-size transfer
Data transfer enable
0 Data transfer is disabled
1 Data transfer is enabled
Rev. 7.00 Sep 21, 2005 page 770 of 878
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Appendix B Internal I/O Register
MAR0B R/E/H/L—Memory Address Register 0B R/E/H/L
23
H'28, H'29,
H'2A, H'2B
22
21
Bit
31
30
29
28
27
26
25
24
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
—
—
—
—
— R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
Read/Write
15
14
13
12
11
19
18
17
16
Undetermined
MAR0BR
Bit
20
DMAC0
MAR0BE
10
Undetermined
9
8
7
6
5
4
3
2
1
0
Undetermined
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MAR0BH
MAR0BL
Source or destination address
Rev. 7.00 Sep 21, 2005 page 771 of 878
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Appendix B Internal I/O Register
ETCR0B H/L—Execute Transfer Count Register 0B H/L
H'2C, H'2D
DMAC0
• Short address mode
I/O mode and idle mode
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
Undetermined
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Not used
Repeat mode
Bit
7
6
5
R/W
R/W
R/W
Initial value
Read/Write
4
3
2
1
0
R/W
R/W
R/W
2
1
0
R/W
R/W
R/W
Undetermined
R/W
R/W
ETCR0BH
Transfer counter
Bit
7
6
5
Initial value
Read/Write
4
3
Undetermined
R/W
R/W
R/W
R/W
R/W
ETCR0BL
Initial count
Rev. 7.00 Sep 21, 2005 page 772 of 878
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Appendix B Internal I/O Register
ETCR0B H/L—Execute Transfer Count Register 0B H/L
(cont)
H'2C, H'2D
DMAC0
• Full address mode
Normal mode
Bit
15
14
13
12
11
10
9
8
7
5
6
4
3
2
1
0
Initial value
Undetermined
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Not used
Block transfer mode
Bit
15
14
13
12
11
10
9
8
7
5
6
4
3
2
1
0
Initial value
Undetermined
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Block transfer counter
IOAR0B—I/O Address Register 0B
Bit
7
6
H'2E
5
Initial value
Read/Write
4
3
DMAC0
2
1
0
R/W
R/W
R/W
Undetermined
R/W
R/W
R/W
R/W
R/W
Short address mode: source or destination address
Full address mode: not used
Rev. 7.00 Sep 21, 2005 page 773 of 878
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Appendix B Internal I/O Register
DTCR0B—Data Transfer Control Register 0B
H'2F
DMAC0
• Short address mode
Bit
7
6
5
4
3
2
1
0
DTE
DTSZ
DTID
RPE
DTIE
DTS2
DTS1
DTS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data transfer select
Bit 2 Bit 1 Bit 0
DTS2 DTS1 DTS0
0
0
0
1
1
0
1
1
0
0
1
0
1
1
Data Transfer Activation Source
Compare match/input capture A interrupt from ITU channel 0
Compare match/input capture A interrupt from ITU channel 1
Compare match/input capture A interrupt from ITU channel 2
Compare match/input capture A interrupt from ITU channel 3
SCI0 transmit-data-empty interrupt
SCI0 receive-data-full interrupt
Falling edge of DREQ input
Low level of DREQ input
Data transfer interrupt enable
0 Interrupt requested by DTE bit is disabled
1 Interrupt requested by DTE bit is enabled
An interrupt request is issued to the CPU when the DTE bit = 0
Repeat enable
RPE DTIE Description
0
0
I/O mode
1
0
1
Repeat mode
1
Idle mode
Data transfer increment/decrement
0 Incremented: If DTSZ = 0, MAR is incremented by 1 after each transfer
If DTSZ = 1, MAR is incremented by 2 after each transfer
1 Decremented: If DTSZ = 0, MAR is decremented by 1 after each transfer
If DTSZ = 1, MAR is decremented by 2 after each transfer
Data transfer size
0 Byte-size transfer
1 Word-size transfer
Data transfer enable
0 Data transfer is disabled
1 Data transfer is enabled
Rev. 7.00 Sep 21, 2005 page 774 of 878
REJ09B0259-0700
Appendix B Internal I/O Register
DTCR0B—Data Transfer Control Register 0B (cont)
H'2F
DMAC0
• Full address mode
Bit
7
6
5
4
3
2
1
0
DTME
—
DAID
DAIDE
TMS
DTS2B
DTS1B
DTS0B
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data transfer select 2B to 0B
Bit 2 Bit 1 Bit 0
Data Transfer Activation Source
DTS2B DTS1B DTS0B Normal Mode
Block Transfer Mode
0
0
0
Auto-request
Compare match/input capture
(burst mode)
A from ITU channel 0
Not available
Compare match/input capture
1
A from ITU channel 1
Compare match/input capture
Auto-request
1
0
A from ITU channel 2
(cycle-steal mode)
Compare match/input capture
Not available
1
A from ITU channel 3
Not available
Not available
1
0
0
Not available
Not available
1
Falling edge of DREQ
Falling edge of DREQ
1
0
1
Low level input at DREQ Not available
Transfer mode select
0 Destination is the block area in block transfer mode
1 Source is the block area in block transfer mode
Destination address increment/decrement (bit 5)
Destination address increment/decrement enable (bit 4)
Bit 5 Bit 4
DAID DAIDE Increment/Decrement Enable
0
0
MARB is held fixed
1
Incremented: If DTSZ = 0, MARB is incremented by 1 after each transfer
If DTSZ = 1, MARB is incremented by 2 after each transfer
1
0
MARB is held fixed
1
Decremented: If DTSZ = 0, MARB is decremented by 1 after each transfer
If DTSZ = 1, MARB is decremented by 2 after each transfer
Data transfer master enable
0 Data transfer is disabled
1 Data transfer is enabled
Rev. 7.00 Sep 21, 2005 page 775 of 878
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Appendix B Internal I/O Register
MAR1A R/E/H/L—Memory Address Register 1A R/E/H/L
Bit
31
30
29
28
27
26
25
24
23
H'30, H'31,
H'32, H'33
22
21
20
19
DMAC1
18
17
16
Undetermined
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
—
—
—
—
— R/W R/W R/W R/W R/W R/W R/W R/W
MAR1AR
Bit
Initial value
Read/Write
15
14
13
12
11
MAR1AE
10
9
Undetermined
8
7
6
5
4
3
2
1
0
Undetermined
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MAR1AH
Note: Bit functions are the same as for DMAC0.
Rev. 7.00 Sep 21, 2005 page 776 of 878
REJ09B0259-0700
MAR1AL
Appendix B Internal I/O Register
ETCR1A H/L—Execute Transfer Count Register 1A H/L
Bit
15
14
13
12
11
10
9
8
7
H'34, H'35
6
5
4
DMAC1
3
2
1
0
Initial value
Undetermined
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
7
6
5
Initial value
Read/Write
4
3
2
1
0
R/W
R/W
R/W
2
1
0
R/W
R/W
R/W
Undetermined
R/W
R/W
R/W
R/W
R/W
ETCR1AH
Bit
7
6
5
Initial value
Read/Write
4
3
Undetermined
R/W
R/W
R/W
R/W
R/W
ETCR1AL
Note: Bit functions are the same as for DMAC0.
IOAR1A—I/O Address Register 1A
Bit
H'36
7
6
5
R/W
R/W
R/W
Initial value
Read/Write
4
3
DMAC1
2
1
0
R/W
R/W
R/W
Undetermined
R/W
R/W
Note: Bit functions are the same as for DMAC0.
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Appendix B Internal I/O Register
DTCR1A—Data Transfer Control Register 1A
H'37
DMAC1
• Short address mode
Bit
7
6
5
4
3
2
1
0
DTE
DTSZ
DTID
RPE
DTIE
DTS2
DTS1
DTS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
• Full address mode
Bit
DTE
DTSZ
SAID
SAIDE
DTIE
DTS2A
DTS1A
DTS0A
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: Bit functions are the same as for DMAC0.
MAR1B R/E/H/L—Memory Address Register 1B R/E/H/L
23
H'38, H'39,
H'3A, H'3B
22
21
Bit
31
30
29
28
27
26
25
24
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
—
—
—
—
— R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
Read/Write
15
14
13
12
11
19
18
17
16
Undetermined
MAR1BR
Bit
20
DMAC1
MAR1BE
10
9
Undetermined
8
7
6
5
4
3
2
1
0
Undetermined
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MAR1BH
Note: Bit functions are the same as for DMAC0.
Rev. 7.00 Sep 21, 2005 page 778 of 878
REJ09B0259-0700
MAR1BL
Appendix B Internal I/O Register
ETCR1B H/L—Execute Transfer Count Register 1B H/L
Bit
15
14
13
12
11
10
9
8
7
H'3C, H'3D
6
5
4
DMAC1
3
2
1
0
Initial value
Undetermined
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
7
6
5
R/W
R/W
R/W
Initial value
Read/Write
4
3
2
1
0
R/W
R/W
R/W
2
1
0
R/W
R/W
R/W
Undetermined
R/W
R/W
ETCR1BH
Bit
7
6
5
Initial value
Read/Write
4
3
Undetermined
R/W
R/W
R/W
R/W
R/W
ETCR1BL
Note: Bit functions are the same as for DMAC0.
IOAR1B—I/O Address Register 1B
Bit
7
6
H'3E
5
Initial value
Read/Write
4
3
DMAC1
2
1
0
R/W
R/W
R/W
Undetermined
R/W
R/W
R/W
R/W
R/W
Note: Bit functions are the same as for DMAC0.
Rev. 7.00 Sep 21, 2005 page 779 of 878
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Appendix B Internal I/O Register
DTCR1B—Data Transfer Control Register 1B
H'3F
DMAC1
• Short address mode
Bit
7
6
5
4
3
2
1
0
DTE
DTSZ
DTID
RPE
DTIE
DTS2
DTS1
DTS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
• Full address mode
Bit
DTME
—
DAID
DAIDE
TMS
DTS2B
DTS1B
DTS0B
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: Bit functions are the same as for DMAC0.
Rev. 7.00 Sep 21, 2005 page 780 of 878
REJ09B0259-0700
Appendix B Internal I/O Register
FLMCR—Flash Memory Control Register
Bit
Initial value*
R/W
H'40
Flash memory
7
6
5
4
3
2
1
0
VPP
VPP E
—
—
EV
PV
E
P
0
0
0
0
0
0
0
0
—
R/W*
R/W*
R/W *
R/W *
R
R/W
—
Program mode
0 Exit from program mode
(Initial value)
1 Transition to program mode
Erase mode
0 Exit from erase mode
1 Transition to erase mode
(Initial value)
Program-verify mode
0 Exit from program-verify mode
1 Transition to program-verify mode
(Initial value)
Erase-verify mode
0 Exit from erase-verify mode
1 Transition to erase-verify mode
(Initial value)
VPP enable
0 VPP pin 12 V power supply is disabled
1 VPP pin 12 V power supply is enabled
Programming power
0 Cleared when 12 V is not applied to VPP
1 Set when 12 V is applied to VPP
(Initial value)
(Initial value)
Note: * The initial value is H'00 in modes 5, 6, and 7 (on-chip flash memory enabled). In modes
1, 2, 3, and 4 (on-chip flash memory disabled), this register cannot be modified and is
always read as H'FF.
H8/3048F
Include this register
H8/3048ZTAT
Not include this register
H8/3048 mask ROM version
H8/3047 mask ROM version
H8/3045 mask ROM version
H8/3044 mask ROM version
Rev. 7.00 Sep 21, 2005 page 781 of 878
REJ09B0259-0700
Appendix B Internal I/O Register
EBR1—Erase Block Register 1
Bit
Initial value*
R/W
H'42
Flash memory
7
6
5
4
3
2
1
0
LB7
LB6
LB5
LB4
LB3
LB2
LB1
LB0
0
0
0
0
0
0
0
0
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
Large block 7 to 0
0 Block LB7 to LB0 is not selected
1 Block LB7 to LB0 is selected
(Initial value)
Note: * The initial value is H'00 in modes 5, 6, and 7 (on-chip flash memory enabled). In modes
1, 2, 3, and 4 (on-chip flash memory disabled), this register cannot be modified and is
always read as H'FF.
H8/3048F
Include this register
H8/3048ZTAT
Not include this register
H8/3048 mask ROM version
H8/3047 mask ROM version
H8/3045 mask ROM version
H8/3044 mask ROM version
Rev. 7.00 Sep 21, 2005 page 782 of 878
REJ09B0259-0700
Appendix B Internal I/O Register
EBR2—Erase Block Register 2
Bit
Initial value*
R/W
H'43
Flash memory
7
6
5
4
3
2
1
0
SB7
SB6
SB5
SB4
SB3
SB2
SB1
SB0
0
0
0
0
0
0
0
0
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
Small block 7 to 0
0 Block SB7 to SB0 is not selected
1 Block SB7 to SB0 is selected
(Initial value)
Note: * The initial value is H'00 in modes 5, 6, and 7 (on-chip flash memory enabled). In modes
1, 2, 3, and 4 (on-chip flash memory disabled), this register cannot be modified and is
always read as H'FF.
H8/3048F
Include this register
H8/3048ZTAT
Not include this register
H8/3048 mask ROM version
H8/3047 mask ROM version
H8/3045 mask ROM version
H8/3044 mask ROM version
Rev. 7.00 Sep 21, 2005 page 783 of 878
REJ09B0259-0700
Appendix B Internal I/O Register
RAMCR—RAM Control Register
H'48
Flash memory
7
6
5
4
3
2
1
0
FLER
—
—
—
RAMS
RAM2
RAM1
RAM0
Initial value
0
1
1
1
0
0
0
0
R/W
R
—
—
—
R/W
R/W
R/W
R/W
Bit
RAM select, RAM 2 to RAM 0
Bit 3
Bit 1
Bit 0
Bit 2
RAMS RAM 2 RAM 1 RAM 0
1/0
0
1/0
1/0
1
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Flash memory error
0 Flash memory is not write/erase-protected
(is not in error protect mode)
1 Flash memory is write/erase-protected
(is in error protect mode)
H8/3048F
Include this register
H8/3048ZTAT
Not include this register
H8/3048 mask ROM version
H8/3047 mask ROM version
H8/3045 mask ROM version
H8/3044 mask ROM version
Rev. 7.00 Sep 21, 2005 page 784 of 878
REJ09B0259-0700
RAM Area
H'FFF000 to H'FFF1FF
H'01F000 to H'01F1FF
H'01F200 to H'01F3FF
H'01F400 to H'01F5FF
H'01F600 to H'01F7FF
H'01F800 to H'01F9FF
H'01FA00 to H'01FBFF
H'01FC00 to H'01FDFF
H'01FE00 to H'01FFFF
(Initial value)
Appendix B Internal I/O Register
DASTCR—D/A Standby Control Register
Bit
H'5C
System control
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
DASTE
Initial value
1
1
1
1
1
1
1
0
Read/Write
—
—
—
—
—
—
—
R/W
D/A standby enable
0 D/A output is disabled in software standby mode
1 D/A output is enabled in software standby mode
DIVCR—Division Control Register
H'5D
System control
7
6
5
7
3
2
1
0
—
—
—
—
—
—
DIV1
DIV0
Initial value
1
1
1
1
1
1
0
0
Read/Write
—
—
—
—
—
—
R/W
R/W
Bit
Divide 1 and 0
Bit 1 Bit 0
DIV1 DIV0
0
0
1
0
1
1
Frequency
Division Ratio
1/1
1/2
1/4
1/8
Rev. 7.00 Sep 21, 2005 page 785 of 878
REJ09B0259-0700
Appendix B Internal I/O Register
MSTCR—Module Standby Control Register
Bit
7
6
H'5E
4
5
3
2
System control
1
0
MSTOP5 MSTOP4 MSTOP3 MSTOP2 MSTOP1 MSTOP0
PSTOP
—
Initial value
0
1
0
0
0
0
0
0
Read/Write
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
Module standby 0
0 A/D converter operates normally
(Initial value)
1 A/D converter is in standby state
Module standby 1
0 Refresh controller operates normally
1 Refresh controller is in standby state
Module standby 2
0 DMAC operates normally
1 DMAC is in standby state
Module standby 3
0 SCI1 operates normally
1 SCI1 is in standby state
Module standby 4
0 SCI0 operates normally
1 SCI0 is in standby state
0 ITU operates normally
1 ITU is in standby state
(Initial value)
ø clock stop
0 ø clock output is enabled (Initial value)
1 ø clock output is disabled
Rev. 7.00 Sep 21, 2005 page 786 of 878
REJ09B0259-0700
(Initial value)
(Initial value)
Module standby 5
(Initial value)
(Initial value)
Appendix B Internal I/O Register
CSCR—Chip Select Control Register
Bit
H'5F
System control
7
6
5
4
3
2
1
0
CS7E
CS6E
CS5E
CS4E
—
—
—
—
Initial value
0
0
0
0
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
—
—
—
—
Chip select 7 to 4 enable
Bit n
CSnE Description
0
Output of chip select signal CSn is disabled
1
Output of chip select signal CSn is enabled
(Initial value)
(n = 7 to 4)
TSTR—Timer Start Register
Bit
H'60
ITU (all channels)
7
6
5
4
3
2
1
0
—
—
—
STR4
STR3
STR2
STR1
STR0
Initial value
1
1
1
0
0
0
0
0
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
Counter start 0
0 TCNT0 is halted
1 TCNT0 is counting
Counter start 1
0 TCNT1 is halted
1 TCNT1 is counting
Counter start 2
0 TCNT2 is halted
1 TCNT2 is counting
Counter start 3
0 TCNT3 is halted
1 TCNT3 is counting
Counter start 4
0 TCNT4 is halted
1 TCNT4 is counting
Rev. 7.00 Sep 21, 2005 page 787 of 878
REJ09B0259-0700
Appendix B Internal I/O Register
TSNC—Timer Synchro Register
Bit
H'61
ITU (all channels)
7
6
5
4
3
2
1
0
—
—
—
SYNC4
SYNC3
SYNC2
SYNC1
SYNC0
Initial value
1
1
1
0
0
0
0
0
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
Timer sync 0
0 TCNT0 operates independently
1 TCNT0 is synchronized
Timer sync 1
0 TCNT1 operates independently
1 TCNT1 is synchronized
Timer sync 2
0 TCNT2 operates independently
1 TCNT2 is synchronized
Timer sync 3
0 TCNT3 operates independently
1 TCNT3 is synchronized
Timer sync 4
0 TCNT4 operates independently
1 TCNT4 is synchronized
Rev. 7.00 Sep 21, 2005 page 788 of 878
REJ09B0259-0700
Appendix B Internal I/O Register
TMDR—Timer Mode Register
Bit
H'62
ITU (all channels)
7
6
5
4
3
2
1
0
—
MDF
FDIR
PWM4
PWM3
PWM2
PWM1
PWM0
Initial value
1
0
0
0
0
0
0
0
Read/Write
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PWM mode 0
0 Channel 0 operates normally
1 Channel 0 operates in PWM mode
PWM mode 1
0 Channel 1 operates normally
1 Channel 1 operates in PWM mode
PWM mode 2
0 Channel 2 operates normally
1 Channel 2 operates in PWM mode
PWM mode 3
0 Channel 3 operates normally
1 Channel 3 operates in PWM mode
PWM mode 4
0 Channel 4 operates normally
1 Channel 4 operates in PWM mode
Flag direction
0 OVF is set to 1 in TSR2 when TCNT2 overflows or underflows
1 OVF is set to 1 in TSR2 when TCNT2 overflows
Phase counting mode flag
0 Channel 2 operates normally
1 Channel 2 operates in phase counting mode
Rev. 7.00 Sep 21, 2005 page 789 of 878
REJ09B0259-0700
Appendix B Internal I/O Register
TFCR—Timer Function Control Register
Bit
H'63
ITU (all channels)
7
6
5
4
3
2
1
0
—
—
CMD1
CMD0
BFB4
BFA4
BFB3
BFA3
Initial value
1
1
0
0
0
0
0
0
Read/Write
—
—
R/W
R/W
R/W
R/W
R/W
R/W
Buffer mode A3
0 GRA3 operates normally
1 GRA3 is buffered by BRA3
Buffer mode B3
0 GRB3 operates normally
1 GRB3 is buffered by BRB3
Buffer mode A4
0 GRA4 operates normally
1 GRA4 is buffered by BRA4
Buffer mode B4
0 GRB4 operates normally
1 GRB4 is buffered by BRB4
Combination mode 1 and 0
Bit 5 Bit 4
CMD1 CMD0 Operating Mode of Channels 3 and 4
0
0
Channels 3 and 4 operate normally
1
0
1
Channels 3 and 4 operate together in complementary PWM mode
1
Channels 3 and 4 operate together in reset-synchronized PWM mode
Rev. 7.00 Sep 21, 2005 page 790 of 878
REJ09B0259-0700
Appendix B Internal I/O Register
TCR0—Timer Control Register 0
Bit
H'64
7
6
5
4
3
ITU0
2
1
0
—
CCLR1
CCLR0
TPSC2
TPSC1
TPSC0
Initial value
1
0
0
0
0
0
0
0
Read/Write
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CKEG1 CKEG0
Timer prescaler 2 to 0
Bit 0
Bit 2
Bit 1
TPSC2 TPSC1 TPSC0
0
0
0
1
0
1
1
0
0
1
1
0
1
1
TCNT Clock Source
Internal clock: φ
Internal clock: φ/2
Internal clock: φ/4
Internal clock: φ/8
External clock A: TCLKA input
External clock B: TCLKB input
External clock C: TCLKC input
External clock D: TCLKD input
Clock edge 1 and 0
Bit 4 Bit 3
CKEG1 CKEG0
0
0
1
1
—
Counted Edges of External Clock
Rising edges counted
Falling edges counted
Both edges counted
Counter clear 1 and 0
Bit 6
Bit 5
CCLR1 CCLR0 TCNT Clear Source
0
0
TCNT is not cleared
1
TCNT is cleared by GRA compare match or input capture
1
0
TCNT is cleared by GRB compare match or input capture
1
Synchronous clear: TCNT is cleared in synchronization
with other synchronized timers
Rev. 7.00 Sep 21, 2005 page 791 of 878
REJ09B0259-0700
Appendix B Internal I/O Register
TIOR0—Timer I/O Control Register 0
Bit
H'65
ITU0
7
6
5
4
3
2
1
0
—
IOB2
IOB1
IOB0
—
IOA2
IOA1
IOA0
Initial value
1
0
0
0
1
0
0
0
Read/Write
—
R/W
R/W
R/W
—
R/W
R/W
R/W
I/O control A2 to A0
Bit 2 Bit 1 Bit 0
IOA2 IOA1 IOA0
0
0
0
1
0
1
1
0
1
0
1
0
1
1
I/O control B2 to B0
Bit 6 Bit 5 Bit 4
IOB2 IOB1 IOB0
0
0
0
1
0
1
1
0
1
0
1
0
1
1
GRA Function
GRA is an output
compare register
GRA is an input
capture register
GRB Function
GRB is an output
compare register
GRB is an input
capture register
Rev. 7.00 Sep 21, 2005 page 792 of 878
REJ09B0259-0700
No output at compare match
0 output at GRA compare match
1 output at GRA compare match
Output toggles at GRA compare match
GRA captures rising edge of input
GRA captures falling edge of input
GRA captures both edges of input
No output at compare match
0 output at GRB compare match
1 output at GRB compare match
Output toggles at GRB compare match
GRB captures rising edge of input
GRB captures falling edge of input
GRB captures both edges of input
Appendix B Internal I/O Register
TIER0—Timer Interrupt Enable Register 0
Bit
H'66
ITU0
7
6
5
4
3
2
1
0
—
—
—
—
—
OVIE
IMIEB
IMIEA
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
R/W
R/W
R/W
Input capture/compare match interrupt enable A
0 IMIA interrupt requested by IMFA flag is disabled
1 IMIA interrupt requested by IMFA flag is enabled
Input capture/compare match interrupt enable B
0 IMIB interrupt requested by IMFB flag is disabled
1 IMIB interrupt requested by IMFB flag is enabled
Overflow interrupt enable
0 OVI interrupt requested by OVF flag is disabled
1 OVI interrupt requested by OVF flag is enabled
Rev. 7.00 Sep 21, 2005 page 793 of 878
REJ09B0259-0700
Appendix B Internal I/O Register
TSR0—Timer Status Register 0
Bit
H'67
ITU0
7
6
5
4
3
2
1
0
—
—
—
—
—
OVF
IMFB
IMFA
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
R/(W)*
R/(W)*
R/(W)*
Input capture/compare match flag A
0 [Clearing condition]
Read IMFA when IMFA = 1, then write 0 in IMFA
1 [Setting conditions]
TCNT = GRA when GRA functions as an output compare
register.
TCNT value is transferred to GRA by an input capture
signal, when GRA functions as an input capture register.
Input capture/compare match flag B
0 [Clearing condition]
Read IMFB when IMFB = 1, then write 0 in IMFB
1 [Setting conditions]
TCNT = GRB when GRB functions as an output compare
register.
TCNT value is transferred to GRB by an input capture
signal, when GRB functions as an input capture register.
Overflow flag
0 [Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
1 [Setting condition]
TCNT overflowed from H'FFFF to H'0000 or
underflowed from H'0000 to H'FFFF
Note: * Only 0 can be written, to clear the flag.
Rev. 7.00 Sep 21, 2005 page 794 of 878
REJ09B0259-0700
Appendix B Internal I/O Register
TCNT0 H/L—Timer Counter 0 H/L
H'68, H'69
ITU0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Up-counter
GRA0 H/L—General Register A0 H/L
H'6A, H'6B
ITU0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Output compare or input capture register
GRB0 H/L—General Register B0 H/L
Bit
Initial value
Read/Write
H'6C, H'6D
ITU0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Output compare or input capture register
TCR1—Timer Control Register 1
Bit
H'6E
ITU1
7
6
5
4
3
2
1
0
—
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
Initial value
1
0
0
0
0
0
0
0
Read/Write
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: Bit functions are the same as for ITU0.
Rev. 7.00 Sep 21, 2005 page 795 of 878
REJ09B0259-0700
Appendix B Internal I/O Register
TIOR1—Timer I/O Control Register 1
Bit
H'6F
ITU1
7
6
5
4
3
2
1
0
—
IOB2
IOB1
IOB0
—
IOA2
IOA1
IOA0
Initial value
1
0
0
0
1
0
0
0
Read/Write
—
R/W
R/W
R/W
—
R/W
R/W
R/W
Note: Bit functions are the same as for ITU0.
TIER1—Timer Interrupt Enable Register 1
Bit
H'70
ITU1
7
6
5
4
3
2
1
0
—
—
—
—
—
OVIE
IMIEB
IMIEA
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
R/W
R/W
R/W
Note: Bit functions are the same as for ITU0.
TSR1—Timer Status Register 1
Bit
H'71
ITU1
7
6
5
4
3
2
1
0
—
—
—
—
—
OVF
IMFB
IMFA
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
R/(W)*
R/(W)*
R/(W)*
Notes: Bit functions are the same as for ITU0.
* Only 0 can be written, to clear the flag.
TCNT1 H/L—Timer Counter 1 H/L
Bit
Initial value
Read/Write
H'72, H'73
ITU1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for ITU0.
Rev. 7.00 Sep 21, 2005 page 796 of 878
REJ09B0259-0700
Appendix B Internal I/O Register
GRA1 H/L—General Register A1 H/L
H'74, H'75
ITU1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for ITU0.
GRB1 H/L—General Register B1 H/L
H'76, H'77
ITU1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for ITU0.
TCR2—Timer Control Register 2
Bit
H'78
ITU2
7
6
5
4
3
2
1
0
—
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
Initial value
1
0
0
0
0
0
0
0
Read/Write
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Notes: 1. Bit functions are the same as for ITU0.
2. When channel 2 is used in phase counting mode, the counter clock source selection by
bits TPSC2 to TPSC0 is ignored.
Rev. 7.00 Sep 21, 2005 page 797 of 878
REJ09B0259-0700
Appendix B Internal I/O Register
TIOR2—Timer I/O Control Register 2
Bit
H'79
ITU2
7
6
5
4
3
2
1
0
—
IOB2
IOB1
IOB0
—
IOA2
IOA1
IOA0
Initial value
1
0
0
0
1
0
0
0
Read/Write
—
R/W
R/W
R/W
—
R/W
R/W
R/W
Note: Bit functions are the same as for ITU0.
TIER2—Timer Interrupt Enable Register 2
Bit
H'7A
ITU2
7
6
5
4
3
2
1
0
—
—
—
—
—
OVIE
IMIEB
IMIEA
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
R/W
R/W
R/W
Note: Bit functions are the same as for ITU0.
TSR2—Timer Status Register 2
Bit
H'7B
ITU2
7
6
5
4
3
2
1
0
—
—
—
—
—
OVF
IMFB
IMFA
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
R/(W)*
R/(W)*
R/(W)*
Notes: Bit functions are the same as for ITU0.
* Only 0 can be written, to clear the flag.
The function is the same as ITU0.
Overflow flag
0
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF.
[Setting condition]
1
The TCNT value overflows (from H'FFFF to H'0000)
or underflows (from H'0000 to H'FFFF)
Rev. 7.00 Sep 21, 2005 page 798 of 878
REJ09B0259-0700
Appendix B Internal I/O Register
TCNT2 H/L—Timer Counter 2 H/L
H'7C, H'7D
ITU2
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Phase counting mode: up/down counter
Other modes:
up-counter
GRA2 H/L—General Register A2 H/L
H'7E, H'7F
ITU2
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for ITU0.
GRB2 H/L—General Register B2 H/L
H'80, H'81
ITU2
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for ITU0.
Rev. 7.00 Sep 21, 2005 page 799 of 878
REJ09B0259-0700
Appendix B Internal I/O Register
TCR3—Timer Control Register 3
Bit
H'82
ITU3
7
6
5
4
3
2
1
0
—
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
Initial value
1
0
0
0
0
0
0
0
Read/Write
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: Bit functions are the same as for ITU0.
TIOR3—Timer I/O Control Register 3
Bit
H'83
ITU3
7
6
5
4
3
2
1
0
—
IOB2
IOB1
IOB0
—
IOA2
IOA1
IOA0
Initial value
1
0
0
0
1
0
0
0
Read/Write
—
R/W
R/W
R/W
—
R/W
R/W
R/W
Note: Bit functions are the same as for ITU0.
TIER3—Timer Interrupt Enable Register 3
Bit
H'84
ITU3
7
6
5
4
3
2
1
0
—
—
—
—
—
OVIE
IMIEB
IMIEA
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
R/W
R/W
R/W
Note: Bit functions are the same as for ITU0.
Rev. 7.00 Sep 21, 2005 page 800 of 878
REJ09B0259-0700
Appendix B Internal I/O Register
TSR3—Timer Status Register 3
Bit
H'85
ITU3
7
6
5
4
3
2
1
0
—
—
—
—
—
OVF
IMFB
IMFA
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
R/(W)*
R/(W)*
R/(W)*
Bit functions are the
same as for ITU0
Overflow flag
0 [Clearing condition]
Read OVF when OVF = 1, then write 1 in OVF
1 [Setting condition]
TCNT overflowed from H'FFFF to H'0000 or underflowed from
H'0000 to H'FFFF
Note: * Only 0 can be written, to clear the flag.
TCNT3 H/L—Timer Counter 3 H/L
Bit
Initial value
Read/Write
H'86, H'87
ITU3
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Complementary PWM mode: up/down counter
Other modes:
up-counter
GRA3 H/L—General Register A3 H/L
H'88, H'89
ITU3
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Output compare or input capture register (can be buffered)
Rev. 7.00 Sep 21, 2005 page 801 of 878
REJ09B0259-0700
Appendix B Internal I/O Register
GRB3 H/L—General Register B3 H/L
H'8A, H'8B
ITU3
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Output compare or input capture register (can be buffered)
BRA3 H/L—Buffer Register A3 H/L
H'8C, H'8D
ITU3
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Used to buffer GRA
BRB3 H/L—Buffer Register B3 H/L
Bit
Initial value
Read/Write
H'8E, H'8F
ITU3
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Used to buffer GRB
Rev. 7.00 Sep 21, 2005 page 802 of 878
REJ09B0259-0700
Appendix B Internal I/O Register
TOER—Timer Output Enable Register
Bit
H'90
ITU (all channels)
7
6
5
4
3
2
1
0
—
—
EXB4
EXA4
EB3
EB4
EA4
EA3
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
R/W
R/W
R/W
R/W
R/W
R/W
Master enable TIOCA3
0 TIOCA 3 output is disabled regardless of TIOR3, TMDR, and TFCR settings
1 TIOCA 3 is enabled for output according to TIOR3, TMDR, and TFCR settings
Master enable TIOCA4
0 TIOCA 4 output is disabled regardless of TIOR4, TMDR, and TFCR settings
1 TIOCA 4 is enabled for output according to TIOR4, TMDR, and TFCR settings
Master enable TIOCB4
0 TIOCB4 output is disabled regardless of TIOR4 and TFCR settings
1 TIOCB4 is enabled for output according to TIOR4 and TFCR settings
Master enable TIOCB3
0 TIOCB 3 output is disabled regardless of TIOR3 and TFCR settings
1 TIOCB 3 is enabled for output according to TIOR3 and TFCR settings
Master enable TOCXA4
0 TOCXA 4 output is disabled regardless of TFCR settings
1 TOCXA 4 is enabled for output according to TFCR settings
Master enable TOCXB4
0 TOCXB4 output is disabled regardless of TFCR settings
1 TOCXB4 is enabled for output according to TFCR settings
Rev. 7.00 Sep 21, 2005 page 803 of 878
REJ09B0259-0700
Appendix B Internal I/O Register
TOCR—Timer Output Control Register
Bit
H'91
ITU (all channels)
7
6
5
4
3
2
1
0
—
—
—
XTGD
—
—
OLS4
OLS3
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
R/W
—
—
R/W
R/W
Output level select 3
0 TIOCB 3 , TOCXA 4 , and TOCXB 4 outputs are inverted
1 TIOCB 3 , TOCXA 4 , and TOCXB 4 outputs are not inverted
Output level select 4
0 TIOCA 3 , TIOCA 4, and TIOCB4 outputs are inverted
1 TIOCA 3 , TIOCA 4, and TIOCB4 outputs are not inverted
External trigger disable
0 Input capture A in channel 1 is used as an external trigger signal in
reset-synchronized PWM mode and complementary PWM mode *
1 External triggering is disabled
Note: * When an external trigger occurs, bits 5 to 0 in TOER are cleared to 0, disabling ITU
output.
Rev. 7.00 Sep 21, 2005 page 804 of 878
REJ09B0259-0700
Appendix B Internal I/O Register
TCR4—Timer Control Register 4
Bit
H'92
ITU4
7
6
5
4
3
2
1
0
—
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
Initial value
1
0
0
0
0
0
0
0
Read/Write
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: Bit functions are the same as for ITU0.
TIOR4—Timer I/O Control Register 4
Bit
H'93
ITU4
7
6
5
4
3
2
1
0
—
IOB2
IOB1
IOB0
—
IOA2
IOA1
IOA0
Initial value
1
0
0
0
1
0
0
0
Read/Write
—
R/W
R/W
R/W
—
R/W
R/W
R/W
Note: Bit functions are the same as for ITU0.
TIER4—Timer Interrupt Enable Register 4
Bit
H'94
ITU4
7
6
5
4
3
2
1
0
—
—
—
—
—
OVIE
IMIEB
IMIEA
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
R/W
R/W
R/W
Note: Bit functions are the same as for ITU0.
TSR4—Timer Status Register 4
Bit
H'95
ITU4
7
6
5
4
3
2
1
0
—
—
—
—
—
OVF
IMFB
IMFA
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
R/(W)*
R/(W)*
R/(W)*
Notes: Bit functions are the same as for ITU0.
* Only 0 can be written, to clear the flag.
Rev. 7.00 Sep 21, 2005 page 805 of 878
REJ09B0259-0700
Appendix B Internal I/O Register
TCNT4 H/L—Timer Counter 4 H/L
H'96, H'97
ITU4
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for ITU3.
GRA4 H/L—General Register A4 H/L
H'98, H'99
ITU4
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for ITU3.
GRB4 H/L—General Register B4 H/L
H'9A, H'9B
ITU4
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for ITU3.
BRA4 H/L—Buffer Register A4 H/L
H'9C, H'9D
ITU4
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for ITU3.
Rev. 7.00 Sep 21, 2005 page 806 of 878
REJ09B0259-0700
Appendix B Internal I/O Register
BRB4 H/L—Buffer Register B4 H/L
H'9E, H'9F
ITU4
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for ITU3.
TPMR—TPC Output Mode Register
Bit
H'A0
TPC
7
6
5
4
—
—
—
—
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
3
2
G3NOV G2NOV
0
1
G1NOV G0NOV
Group 0 non-overlap
0 Normal TPC output in group 0
Output values change at compare match A in the selected ITU channel
1 Non-overlapping TPC output in group 0, controlled by compare match
A and B in the selected ITU channel
Group 1 non-overlap
0 Normal TPC output in group 1
Output values change at compare match A in the selected ITU channel
1 Non-overlapping TPC output in group 1, controlled by compare match
A and B in the selected ITU channel
Group 2 non-overlap
0 Normal TPC output in group 2
Output values change at compare match A in the selected ITU channel
1 Non-overlapping TPC output in group 2, controlled by compare match
A and B in the selected ITU channel
Group 3 non-overlap
0 Normal TPC output in group 3
Output values change at compare match A in the selected ITU channel
1 Non-overlapping TPC output in group 3, controlled by compare match
A and B in the selected ITU channel
Rev. 7.00 Sep 21, 2005 page 807 of 878
REJ09B0259-0700
Appendix B Internal I/O Register
TPCR—TPC Output Control Register
Bit
7
6
H'A1
5
4
3
2
TPC
1
0
G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Group 0 compare match select 1 and 0
Bit 1
Bit 0
G0CMS1 G0CMS0
0
0
1
1
0
1
ITU Channel Selected as Output Trigger
TPC output group 0 (TP3 to TP0) is triggered by compare match in ITU channel 0
TPC output group 0 (TP3 to TP0) is triggered by compare match in ITU channel 1
TPC output group 0 (TP3 to TP0) is triggered by compare match in ITU channel 2
TPC output group 0 (TP3 to TP0) is triggered by compare match in ITU channel 3
Group 1 compare match select 1 and 0
Bit 3
Bit 2
G1CMS1 G1CMS0
0
0
1
1
0
1
ITU Channel Selected as Output Trigger
TPC output group 1 (TP7 to TP4 ) is triggered by compare match in ITU channel 0
TPC output group 1 (TP7 to TP4 ) is triggered by compare match in ITU channel 1
TPC output group 1 (TP7 to TP4 ) is triggered by compare match in ITU channel 2
TPC output group 1 (TP7 to TP4 ) is triggered by compare match in ITU channel 3
Group 2 compare match select 1 and 0
Bit 5
Bit 4
G2CMS1 G2CMS0
0
0
1
1
0
1
ITU Channel Select