ICX063AL Diagonal 11mm (Type 2/3) CCD Image Sensor for CCIR B/W Video Camera Description The ICX063AL is an interline CCD solid-state image sensor suitable for CCIR black-and-white video cameras with a diagonal 11mm (Type 2/3) system. High sensitivity is achieved by adopting HAD (Hole-Accumulation Diode) sensors. The chip features a field period readout system and an electronic shutter with variable charge-storage time. 20 pin DIP (Ceramic) AAAAA AAAAA AAAAA AAAAA AAAAA Features • High resolution • Low smear • High sensitivity, low dark current • Excellent antiblooming characteristics • Continuous variable-speed shutter Pin 1 2 V 10 3 Device Structure 55 H Pin 11 • Image size: Diagonal 11mm (Type 2/3) • Number of effective pixels: 980 (H) × 582 (V), approx. 570K pixels Optical black position • Total number of pixels: 1038 (H) × 594 (V), approx. 620K pixels (Top View) • Interline CCD image sensor • Chip size: 10.75mm (H) × 8.7mm (V) • Unit cell size: 9.4µm (H) × 11.4µm (V) • Optical black: Horizontal (H) direction; front 3 pixels, rear 55 pixels Vertical (V) direction; front 10 pixels, rear 2 pixels • Number of dummy bits: Horizontal 25 Vertical 1 (even fields only) • Substrate material: Silicon Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E95633D99 ICX063AL Block Diagram and Pin Configuration (Top View) Vertical Register (Note) VL 7 Output Unit VDD 10 VOUT 11 VGG 12 VSS 13 1 Vφ4 2 Vφ3 3 Vφ2 4 SUB 5 GND 6 Vφ1 Horizontal Register GND 14 15 16 17 18 RD RG VL Hφ1 Hφ2 (Note) 19 20 HIS : Photo sensor Pin Description Pin No. Symbol Description Pin No. Symbol Description 1 Vφ4 Vertical register transfer clock 11 VOUT Signal output 2 Vφ3 Vertical register transfer clock 12 VGG Output amplifier gate bias 3 Vφ2 Vertical register transfer clock 13 VSS Output amplifier source 4 SUB Substrate (overflow drain) 14 GND GND 5 GND GND 15 RD Reset drain 6 Vφ1 Vertical register transfer clock 16 RG Reset gate clock 7 VL Protective transistor bias 17 VL Protective transistor bias 8 NC 18 Hφ1 Horizontal register transfer clock 9 NC 19 Hφ2 Horizontal register transfer clock 10 VDD 20 HIS Horizontal register input source bias Output amplifier drain power –2– ICX063AL Absolute Maximum Ratings Item Ratings Unit –0.3 to +55 V HIS, VDD, RD, VOUT, VSS – GND –0.3 to +20 V HIS, VDD, RD, VOUT, VSS – SUB –55 to +10 V –15 to +20 V –65 to +10 V Voltage difference between vertical clock input pins to +15 V Voltage difference between horizontal clock input pins to +17 V Hφ1, Hφ2 – Vφ4 –17 to +17 V RG, VGG – GND –10 to +15 V RG, VGG – SUB –55 to +10 V VL – SUB –65 to +0.3 V Vφ1, Vφ2, Vφ3, Vφ4, Hφ1, Hφ2, HIS, VDD, RD, VOUT, VSS, RG, VGG – VL –0.3 to +30 V Storage temperature –30 to +80 °C Operating temperature –10 to +60 °C Substrate voltage SUB – GND Supply voltage Vertical, horizontal Vφ1, Vφ2, Vφ3, Vφ4, Hφ1, Hφ2 – GND clock input voltage Vφ1, Vφ2, Vφ3, Vφ4, Hφ1, Hφ2 – SUB Remarks ∗1 ∗1 +27V (max.) when clock width < 10µs and the clock duty factor < 0.1%. Bias Conditions Item Symbol Min. Typ. Max. Unit Output amplifier drain voltage VDD 14.7 15.0 15.3 V Reset drain voltage VRD 14.7 15.0 15.3 V Output amplifier gate voltage VGG 1.6 2.0 2.6 V Output amplifier source VSS Substrate voltage adjustment range VSUB 9 19 V Substrate voltage adjustment accuracy ∆VSUB –3 +3 % Reset gate clock voltage adjustment range VRGL 0 3.0 V Reset gate clock voltage adjustment accuracy ∆VRGL –3 +3 % Protective transistor bias VL –13 –10 V ∗2 Horizontal register input source bias VHIS 14.7 15.3 V VHIS = VDD –3– Grounded with 390Ω resistor 15.0 Remarks VRD = VDD ±5% ∗1 ∗1 ICX063AL DC Characteristics Item Symbol Min. Typ. Max. Unit 5 Remarks Output amplifier drain current IDD mA Input current IIN1 1 µA ∗3 Input current IIN2 10 µA ∗4 ∗1 Indications of substrate voltage (VSUB) and reset gate clock voltage (VRGL) setting value The setting value of the substrate voltage and reset gate clock voltage are indicated on the back of the image sensor by a special code. Adjust the substrate voltage (VSUB) and reset gate clock voltage (VRGL) to the indicated voltage. The adjustment accuracy is ±3%. VSUB code – one character indication VRGL code – one character indication ↑ ↑ VRGL code VSUB code "Code" and optimal setting correspond to each other as follows. VRGL code 1 2 3 Optimal setting 0 0.5 1.0 1.5 2.0 2.5 3.0 VSUB code D E f 4 G 5 h 6 J 7 K L m N P Q R S T U V W X Y Z Optimal setting 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.014.5 15.0 15.5 16.0 16.5 17.0 17.5 18.0 18.5 19.0 <Example> "5K"→ VRGL = 2.0V VSUB = 12.0V ∗2 This must no exceed the VVL voltage of the vertical clock waveform. ∗3 1) Current to each pin when 20V is applied to VDD, RD, VOUT, Vss, HIS, and SUB pins, while pins that are not tested are grounded. 2) Current to each pin when 20V is applied sequentially to Vφ1, Vφ2, Vφ3, Vφ4, Hφ1, and Hφ2 pins, while pins that are not tested are grounded. However, 20V is applied to SUB pin. 3) Current to each pin when 15V is applied sequentially to RG and VGG pins, while pins that are not tested are grounded. However, 15V is applied to SUB pin. 4) Current to VL pin when 30V is applied to all pins except the pin being tested and when VL pin is grounded. However, GND and SUB pins are left open. ∗4 Current to SUB pin when 55V is applied to SUB pin, while pins that are not tested are grounded. –4– ICX063AL Clock Voltage Conditions Item Readout clock voltage Min. Typ. Max. Unit Waveform diagram VVT 14.5 15.0 15.5 V 1 VVH1, VVH2, VVH3, VVH4 –0.6 0 V 2 VVH = (VVH1 + VVH2)/2 V 2 VVL = (VVL3 + VVL4)/2 V 2 VφV = VVHn – VVLn (n = 1 to 4) 0.2 V 2 Symbol VVL1, VVL2, VVL3, VVL4 VφV Vertical transfer clock voltage –9.6 8.9 I VVH1 – VVH2 I Remarks VVH3 – VVH –0.5 0 V 2 VVH4 – VVH –0.5 0 V 2 VVHH 0.8 V 2 High-level coupling VVHL 1.0 V 2 High-level coupling VVLH 0.8 V 2 Low-level coupling VVLL 0.8 V 2 Low-level coupling Horizontal transfer clock voltage VφH 6.0 8.0 V 3 VHL –4.0 –3.5 V 3 Reset gate clock voltage VφRG 6.0 13.0 V 3 VRGL 0 3.0 V 3 27.0 32.0 V 4 Substrate clock voltage VφSUB ∗1 ∗2 ∗1 The reset gate clock voltage need not be adjusted when the reset gate clock is driven when the specifications are as given below. In this case, the reset gate clock voltage setting indicated on the back of the image sensor has not significance. Item Reset gate clock voltage Min. Typ. Max. Unit Waveform diagram VRGL –0.2 0 0.2 V 3 VφRG 8.5 9.0 9.5 V 3 Symbol ∗2 The electronic shutter speed must be between 1/50 and 1/2000s. –5– Remarks ICX063AL Clock Equivalent Circuit Constant Item Symbol Min. Typ. Max. Unit CφV1, CφV3 2700 pF CφV2, CφV4 2700 pF CφV12, CφV34 2600 pF CφV23, CφV41 950 pF CφV13 1000 pF CφV24 500 pF Capacitance between horizontal transfer clock and GND CφH1, CφH2 47 pF Capacitance between horizontal transfer clocks CφHH 58 pF Capacitance between reset gate clock and GND CφRG 7 pF Capacitance between substrate clock and GND CφSUB 800 pF Vertical transfer clock serial resistor R1, R2, R3, R4 22 Ω Vertical transfer clock ground resistor RGND 3 Ω Horizontal transfer clock serial resistor RφH 10 Ω Capacitance between vertical transfer clock and GND Capacitance between vertical transfer clocks Vφ1 Vφ2 CφV12 R1 R2 RφH RφH Hφ1 CφV1 CφV23 CφH1 CφH2 CφV13 CφV24 CφV4 R4 Hφ2 CφHH CφV2 CφV41 Vφ4 Remarks RGND CφV34 CφV3 R3 Vφ3 Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit –6– ICX063AL Drive Clock Waveform Conditions (1) Readout clock waveform 100% 90% II II φM VVT φM 2 10% 0% tr twh 0V tf (2) Vertical transfer clock waveform Vφ1 Vφ3 VVHH VVH1 VVHH VVH VVHL VVHL VVH3 VVHL VVL1 VVH VVHH VVHH VVHL VVL3 VVLH VVLH VVLL VVLL VVL VVL Vφ2 Vφ4 VVHH VVHH VVH VVH VVHH VVHH VVHL VVH2 VVHL VVHL VVL2 VVH4 VVHL VVLH VVLH VVLL VVLL VVL VVL4 –7– VVL ICX063AL (3) Horizontal transfer clock waveform and reset gate clock waveform tr twh tf 90% twl VφH, VφRG 10% VHL, VRGL (4) Substrate clock waveform 100% 90% φM VφSUB VSUB 10% 0% tr twh φM 2 tf Clock Switching Characteristics Item Symbol twh twl tr tf Unit Remarks Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Readout clock VT Vertical transfer Vφ1, Vφ2 clock Vφ3, Vφ4 Horizontal transfer clock 2.4 0.1 µs µs During µs imaging 62.6 0.74 0.1 0.1 1.3 62.1 0.1 0.1 Hφ 20 20 8 8 Hφ1 4.94 0.01 0.01 4.94 0.01 0.01 µs During parallel-serial µs conversion 41.6 2.0 2.0 ns 0.08 0.1 µs Hφ2 Reset gate clock During readout 0.2 φRG Substrate clock φSUB 10 1.9 –8– ns During imaging During drain charge ICX063AL Image Sensor Characteristics Item (Ta = 25°C) Symbol Min. Typ. Sensitivity S 350 600 Saturation signal Vsat 640 Smear Sm Unit Measurement method mV 1 mV 2 0.002 % 3 Video signal shading SH 25 % 4 Dark signal Vdt 2 mV 5 Ta = 60°C Dark signal shading ∆Vdt 1 mV 6 Ta = 60°C Flicker F 5 % 7 Lag Lag 0.5 % 8 0.0003 Max. Remarks Ta = 60°C Image Sensor Characteristics Measurement Method Measurement conditions 1) In the following measurements, the substrate voltage and the reset gate clock voltage are set to the values indicated on the device, and the device drive conditions are at the typical values of the bias and clock voltage conditions. 2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black (OB) level is used as the reference for the signal output, and the value measured at point [∗A] in the Drive Circuit is used. Definition of Standard Imaging Conditions 1) Standard imaging condition I: Use a pattern box (luminance 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and image at F8. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity. 2) Standard imaging condition II: Image a light source with a uniformity of brightness within 2% at all angles. Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. 1. Sensitivity Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of 1/250s, measure the signal output (Vs) at the center of the screen and substitute the value into the following formula. S = Vs × 250 50 [mV] 2. Saturation signal Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with average value of the signal output is 200mV, measure the minimum value of the signal output. –9– ICX063AL 3. Smear Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to 500 times the intensity with average value of the signal output, 200mV. When the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value VSm [mV] of the signal output, and substitute the value into the following formula. Sm = 1 VSm 1 × × 10 200 500 × 100 [%] (1/10V method conversion value) 4. Video signal shading Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so that the average value of the signal output is 200 mV. Then measure the maximum (Vmax [mV]) and minimum (Vmin [mV]) values of the signal output, and substitute the values into the following formula. SH = (Vmax – Vmin)/200 × 100 [%] 5. Dark signal Measure the average value (Vdt [mV]) of the signal output with the device ambient temperature 60°C and the device in the light-obstructed state, using the horizontal idle transfer level as a reference. 6. Dark signal shading After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark signal output, and substitute the values into the following formula. ∆Vdt = Vdmax – Vdmin [mV] 7. Flicker Set to standard imaging condition II. Adjust luminous intensity so that the average value of the signal output is 200mV, and then measure the difference in the signal level between fields (∆Vf [mV]). Then substitute the value into the following formula. F = (∆Vf/200) × 100 [%] 8. Lag Adjust the signal output value generated by strobe light to 200mV. After setting the strobe light so that it strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following formula. Lag = (Vlag/200) × 100 [%] FLD SG1 Light Strobe light timing Signal output 200mV Output – 10 – Vlag (lag) 6V XRG XH1 XH2 –12V XV3 XSG2 XV4 XV2 XSG1 XV1 2.2/16V 0.1 9 12 74AC04 11 10 13 8 6 5 0.1 0.1 15 16 CXD1268M 0.1 14 7 0.1 3.3/25V 18 3 1/16V 17 4 19 2 33k 100k 91k 20 1 100k 0.01 10 10 47k 0.1 3.3/ 16V 10k 3 18 4 2200P 5 1M 6 22k 1000P 33k 0.01 10k 7 10/10V 100k 17 16 15 3.3/16V 3.3k 100 10 12k 3.3/ 16V 11 12 390 18k 14 9 3.3/35V 13 8 15 15 ICX063AL (BOTTOM VIEW) 19 2 20 1 Vφ4 HIS 22/20V Vφ3 Hφ2 5V 27k 47k 15k 39k Vφ2 Hφ1 –9V 3.3/ 35V SUB VL 15k GND RG 270k Vφ1 RD 56k VL GND XSUB NC VSS 15V NC VGG 30V VDD – 11 – VOUT Drive Circuit 0.01 [∗A] CCD OUT 3.3/16V 3.3/25V ICX063AL ICX063AL Spectral Sensitivity Characteristics (includes lens characteristics, excludes light source characteristics) 1.0 0.9 0.8 Relative Response 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 400 500 600 700 800 900 1000 1100 1200 Wave Length [nm] Sensor Readout Clock Timing Chart HD V1 V2 Odd Field V3 V4 V1 V2 Even Field V3 V4 42.1 1.5 2.5 – 12 – 2.5 2.5 2.5 Unit : µs – 13 – CCD OUT HCLP VCLP SUB V4 V3 V2 V1 HD BLK VD 582 581 5 (625)0 1 620 Drive Timing Chart (Vertical Sync) 25 1 3 2 4 581 582 335 2 4 1 3 ICX063AL 330 325 320 315 310 20 15 10 – 14 – SHD SHP RG H2 H1 HCLP VCLP SUB V4 V3 V2 V1 CLK BLK HD 20 10 (1152) 0 Drive Timing Chart (Horizontal Sync) 50 40 30 Horizontal sync timing, expanded 70 SHD SHP RG H2 H1 CLK ICX063AL 170 160 150 140 130 120 110 100 90 80 60 ICX063AL Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an imaging device, do not use a solder suction equipment. When using an electric desoldering tool, use a thermal controller of the zero cross On/Off type and connect it to ground. 3) Dust and dirt protection Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. Clean glass plates with the following operation as required, and use them. a) Operate in clean environments (around class 1000 is appropriate). b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. e) When a protective tape is applied before shipping, just before use remove the tape applied for electrostatic protection. Do not reuse the tape. 4) Do not expose to strong light (sun rays) for long periods. For continuous using under cruel condition exceeding the normal using condition, consult our company. 5) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subjected to too much mechanical shocks. – 15 – – 16 – V H 31.0 ± 0.4 27.0 ± 0.3 Ceramic GOLD PLATING 42 ALLOY 5.9g LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT M 0.46 1.27 PACKAGE MATERIAL 0.3 11 0.5 10 A 26.00 ± 0.25 1 13.18 20 PACKAGE STRUCTURE 2.54 1Pin Index B + 0.15 φ2.00 0 (Reference Hole) 0.35 5.0 + 0.25 2-φ2.50 0 C 0° to 9° 20pin DIP (800mil) D ~ 2R3 . 0 ~ 0.25 26.0 9. The thickness of the cover glass is 0.75mm and the refractive index is 1.5. 8. Planar orientation of the effective image area relative to the bottom “D” is less than 60µm. 7. The height from the bottom “D” to the effective image area is 1.46 ± 0.15mm. 6. The angle of rotation relative to the reference line “B” is less than ± 1°. 5. The center of the effective image area, specified relative to the reference hole is (H, V) = (13.18, 5.0) ± 0.15mm. 4. The bottom “D” is the height reference. 3. A straight line “C” which passes through the center of the reference hole at right angles to vertical reference line “B” is the reference axis of the horizontal direction. 2. A straight line “B” which passes through the centers of the reference hole and the elongated hole is the reference axis of vertical direction. 1. “A” is the center of the effective image sensor area. + 0.15 2.00 0 × 2.5 (Elongated Hole) 20.2 ± 0.3 1.0 20.32 Unit: mm 3.2 ± 0.3 5.5 ± 0.2 (AT STAND OFF) Package Outline ICX063AL