ISSI IS61DDPB24M18-375M3 72 mb (2m x 36 & 4m x 18) ddr-iip (burst of 2) cio synchronous sram Datasheet

72 Mb (2M x 36 & 4M x 18)
DDR-IIP (Burst of 2) CIO Synchronous SRAMs
.
(2.5 Cycle Read Latency)
Features
• 2M x 36 or 4M x 18.
• On-chip delay-locked loop (DLL) for wide data
valid window.
• Common data input/output bus.
• Synchronous pipeline read with self-timed late
write operation.
• Double data rate (DDR-IIP) interface for read and
write input ports.
• Fixed 2-bit burst for read and write operations.
• Clock stop support.
• Two input clocks (K and K) for address and control registering at rising edges only.
• Industrial temperature available upon request.
Advanced Information
May 2009
• Two echo clocks (CQ and CQ) that are delivered
simultaneously with data.
• +1.8V core power supply and 1.5, 1.8V VDDQ,
used with 0.75, 0.9V VREF.
• HSTL input and output levels.
• Registered addresses, write and read controls,
byte writes, data in, and data outputs.
• Full data coherency.
• Boundary scan using limited set of JTAG 1149.1
functions.
• Byte write capability.
• Fine ball grid array (FBGA) package
- 15mm x 17mm body size
- 1mm pitch
- 165-ball (11 x 15) array
• Programmable impedance output drivers via 5x
user-supplied precision resistor.
Description
The 72Mb IS61DDPB22M36 and
IS61DDPB24M18 are synchronous, high-performance CMOS static random access memory
(SRAM) devices. These SRAMs have a common I/O
bus. The rising edge of K clock initiates the
read/write operation, and all internal operations are
self-timed.
Refer to the Timing Reference Diagram for Truth
Table on page 8 for a description of the basic operations of these DDR-IIP (Burst of 2) CIO SRAMs.
The input addresses are registered on all rising
edges of the K clock. The DQ bus operates at
double data rate for reads and writes. The following
are registered internally on the rising edge of the K
clock:
• Read and write addresses
• Address load
• Read/write enable
Byte writes
• Data-in
• Data-out
Integrated Silicon Solution, Inc.
Rev. 00A
03/31/08
The following are registered on the rising edge of
the K clock:
• Byte writes
• Data-in for second burst addresses
• Data-out
Byte writes can change with the corresponding datain to enable or disable writes on a per-byte basis. An
internal write buffer enables the data-ins to be registered one cycle later than the write address. The first
data-in burst is clocked with the rising edge of the
next K clock, and the second burst is timed to the
following rising edge of the K clock.
During the burst read operation, at the first burst the
data-outs are updated from output registers off the
second rising edge of the K clock (2.5 cycles later).
At the second burst, the data-outs are updated with
the fourth rising edge of the corresponding K clock
(see page 8).
The device is operated with a single +1.8V power
supply and is compatible with HSTL I/O interfaces.
1
I
D72 Mb (2M x 36 & 4M x 18)
DDR-IIP (Burst of 2) CIO Synchronous SRAMs
3
x36 FBGA Pinout (Top View)
A
1
2
3
4
5
6
7
8
9
10
11
CQ
NC/SA*
SA
R/W
BW2
K
BW1
LD
SA
SA
CQ
B
NC
DQ27
DQ18
SA
BW3
K
BW0
SA
NC
NC
DQ8
C
NC
NC
DQ28
VSS
SA
NC
SA
VSS
NC
DQ17
DQ7
D
NC
DQ29
DQ19
VSS
VSS
VSS
VSS
VSS
NC
NC
DQ16
E
NC
NC
DQ20
VDDQ
VSS
VSS
VSS
VDDQ
NC
DQ15
DQ6
F
NC
DQ30
DQ21
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ5
G
NC
DQ31
DQ22
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ14
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
DQ32
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ13
DQ4
K
NC
NC
DQ23
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ12
DQ3
L
NC
DQ33
DQ24
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
M
NC
NC
DQ34
VSS
VSS
VSS
VSS
VSS
NC
DQ11
DQ1
N
NC
DQ35
DQ25
VSS
SA
SA
SA
VSS
NC
NC
DQ10
P
NC
NC
DQ26
SA
SA
NC
SA
SA
NC
DQ9
DQ0
R
TDO
TCK
SA
SA
SA
NC
SA
SA
SA
TMS
TDI
* The following pins are reserved for higher densities: 2A for 144Mb
•
BW0 controls writes to DQ0–DQ8; BW1 controls writes to DQ9–DQ17; BW2 controls writes to DQ18–DQ26; BW3 controls
writes to DQ27–DQ35.
x18 FBGA Pinout (Top View)
1
2
3
SA
4
5
6
7
8
9
10
11
R/W
BW1
K
NC/SA*
LD
SA
SA
CQ
BW0
SA
NC
NC
DQ8
VSS
NC
DQ7
A
CQ
SA
B
NC
DQ9
NC
SA
NC/SA*
K
C
NC
NC
NC
VSS
SA
NC
SA
NC
D
NC
NC
DQ10
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
DQ11
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ6
F
NC
DQ12
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ5
G
NC
NC
DQ13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ4
NC
K
NC
NC
DQ14
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ3
L
NC
DQ15
NC
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
DQ1
NC
N
NC
NC
DQ16
VSS
SA
SA
SA
VSS
NC
NC
NC
P
NC
NC
DQ17
SA
SA
NC
SA
SA
NC
NC
DQ0
R
TDO
TCK
SA
SA
SA
NC
SA
SA
SA
TMS
TDI
*
The following pin is reserved for higher densities: 7A for 144Mb, 5B for 288Mb.
• BW0 controls writes to DQ0–DQ8; BW1 controls writes to DQ9–DQ17
2
Integrated Silicon Solution, Inc.
Rev. 00A
03/31/08
I
3
D
72DMb (2M x 36 & 4M x 18)
DDR-IIP (Burst of 2) CIO Synchronous SRAMs
Pin Description
Symbol
Pin Number
Description
K, K
6B, 6A
Input clock.
CQ, CQ
11A, 1A
Output echo clock.
Doff
1H
DLL disable when low.
SA
3A, 9A, 10A, 4B, 8B, 5C, 7C, 5N, 6N, 7N, 4P, 5P, 7P, 8P, 3R, 4R,
2M x 36 address inputs.
5R, 7R,8R, 9R
SA
2A, 3A, 9A, 10A, 4B, 8B, 5C, 7C, 5N, 6N, 7N, 4P, 5P, 7P, 8P, 3R,
4M x 18 address inputs.
4R, 5R, 7R, 8R, 9R
DQ0–DQ8
DQ9–DQ17
DQ18–DQ26
DQ27–DQ35
11P, 11M, 11L, 11K, 11J, 11F, 11E, 11C, 11B
10P, 11N, 10M, 10K, 10J, 11G, 10E, 11D, 10C
3B, 3D, 3E, 3F, 3G, 3K, 3L, 3N, 3P
2B, 3C, 2D, 2F, 2G, 3J, 2L, 3M, 2N
2M x 36 DQ pins
DQ0–DQ8
DQ9–DQ17
11P, 10M, 11L, 11K, 10J, 11F, 11E, 10C, 11B
2B, 3D, 3E, 2F, 3G, 3K, 2L, 3N, 3P
4M x 18 DQ pins
R/W
4A
Read/write control. Read when active high.
LD
8A
Synchronizes load. Loads new address
when low.
BW0, BW1, BW2, BW3 7B, 7A, 5A,5B
2M x 36 byte write control, active low.
BW0, BW1
7B, 5A
4M x 18 byte write control, active low.
VREF
2H, 10H
Input reference level.
VDD
5F, 7F, 5G, 7G, 5H, 7H, 5J, 7J, 5K, 7K
Power supply.
VDDQ
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
Output power supply.
VSS
4C, 8C, 4D, 5D, 6D, 7D, 8D, 5E, 6E, 7E, 6F, 6G, 6H, 6J,
6K, 5L, 6L, 7L, 4M, 5M, 6M, 7M, 8M, 4N, 8N
Ground
ZQ
11H
Output driver impedance control.
TMS, TDI, TCK
10R, 11R, 2R
IEEE 1149.1 test inputs (1.8V LVTTL levels).
TDO
1R
IEEE 1149.1 test output (1.8V LVTTL level).
NC
2A, 1B, 9B, 10B, 1C, 2C, 9C, 1D, 9D, 10D, 1E, 2E, 9E, 1F, 9F,
10F, 1G, 9G, 10G, 1J, 2J, 9J, 1K, 2K, 9K, 1L, 9L, 10L, 1M, 2M,
9M, 1N, 9N, 10N, 1P, 2P, 9P, 6R, 6P, 6C
x36 Configuration
NC
7A, 1B, 3B, 5B, 9B, 10B, 1C, 2C, 3C, 9C, 11C, 1D, 2D, 9D, 10D, x18 Configuration
11D, 1E, 2E, 9E, 10E, 1F, 3F, 9F, 10F, 1G, 2G, 9G, 10G, 11G,
1J, 2J, 3J, 9J, 11J, 1K, 2K, 9K, 10K, 1L, 3L, 9L, 10L, 1M, 2M, 3M,
9M, 11M, 1N, 2N, 9N, 10N, 11N, 1P, 2P, 9P, 10P, 6R, 6P, 6C
Integrated Silicon Solution, Inc.
Rev. 00A
03/31/08
3
I
72
D Mb (2M x 36 & 4M x 18)
DDR-IIP (Burst of 2) CIO Synchronous SRAMs
3
Block Diagram
36 (or 18)
Data
Reg
36 (or 18)
4 (or 2)
72
(or 36)
Output Driver
2M x 36
(4M x 18)
Memory
Array
36
(or 18)
Output Select
R/W
BWx
Control
Logic
20 (or 21)
Sense Amps
LD
Add Reg &
Burst
Control
Write/Read Decode
20 (or 21)
Output Reg
Write Driver
Address
A0
36 (or 18)
DQ (Data-Out
& Data-In)
CQ, CQ
(Echo Clock Out)
K
K
DOFF
Clock
Gen
Select Output Control
SRAM Features
Read Operations
The SRAM operates continuously in a burst-of-two mode. Read cycles are started by registering R/W in
active high state at the rising edge of the K clock. The K and K clocks are also used to control the timing to
the outputs. The data corresponding to the first address is clocked 2.5 cycles later by the rising edge of the
K clock. The data corresponding to the second burst is clocked 3 cycles later by the following rising edge of
the K clock. A set of free-running echo clocks, CQ and CQ, are produced internally with timings identical to
the data-outs. The echo clocks can be used as data capture clocks by the receiver device.
Whenever LD is low, a new address is registered at the rising edge of the K clock. A NOP operation (LD is
high) does not terminate the previous read. The output drivers disable automatically to a high state.
Write Operations
Write operations can also be initiated at every rising edge of the K clock whenever R/W is low. The write
address is also registered at that time. When the address needs to change, LD needs to be low
simultaneously to be registered by the rising edge of K. Again, the write always occurs in bursts of two.
Because of its common I/O architecture, the data bus must be tri-stated at least one cycle before the new
data-in is presented at the DQ bus.
The write data is provided in a ‘late write’ mode; that is, the data-in corresponding to the first address of the
burst, is presented one cycle later or at the rising edge of the next K clock. The data-in corresponding to the
second write burst address follows next, registered by the rising edge of K.
4
Integrated Silicon Solution, Inc.
Rev. 00A
03/31/08
72 Mb (2M x 36 & 4M x 18)
DDR-II (Burst of 2) CIO Synchronous SRAMs
72 Mb (2M x 36 & 4M x 18)
DDR-IIP
(Burst of 2) CIO Synchronous SRAMs
D
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3
The data-in provided for writing is initially kept in write buffers. The information on these buffers is written into
the array on the following write cycle. A read cycle to the last write address produces data from the write
buffers. Similarly, a read address followed by the same write address produces the latest write data. The
SRAM maintains data coherency.
During a write, the byte writes independently control which byte of any of the two burst addresses is written
(see X18/X36 Write Truth Tables on page 9 and Timing Reference Diagram for Truth Table on page 8).
Whenever a write is disabled (R/W is high at the rising edge of K), data is not written into the memory.
RQ Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to enable the SRAM
to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance
driven by the SRAM. For example, an RQ of 250Ω results in a driver impedance of 50Ω. The allowable range
of RQ to guarantee impedance matching is between 175Ω and 350Ω, with the tolerance described in
Programmable Impedance Output Driver DC Electrical Characteristics on page 13. The RQ resistor should
be placed less than two inches away from the ZQ ball on the SRAM module. The capacitance of the loaded
ZQ trace must be less than 3 pF.
The ZQ pin can also be directly connected to VDDQ to obtain a minimum impedance setting. ZQ must never
be connected to VSS.
Programmable Impedance and Power-Up Requirements
Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by
drifts in supply voltage and temperature. At power-up, the driver impedance is in the middle of allowable
impedances values. The final impedance value is achieved within 2048 clock cycles.
Integrated Silicon Solution, Inc.
Rev. 00A
03/31/08
5
72 Mb (2M x 36 & 4M x 18)
DDR-IIP (Burst of 2) CIO Synchronous SRAMs
Application Example
The following figure depicts an implementation of four 4M x 18 DDR-IIP SRAMs with common I/Os.
SRAM #1
SRAM #4
ZQ R=250
CQ/CQ
ZQ R=250
CQ/CQ
DQ0–17
Vt
R
SA LD R/W BW0 BW1
K K
DQ0–17
LD R/W BW0 BW1
SA
K K
Data-In/Data-Out
Echo Clock
Echo Clock
Address
R
Vt
LD
R/W
BW
Memory
Controller
Source CLK
Source CLK
R=50 Vt=VREF
Power-Up and Power-Down Sequences
The following sequence is used for power-up:
1. The power supply inputs must be applied in the following order while keeping Doff in LOW logic state:
1) VDD
2) VDDQ
3) VREF
2. Start applying stable clock inputs (K, K, C, and C).
3. After clock signals have stabilized, change Doff to HIGH logic state.
4. Once the Doff is switched to HIGH logic state, wait an additional 1024 clock cycles to lock the DLL.
NOTES:
1. The power-down sequence must be done in reverse of the power-up sequence.
2. VDDQ can be allowed to exceed VDD by no more than 0.6V.
3. VREF can be applied concurrently with VDDQ.
6
Integrated Silicon Solution, Inc.
Rev. 00A
03/31/08
72 Mb (2M x 36 & 4M x 18)
72
Mb (2M
x 36 of
& 2)
4MCIO
x 18)
DDR-II
(Burst
Synchronous SRAMs
DDR-IIP (Burst of 2) CIO Synchronous SRAMs
D
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3
State Diagram
Power Up
Load
NOP
Load
Load
Write
Load
Load New Address
Load
Read
DDR-IIP Read
Write
Load
DDR-IIP Write
Notes:
1. Read refers to read active status with R/W = high.
2. Write refers to write active status with R/W = low.
3. Load refers to read new address active status with LD = low.
4. Load is read new address inactive status with LD = high.
The Timing Reference Diagram for Truth Table on page 8 is helpful in understanding the clock and write truth
tables, as it shows the cycle relationship between clocks, address, data in, data out, and controls. All read
and write commands are issued at the beginning of cycle “t”.
Linear Burst Sequence Table
Burst Sequence
SA0
First Address
1
Second Address
0
Integrated Silicon Solution, Inc.
Rev. 00A
03/31/08
7
I
D72 Mb (2M x 36 & 4M x 18)
DDR-IIP (Burst of 2) CIO Synchronous SRAMs
3
Timing Reference Diagram for Truth Table
Cycle
t
t+1
Read A
t+2.5
t+2
NOP
NOP
tw
Write B
t+3
Write B
tw+1
K Clock
K Clock
LD
R/W
BW 0,1,2,3
Address
A
B
Data-In/
Data-Out (DQ)
QA
DB
QA+1
CQ Clock
CQ Clock
Clock Truth Table (Use the following table with the Timing Reference Diagram for Truth Table.)
Mode
Clock
Controls
Data-Out/Data-In
K
LD
R/W
QA / DB
QA+1 / DB+1
Stop Clock
Stop
X
X
Previous state
Previous state
No Operation (NOP)
L H
H
H
High-Z
High-Z
Read A
L H
L
X
D out at K (t + 2.5)
Write B
L H
X
L
DB (tW + 1)
D out at K (t + 3)
DB (tW + 1.5)
Notes:
1. The internal burst counter is always fixed as two-bit.
2. X = don’t care; H = logic “1”; L = logic “0”.
3. A read operation is started when control signal R/W is active high.
4. A write operation is started when control signal R/W is active low.
5. Before entering into the stop clock, all pending read and write commands must be completed.
6. For timing definitions, refer to the AC Characteristics on page 15. Signals must have AC specifications at timings indicated in
parenthesis with respect to switching clocks K and K.
8
Integrated Silicon Solution, Inc.
Rev. 00A
03/31/08
72 Mb (2M x 36 & 4M x 18)
D
DDR-IIP (Burst of 2) CIO Synchronous SRAMs
3
X36 Write Truth Table Use the following table with the Timing Reference Diagram for Truth Table on
page 8.
Operation
K
(tw)
Write Byte 0
K
(tw + 0.5)
BW0
BW1
BW2
BW3
DB
L→Η
L
H
H
H
D0-8 (tw + 1)
Write Byte 1
L→H
H
L
H
H
D9-17 (tw + 1)
Write Byte 2
L→H
H
H
L
H
D18-26 (tw + 1)
Write Byte 3
L→H
H
H
H
L
D27-35 (tw + 1)
Write All Bytes
L→H
L
L
L
L
D0-35 (tw + 1)
Abort Write
L→H
H
H
H
H
Don’t care
DB+1
Write Byte 0
L→H
L
H
H
H
D0-8 (tw + 1.5)
Write Byte 1
L→H
H
L
H
H
D9-17 (tw+1.5)
Write Byte 2
L→H
H
H
L
H
D18-26 (tw+1.5)
Write Byte 3
L→H
H
H
H
L
D27-35 (tw+1.5)
Write All Bytes
L→H
L
L
L
L
D0-35 (tw+1.5)
Abort Write
L→H
H
H
H
H
Don’t care
Notes;
1. For all cases. R/W must be active low during the rising edge of K occurring at time tW.
2. For timing definitions, refer to the AC Characteristics on page 15. Signals must have AC specifications with respect to switching
clocks K and K.
X18 Write Truth Table (Use this table with the Timing Reference Diagram for Truth Table on page 8.)
Operation
K
(tw)
Write Byte 0 on B
K
(tw+0.5)
BW0
BW1
DB
L→H
L
H
D0-8 (tw + 1)
Write Byte 1 on B
L→H
H
L
D9–17 (tw + 1)
Write All Bytes on B
L→H
L
L
D0–17 (tw + 1)
Abort Write on B
L→H
H
H
Don’t care
DB+1
Write Byte 1 on B+1
L→H
L
H
D0–8 (tw + 1.5)
Write Byte 2 on B+1
L→H
H
L
D9–17 (tw + 1.5)
Write All Bytes on B+1
L→H
L
L
D0–17 (tw + 1.5)
Abort Write on B+1
L→H
H
H
Don’t care
Notes;
1. Refer to Timing Reference Diagram for Truth Table on page 8. Cycle time starts at n and is referenced to the K clock.
2. For all cases, R/W must be active low during the rising edge of K occurring at tw.
3. For timing definitions, refer to the AC Characteristics on page 15. Signals must have AC specs with respect to switching clocks K
and K.
Integrated Silicon Solution, Inc.
Rev. 00A
03/31/08
9
3
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72 Mb (2M x 36 & 4M x 18)
D
DDR-IIP (Burst of 2) CIO Synchronous SRAMs
Absolute Maximum Ratings
Item
Symbol
Rating
Units
Power supply voltage
VDD
-0.5 to 2.9
V
Output power supply voltage
VDDQ
-0.5 to 2.9
V
-0.5 to VDD+0.3
V
VDOUT
-0.5 to 2.6
V
Operating temperature
TA
0 to 70
°C
Junction temperature
TJ
110
°C
Storage temperature
TSTG
-55 to +125
°C
Input voltage
Data out voltage
VIN
Note: Stresses greater than those listed in this table can cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this datasheet is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
10
Integrated Silicon Solution, Inc.
Rev. 00A
03/31/08
I
72 Mb (2M x 36 & 4M x 18)
D
DDR-IIP (Burst of 2) CIO Synchronous SRAMs
3
Recommended DC Operating Conditions (TA = 0 to +70° C)
Parameter
Maximum
Units
Notes
1.8 - 5%
1.8 + 5%
V
1
VDDQ
1.4
1.9
V
1
Input high voltage
VIH
VREF +0.1
VDDQ + 0.2
V
1, 2
Input low voltage
VIL
-0.2
VREF - 0.1
V
1, 3
VREF
0.68
0.95
V
1, 5
VIN - CLK
-0.2
VDDQ + 0.2
V
1, 4
Supply voltage
Output driver supply voltage
Input reference voltage
Clocks signal voltage
1.
2.
3.
4.
5.
Symbol
Minimum
VDD
Typical
All voltages are referenced to VSS. All VDD, VDDQ, and VSS pins must be connected.
VIH(Max) AC = See 0vershoot and Undershoot Timings.
VIL(Min) AC = See 0vershoot and Undershoot Timings.
VIN-CLK specifies the maximum allowable DC excursions of each clock (K and K).
Peak-to-peak AC component superimposed on VREF may not exceed 5% of VREF.
0vershoot and Undershoot Timings
20% Min Cycle Time
VIL(Min) AC
VDDQ+0.6V
Undershoot Timing
VDDQ
GND
VIH(Max) AC
Overshoot Timing
GND-0.6V
20% Min Cycle Time
PBGA Thermal Characteristics
Item
Symbol
Rating
Units
Thermal resistance junction to ambient (airflow = 1m/s)
RΘJA
TBD
° C/W
Thermal resistance junction to case
RΘJC
TBD
° C/W
Thermal resistance junction to pins
RΘJB
TBD
° C/W
Integrated Silicon Solution, Inc.
Rev. 00A
03/31/08
11
D
72 Mb (2M x 36 & 4M x 18)
DDR-IIP (Burst of 2) CIO Synchronous SRAMs
3
I
Capacitance (TA = 0 to +70° C, VDD = 1.8V -5%, +5%, f = 1MHz)
Parameter
Symbol
Test Condition
Maximum
Units
Input capacitance
CIN
VIN = 0V
4
pF
Data-in/Out capacitance (DQ0–DQ35)
CDQ
VDIN = 0V
4
pF
VCLK = 0V
4
pF
Clocks Capacitance (K and K)
CCLK
DC Electrical Characteristics (TA = 0 to + 70 C, VDD = 1.8V -5%, +5%)
Parameter
Symbol
Minimum
Maximum
Units
Notes
IDD33
IDD40
IDD50
—
—
—
600
550
500
x18 average power supply operating current
(IOUT = 0, VIN = VIH or VIL)
IDD33
IDD40
IDD50
—
—
—
600
550
500
Power supply standby current
(R = VIH, W = VIH. All other inputs = VIH or VIH, IIH = 0)
ISBSS
—
200
mA
Input leakage current, any input (except JTAG)
(VIN = VSS or VDD)
ILI
-2
+2
uA
Output leakage current
(VOUT = VSS or VDDQ, Q in High-Z)
ILO
-2
+2
uA
Output “high” level voltage (IOH = -6mA)
VOH
VDDQ -.4
VDDQ
V
2, 4
Output “low” level voltage (IOL = +6mA)
VOL
VSS
VSS+.4
V
2, 4
ILIJTAG
-100
+100
uA
5
x36 average power supply operating current
(IOUT = 0, VIN = VIH or VIL)
JTAG leakage current
(VIN = VSS or VDD)
mA
1, 3
mA
1, 3
1
1. IOUT = chip output current.
2. Minimum impedance output driver.
3. The numeric suffix indicates the part operating at speed, as indicated in AC Characteristics on page 15.
2
4. JEDEC Standard JESD8-6 Class 1 compatible.
5. For JTAG inputs only.
6. Currents are estimates only and need to be verified.
12
Integrated Silicon Solution, Inc.
Rev. 00A
03/31/08
I
D
72 Mb (2M x 36 & 4M x 18)
DDR-IIP (Burst of 2) CIO Synchronous SRAMs
3
Typical AC Input Characteristics
Item
Symbol
Minimum
AC input logic high
VIH (ac)
VREF + 0.2
AC input logic low
VIL (ac)
Clock input logic high (K, K)
VIH-CLK (ac)
Clock input logic low (K, K)
VIL-CLK (ac)
1.
2.
3.
4.
Maximum
Notes
1, 2, 3, 4
VREF - 0.2
VREF + 0.2
1, 2, 3, 4
1, 2, 3
VREF - 0.2
1, 2, 3
The peak-to-peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF.
Performance is a function of VIH and VIL levels to clock inputs.
See the AC Input Definition diagram.
See the AC Input Definition diagram. The signals should swing monotonically with no steps rail-to-rail with input signals never ringing back past VIH (AC) and VIL (AC) during the input setup and input hold window. VIH (AC) and VIL (AC) are used for timing purposes only.
AC Input Definition
K
VREF
K
VRAIL
VIH (AC)
VREF
Setup
Time
Hold
Time
VIL (AC)
V-RAIL
Programmable Impedance Output Driver DC Electrical Characteristics
(TA = 0 to +70° C, VDD = 1.8V -5%, +5%, VDDQ = 1.5, 1.8V)
Parameter
Symbol
Minimum
Maximum
Units
Notes
Output “high” level voltage
VOH
VDDQ / 2
VDDQ
V
1, 3
Output “low” level voltage
VOL
VSS
VDDQ / 2
V
2, 3
 VDDQ-
1. IOH =  ----------------2 
⁄
 RQ
--------
 5  ± 15% @ VOH = VDDQ / 2 For: 175Ω ≤RQ ≤350Ω.
RQ
 VDDQ- ⁄  -------2. IOL =  ---------------- 5  ± 15% @ VOL = VDDQ / 2 For: 175Ω ≤RQ ≤350Ω.
2 
3. Parameter tested with RQ = 250Ω and VDDQ = 1.5V.
Integrated Silicon Solution, Inc.
Rev. 00A
03/31/08
13
3
I
D 72 Mb (2M x 36 & 4M x 18)
DDR-IIP (Burst of 2) CIO Synchronous SRAMs
AC Test Conditions (TA = 0 to +70° C, VDD = 1.8V -5%, +5%, VDDQ = 1.5, 1.8V)
Parameter
Symbol
Conditions
Units
VDDQ
1.5, 1.8
V
Input high level
VIH
VREF+0.5
V
Input Low Level
VIL
VREF-0.5
V
VREF
0.75, 0.9
V
Input rise time
TR
0.35
ns
Input fall time
TF
0.35
ns
Output timing reference level
VREF
V
Clocks reference level
VREF
V
Output driver supply voltage
Input reference voltage
Output load conditions
Notes
1, 2
1. See AC Test Loading.
2. Parameter tested with RQ = 250Ω and VDDQ = 1.5V.
AC Test Loading
50 Ω
Q
50 Ω
0.75, 0.9V
5pF
Test
Comparator
0.75, 0.9V
14
Integrated Silicon Solution, Inc.
Rev. 00A
03/31/08
72 Mb (2M x 36 & 4M x 18)
DDR-IIP (Burst of 2) CIO Synchronous SRAMs
AC CHARACTERISTICS (Vdd = 1.8V + 0.1V, TA = 0 ºC to 70 ºC)
DDR IIP
ISSI Parameter
Description
400
min
375
max min
333
max min
300
max min
max
unit
tKHKH
K Clock Cycle Time
2.50 7.50 2.66 7.50
3.00 7.50
3.30 7.50
tKHKL
Input Clock (K/K) HIGH
0.40
0.40
0.40
0.40
tKHKH
tKLKH
tKHKH
Input Clock (K/K) LOW
K Clock Rise to K Clock Rise (rising edge to rising
0.40
1.06
0.40
1.13
0.40
1.28
0.40
1.40
tKHKH
ns
notes
ns
edge)
Setup Times
tAVKH
Address Setup to K Clock Rise
0.40
0.40
0.40
0.40
ns
2
tIVKH
tIVKH
Control Setup to K Clock Rise (R, W)
Double Data Rate Control Setup to Clock (K, K)
0.40
0.28
0.40
0.28
0.40
0.28
0.40
0.28
ns
ns
2
tDVKH
Data Input Setup to Clock (K/K) Rise
0.28
0.28
0.28
0.28
ns
2
Rise (BWS 0, BWS 1, BWS 2, BWS 3)
2
Hold Times
tKHAX
Address Hold after K Clock Rise
0.40
0.40
0.40
0.40
ns
tKHIX
tKHIX
Control Hold after K Clock Rise
Double Data Rate Control Hold after Clock (K/K)
0.40
0.28
0.40
0.28
0.40
0.28
0.40
0.28
ns
ns
tKHDX
Rise (BWS 0, BWS 1, BWS 2, BWS 3)
Data Input Hold after Clock (K/K) Rise
0.28
0.28
0.28
0.28
ns
Output Times
K/K Clock Rise to Data Valid
tCHQV
tCHQX
Data Output Hold after Output K/K Clock Rise
(Active to Active)
K/K Clock Rise to Echo Clock Valid
-0.45
tCHCQV
-0.45
tCHCQX
Echo Clock Hold after K/K Clock Rise
tCQHQV
Echo Clock High to Data Valid
tCQHQX
tCHQZ
Echo Clock High to Data Invalid
tCHQX1
Clock (K/K) Rise to High-Z
(Active to High-Z)
Clock (K/K) Rise to Low-Z
0.45
0.45
-0.45
0.45
-0.45
0.45
-0.45
0.20
-0.20
0.45
-0.45
-0.20
-0.45
ns
ns
0.45
ns
0.20
ns
1
0.45
ns
ns
1
1
ns
1
ns
-0.20
0.45
-0.45
1
1
-0.45
0.20
0.45
0.45
-0.45
0.45
0.20
-0.20
-0.45
0.45
-0.45
DLL Timing
tKC Var
Clock Phase Jitter
tKC lock
DLL Lock Time (K)
tDoffLowToReset
Doff Low period to DLL Reset
0.20
0.20
0.20
2048
2048
2048
5
5
5
0.20
ns
cycles
ns
Notes:
1. See AC Test Loading on page 14.
2. During normal operation, VIH, VIL, TRISE, and TFALL of inputs must be within 20% of VIH, VIL, TRISE, and TFALL of clock.
Integrated Silicon Solution, Inc.
Rev. 00A
03/31/08
15
72 Mb (2M x 36 & 4M x 18)
DDR-IIP (Burst of 2) CIO Synchronous SRAMs
Read, Write, and NOP Timing Diagram
NOP
Read
Read
Read
NOP
NOP
Write
Write
Read
Read
NOP
NOP
1
2
3
4
5
6
7
8
9
10
11
12
A2
A3
A4
(burst of 2) (burst of 2) (burst of 2)
4.5
(Note 3)
(burst of 2) (burst of 2) (burst of 2)
(burst of 2)
K
tKHKL
tKHKH
tKHKL
tKHKH
tKLKH
K
tIVKH
tKHIX
LD
R/W
SA
A0
A1
tAVKH
tKHAX
DQ
tCHQV
tCHQZ
tCHQX
tCHQX1
Q01
Q02
Q11
Q12
A5
tDVKH
tKHDX
tCHQV
D21 D22 D31 D32
Q41
Q42
tCHCQV
tCHCQX
CQ
tCHCQV
tCHCQX
CQ
Don’t Care
16
Undefined
Integrated Silicon Solution, Inc.
Rev. 00A
03/31/08
72 Mb (2M x 36 & 4M x 18)
DDR-IIP (Burst of 2) CIO Synchronous SRAMs
3
I
D
IEEE 1149.1 TAP and Boundary Scan
The SRAM provides a limited set of JTAG functions to test the interconnection between SRAM I/Os and
printed circuit board traces or other components. There is no multiplexer in the path from I/O pins to the RAM
core.
In conformance with IEEE Standard 1149.1, the SRAM contains a TAP controller, instruction register,
boundary scan register, bypass register, and ID register.
The TAP controller has a standard 16-state machine that resets internally on power-up. Therefore, a TRST
signal is not required.
Signal List
•
•
•
•
TCK: test clock
TMS: test mode select
TDI: test data-in
TDO: test data-out
JTAG DC Operating Characteristics (TA = 0 to +70° C)
Operates with JEDEC Standard 8-5 (1.8V) logic signal levels
Parameter
Symbol
Minimum
Typical
Maximum
Units
Notes
JTAG input high voltage
VIH1
1.3
—
VDD+0.3
V
1
JTAG input low voltage
VIL1
-0.3
—
0.5
V
1
JTAG output high level
VOH1
VDD-0.4
—
VDD
V
1, 2
JTAG output low level
VOL1
VSS
—
0.4
V
1, 3
1.
2.
3.
All JTAG inputs and outputs are LVTTL-compatible.
IOH1 ≥ -2mA
IOL1 ≥ +2mA.
JTAG AC Test Conditions (TA = 0 to +70° C, VDD = 1.8V -5%, +5%)
Parameter
Symbol
Conditions
Units
Input pulse high level
VIH1
1.3
V
Input pulse low level
VIL1
0.5
V
Input rise time
TR1
1.0
ns
Input fall time
TF1
1.0
ns
0.9
V
Input and output timing reference level
Integrated Silicon Solution, Inc.
Rev. 00A
03/31/08
17
72 Mb (2M x 36 & 4M x 18)
D
DDR-IIP
(Burst of 2) CIO Synchronous SRAMs
I
3
JTAG AC Characteristics (TA = 0 to +70° C, VDD = 1.8V -5%, +5%)
Parameter
Symbol
Minimum
Maximum
Units
TCK cycle time
tTHTH
20
—
ns
TCK high pulse width
tTHTL
7
—
ns
TCk low pulse width
tTLTH
7
—
ns
TMS setup
tMVTH
4
—
ns
TMS hold
tTHMX
4
—
ns
TDI setup
tDVTH
4
—
ns
TDI hold
tTHDX
4
—
ns
TCK low to valid data
tTLOV
—
7
ns
Notes
1
1. See AC Test Loading on page 14.
JTAG Timing Diagram
tTHTL
tTLTH
tTHTH
TCK
tTHMX
TMS
tMVTH
tTHDX
TDI
tDVTH
TDO
tTLOV
18
Integrated Silicon Solution, Inc.
Rev. 00A
03/31/08
72 Mb (2M x 36 & 4M x 18)
D DDR-IIP (Burst of 2) CIO Synchronous SRAMs
3
I
Scan Register Definition
Register Name
Bit Size x18 or x36
Instruction
3
Bypass
1
ID
32
Boundary Scan
109
ID Register Definition
Field Bit Number and Description
Part
Revision Number
(31:29)
Part Configuration
(28:12)
JEDEC Code
(11:1)
Start Bit
(0)
4M x 18
000
00def0wx0t0q0b0s0
000 101 001 00
1
2M x 36
000
00def0wx0t0q0b0s0
000 101 001 00
1
Part Configuration Definition:
def = 011 for 72Mb
wx = 11 for x36, 10 for x18
t = 1 for DLL, 0 for non-DLL
q = 1 for QUADB2, 0 for DDR-II, DDR-IIP
b = 1 for burst of 4, 0 for burst of 2
s = 1 for separate I/0, 0 for common I/O
Integrated Silicon Solution, Inc.
Rev. 00A
03/31/08
19
I
72
D Mb (2M x 36 & 4M x 18)
DDR-IIP (Burst of 2) CIO Synchronous SRAMs
3
Instruction Set
Code
Instruction
TDO Output
Notes
000
EXTEST
Boundary Scan Register
2,6
001
IDCODE
32-bit Identification Register
010
SAMPLE-Z
Boundary Scan Register
1, 2
011
PRIVATE
Do not use
5
100
SAMPLE
Boundary Scan Register
4
101
PRIVATE
Do not use
5
110
PRIVATE
Do not use
5
111
BYPASS
Bypass Register
3
1. Places Qs in high-Z in order to sample all input data, regardless of other SRAM inputs.
2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data.
3. BYPASS register is initiated to VSS when BYPASS instruction is invoked. The BYPASS register also holds the last serially loaded
TDI when exiting the shift-DR state.
4. SAMPLE instruction does not place DQs in high-Z.
5. This instruction is reserved. Invoking this instruction will cause improper SRAM functionality.
6. This EXTEST is not IEEE 1149.1-compliant. By default, it places Q in high-Z. If the internal register on the scan chain is set high,
Q will be updated with information loaded via a previous SAMPLE instruction. The actual transfer occurs during the update IR
state after EXTEST is loaded. The value of the internal register can be changed during SAMPLE and EXTEST only.
List of IEEE 1149.1 Standard Violations
•
•
•
•
•
7.2.1.b, e
7.7.1.a-f
10.1.1.b, e
10.7.1.a-d
6.1.1.d
JTAG Block Diagram
TDI
Bypass Register (1 bit)
Identification Register (32 bits)
TDO
Instruction Register (3 bits)
Control Signals
TMS
TAP Controller
TCK
20
Integrated Silicon Solution, Inc.
Rev. 00A
03/31/08
72 Mb (2M x 36 & 4M x 18)
D DDR-IIP (Burst of 2) CIO Synchronous SRAMs
3
I
TAP Controller State Machine
1
Test Logic Reset
0
0
Run Test Idle
1
1
Select DR
0
0
1
1
Select IR
1
Capture IR
Capture DR
0
0
0
Shift IR
0
Shift DR
1
1
1
1
Exit1 IR
Exit1 DR
0
0
0
0
Pause DR
Pause IR
1
1
Exit2 DR
Exit2 IR
0
0
1
1
Update DR
0
Integrated Silicon Solution, Inc.
Rev. 00A
03/31/08
1
Update IR
1
0
21
3
72 Mb (2M x 36 & 4M x 18)
D
DDR-IIP
(Burst of 2) CIO Synchronous SRAMs
D
I
Boundary Scan Exit Order The same length is used for x18 and x36 I/O configuration.
Order
Pin ID
Order
Pin ID
1
2
3
4
Order
Pin ID
6R
37
6P
37
10D
73
2C
9E
74
3E
6N
7P
39
10C
75
2D
40
11D
76
2E
5
7N
41
9C
77
1E
6
7R
7
8R
42
9D
78
2F
43
11B
79
3F
8
8P
44
9
9R
45
11C
80
1G
9B
81
1F
10
11P
46
10B
82
3G
11
10P
47
11A
83
2G
12
10N
48
10A
84
1H
13
9P
49
9A
85
1J
14
10M
50
8B
86
2J
15
11N
51
7C
87
3K
16
9M
52
6C
88
3J
17
9N
53
8A
89
2K
18
11L
54
7A
90
1K
19
11M
55
7B
91
2L
20
9L
56
6B
92
3L
21
10L
57
6A
93
1M
22
11K
58
5B
94
1L
23
10K
59
5A
95
3N
24
9J
60
4A
96
3M
25
9K
61
5C
97
1N
26
10J
62
4B
98
2M
27
11J
63
3A
99
3P
28
11H
64
2A
100
2N
29
10G
65
1A
101
2P
30
9G
66
2B
102
1P
31
11F
67
3B
103
3R
32
11G
68
1C
104
4R
33
9F
69
1B
105
4P
34
10F
70
3D
106
5P
35
11E
71
3C
107
5N
36
10E
72
1D
108
5R
109
Internal
Notes:
1) NC pins as defined on FBGA pinouts on page 2 are read as “don’t cares”.
2) State of Internal pin (#109) is loaded via JTAG
22
Integrated Silicon Solution, Inc.
Rev. 00A
03/31/08
72 Mb (2M x 36 & 4M x 18)
DDR-IIP (Burst of 2) CIO Synchronous SRAMs
11 x 15 FBGA Dimensions
Integrated Silicon Solution, Inc.
Rev. 00A
03/31/08
23
72 Mb (2M x 36 & 4M x 18)
DDR-IIP (Burst of 2) CIO Synchronous SRAMs
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed
400 MHz
375 MHz
24
Order Part No.
IS61DDPB22M36-400M3
IS61DDPB22M36-400M3L
IS61DDPB24M18-400M3
IS61DDPB24M18-400M3L
IS61DDPB22M36-375M3
IS61DDPB22M36-375M3L
IS61DDPB24M18-375M3
IS61DDPB24M18-375M3L
Organization
2Mx36
2Mx36
4Mx18
4Mx18
2Mx36
2Mx36
4Mx18
4Mx18
Package
165 BGA
165 BGA, Lead-free
165 BGA
165 BGA, Lead-free
165 BGA
165 BGA, Lead-free
165 BGA
165 BGA, Lead-free
Integrated Silicon Solution, Inc.
Rev. 00A
03/31/08