SLS LS86 Quad 2-input exclusive or gate Datasheet

SL74LS86
Quad 2-Input Exclusive OR
Gate
This device contains four independent 2-input Exclusive-OR gates.
It performs the Boolean functions Y=A ⊕ B=AB+AB in positive logic.
ORDERING INFORMATION
SL74LS86N Plastic
SL74LS86D SOIC
TA = 0° to 70° C for all
packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
PIN 14 =VCC
PIN 7 = GND
SLS
System Logic
Semiconductor
Output
A
B
Y
L
L
L
L
H
H
H
L
H
H
H
L
SL74LS86
MAXIMUM RATINGS *
Symbol
Parameter
Value
Unit
VCC
Supply Voltage
7.0
V
VIN
Input Voltage
7.0
V
VOUT
Output Voltage
5.5
V
Tstg
Storage Temperature Range
-65 to +150
°C
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
5.25
V
VCC
Supply Voltage
4.75
VIH
High Level Input Voltage
2.0
VIL
Low Level Input Voltage
0.8
V
IOH
High Level Output Current
-0.4
mA
IOL
Low Level Output Current
8.0
mA
TA
Ambient Temperature Range
+70
°C
0
V
DC ELECTRICAL CHARACTERISTICS over full operating conditions
Guaranteed Limit
Symbol
Parameter
Test Conditions
Min
Max
Unit
-1.5
V
VIK
Input Clamp Voltage
VCC = min, IIN = -18 mA
VOH
High Level Output Voltage
VCC = min, IOH = -0.4 mA
VOL
Low Level Output Voltage
VCC = min, IOL = 4 mA
0.4
VCC = min, IOL = 8 mA
0.5
VCC = max, VIN = 2.7 V
40
µA
VCC = max, VIN = 7.0 V
0.2
mA
-0.8
mA
-100
mA
10
mA
IIH
High Level Input Current
IIL
Low Level Input Current
VCC = max, VIN = 0.4 V
IO
Output Short Circuit Current
VCC = max, VO = 0 V
(Note 1)
ICC
Supply Current
VCC = max
Total with
outputs high
2.7
-20
Total with
outputs low
V
V
15
Note 1: Not more than one output should be shorted at a time, and duration should not exceed one second.
SLS
System Logic
Semiconductor
SL74LS86
AC ELECTRICAL CHARACTERISTICS (TA=25°C, VCC = 5.0 V, CL = 15 pF, RL = 2 kΩ, t r =15
ns, tf = 6.0 ns)
Symbol
Parameter
Min
Max
Unit
tPLH
Propagation Delay, Input A or B to Output Y
(Other input low)
23
ns
tPHL
Propagation Delay, Input A or B to Output Y
(Other input low)
17
ns
tPLH
Propagation Delay, Input A or B to Output Y
(Other input high)
30
ns
tPHL
Propagation Delay, Input A or B to Output Y
(Other input high)
22
ns
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
NOTES A. CL includes probe and jig capacitance.
B. All diodes are 1N916 or 1N3064.
Figure 3. Test Circuit
SLS
System Logic
Semiconductor