PRELIMINARY
SPECIFICATION
EEPROM
Austin Semiconductor, Inc.
PIN ASSIGNMENT
128K x 32 Radiation Tolerant EEPROM
(Top View)
68 Lead CQFP
RES\
A0
A1
A2
A3
A4
A5
CS3\
GND
CS4\
WE1\
A6
A7
A8
A9
A10
Vcc
AVAILABLE AS MILITARY SPECIFICATIONS
• MIL-PRF-38534 compliant
• SPACE Level Process Flow
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
FEATURES
-250
-300
• Package
Ceramic Quad Flat pack w/ formed leads
Ceramic Quad Flat pack w/ tie bar
Shielded Ceramic Quad Flat pack
Shielded Ceramic Quad Flat pack
Q
QB
SQ
SQB
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
*Pin #'s 31 and 32, A15 and A14 respectively, are reversed from the AS8E128K32. Correct
use of these address lines is required for operation of the SDP mode to work properly.
PIN NAME
A0 to A16
I/O0 to I/O31
OE\
CE\
WE\
VCC
FUNCTION
Address Input
Data Input/Output
Output Enable
Chip Enable
Write Enable
Power Supply
Ground
VSS
RDY/BUSY\ Ready Busy
RES\
Reset
MARKINGS
• Timing
250 ns
300 ns
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10
60
11
59
12
58
13
57
14
56
15
55
16
54
17
53
18
52
19
51
20
50
21
49
22
48
23
47
24
46
25
45
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Vcc
A11
A12
A13
*A15
*A14
A16
CS1\
OE\
CS2\
NC
WE2\
WE3\
WE4\
NC
NC
RDY
• Access time of 250ns , 300ns
• Operation with single 3.3V (+ .3V) supply
• LOW Power Dissipation:
Active(Worst case): 300mW (MAX), Max Speed Operation
Standby(Worst case): 7.2mW(MAX), Battery Back-up Mode
• Automatic Byte Write: 15 ms (MAX)
• Automatic Page Write (128 bytes): 15 ms (MAX)
• Data protection circuit on power -on/off
• Low power CMOS MNOS cell Technology
• 104 Erase/Write cycles (in Page Mode)
• Software data protection
• TTL Compatible Inputs and Outputs
• Data Retention: 10 years
• Ready/Busy\ and Data Polling Signals
• Write protection by RES\ pin
• Radiation Tolerant: Proven total dose 40K to 100K RADS*
• Shielded Package for Best Radiation Immunity
• Operating Temperature Ranges:
Military: -55oC to +125oC
Industrial: -40oC to +85oC
OPTIONS
AS8ERLC128K32
No. 703Q
No. 703QB
No. 703SF
No. 703SQB
GENERAL DESCRIPTION
The Austin Semiconductor, Inc. AS8ERLC128K32 is a 4 Megabit Radiation Tolerant EEPROM Module organized as 128K x 32 bit.
User configurable to 256K x16 or 512Kx 8. The module achieves high
speed access, low power consumption and high reliability by
employing advanced CMOS memory technology.
The military grade product is manufactured in compliance to
MIL-STD 883, making the AS8ERLC128K32 ideally suited for military or space applications.
The module is offered as a 68 lead 0.880 inch square ceramic
quad flat pack. It has a max. height of 0.200 inch (non-shielded). This
package design is targeted for those applications which require low
profile SMT Packaging.
FUNCTIONAL BLOCK DIAGRAM
For more products and information
please visit our web site at
www.austinsemiconductor.com
* contact factory for test reports. ASI does not guarantee or warrant
these performance levels, but references these third party reports.
AS8ERLC128K32
Rev. 1.9 06/06
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
PRELIMINARY
SPECIFICATION
EEPROM
Austin Semiconductor, Inc.
AS8ERLC128K32
TRUTH TABLE
MODE
CE\
OE\
Read
VIL
VIL
Standby
VIH
Write
Deselect
Wirte Inhibit
Data\ Polling
Program Reset
WE\
RES\
2
RDY/BUSY\
1
I/O
High-Z
Dout
X
High-Z
High-Z
VIL
VH
High-Z to VOL
Din
VIH
VIH
VH
High-Z
High-Z
X
X
VIH
X
---
---
X
VIL
X
X
---
---
VIL
VIL
VIH
VH
VOL
Dout (I/O7)
X
X
X
VIL
High-Z
High-Z
VIH
VH
X
X
VIL
VIH
VIL
3
NOTES: 1. RDY/Busy\ output has only active LOW VOL and high impedance state. It can not go to HIGH (VOH) state.
2. VCC - 0.5V < VH < VCC+0.5V
3. X : DON'T CARE
AS8ERLC128K32
Rev. 1.9 06/06
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
PRELIMINARY
SPECIFICATION
EEPROM
AS8ERLC128K32
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vcc Supply Relative to Vss
Vcc ............................................................................-0.6V to +7.0V
Operating Temperature Range(1) ..................-55°C to +125°C
Storage Temperature Range .........................-65°C to +150°C
Voltage on any Pin Relative to Vss...................-0.5V to +7.0V (2)
Max Junction Temperature**.......................................+150°C
Thermal Resistance junction to case (θJC):
Package Type Q...........................................11.3° C/W
Package Type P & PN..................................2.8° C/W
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
**Junction temperature depends upon package type, cycle time,
loading, ambient temperature and airflow, and humidity
(plastics).
NOTES:
1) Including electrical characteristics and data retention.
2) VIN MIN = -1.0V for pulse width < 20ns.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55oC<TA<125oC or -40oC to +85oC; Vcc = 3.3V +/-.3V)
PARAMETER
Input High Voltage
CONDITIONS
SYMBOL
VIH
Input High Voltage (RES\)
VH
Input Low Voltage
VIL
MIN
2.2
VCC -0.3
-0.31
Input Low Voltage (RES\)
VL
-0.31
MAX
VCC +0.3
0.4
UNITS
V
VCC +.3
V
0.8
V
V
LOW INPUT Leakage(RES\ Signal)
RES\=0V, VCC=3.6V
ILI(RES)
-300
P$
HIGH INPUT Leakage(RES\ Signal)
RES\=3.6V, VCC=3.6V
IHI(RES)
-10.0
P$
HIGH INPUT Leakage(RES\ Signal)
RES\=3.3V, VCC=3.3V
OV < VIN < VCC
IHI(RES)
-30.0
ILI
-10
10
P$
Outputs(s) Disabled,
OV < VOUT < VCC
ILO
-10
10
P$
Output High Voltage
IOH = -0.4mA
VOH
VCCx.8
--
V
Output High Voltage
IOH = -0.1mA
VOH
VCC-0.3
--
V
Output Low Voltage
IOL = 2.1mA
VOL
--
0.4
V
Output Low Voltage
IOL = 0.1mA
VOL
--
0.2
V
VCC
3
3.6
V
INPUT LEAKAGE CURRENT2
2
OUTPUT LEAKAGE CURRENT
Supply Voltage
NOTE:
P$
1) VIL (MIN): -1.0V for pulse width < 20ns.
2) All other Signal pins except RES\
PARAMETER
Power Supply Current:
Operating
CONDITIONS
SYM
Iout = 0mA, V CC = 3.6V
Cycle = 1µS, Duty = 100%
MAX
-250
MAX
-300
30
30
mA
Icc3
Iout = 0mA, V CC = 3.6V
Cycle = MIN, Duty = 100%
UNITS
80
70
CE\ = VCC, VCC = 3.6V
ICC1
0.4
0.4
mA
CE\ = VIH, VCC = 3.6V
ICC2
4
4
mA
Power Supply Current:
Standby
AS8ERLC128K32
Rev. 1.9 06/06
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
PRELIMINARY
SPECIFICATION
EEPROM
Austin Semiconductor, Inc.
AS8ERLC128K32
CAPACITANCE TABLE1 (VIN = 0V, f = 1 MHz, TA = 25oC, VCC=3.3V)
SYMBOL
CADD
COE
CWE, CCE
CIO
PARAMETER
A0 - A16 Capacitance
OE\, RES\, RDY Capacitance
WE\ and CE\ Capacitance
I/O 0- I/O 31 Capacitance
MAX
40
40
12
20
UNITS
pF
pF
pF
pF
NOTE: 1. This parameter is guaranteed but not tested.
AC TEST CHARACTERISTICS
TEST SPECIFICATIONS
IOL
Input pulse levels...........................................VSS to 3V
Input rise and fall times...........................................5ns
Input timing reference levels.................................1.5V
Output reference levels.........................................1.5V
Output load................................................See Figure 1
Current Source
Device
Under
Test
-
+
Vz = 1.5V
(Bipolar
Supply)
+
Ceff = 50pf
NOTES:
Vz is programmable from -2V to + 5V.
IOL and IOH programmable from 0 to 16 mA.
Vz is typically the midpoint of VOH and VOL.
IOL and IOH are adjusted to simulate a typical resistive load
circuit.
IOH
Current Source
Figure 1
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(-55oC < TA < +125oC or -40oC to +85oC; Vcc = 3.3V +.3V)
DESCRIPTION
TEST CONDITIONS
-250
SYMBOL MIN MAX
tACC
250
-300
MIN MAX UNITS
300
ns
Address to Output Delay
CE\ = OE\ = V IL, WE\ = V IH
CE\ to Output Delay
OE\ = V IL, WE\ = V IH
tCE
OE\ to Output Delay
OE\ = V IL, WE\ = V IH
tOE
10
Address to Output Hold
CE\ = OE\ = V IL, WE\ = V IH
tOH
0
CE\ or OE\ high to Output Float (1)
OE\ = V IL, WE\ = V IH
tDF
0
50
0
50
ns
RES\ low to Output Float (1)
CE\ = OE\ = V IL, WE\ = V IH
tDFR
0
350
0
350
ns
RES\ to Output Delay
CE\ = OE\ = V IL, WE\ = V IH
tRR
0
600
0
600
ns
AS8ERLC128K32
Rev. 1.9 06/06
250
120
10
300
ns
130
ns
0
ns
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
PRELIMINARY
SPECIFICATION
EEPROM
AS8ERLC128K32
Austin Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC WRITE CHARACTERISTICS
(-55oC < TA < +125oC; Vcc = 3.3V +.3V)
SYMBOL
MIN(2)
PARAMETER
tAS
Address Setup Time
tAH
Address Hold Time
tCS
MAX
UNITS
0
ms
150
ns
CE\ to Write Setup Time (WE\ controlled)
0
ns
tCH
CE\ Hold Time (WE\ controlled)
0
ns
tWS
WE\ to Write Setup Time (CE\ controlled)
0
ns
tWH
WE\ to Hold Time (CE\ controlled)
0
ns
tOES
OE\ to Write Setup Time
0
ns
tOEH
OE\ to Hold Time
0
ns
tDS
Data Setup Time
100
ns
tDH
Data Hold Time
10
ns
tWP
WE\ Pulse Width (WE\ controlled)
250
ns
tCW
CE\ Pulse Width (CE\ controlled)
250
ns
tDL
Data Latch Time
750
ns
tBLC
Byte Load Cycle
1
tBL
Byte Load Window
tWC
Write Cycle Time
tDB
Time to Device Busy
Write Start Time
tRP
Reset Protect Time
Reset High Time
µs
100
µs
15
tDW
tRES
30
(3)
ms
150
250
(5)
ns
(4)
ns
100
µs
2
µs
READ TIMING WAVEFORM
ADDRESS
t ACC
CE\
OE\
WE\
Data Out
t OH
tCE
tOE
VIH
HIGH-Z
t DF
DATA OUT VALID
tRR
t DFR
RES\
AS8ERLC128K32
Rev. 1.9 06/06
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
PRELIMINARY
SPECIFICATION
EEPROM
AS8ERLC128K32
Austin Semiconductor, Inc.
BYTE WRITE TIMING WAVEFORM (WE\ CONTROLLED)
tWC
Address
tCS
t CH
t AH
CE\
tBL
tAS
WE\
tWP
tOES
t OEH
OE\
tDS
t DH
Din
t DW
t DB
RDY/Busy\
HIGH-Z
HIGH-Z
VOL
t RP
tRES
RES\
VCC
BYTE WRITE TIMING WAVEFORM (CE\ CONTROLLED)
Address
tWS
t AH
tCW
CE\
WE\
tWC
tBL
tAS
tWH
t OEH
tOES
OE\
tDS
t DH
Din
RDY/Busy\
t DW
t DB
HIGH-Z
tRES
VOL
t RP
HIGH-Z
RES\
VCC
AS8ERLC128K32
Rev. 1.9 06/06
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
6
PRELIMINARY
SPECIFICATION
EEPROM
AS8ERLC128K32
Austin Semiconductor, Inc.
PAGE WRITE TIMING WAVEFORM (WE\ CONTROLLED)
Address(6)
A0 to A16
tAS
WE\
t AH
tWP
tDL
tCS
CE\
tBL
t CH
tBLC
tWC
tOES
OE\
tOEH
tDS
t DH
HIGH-Z
Din
HIGH-Z
t DW
t DB
RDY/Busy\
t RP
RES\
tRES
VCC
PAGE WRITE TIMING WAVEFORM (CE\ CONTROLLED)
Address(6)
A0 to A16
tAS
CE\
WE\
t AH
tCW
tBL
tDL
tWH
tWS
tBLC
tWC
tOES
OE\
Din
tOEH
tDS
t DH
HIGH-Z
HIGH-Z
t DW
t DB
RDY/Busy\
t RP
RES\
tRES
VCC
AS8ERLC128K32
Rev. 1.9 06/06
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
7
PRELIMINARY
SPECIFICATION
Austin Semiconductor, Inc.
EEPROM
AS8ERLC128K32
DATA POLLING TIMING WAVEFORM
Address
An
An
CE\
tCE(7)
WE\
tOES
t OEH
OE\
tOE(7)
I\O7
Din X
t DW
Dout X
Dout X
tWC
NOTES:
1. tDF and tDFR are defined as the time at which the outputs achieve the open circuit conditions and are no longer driven.
2. Use this device in longer cycle than this value.
3. tWC must be longer than this value unless polling techniques or RDY/Busy\ are used. This device automatically completes the internal write operation within this value.
4. Next read or write operation can be initiated after tDW if polling techniques or RDY/Busy\ are used.
5. This parameter is sampled and not 100% tested.
6. A7 to A16 are page addresses and must be same(i.e. Not Change) during the page write operation.
7. See AC read characteristics.
AS8ERLC128K32
Rev. 1.9 06/06
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
8
PRELIMINARY
SPECIFICATION
EEPROM
Austin Semiconductor, Inc.
AS8ERLC128K32
TOGGLE BIT
This device provides another function to determine the internal programming cycle. If the EEPROM is set to read mode
during the internal programming cycle, I/O6 will charge from "1" to "0" (toggling) for each read. When the internal programming cycle is finished, toggling of I/O6 will stop and the device can be accessible for next read or program.
TOGGLE BIT WAVEFORM
4
Next Mode
Address
tCE3
CE\
WE\
tOE3
OE\
tOES
t OEH
I/O6
Dout
Din
1
Dout
Dout
2
Dout
2
t DW
tWC
NOTES:
1) I/O6 beginning state is "1".
2) I/O6 ending state will vary.
3) See AC read characteristics.
4) Any locations can be used, but the address must be fixed.
SOFTWARE DATA PROTECTION TIMING WAVEFORM (In protection mode)
VCC
WE\
tBLC
Address
5555
Data (each byte)
AA
tBLC
AAAA or
2AAA
55
tBLC
5555
A0
{
CE\
tWC
Write Address*
Write Data
* During this write cycle, data is physically written to the address provided.
AS8ERLC128K32
Rev. 1.9 06/06
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
9
PRELIMINARY
SPECIFICATION
Austin Semiconductor, Inc.
EEPROM
AS8ERLC128K32
SOFTWARE DATA PROTECTION TIMING WAVEFORM (In non-protection mode)
VCC
tWC
Normal
active mode
CE\
WE\
Address
5555
AAAA
or
2AAA
5555
5555 AAAA
or
2AAA
Data (each byte)
AA
55
80
AA
55
5555
20
FUNCTIONAL DESCRIPTION
Automatic Page Write
Page-mode write feature allows 1 to 128 bytes of data to be
written into the EEPROM in a single write cycle. Following
the initial byte cycle, an additional 1 to 128 bytes can be written in the same manner. Each additional byte load cycle must
be started within 30µs from the preceding falling edge of WE\
or CE\. When CE\ or WE\ is kept high for 100µs after data input,
the EEPROM enters write mode automatically and the input
data are written into the EEPROM.
RDY/Busy\ Signal
RDY/Busy\ signal also allows status of the EEPROM to be
determined. The RDY/Busy\ signal has high impedance except in write cycle and is lowered to VOL after the first write
signal. At the end of write cycle, the RDY/Busy\ signal changes
state to high impedance.
RES\ Signal
When RES\ is low, the EEPROM cannot be read or programmed. Therefore, data can be protected by keeping RES\
low when VCC is switched. RES\ should be high during read
and programming because it doesn't provide a latch function.
See timing diagram below.
DATA\ Polling
DATA\ polling allows the status of the EEPROM to be determined. If EEPROM is set to read mode during the write cycle,
an inversion of the last byte of data to be loaded outputs from
I/O's 7, 15, 23, and 31 to indicate that the EEPROM is performing a write operation.
RES\ Signal Diagram
VCC
Read inhibit
Read inhibit
RES\1
Program inhibit
Program inhibit
Note(s):
1- RES\=TRUE=VL >/=-0.3v </=0.4v
AS8ERLC128K32
Rev. 1.9 06/06
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
10
PRELIMINARY
SPECIFICATION
EEPROM
AS8ERLC128K32
Austin Semiconductor, Inc.
WE\, CE\ Pin Operation
During a write cycle, address are latched by the falling edge
of WE\ or CE\, and data is latched by the rising edge of WE\
or CE\.
Write/Erase Endurance and Data Retention Time
The endurance is 104 cycles in case of the page programming
and 103 cycles in case of the byte programming (1% cumulative failure rate). The data retention time is more than 10
years when a device is page-programmed less than 104 cycles.
RDY/Busy\ SIGNAL
RDY/Busy\ signal also allows status of the EEPROM to
be determined. The RDY/Busy\ signal has high impedance
except in write cycle and is lowered to VOL after the first write
signal. At the end of the write cycle, the RDY/Busy\ signal
changes state to high impedance. This allows many
AS8ERLC128K32 devices RDY/Busy\ signal lines to be wiredOR together.
may act as a trigger and turn the EEPROM to programming
mode by mistake. To prevent this phenomenon, this device has
a noise cancellation function that cuts noise if its width is 20ns
or less in program mode.
Be careful not to allow noise of a width more than
20ns on the control pins. See Diagram 1 below.
2. Data Protection at VCC On/Off
When VCC is turned on or off, noise on the control
pins generated by external circuits (CPU, etc.) may act as a
trigger and turn the EEPROM to program mode by mistake.
To prevent this unintentional programming, the EEPROM must
be kept in an unprogrammable state while the CPR is in an
unstable state.
NOTE: The EEPROM should be kept in
unprogrammable state during VCC on/off by using CPU RESET signal. See the timing diagram below.
DIAGRAM 1
PROGRAMMING/ERASE
The AS8ERLC128K32 does NOT employ a BULK-erase
function. The memory cells can be programmed ‘0’ or ‘1’. A
write cycle performs the function of erase & write on every
cycle with the erase being transparent to the user. The internal
erase data state is considered to be ‘1’. To program the memory
array with background of ALL 0’s or All 1’s, the user would
program this data using the page mode write operation to program all 1024 128-byte pages.
Data Protection
1. Data Protection against Noise on Control Pins (CE\,
OE\, WE\) During Operation
During readout or standby, noise on the control pins
DATA PROTECTION AT VCC ON/OFF
VCC
CPU
RESET
*Unprogrammable
AS8ERLC128K32
Rev. 1.9 06/06
*Unprogrammable
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11
PRELIMINARY
SPECIFICATION
EEPROM
Austin Semiconductor, Inc.
Data Protection Cont.
a. Protection by RES\
The unprogrammable state can be realized by the
CPU's reset signal inputs directly to the EEPROM's RES pin.
RES should be kept VSS level during VCC on/off.
The EEPROM brakes off programming operation
when RES becomes low, programming operation doesn't finish correctly in case that RES falls low during programming
operation. RES should be kept high for 10ms after the last
data inputs. See the timing diagram below.
3. Software data protection
To prevent unintentional programming, this device
has the software data protection (SDP) mode. The SDP is
enabled by inputting the 3 bytes code and write data in
Chart 1. SDP is not enabled if only the 3 bytes code is input.
AS8ERLC128K32
To program data in the SDP enable mode, 3 bytes code must
be input before write data. This 4th cycle during write is
required to initiate the SDP and physically writes the address
and data. While in SDP the entire array is protected in which
writes can only occur if the exact SDP sequence is
re-executed or the unprotect sequence is executed.
The SDP is disabled by inputting the 6 bytes code in
Chart 2. Note that, if data is input in the SDP disable cycle,
data can not be written.
The software data protection is not enabled at the
shipment.
NOTE: These are some differences between ASI's
and other company's for enable/disable sequence of software
data protection. If these are any questions, please contact ASI.
PROTECTION BY RES\
VCC
RES\
Program inhibit
Program inhibit
WE\ or CE\
1µ min
100µ min
10 ms min
CHART 1
Address
CHART 2
Address
Data
Data
(each Byte)
(each Byte)
5555
AA
5555
AA
AAAA or 2AAA
55
AAAA or 2AAA
55
5555
A0
5555
80
5555
AA
AAAA or 2AAA
55
5555
20
Write Address
AS8ERLC128K32
Rev. 1.9 06/06
Write Data} Normal data input
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
12
PRELIMINARY
SPECIFICATION
EEPROM
Austin Semiconductor, Inc.
AS8ERLC128K32
MECHANICAL DEFINITIONS*
ASI Case #703 (Package Designator Q)
4 x D2
4 x D1
DETAIL A
4xD
R
Pin 1
A2
0o - 7o
B
b
L1
SEE DETAIL A
e
A1
A
D3
SYMBOL
A
A1
A2
b
B
D
D1
D2
D3
e
R
L1
ASI PACKAGE SPECIFICATIONS
MIN
MAX
0.123
0.200
0.118
0.186
0.000
0.020
0.013
0.017
0.010 REF
0.800 BSC
0.870
0.890
0.980
1.000
0.936
0.956
0.050 BSC
0.005
0.035
0.045
*All measurements are in inches.
AS8ERLC128K32
Rev. 1.9 06/06
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
13
PRELIMINARY
SPECIFICATION
Austin Semiconductor, Inc.
EEPROM
AS8ERLC128K32
MECHANICAL DEFINITIONS*
ASI Case #703SQ
AS8ERLC128K32
Rev. 1.9 06/06
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
14
PRELIMINARY
SPECIFICATION
Austin Semiconductor, Inc.
EEPROM
AS8ERLC128K32
MECHANICAL DEFINITIONS*
ASI Case #703SQB
AS8ERLC128K32
Rev. 1.9 06/06
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
15
PRELIMINARY
SPECIFICATION
Austin Semiconductor, Inc.
EEPROM
AS8ERLC128K32
MECHANICAL DEFINITIONS*
ASI Case (Package Designator QB)
*All measurements are in inches.
AS8ERLC128K32
Rev. 1.9 06/06
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
16
PRELIMINARY
SPECIFICATION
EEPROM
Austin Semiconductor, Inc.
AS8ERLC128K32
ORDERING INFORMATION
EXAMPLE:
AS8ERLC128K32Q-250/Q
AS8ERLC128K32QB-300/SPACE
Device NumbERLV
Package Type
Speed ns
Process
AS8ERLC128K32
Q
-250
/*
AS8ERLC128K32
Q
-300
/*
AS8ERLC128K32
QB
-250
/*
AS8ERLC128K32
QB
-300
/*
AS8ERLC128K32
SQ
-250
/*
AS8ERLC128K32
SQ
-300
/*
AS8ERLC128K32
SQB
-250
/*
AS8ERLC128K32
SQB
-300
/*
*AVAILABLE PROCESSES
IT = Industrial Temperature Range
XT = Extended Temperature Range
Q= MIL-PRF-38534, Class H compliant
SPACE = ASI Class 'S' Flow
AS8ERLC128K32
Rev. 1.9 06/06
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
17
PRELIMINARY
SPECIFICATION
Austin Semiconductor, Inc.
EEPROM
AS8ERLC128K32
ASI TO DSCC PART NUMBER
CROSS REFERENCE*
Package Designator Q
ASI Part #
AS8ERLC128K32Q
AS8ERLC128K32Q
SMD Part
to be determined
to be determined
Package Designator QB
ASI Part #
AS8ERLC128K32QB
AS8ERLC128K32QB
SMD Part
to be determined
to be determined
* ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD.
AS8ERLC128K32
Rev. 1.9 06/06
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
18