HY62V8400A Series 512Kx8bit CMOS SRAM Document Title 512K x8 bit 3.3V Low Power CMOS slow SRAM Revision History Revision No History Draft Date 03 Revision History Insert Revised - Improved standby current Isb1 : 30uA ¡ æ20uA Jul.06.2000 Final 04 Revised - Change Iccdr Value : 15uA => 20uA Aug.04.2000 Final 05 Marking Information Add Revised - E.T (-25~85°C), I.T (-40~85°C) Part Insert - AC Test Condition Add : 5pF Test Load - VIH max : Vcc + 0.2V => Vcc + 0.3V - VIL min : - 0.2V => - 0.3V Dec.04.2000 Final 06 Changed Logo - HYUNDAI -> hynix - Marking Information Change Apr.30.2001 Final Remark This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 06 / Apr. 2001 Hynix Semiconductor HY62V8400A Series DESCRIPTION FEATURES The HY62V8400A is a high-speed, low power and 4M bits CMOS SRAM organized as 512K words by 8 bits. The HY62V8400A uses Hynix's high performance twin tub CMOS process technology and was designed for high-speed and low power circuit technology. It is particularly well suited for use in high-density and low power system applications. This device has a data retention mode that guarantees data to remain valid at the minimum power supply voltage of 2.0V. • • • • Product Voltage Speed No. (V) (ns) HY62V8400A 3.0~3.6 70/85/100 HY62V8400A-E 3.0~3.6 70/85/100 HY62V8400A-I 3.0~3.6 70/85/100 Note 1. Current value is max. Fully static operation and Tri-state outputs TTL compatible inputs and outputs Low power consumption Battery backup(LL-part) -. 2.0V(min) data retention • Standard pin configuration -. 32pin 525mil SOP -. 32pin 400mil TSOP-II (Standard and Reversed) Operation Current/Icc(mA) 5 5 5 Standby Current(uA) LL 20 30 30 Temperature (°C) 0~70 -25~70 -40~70 PIN CONNECTION A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 Vss 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Vcc A15 A17 /WE A13 A8 A9 A11 /OE A10 /CS I/O8 I/O7 I/O6 I/O5 I/O4 SOP A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Vcc A15 A17 /WE A13 A8 A9 A11 /OE A10 /CS I/O8 I/O7 I/O6 I/O5 I/O4 TSOP-II(Standard) Vcc A15 A17 /WE A13 A8 A9 A11 /OE A10 /CS I/O8 I/O7 I/O6 I/O5 I/O4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 TSOP-II(Reversed) PIN DESCRIPTION ROW DECODER A0 WRITE DRIVER MEMORY ARRAY 512Kx 8 I/O1 DATA I/O BUFFER SENSE AMP COLUMN DECODER Pin Function Chip Select Write Enable Output Enable Address Input Data Input/Output Power(3.0~3.6V) Ground BLOCK DIAGRAM ADD INPUT BUFFER Pin Name /CS /WE /OE A0 ~ A18 I/O1 ~ I/O8 Vcc Vss A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 I/O8 A18 /OE /WE Rev 06 / Apr. 2001 CONTROL LOGIC /CS 2 HY62V8400A Series ORDERING INFORMATION Part No. HY62V8400ALLG HY62V8400ALLG-E HY62V8400ALLG-I HY62V8400ALLT2 HY62V8400ALLT2-E HY62V8400ALLT2-I HY62V8400ALLR2 HY62V8400ALLR2-E HY62V8400ALLR2-I Speed 70/85/100 70/85/100 70/85/100 70/85/100 70/85/100 70/85/100 70/85/100 70/85/100 70/85/100 Power LL-part LL-part LL-part LL-part LL-part LL-part LL-part LL-part LL-part Temp 0~70 °C -25~85 °C -40~85 °C 0~70 °C -25~85 °C -40~85 °C 0~70 °C -25~85 °C -40~85 °C Package SOP SOP SOP TSOP-II (Standard) TSOP-II (Standard) TSOP-II (Standard) TSOP-II (Reversed) TSOP-II (Reversed) TSOP-II (Reversed) ABSOLUTE MAXIMUM RATING (1) Symbol Vcc, VIN, VOUT TA TSTG PD IOUT TSOLDER Parameter Power Supply, Input/Output Voltage Operating Temperature HY62V8400A HY62V8400A-E HY62V8400A-I Storage Temperature Power Dissipation Data Output Current Lead Soldering Temperature & Time Rating -0.5 to 4.0 0 to 70 -25 to 85 -40 to 85 -65 to 150 1.0 50 260 •10 Unit V °C °C °C °C W MA °C•sec Note 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliablity. TRUTH TABLE /CS H L L L /WE X H H L /OE X H L X MODE Deselected Output Disabled Read Write I/O OPERATION High-Z High-Z Data Out Data In Power Standby Active Active Active Note : 1. H=VIH, L=VIL, X=don't care (VIH or VIL) Rev 06 / Apr. 2001 2 HY62V8400A Series RECOMMENDED DC OPERATING CONDITION TA = 0¡ Éto 70¡ É(Normal)/-25°C to 85°C (Extended) /-40°C to 85°C (Industrial), unless otherwise specified. Symbol Parameter Min. Typ. Max. Unit Vcc Supply Voltage 3.0 3.3 3.6 V Vss Ground 0 0 0 V VIH Input High Voltage 2.2 Vcc+0.3 V VIL Input Low Voltage -0.3(1) 0.4 V Note : 1. VIL = -1.5V for pulse width less than 30ns and not 100% tested. DC ELECTRICAL CHARACTERISTICS TA = 0¡ Éto 70¡ É(Normal)/-25°C to 85°C (Extended) /-40°C to 85°C (Industrial), unless otherwise specified. Symbol Parameter Test Condition Min Typ Max Unit ILI Input Leakage Current Vss < VIN < Vcc -1 1 uA ILO Output Leakage Current Vss < VOUT < Vcc, /CS = VIH or -1 1 uA /OE = VIH or /WE = VIL Icc Operating Power Supply /CS = VIL, 5 mA Current VIN = VIH or VIL, II/O = 0mA 40 mA ICC1 Average Operating Current /CS = VIL Min Duty Cycle = 100%, VIN = VIH or VIL, II/O = 0mA ISB TTL Standby Current /CS = VIH , 0.5 mA (TTL Input) VIN = VIH or VIL Standby Current ISB1 /CS > Vcc - 0.2V, LL 20 uA (CMOS Input) VIN > Vcc - 0.2V or LL-E/I 30 uA VIN < Vss + 0.2V VOL Output Low Voltage IOL = 2.1mA 0.4 V VOH Output High Voltage IOH = -1mA 2.2 V Note : Typical values are at Vcc = 3.3V, TA = 25°C CAPACITANCE Temp = 25°C, f= 1.0MHz Symbol Parameter CIN Input Capacitance COUT Output Capacitance Condition VIN = 0V VI/O = 0V Max. 6 8 Unit pF pF Note : This parameter is sampled and not 100% tested Rev 06 / Apr. 2001 3 HY62V8400A Series AC CHARACTERISTICS TA = 0¡ Éto 70¡ É(Normal)/-25°C to 85°C (Extended) /-40°C to 85°C (Industrial), unless otherwise specified. 70ns 85ns 100ns # Symbol Parameter Unit Min. Max. Min. Max. Min Max. READ CYCLE 1 tRC Read Cycle Time 70 85 100 ns 2 tAA Address Access Time 70 85 100 ns 3 tACS Chip Select Access Time 70 85 100 ns 4 tOE Output Enable to Output Valid 40 45 50 ns 5 tCLZ Chip Select to Output in Low Z 10 10 10 ns 6 tOLZ Output Enable to Output in Low Z 5 5 5 ns 7 tCHZ Chip Deselecting to Output in High Z 0 25 0 30 0 30 ns 8 tOHZ Out Disable to Output in High Z 0 25 0 30 0 30 ns 9 tOH Output Hold from Address Change 15 15 15 ns WRITE CYCLE 10 tWC Write Cycle Time 70 85 100 ns 11 tCW Chip Selection to End of Write 60 70 80 ns 12 tAW Address Valid to End of Write 60 70 80 ns 13 tAS Address Set-up Time 0 0 0 ns 14 tWP Write Pulse Width 50 60 70 ns 15 tWR Write Recovery Time 0 0 0 ns 16 tWHZ Write to Output in High Z 0 25 0 30 0 30 ns 17 tDW Data to Write Time Overlap 30 35 40 ns 18 tDH Data Hold from Write Time 0 0 0 ns 19 tOW Output Active from End of Write 5 5 5 ns AC TEST CONDITIONS TA = 0¡ Éto 70¡ É(Normal)/-25°C to 85°C (Extended) /-40°C to 85°C (Industrial), unless otherwise specified. Parameter Value Input Pulse Level 0.4V to 2.2V Input Rise and Fall Time 5ns Input and Output Timing Reference Level 1.5V Output Load tCLZ,tOLZ,tCHZ,tOHZ,tWHZ CL = 5pF + 1TTL Load Others CL = 100pF + 1TTL Load AC TEST LOADS TTL CL(1) Note 1. Including jig and scope capacitance Rev 06 / Apr. 2001 4 HY62V8400A Series TIMING DIAGRAM READ CYCLE 1(Note 1,4) tRC ADDR tAA tOH tACS /CS tCHZ(3) tOE /OE tOLZ(3) Data Out High-Z tOHZ(3) tCLZ(3) Data Valid READ CYCLE 2(Note 1,2,4) tRC ADDR tAA tOH tOH Data Out Previous Data Data Valid READ CYCLE 3(Note 1,2,4) /CS tACS tCLZ(3) Data Out tCHZ(3) Data Valid Notes: 1. A read occurs during the overlap of a low /OE, a high /WE, and a low /CS. 2. /OE = VIL 3. Transition is measured + 200mV from steady state voltage. This parameter is sampled and not 100% tested. 4. /CS in high for the standby, low for active Rev 06 / Apr. 2001 5 HY62V8400A Series WRITE CYCLE 1(1,4,5,8) (/WE Controlled) tWC ADDR tWR(2) tCW /CS tAW /WE tWP tAS Data In tDW High-Z tDH Data Valid tWHZ(3,7) tOW (5) (6) Data Out WRITE CYCLE 2 (Note 1,4,5,8) (/CS Controlled) tWC ADDR tCW tAS tWR(2) /CS tAW tWP /WE tDW Data In Data Out Rev 06 / Apr. 2001 High-Z tDH Data Valid High-Z 6 HY62V8400A Series Notes: 1. A write occurs during the overlap of a low /WE and a low /CS. 2. tWR is measured from the earlier of /CS or /WE going high to the end of write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. If the /CS low transition occur simultaneously with the /WE low transition or after the /WE transition, outputs remain in a high impedance state. 5. Q(data out) is the same phase with the write data of this write cycle. 6. Q(data out) is the read data of the next address. 7. Transition is measured + 200mV from steady state. This parameter is sampled and not 100% tested. 8. /CS in high for the standby, low for active DATA RETENTION ELECTRIC CHARATERISTIC TA = 0¡ Éto 70¡ É(Normal)/-25°C to 85°C (Extended) /-40°C to 85°C (Industrial), unless otherwise specified. Symbol Parameter Test Condition Min Typ Max Unit VDR Vcc for Data Retention /CS > Vcc - 0.2V, 2.0 V VIN > Vcc - 0.2V or VIN < Vss + 0.2V ICCDR Data Retention Current Vcc = 3.0V, /CS >Vcc - 0.2V, LL 20 uA VIN>Vcc-0.2V or LL-E 30 uA VIN<Vss+0.2V LL-I 30 uA tCDR Chip Deselect to Data 0 ns Retention Time tR Operating Recovery Time tRC(2) ns Notes: 1. Typical values are at the condition of TA = 25°C. 2. tRC is read cycle time. DATA RETENTION TIMING DIAGRAM DATA RETENTION MODE VCC 3.0V tCDR tR 2.2V VDR /CS > VCC-0.2V /CS VSS Rev 06 / Apr. 2001 7 HY62V8400A Series PACKAGE INFORMATION 32pin 400mil Thin Small Outline Package Standard(T2) 0.404(10.2620) 0.396(10.0580() UNIT : INCH(mm) MAX. MIN. 0.470(11.9380) 0.462(11.7350) 0.829(21.0570) 0.822(20.8790) GAGE PLANE BASE PLANE 0-5 0.0235(0.5970) 0.050BSC (1.2700) 0.017(0.4500) 0.012(0.3050) 0.047(1.1940) SEATING PLANE 0.0160(0.4060) 0.0059(0.1500) 0.0083(0.2100) 0.0020(0.0500) 0.0047(0.1200) 0.039(0.9910) 32pin 400mil Thin Small Outline Package Reversed(R2) 0.404(10.2620) 0.396(10.0580) UNIT : INCH(mm) MAX. MIN. 0.470(11.9380) 0.462(11.7350) 0.829(21.0570) 0.822(20.8790) GAGE PLANE BASE PLANE 0-5 0.0235(0.5970) 0.050 BSC (1.2700) 0.047(1.1940) 0.039(0.9910) Rev 06 / Apr. 2001 0.017(0.4500) 0.012(0.3050) SEATING PLANE 0.0059(0.1500) 0.0020(0.0500) 0.0160(0.4060) 0.0083(0.2100) 0.0047(0.1200) 8 HY62V8400A Series 32pin 525mil Small Outline Package(G) UNIT : INCH(mm) 0.810(20.574) 0.804(20.422) 0.444(11.278) 0.438(11.125) 0.564(14.326) 0.546(13.868) 0.109(2.769) 0.099(2.515) 0.011(0.279) 0.004(0.102) 0.050(1.27)BSC Rev 06 / Apr. 2001 0.0125(0.318) 0.0061(0.155) 0.020(0.508) 0 deg 0.0425(1.080) 0.014(0.356) 8 deg 0.0235(0.597) 9 HY62V8400A Series MARKING INFORMATION Package SOP TSOP-II Marking Example h y n i x H Y 6 2 V y y w w p h y n i x H Y 6 2 V y y w w p 8 8 4 4 0 0 A c c 0 0 A c c T K O R E A G - s s t K O R E A 2 - s s t Index • hynix • KOREA • HY62V8400A • yy • ww •p • cc • G / T2 • ss •t Note - Capital Letter - Small Letter Rev 06 / Apr. 2001 : hynix Logo : Origin Country : Part Name : Year ( ex : 00 = year 2000, 01 = year 2001 ) : Work Week ( ex : 12 = ww12 ) : Process Code : Power Consumption -L : Low Power - LL : Low Low Power : Package Type -G : SOP - T2 : TSOP-II : Speed - 70 : 70ns - 85 : 85ns : Temperature - Blank : Commercial ( 0 ~ 70 °C ) -E : Extended ( -25 ~ 85 °C ) -I : Industrial ( -40 ~ 85 °C ) : Fixed Item : Non-fixed Item (Except hynix) 10