DISCRETE SEMICONDUCTORS DATA SHEET BT137X-600D Triacs logic level Product specification June 2001 1;3 Semiconductors Product specification Triacs logic level GENERAL DESCRIPTION Passivated, sensitive gate triac in a full pack plastic envelope, intended for use in general purpose bidirectional switching and phase control applications. This device is intended to be interfaced directly to microcontrollers, logic integrated circuits and other low power gate trigger circuits. PINNING - SOT186A PIN BT137X-600D QUICK REFERENCE DATA SYMBOL PARAMETER VDRM IT(RMS) ITSM Repetitive peak off-state voltages RMS on-state current Non-repetitive peak on-state current PIN CONFIGURATION MAX. UNIT 600 8 65 V A A SYMBOL DESCRIPTION case 1 main terminal 1 2 main terminal 2 3 gate T2 T1 G 1 2 3 case isolated LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134). SYMBOL PARAMETER VDRM Repetitive peak off-state voltages IT(RMS) ITSM RMS on-state current Non-repetitive peak on-state current I2t dIT/dt IGM VGM PGM PG(AV) Tstg Tj I2t for fusing Repetitive rate of rise of on-state current after triggering Peak gate current Peak gate voltage Peak gate power Average gate power Storage temperature Operating junction temperature CONDITIONS full sine wave; Ths ≤ 73 ˚C full sine wave; Tj = 25 ˚C prior to surge t = 20 ms t = 16.7 ms t = 10 ms ITM = 12 A; IG = 0.2 A; dIG/dt = 0.2 A/μs T2+ G+ T2+ GT2- GT2- G+ over any 20 ms period MIN. MAX. UNIT - 6001 V - 8 A - 65 71 21 A A A2s -40 - 50 50 50 10 2 5 5 0.5 150 125 A/μs A/μs A/μs A/μs A V W W ˚C ˚C 1 Although not recommended, off-state voltages up to 800V may be applied without damage, but the triac may switch to the on-state. The rate of rise of current should not exceed 6 A/μs. June 2001 1 Rev 1.000 1;3 Semiconductors Product specification Triacs logic level BT137X-600D ISOLATION LIMITING VALUE & CHARACTERISTIC Ths = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Visol R.M.S. isolation voltage from all three terminals to external heatsink f = 50-60 Hz; sinusoidal waveform; R.H. ≤ 65% ; clean and dustfree - - 2500 V Cisol Capacitance from T2 to external f = 1 MHz heatsink - 10 - pF MIN. TYP. MAX. UNIT - 55 4.5 6.5 - K/W K/W K/W MIN. TYP. MAX. UNIT T2+ G+ T2+ GT2- GT2- G+ - 2.5 3.5 3.5 6.5 5 5 5 10 mA mA mA mA T2+ G+ T2+ GT2- GT2- G+ VD = 12 V; IGT = 0.1 A IT = 10 A VD = 12 V; IT = 0.1 A VD = 400 V; IT = 0.1 A; Tj = 125 ˚C VD = VDRM(max); Tj = 125 ˚C 0.25 - 1.6 8.5 1.2 2.5 1.5 1.3 0.7 0.4 0.1 15 20 15 20 10 1.65 1.5 0.5 mA mA mA mA mA V V V mA MIN. TYP. MAX. UNIT - 5 - V/μs - 2 - μs THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS Rth j-hs Thermal resistance junction to heatsink Rth j-a Thermal resistance junction to ambient full or half cycle with heatsink compound without heatsink compound in free air STATIC CHARACTERISTICS Tj = 25 ˚C unless otherwise stated SYMBOL PARAMETER CONDITIONS IGT Gate trigger current VD = 12 V; IT = 0.1 A IL Latching current IH VT VGT Holding current On-state voltage Gate trigger voltage ID Off-state leakage current VD = 12 V; IGT = 0.1 A DYNAMIC CHARACTERISTICS Tj = 25 ˚C unless otherwise stated SYMBOL PARAMETER CONDITIONS dVD/dt Critical rate of rise of off-state voltage Gate controlled turn-on time VDM = 67% VDRM(max); Tj = 125 ˚C; exponential waveform; RGK = 1 kΩ ITM = 12 A; VD = VDRM(max); IG = 0.1 A; dIG/dt = 5 A/μs tgt June 2001 2 Rev 1.000 1;3 Semiconductors Product specification Triacs logic level 12 BT137X-600D Ths(max) / C 71 = 180 Ptot / W 120 10 10 80 8 73 C 89 60 6 30 6 BT137X 8 90 1 IT(RMS) / A 98 4 4 107 2 116 0 0 2 4 6 IT(RMS) / A 2 125 10 8 0 -50 ITSM / A IT 50 Ths / C 100 150 Fig.4. Maximum permissible rms current IT(RMS) , versus heatsink temperature Ths. Fig.1. Maximum on-state dissipation, Ptot, versus rms on-state current, IT(RMS), where α = conduction angle. 1000 0 I TSM 25 time 20 IT(RMS) / A Tj initial = 25 C max 15 100 dI T /dt limit 10 T2- G+ quadrant 5 10 10us 100us 1ms T/s 10ms 0 0.01 100ms Fig.2. Maximum permissible non-repetitive peak on-state current ITSM, versus pulse width tp, for sinusoidal currents, tp ≤ 20ms. 80 60 50 1.6 ITSM IT T 10 Fig.5. Maximum permissible repetitive rms on-state current IT(RMS), versus surge duration, for sinusoidal currents, f = 50 Hz; Ths ≤ 73˚C. ITSM / A 70 0.1 1 surge duration / s VGT(Tj) VGT(25 C) 1.4 time Tj initial = 25 C max 1.2 40 1 30 0.8 20 0.6 10 0 1 10 100 Number of cycles at 50Hz 0.4 -50 1000 Fig.3. Maximum permissible non-repetitive peak on-state current ITSM, versus number of cycles, for sinusoidal currents, f = 50 Hz. June 2001 0 50 Tj / C 100 150 Fig.6. Normalised gate trigger voltage VGT(Tj)/ VGT(25˚C), versus junction temperature Tj. 3 Rev 1.000 1;3 Semiconductors Product specification Triacs logic level 3 BT137X-600D IGT(Tj) IGT(25 C) 25 Tj = 125 C Tj = 25 C T2+ G+ T2+ GT2- GT2- G+ 2.5 IT / A 2 max typ 20 Vo = 1.264 V Rs = 0.0378 Ohms 15 1.5 10 1 5 0.5 0 -50 0 50 Tj / C 100 0 150 0.5 1 1.5 VT / V 2 2.5 3 Fig.10. Typical and maximum on-state characteristic. Fig.7. Normalised gate trigger current IGT(Tj)/ IGT(25˚C), versus junction temperature Tj. 3 0 IL(Tj) IL(25 C) 10 Zth j-hs (K/W) with heatsink compound without heatsink compound 2.5 unidirectional 1 2 bidirectional 1.5 0.1 1 P D tp t 0.5 0 -50 0 50 Tj / C 100 0.01 10us 150 1ms 10ms 0.1s 1s 10s tp / s Fig.11. Transient thermal impedance Zth j-hs, versus pulse width tp. Fig.8. Normalised latching current IL(Tj)/ IL(25˚C), versus junction temperature Tj. 3 0.1ms IH(Tj) IH(25C) 1000 dVD/dt (V/us) 2.5 100 2 1.5 10 1 0.5 0 -50 0 50 Tj / C 100 1 150 50 100 150 Tj / C Fig.9. Normalised holding current IH(Tj)/ IH(25˚C), versus junction temperature Tj. June 2001 0 Fig.12. Typical, critical rate of rise of off-state voltage, dVD/dt versus junction temperature Tj. 4 Rev 1.000 1;3 Semiconductors Product specification Triacs logic level BT137X-600D MECHANICAL DATA Dimensions in mm Net Mass: 2 g 10.3 max 4.6 max 3.2 3.0 2.9 max 2.8 Recesses (2x) 2.5 0.8 max. depth 6.4 15.8 max. 19 max. 15.8 max seating plane 3 max. not tinned 3 2.5 13.5 min. 1 0.4 2 3 M 1.0 (2x) 0.6 2.54 0.9 0.7 0.5 2.5 5.08 1.3 Fig.13. SOT186A; The seating plane is electrically isolated from all terminals. Notes 1. Refer to mounting instructions for F-pack envelopes. 2. Epoxy meets UL94 V0 at 1/8". June 2001 5 Rev 1.000 NXP Semiconductors Legal information DATA SHEET STATUS DOCUMENT STATUS(1) PRODUCT STATUS(2) DEFINITION Objective data sheet Development This document contains data from the objective specification for product development. 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