WEDC EDI8F81024C 1mx8 static ram cmos, module Datasheet

White Electronic Designs
EDI8F81024C
1Mx8 Static RAM CMOS, Module
FEATURES
DESCRIPTION
1024Kx8 bit CMOS Static
Random Access Memory
•
•
•
•
Access Times 70 thru 100ns
Data Retention Function (EDI8F81024LP)
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
High Density Packaging
• 36 Pin SIP, No. 62
Single +5V (±10%) Supply Operation
*This product is subject to change without notice.
The EDI8F81024C is a 8Mb CMOS Static RAM based on eight
128Kx8 Static RAMs mounted on a multi-layered epoxy laminate
(FR4) substrate.
A version featuring Low Power with Data Retention (EDI8F81024LP)
is also available.
The EDI8F81024C is offered in a double sided, 36 pin single-in-line
Package (SIP). Surface mount SIP technology is a cost effective
solution to very high packing density requirements.
All inputs and outputs are TTL compatible and operate from a single
5V supply. Fully asynchronous, the EDI8F81024C requires no clocks
or refreshing for operation.
PIN NAMES
PIN CONFIGURATIONS AND BLOCK DIAGRAM
NC
VCC
W#
DQ2
DQ3
DQ0
A1
A2
A3
A4
VSS
DQ5
A10
A11
A5
A13
A14
A19
E#
A15
A16
A12
A18
A6
DQ1
VSS
A0
A7
A8
A9
DQ7
DQ4
DQ6
A17
VCC
G#
AØ-A19
E#
W#
G#
DQØ-DQ7
VCC
VSS
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
A0-A16
W#
G#
A19
A18
A17
E#
Address Inputs
Chip Enable
Write Enable
Output Enable
Common Data Input/Output
Power (+5V±10%)
Ground
No Connection
DEC
DQ0-DQ7
128K
X8
128K
X8
128K
X8
128K
X8
128K
X8
128K
X8
128K
X8
128K
X8
PIN OUT
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2002
Rev. 8
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
RECOMMENDED DC OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative to VSS
Operating Temperature TA (Ambient)
Commercial
Industrial
Storage Temperature
Plastic
Power Dissipation
Output Current
EDI8F81024C
-0.5V to 7.0V
0°C to +70°C
-40°C to +85°C
-55°C to +125°C
1 Watt
20 mA
Parameter
Sym
Min
Typ
Max
Supply Voltage
VCC
4.5
5.0
5.5
Units
V
Supply Voltage
VSS
0
0
0
V
Input High Voltage
VIH
2.2
–
6.0
V
Input Low Voltage
VIL
-0.3
–
0.8
V
AC TEST CONDITIONS
VSS to 3.0V
5ns
1.5V
1TTL, CL = 100pF
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
*Stress greater than those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions greater
than those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
(note: For TEHQZ,TGHQZ and TWLQZ, CL = 5pF)
DC ELECTRICAL CHARACTERISTICS
Parameter
Sym
Conditions
Operating Power Supply Current
ICC1
Standby (TTL) Power Supply Current
ICC2
Full Standby Power Supply Current
(CMOS)
ICC3
E# ≥ VCC-0.2V
VIN ≥ VCC-0.2V or
VIN ≤ 0.2V
ILI
VIN = 0V to VCC
Output Leakage Current
ILO
Output High Voltage
VOH
Output Low Voltage
VOL
Input Leakage Current
Min
Typ*
Max
Units
W#, E# = VIL, II/O = 0mA, Min Cycle
80
130
mA
E# ≥ VIH, VIN ≤ VIL or VIN ≥ VIH
40
90
mA
10
400
20
950
mA
µA
–
–
±10
µA
V I/O = 0V to VCC
–
–
±10
µA
IOH = -1.0mA
2.4
–
–
V
IOL = 2.1mA
–
–
0.4
V
C
LP
*Typical: TA = 25°C, VCC = 5.0V
CAPACITANCE
TRUTH TABLE
(f=1.0MHz, VIN=VCC or VSS)
Parameter
Input Capacitance
(Except DQ Pins)
Sym
Max
Unit
CI
58
pF
ICC1
Capacitance (DQ Pins)
CD/Q
43
pF
ICC1
ICC1
Input (E#) Control Lines
CC
10
pF
Input (W#) Line (G#)
CW
60
pF
G#
E#
W#
Mode
Output
Power
X
H
X
Standby
HIGH Z
ICC2/ICC3
HIGH Z
DOUT
DIN
H
L
H
Output
Deselect
L
X
L
L
H
L
Read
Write
These parameters are sampled, not 100% tested.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2002
Rev. 8
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
EDI8F81024C
AC CHARACTERISTICS READ CYCLE
Symbol
Parameter
Read Cycle Time
JEDEC
TAVAV
Alt.
TRC
70ns
Min
70
85ns
Max
Min
85
100ns
Max
Min
100
Max
Units
ns
ns
Address Access Time
TAVQV
TAA
70
85
100
Chip Enable Access
TELQV
TACS
70
85
100
Chip Enable to Output in Low Z (1)
TELQX
TCLZ
Chip Disable to Output in High Z (1)
TEHQZ
TCHZ
Output Hold from Address Change
TAVQX
TOH
Output Enable to Output Valid
TGLQV
TOE
Output Enable to Output in Low Z (1)
TGLQX
TOLZ
Output Disable to Output in High Z(1)
TGHQZ
TOHZ
5
5
30
5
35
3
3
40
40
3
45
0
0
30
ns
ns
50
0
35
ns
ns
ns
ns
40
ns
Note 1: Parameter guaranteed, but not tested.
READ CYCLE 1 - W# HIGH, G#, E# LOW
TAVAV
A
ADDRESS 1
ADDRESS 2
TAVQV
TAVQX
Q
DATA 2
DATA 1
READ CYCLE 2 - W# HIGH
TAVAV
A
TAVQV
E#
TELQV
TEHQZ
TELQX
G#
TGLQV
TGHQZ
TGLQX
Q
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2002
Rev. 8
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
EDI8F81024C
AC CHARACTERISTICS WRITE CYCLE
Symbol
70ns
85ns
Max
JEDEC
Alt.
Min
Write Cycle Time
TAVAV
TWC
70
85
100
ns
Chip Enable to End of Write
TELWH
TELEH
TCW
TCW
65
65
70
70
80
80
ns
ns
Address Setup Time
TAVWL
TAVEL
TAS
TAS
0
0
0
0
0
0
ns
ns
Address Valid to End of Write
TAVWH
TAVEH
TAW
TAW
65
65
70
70
80
80
ns
ns
Write Pulse Width
TWLWH
TWLEH
TWP
TWP
65
65
70
70
80
80
ns
ns
Write Recovery Time
TWHAX
TEHAX
TWR
TWR
0
0
0
0
0
0
ns
ns
Data Hold Time
TWHDX
TEHDX
TDH
TDH
0
0
0
0
0
0
ns
ns
Write to Output in High Z (1)
TWLQZ
TWHZ
0
Data to Write Time
TDVWH
TDVEH
TDW
TDW
30
30
35
35
40
40
ns
ns
Output Active from End of Write (1)
TWHQX
TWLZ
5
5
5
ns
30
Min
100ns
Parameter
Max
0
Min
35
0
Max
40
Units
ns
Note 1: Parameter guaranteed, but not tested.
WRITE CYCLE 1 - W# CONTROLLED
TAVAV
A
E#
TELWH
TWHAX
TAVWH
TWLWH
W#
TAVWL
TDVWH
D
TWHDX
DATA VALID
TWHQX
TWLQZ
HIGH Z
Q
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2002
Rev. 8
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
EDI8F81024C
WRITE CYCLE 2 - E# CONTROLLED
TAVAV
A
TAVEL
TELEH
E#
TAVEH
TEHAX
TWLEH
W#
TDVEH
D
TEHDX
DATA VALID
HIGH Z
Q
Characteristic
Sym
Test Conditions
Data Retention Voltage
Data Retention Quiescent Current
VCC
ICCDR
VCC = 0.2V
E# ≥ VCC -0.2V
VIN ≥ VCC -0.2V
Chip Disable to Data Retention Time (1)
TCDR
or VIN ≤ 0.2V
Operation Recovery Time (1)
VCC
Min
2V
3V
TR
Typ
Max
Unit
2
–
–
–
25
50
70°C
–
300
450
85°C
–
400
550
V
µA
µA
0
–
–
–
ns
TAVAV*
–
–
–
ns
Note 1: Parameter guaranteed, but not tested.
* Read Cycle Time
DATA RETENTION E# CONTROLLED
DATA RETENTION MODE
4.5V
VCC
4.5V
VCC
TCDR
E#
TR
E#≥VDD-0.2V
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2002
Rev. 8
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
EDI8F81024C
ORDERING INFORMATION
Standard Power
EDI8F81024C70BSC
Low Power with
Data Retention
Speed
(ns)
Package
No.
EDI8F81024LP70BSC
70
62
EDI8F81024C85BSC
EDI8F81024LP85BSC
85
62
EDI8F81024C100BSC
EDI8F81024LP100BSC
100
62
Note: To order an Industrial grade product substitute the letter C in the Suffix with the letter I,
e.g. EDI8F81024C70BSC becomes EDI8F81024C70BSI.
PACKAGE DESCRIPTION
PACKAGE NO. 62: 36 PIN SINGLE-IN-LINE PACKAGE
.200
MAX.
4.040 MAX.
.050
.575
MAX.
.050
.175
.125
.100 TYP.
.270
MAX.
35 X .100
3.500 REF.
ALL DIMENSIONS ARE IN INCHES
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2002
Rev. 8
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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