IRMCF588 Dual Motor High Performance Sensorless Control IC Description IRMCF588 is a high performance Flash based motion control IC designed and optimized for complete air conditioner control which contains two kinds of computation engines integrated into one chip. There are two TM Motion Control Engines (MCE ) for sensorless control of permanent magnet motors and the other is an 8-bit high-speed microcontroller (8051). The user can program a motion control algorithm by connecting these control elements using a graphic compiler. Key components of the complex sensorless control algorithms, such as the Angle Estimator, are provided as complete pre-defined control blocks. A unique analog/digital circuit and algorithm fully supports single shunt or leg shunt current reconstruction. IRMCF588 performs a PFC (Power Factor Correction) function in addition to the motor control. IRMCF588 comes in a 100 pin QFP package. Features • • • • • • • • • • • • • • • • Product Summary TM Dual MCE (Flexible Motion Control Engine) Dedicated computation engine for high efficiency sinusoidal sensorless motor control Built-in hardware peripheral for single or two shunt current feedback reconstruction and OP amp analog circuits Integrated temperature sensor Supports both interior and surface permanent magnet motor sensorless control Zero speed sensorless control for ultra-low speed operation Dedicated PFC PWM for digital PFC control Loss minimization Space Vector PWM Five-channel analog output (PWM) Embedded 8-bit high speed microcontroller (8051) for flexible I/O and man-machine control JTAG programming port for emulation/debugger Two Serial communication interface (UART) I2Cserial interface Watchdog timer with independent internal clock Internal 64 Kbyte flash plus 16Kbyte OTP memory 3.3V single supply Factory calibrated analog inputs Base Part Number Package Type IRMCF588 LQFP100 1 www.irf.com Maximum clock input (fcrystal) Maximum Internal clock (SYSCLK) Maximum 8051 clock (8051CLK) Sensorless control computation time TM MCE computation data range 8051 Program Flash 8051/MCE Data RAM MCE Program RAM MCE Program OTP GateKill latency (digital filtered) PWM carrier frequency A/D input channels A/D converter resolution A/D converter conversion speed Analog output (PWM) resolution UART baud rate (typ) Number of digital I/O (max) Package (lead free) Typical 3.3V operating current Standard Pack 60 MHz 120MHz 30MHz 35 μsec@100MHz 16 bit signed 52KB 2 x 4KB 2 x 12KB 16KB 2 μsec 20 bits/ SYSCLK 15 12 bits 2 μsec 8 bits 57.6K bps 31 QFP100 50mA Orderable Part Number Form Quantity Tray 900 IRMCF588QTY Tape & Reel 1000 IRMCF588QTR © 2015 International Rectifier February 20, 2015 IRMCF588 Table of Contents 1 OVERVIEW .................................................................................................................................................................... 5 2 PINOUT ......................................................................................................................................................................... 6 3 IRMCF588 BLOCK DIAGRAM AND MAIN FUNCTIONS .................................................................................................... 7 4 APPLICATION CONNECTION AND PIN FUNCTION .......................................................................................................... 9 4.1 4.2 4.3 4.4 4.5 4.6 5 8051 PERIPHERAL INTERFACE GROUP .................................................................................................................................. 11 MOTION PERIPHERAL INTERFACE GROUP .............................................................................................................................. 12 ANALOG INTERFACE GROUP ............................................................................................................................................... 13 POWER INTERFACE GROUP ................................................................................................................................................. 14 TEST INTERFACE GROUP .................................................................................................................................................... 14 FACTORY USE GROUP ........................................................................................................................................................ 14 DC CHARACTERISTICS.................................................................................................................................................. 15 5.1 5.2 5.3 5.4 5.5 5.5 5.6 5.7 6 ABSOLUTE MAXIMUM RATINGS .......................................................................................................................................... 15 SYSTEM CLOCK FREQUENCY AND POWER CONSUMPTION ......................................................................................................... 15 DIGITAL I/O DC CHARACTERISTICS ...................................................................................................................................... 16 ANALOG I/O DC CHARACTERISTICS...................................................................................................................................... 17 A/D ACCURACY............................................................................................................................................................... 17 UNDER VOLTAGE LOCKOUT DC CHARACTERISTICS ................................................................................................................... 17 ITRIP COMPARATOR DC CHARACTERISTICS ............................................................................................................................. 18 AREF CHARACTERISTICS .................................................................................................................................................... 18 AC CHARACTERISTICS .................................................................................................................................................. 19 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 DIGITAL PLL AC CHARACTERISTICS ...................................................................................................................................... 19 ANALOG TO DIGITAL CONVERTER AC CHARACTERISTICS ........................................................................................................... 20 OP AMP AC CHARACTERISTICS ............................................................................................................................................ 21 SYNC TO SVPWM AND A/D CONVERSION AC TIMING .......................................................................................................... 22 GATEKILL TO SVPWM AC TIMING ................................................................................................................................... 23 INTERNAL OVERCURRENT TRIP AC TIMING ............................................................................................................................ 23 INTERRUPT AC TIMING ...................................................................................................................................................... 24 2 I C AC TIMING ................................................................................................................................................................ 25 UART AC TIMING ............................................................................................................................................................ 26 CAPTURE INPUT AC TIMING ......................................................................................................................................... 27 JTAG AC TIMING ......................................................................................................................................................... 28 7 I/O STRUCTURE........................................................................................................................................................... 29 8 PIN LIST ....................................................................................................................................................................... 32 9 PACKAGE DIMENSIONS ............................................................................................................................................... 35 10 PART MARKING INFORMATION............................................................................................................................... 36 11 QUALIFICATION INFORMATION............................................................................................................................... 36 2 www.irf.com © 2015 International Rectifier February 20, 2015 IRMCF588 List of Tables Table 1. Analog channel sensing functions in Leg and Single Shunt Modes ............................................ 13 Table 2. Absolute Maximum Ratings ........................................................................................................ 15 Table 3. System Clock Frequency.............................................................................................................. 15 Table 4. Digital I/O DC Characteristics ...................................................................................................... 16 Table 7. UVcc DC Characteristics .............................................................................................................. 18 Table 8. Itrip DC Characteristics ................................................................................................................ 18 Table 9. CMEXT and AREF DC Characteristics ........................................................................................... 18 Table 10. PLL AC Characteristics ............................................................................................................... 19 Table 11 . A/D Converter AC Characteristics ............................................................................................ 20 Table 12 Current Sensing OP Amp AC Characteristics .............................................................................. 21 Table 13. SYNC AC Characteristics ............................................................................................................ 22 Table 14. GATEKILL to SVPWM AC Timing ................................................................................................ 23 Table 15. Itrip AC Timing ........................................................................................................................... 23 Table 16. Interrupt AC Timing ................................................................................................................... 24 Table 17. I2C AC Timing ............................................................................................................................ 25 Table 18. UART AC Timing......................................................................................................................... 26 Table 19. CAPTURE AC Timing .................................................................................................................. 27 Table 20. JTAG AC Timing ......................................................................................................................... 28 Table 21. Pin List ....................................................................................................................................... 34 3 www.irf.com © 2015 International Rectifier February 20,2015 IRMCF588 List of Figures Figure 1. Typical Application Block Diagram Using IRMCF588 .......................................... 5 Figure 2. Pinout of IRMCF588 .......................................................................................... 6 Figure 3. IRMCF588 Block Diagram .................................................................................. 7 Figure 4. IRMCF588 Single Shunt Connection Diagram .................................................... 9 Figure 5. IRMCF588 Analog Front End Diagram ............................................................. 10 Figure 6. Crystal circuit example .................................................................................... 19 Figure 7. Voltage droop and S/H hold time .................................................................... 20 Figure 8. Op amp output capacitor ................................................................................ 21 Figure 9. SYNC timing ..................................................................................................... 22 Figure 10. Gatekill timing ............................................................................................... 23 Figure 11. ITRIP timing ................................................................................................... 23 Figure 12. Interrupt timing ............................................................................................. 24 Figure 13. I2C Timing ...................................................................................................... 25 Figure 14. UART timing .................................................................................................. 26 Figure 15. CAPTURE timing ............................................................................................ 27 Figure 16. JTAG timing ................................................................................................... 28 Figure 17. Compressor, Fan and PFC PWM outputs ....................................................... 29 Figure 18. All digital I/O except PWM output ................................................................. 29 Figure 19. RESET, GATEKILL I/O ...................................................................................... 30 Figure 20. Analog input .................................................................................................. 30 Figure 22 Analog operational amplifier output and AREF I/O structure ........................ 30 Figure 23. VSS,AVSS pin I/O structure ............................................................................ 31 Figure 24. VDD,VDDCAP pin I/O structure...................................................................... 31 Figure 25. XTAL0/XTAL1 pins structure .......................................................................... 31 4 www.irf.com © 2015 International Rectifier February 20,2015 IRMCF588 1 Overview IRMCF588 is a new generation International Rectifier integrated circuit device primarily designed as a one-chip solution for complete two motor inverterized appliance motor control applications. Particular application includes a full DC inverter Air Conditioner which requires two motor sensorless control plus power factor control. Unlike a traditional microcontroller or DSP, the IRMCF588 provides a built-in two parallel running computation engines for TM two closed loop sensorless control algorithm using the unique Flexible Motion Control Engine (MCE ). The TM MCE consists of a collection of control elements, motion peripherals, a dedicated motion control sequencer and dual port RAM to map internal signal nodes. IRMCF588 also employs a unique single shunt current reconstruction circuit to eliminate additional analog/digital circuitry and enables a direct shunt resistor interface to the IC, while still supporting leg shunt current sensing. Motion control programming is achieved using a TM dedicated graphical compiler integrated into the MATLAB/Simulink development environment. Sequencing, user interface, host communication, and upper layer control tasks can be implemented in the 8051 high-speed 8bit microcontroller. The 8051 microcontroller is equipped with a JTAG port to facilitate emulation and debugging. Figure 1 shows a typical application schematic using the IRMCF588 in leg shunt mode. IRMCF588 contains 64K bytes of Flash program memory plus 16K bytes of OTP memory and comes in a 100-pin QFP package. RS232C Serial Comm (Indoor unit) RS232C Serial Comm (Mainnance) IR PFC+Inverter IPM (IRAM630-1562F) DC bus Compressor Motor AC input (100230V) PWM 7 EMI Filter FAULT IRMCF588 Temperature feedback Analog actuators IPM 12 Analog input Analog output 5 PWM 21 Relay, Valves, Switches PFC + 3-Phase HVIC Driver Digital I/O 6 3-Phase HVIC Driver SPM Outdoor Fan 40-60W IR uIPM (IRSM836-035MA) Figure 1. Typical Application Block Diagram Using IRMCF588 5 www.irf.com © 2015 International Rectifier February 20,2015 IRMCF588 10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 1 2 74 3 73 4 72 5 71 6 70 7 69 8 68 9 67 66 10 11 65 12 64 13 63 14 62 15 61 (Top View) 16 60 17 59 18 58 19 57 20 56 21 55 22 54 53 23 24 52 25 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 FS3 FS3 FS4 FS4 P3.4/T0 P1.2/TXD1 VSS P1.1/RXD1 RESET TCK P4.7/TXD2 P5.1/TDI P5.3/TDO P4.6/RXD2 P5.2/TMS P4.5/CAP P3.0 CGATEKILL P4.4 PFCGKILL PFCPWM P1.5 P4.3 CPWMUH CPWMVH P4.1/AOPWM3 P4.2/AOPWM4 P3.7 P2.1 P3.6 P4.0/ITRIP P3.1/AOPWM2 FPWMUL FPWMVL FPWMWL CPWMWL CPWMVL CPWMUL CPWMWH IRMCF588 VSS IPFCIPFC+ IPFCO AVSS VDDCAP FPWMUH FPWMVH FPWMWH VDD VSS IFBF2+ P2.5 P2.6/AOPWM0 P2.7/AOPWM1 IFBF1O IFBC2O IFBC2IFBC2+ IFBF1IFBF1+ AIN0 AIN1 AIN2 AIN3 VDDCAP AIN4 AIN5 VDD IFBC1IFBC1+ IFBC1O VSS VSS VPP AREF AIN7 P1.7 P1.6 P2.4 AIN8 AIN9 FS2 FS1 FS1 FS2 SDA SCL P1.0/T2 XTAL0 XTAL1 IFBF2IFBF2O P2.3 P2.2 P3.2/INT0 P2.0/NMI VDDCAP VSS AIN6 VDD 2 Pinout Figure 2. Pinout of IRMCF588 6 www.irf.com © 2015 International Rectifier February 20,2015 IRMCF588 3 IRMCF588 Block Diagram and Main Functions IRMCF588 block diagram for leg shunt mode is shown in Figure 3. Dual Motion Control Engine 3 Monitoring Speed command D/A ( PWM) Capture 6 Timer Counnter0,1,2 SND Watchdog Timer UART Program Flash 64kB RCV I2C SCL SDA CGATEKILL PFC IGBT PFCGKILL PFC PWM Compressor MCE MCE Program RAM 12kbyte IPFC ADC S/H OP amp 6 8bit CPU Core PORT1 PORT2 Digital I/Os Local RAM 2 kbyte PORT3 PORT 5 8bit uP Address/data bus Host Interface CPWM Low Loss SVPWM Dual Port RAM 2 kbyte Interrupt Control 8 bit ( 8051) microcontroller Ceramic Resonator (4MHz) 4 Low Loss SVPWM Fan MCE OTP 16kB 6 2 Freq Synthesizer IFBC2 AIN0-5 FPWM 3 ADC S/H OP amp 3 4 Dual Port RAM 2 kbyte AIN6-9 TXD2/RXD2, SCL/SCA UART & I2C D/A (PWM) To MCE IFBF1 IFBF2 PX.X 30MHz 120MHz 3 ITRIP MCE Program RAM 12kbyte JTAG IFBC1 ADCL GPIO Port Emulator Debugger 3 2 AOPWM Figure 3. IRMCF588 Block Diagram IRMCF588 contains the following functions for sensorless AC motor control applications: TM Motion Control Engine (MCE ) • Sensorless FOC (complete sensorless field oriented control) • Proportional plus Integral block • Low pass filter • Differentiator and lag (high pass filter) • Ramp • Limit • Angle estimate (sensorless control) • Inverse Clark transformation • Vector rotator • Bit latch • Peak detect • Transition • Multiply-divide (signed and unsigned) 7 www.irf.com 8051 microcontroller • Two 16 bit timer/counters • One 16 bit periodic timer • One 16 bit watchdog timer • One 16 bit capture timer • Up to 31 discrete digital I/Os • Ten-channel 12 bit A/D o Buffered (current sensing) three channels (0 – 1.2V input) o Unbuffered seven channels (0 – 1.2V input) • JTAG port (4 pins) • Up to five channels of analog output (8 bit PWM) • UART © 2015 International Rectifier February 20,2015 IRMCF588 • • • • • • • • • • • • • 2 I C port TM Dual MCE control sequencer Adder TM MCE program memory (12 K byte X 2 ) Divide (signed and unsigned) Subtractor Comparator Counter Accumulator Switch Shift ATAN (arc tangent) Function block (any curve fitting, nonlinear function) 16 bit wide Logic operations (AND, OR, XOR, NOT, NEGATE) • 8 www.irf.com • • 64K byte Flash memory 2K byte data RAM © 2015 International Rectifier February 20,2015 IRMCF588 4 Application connection and Pin function Figure 4 shows the application connections in single shunt mode. Figure 5 shows the analog front end diagram with a single shunt configuration. AC 230V System Clock XTAL0 4MHz Crystal XTAL1 Frequency Synthesizer System clock Watchdog Timer P1.2/TXD P1.1/RXD SDA SCL Other Communication (I2C) Digital I/O Control P2.6/AOPWM0 P2.7/AOPWM1 Analog Output P3.1/AOPWM2 TCLK TDI TSM TDO Compressor MCE Dual Port Memory (2kB) & MCE Memory (12kB) Timers UART (Indoor unit) 8051 CPU RS232C I2C PORT1 PORT2 PORT3 Low Loss Space Vector PWM PFC PWM Current sensing PWM signals 6 CGATEKILL PFCPWM IPFC+ 0.6V S/H IPFCIPFCO 0.6V IFBC1+ Program Flash (64kByte) PWM0 PWM1 PWM2 12bit A/D & MUX S/H HVIC IFBC1IFBC1O IFBC2+ IFBC2- Local RAM (2kByte) JTAG Interface IFBC2O 6 AIN0,AIN1,AIN2, AIN3, AIN4, AIN5 Other analog input Comp Motor System Reset RESET RESET Digital I/O Control P4.1/AOPWM3 Analog Output P4.2/AOPWM4 PORT4 PORT5 PWM3 PWM4 Fan MCE VPP VDDCAP VSS 1.8V 1.8V Voltage Regulator 6 P4.0/ITRIP 0.6V IFBF1+ HVIC S/H IFBF1IFBF1O Local RAM (4kByte) VDD 3.3V PWM signals Current sensing MCE Memory (12kB) Program OTP (16kByte) Fan OTP Programming (6.5V) Low Loss Space Vector PWM 12bit A/D & MUX IFBF2+ S/H IFBF2IFBF2O 4 AIN6,AIN7,AIN9, AIN9 Other analog input IRMCF588 Fan Motor Figure 4. IRMCF588 Single Shunt Connection Diagram 9 www.irf.com © 2015 International Rectifier February 20,2015 IRMCF588 P4.0/ITRIP Comparators Fan Motor Enable/Disable set reset F/F Digital Filter IFBF2O IFBF2- OP amplifier A N A L O G IFBF2+ IFBF1O 0.6V IFBF1- OP amplifier IFBF1+ M U L T I P L E X E R 0.6V AIN6 AIN7 AIN8 AIN9 F/F Enable/Disable Comparator IFBC1O set reset Enable external Gatekill Enable/Disable IFBC1- MCE2 Enable external Gatekill CGATEKILL Compressor Motor 12bit A/D Digital Filter F/F set reset OP amplifier IFBC1+ 0.6V IFBC2O IFBC2- OP amplifier IFBC2+ PFCGKIL Enable/Disable IPFCO IPFC- OP amplifier A N A L O G M U L T I P L E X E R IPFC+ 0.2V AIN0 AIN1 12bit A/D MCE1 AIN2 AC230V AIN3 ADCL AIN5 Figure 5. IRMCF588 Analog Front End Diagram 10 www.irf.com © 2015 International Rectifier February 20,2015 IRMCF588 4.1 8051 Peripheral Interface Group UART Interface P1.2/TXD P1.1/RXD P4.6/TXD2 P4.7/RXD2 Output, Channel 1 Transmit data from IRMCF588 Input, Channel 1 Receive data to IRMCF588 Output, Channel 2 Transmit data from IRMCF588 Input, Channel 2 Receive data to IRMCF588 Discrete I/O Interface P1.0/T2 P1.1/RXD P1.2/TXD P1.5 P1.6 P1.7 P2.0/NMI P2.1 P2.2 P2.3 P2.4 P2.5 P2.6/AOPWM0 P2.7/AOPWM1 P3.0 P3.1/AOPWM2 P3.2/INT0 P3.4/T0 P3.6 P3.7 P4.0/ITRIP P4.1/AOPWM3 P4.2/AOPWM4 P4.3 P4.4 P4.5/CAP P4.6/TXD2 P4.7/RXD2 P5.1/TDI P5.2/TMS P5.3/TDO Input/output port 1.0, can be configured as Timer/Counter 2 input Input/output port 1.1, can be configured as RXD input Input/output port 1.2, can be configured as TXD output Input/output port 1.5 Input/output port 1.6 Input/output port 1.6 Input/output port 2.0, can be configured as non-maskable interrupt input Input/output port 2.1 Input/output port 2.2 Input/output port 2.3 Input/output port 2.4 Input/output port 2.5 Input/output port 2.6, can be configured as AOPWM0 output Input/output port 2.7, can be configured as AOPWM1 output Input/output port 3.0 Input/output port 3.1, can be configured as AOPWM2 output Input/output port 3.2, can be configured as INT0 input Input/output port 3.4, can be configured as T0 input for counter mode Input/output port 3.6 Input/output port 3.7 Input/output port 4.0, can be configured as overcurrent trip input for Fan motor Input/output port 4.1, can be configured as AOPWM3 analog output Input/output port 4.2, can be configured as AOPWM4 analog output Input/output port 4.3 Input/output port 4.4 Input/output port 4.5, can be configured as Capture Timer input Input/output port 4.6, can be configured as UART2 transmit Input/output port 4.7, can be configured as UART2 receive Input port 5.1, configured as JTAG port by default Input port 5.2, configured as JTAG port by default Output port 5.3, configured as JTAG port by default Analog Output Interface P2.6/AOPWM0 Input/output, can be configured as 8-bit PWM output 0 with programmable carrier frequency P2.7/AOPWM1 Input/output, can be configured as 8-bit PWM output 1 with programmable carrier frequency P3.1/AOPWM2 Input/output, can be configured as 8-bit PWM output 2 with programmable carrier frequency P4.1/AOPWM3 Input/output, can be configured as 8-bit PWM output 3 with programmable carrier frequency P4.2/AOPWM4 Input/output, can be configured as 8-bit PWM output with programmable carrier frequency 11 www.irf.com © 2015 International Rectifier February 20,2015 IRMCF588 Crystal Interface XTAL0 XTAL1 Input, connected to crystal Output, connected to crystal Reset Interface RESET Input and Output, system reset, doesn’t require external RC time constant 2 I C Interface SCL SDA 4.2 2 Output, I C clock output 2 Input/output, I C Data line Motion Peripheral Interface Group PWM CPWMUH CPWMUL CPWMVH CPWMVL CPWMWH CPWMWL PFCPWM FPWMUH FPWMUL FPWMVH FPWMVL FPWMWH FPWMWL Fault CGATEKILL PFCGKILL P4.0/ITRIP 12 www.irf.com Output, Compressor motor PWM phase U high side gate signal, internally pulled down by 58kΩ, configured high true at a power up Output, Compressor motor PWM phase U low side gate signal, internally pulled down by 58kΩ, configured high true at a power up Output, Compressor motor PWM phase V high side gate signal, internally pulled down by 58kΩ, configured high true at a power up Output, Compressor motor PWM phase V low side gate signal, internally pulled down by 58kΩ, configured high true at a power up Output, Compressor motor PWM phase W high side gate signal, internally pulled down by 58kΩ, configured high true at a power up Output, Compressor motor PWM phase W low side gate signal, internally pulled down by 58kΩ, configured high true at a power up Output, Compressor motor PFCPWM output signal, internally pulled up by 70kΩ, configured low true at a power up Output, Fan motor PWM phase U high side gate signal, internally pulled down by 58kΩ, configured high true at a power up Output, Fan motor PWM phase U low side gate signal, internally pulled down by 58kΩ, configured high true at a power up Output, Fan motor PWM phase V high side gate signal, internally pulled down by 58kΩ, configured high true at a power up Output, Fan motor PWM phase V low side gate signal, internally pulled down by 58kΩ, configured high true at a power up Output, Fan motor PWM phase W high side gate signal, internally pulled down by 58kΩ, configured high true at a power up Output, Fan motor PWM phase W low side gate signal, internally pulled down by 58kΩ, configured high true at a power up Input, upon assertion this negates all six PWM signals, active low, internally pulled up by 70kΩ Input, upon assertion, this negates PFCPWM signal, active low, internally pulled up by 70kΩ Input/output port 4.0, can be configured as overcurrent trip input for Fan motor according to the setting of active_pol register, pulled up by 49kOhm internal resistor © 2015 International Rectifier February 20,2015 IRMCF588 4.3 Analog Interface Group AVSS AREF Analog power return, (analog internal 1.8V power is shared with VDDCAP) 0.6V buffered output IFBC1+ IFBC1IFBC1O Input, Operational amplifier positive input for compressor motor shunt sensing Input, Operational amplifier negative input for compressor motor shunt sensing Output, Operational amplifier output for compressor motor shunt sensing IFBC2+ IFBC2- Input, Operational amplifier positive input for compressor motor leg shunt sensing Input, Operational amplifier negative input for compressor motor leg shunt sensing IFBC2O Output, Operational amplifier output for compressor motor leg shunt sensing IPFC+ IPFCIPFCO Input, Operational amplifier positive input for PFC current sensing Input, Operational amplifier negative input for PFC current sensing Output, Operational amplifier output for PFC current sensing IFBF1+ IFBF1IFBF1O Input, Operational amplifier positive input for Fan motor shunt sensing Input, Operational amplifier negative input for Fan motor shunt sensing Output, Operational amplifier output for Fan motor shunt sensing IFBF2+ IFBF2IFBF2O Input, Operational amplifier positive input for Fan motor leg shunt sensing Input, Operational amplifier negative input for Fan motor leg shunt sensing Output, Operational amplifier output for Fan motor leg shunt sensing AIN0 Input, DC voltage sensing or Analog input channel 0 (0 – 1.2V), needs to be pulled down to AVSS if unused Input, AC Input voltage sensing or Analog input channel 1 (0 – 1.2V), needs to be pulled down to AVSS if unused Input, Analog input channel 2 (0 – 1.2V), needs to be pulled down to AVSS if unused Input, Analog input channel 3 (0 – 1.2V), needs to be pulled down to AVSS if unused Input, Analog input channel 3 (0 – 1.2V), needs to be pulled down to AVSS if unused Input, Analog input channel 5 (0 – 1.2V), needs to be pulled down to AVSS if unused Input, Analog input channel 6 (0 – 1.2V), associated with Fan MCE, needs to be pulled down to AVSS if unused Input, Analog input channel 7 (0 – 1.2V), associated with Fan MCE, needs to be pulled down to AVSS if unused Input, Analog input channel 8 (0 – 1.2V), associated with Fan MCE, needs to be pulled down to AVSS if unused Input, Analog input channel 9 (0 – 1.2V), associated with Fan MCE, needs to be pulled down to AVSS if unused AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 Analog Channel IPFC IFBC1 IFBC2 AIN1 13 Leg Shunt Mode Single Shunt Mode Pin number(s) PFC Current PFC Current 27,28,29 Motor U Phase Current Motor Shunt Current 19,20,21 Motor V Phase Current 6,7,8 AC Voltage AC Voltage 12 Table 1. Analog channel sensing functions in Leg and Single Shunt Modes www.irf.com © 2015 International Rectifier February 20,2015 IRMCF588 4.4 Power Interface Group VDD VDDCAP VSS 4.5 Test Interface Group P5.2/TMS P5.3/TDO P5.1/TDI TCK 4.6 Digital power (3.3V) Internal 1.8V output, requires capacitors to the pin. Shared with analog power pad internally Note: The internal 1.8V supply is not designed to power any external circuits or devices. Only capacitors should be connected to this pin. System common JTAG test mode input or input digital port for compressor MCE JTAG data output port for compressor MCE JTAG data input, or input digital port for compressor MCE JTAG test clock port for compressor MCE Factory use Group FS1 Pin82 and Pin83 need to be connected and pulled up by 4.7K resistor for factory purpose Pin81 and Pin84 need to be connected and pulled up by 4.7K resistor for factory purpose Pin74 and Pin75 need to be connected and pulled up by 4.7K resistor for factory purpose Pin73 and Pin72 need to be connected and pulled up by 4.7K resistor for factory purpose FS2 FS3 FS4 14 www.irf.com © 2015 International Rectifier February 20,2015 IRMCF588 5 DC Characteristics 5.1 Absolute Maximum Ratings Symbol VDD VIA VID TA TS Parameter Supply Voltage Analog Input Voltage Digital Input Voltage Ambient Temperature Storage Temperature Min Typ Max -0.3 V 3.6 V -0.3 V 1.98 V -0.3 V 6.0 V -40 ˚C 85 ˚C -65 ˚C 150 ˚C Table 2. Absolute Maximum Ratings Condition Respect to VSS Respect to AVSS Respect to VSS Caution: Stresses beyond those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and function of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. 5.2 System Clock Frequency and Power Consumption CAREF = 1nF, CMEXT= 100nF. VDD=3.3V, Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max SYSCLK System Clock 32 120 1 PD Power consumption 150 Table 3. System Clock Frequency Unit MHz mW Note 1) The value is based on the condition of MCE clock=100MHz, 8051 clock 20MHz with an actual motor and PFC running by a typical MCE application program and 8051 code. 15 www.irf.com © 2015 International Rectifier February 20,2015 IRMCF588 5.3 Digital I/O DC Characteristics Symbol VDD1 VIL VIH CIN IL (2) IOL1 Parameter Supply Voltage Input Low Voltage Input High Voltage Input capacitance Input leakage current Low level output current (2) IOH1 (3) IOL2 (3) IOH2 Min 3.0 V -0.3 V 2.0 V - Typ 3.3 V - 8.9 mA 3.6 pF ±10 nA 13.2 mA Max 3.6 V 0.8 V 3.6 V ±1 μA 15.2 mA High level output current Low level output current 12.4 mA 24.8 mA 38 mA VOH = 2.4 V 17.9 mA 26.3 mA 33.4 mA VOL = 0.4 V High level output current 24.6 mA 49.5 mA 81 mA VOH = 2.4 V Condition Recommended Recommended Recommended (1) VO = 3.3 V or 0 V VOL = 0.4 V (1) (1) (1) (1) Table 4. Digital I/O DC Characteristics Note: (1) Data guaranteed by design. (2) Applied to SCL, SDA pins. (3) Applied to all digital I/O pins except SCL and SDA pins. 16 www.irf.com © 2015 International Rectifier February 20,2015 IRMCF588 5.4 Analog I/O DC Characteristics - OP amps for compressor, fan and PFC current sensing CAREF = 1nF. VDD=3.3V, Unless specified, Ta = 25˚C. Symbol Parameter Min VOFFSET Input Offset Voltage VI Input Voltage Range 0V VOUTSW OP amp output 50 mV (1) operating range CIN Input capacitance RFDBK OP amp feedback 5 kΩ resistor OP GAINCL Typ - Max 26 mV 1.2 V 1.2 V Condition VAVDD = 1.8 V Recommended VAVDD = 1.8 V 3.6 pF - 20 kΩ (1) Operating Close loop 80 db Gain Common Mode 80 db Rejection Ratio Op amp output source 1 mA current Op amp output sink 100 μA current Min Voltage for Ain 0 -9 60 mV NA NA Table 5. Analog I/O DC Characteristics CMRR ISRC ISNK Vmin Requested between IFBO and IFB(1) (1) VOUT = 0.6 V (1) VOUT = 0.6 V (1) (1) Note: (1) Data guaranteed by design. 5.5 A/D Accuracy Unless specified, Ta = 25˚C. A/D accuracy for current sensing (IFBC1+,IFBC1-,IFBC1O, IFBC2+,IFBC2-,IFBC2O, IFBF1+,IFBF1-,IFBF1O, IFBF2+,IFBF2-,IFBF2O,IPFC+,IPFC-,IPFCO), and analog input channels (AIN0-AIN9) Symbol ADCerror Parameter Error is the difference between ideal counts and compensated counts for any applied voltage in 0-1.2V range Min - Typ ±10Counts Max - (1) (1) Condition Table 5. A/D Accuracy Note: (1) Characterized not tested at manufacturing. 5.5 Under Voltage Lockout DC characteristics Unless specified, Ta = 25˚C. Symbol Parameter UVCC+ UVcc positive going Threshold UVCCUVcc negative going Threshold 17 www.irf.com Min 2.78 V Typ 3.04 V Max 3.23 V 2.78 V 2.97 V 3.23 V Condition © 2015 International Rectifier February 20,2015 IRMCF588 UVCCH UVcc Hysteresys 73 mV Table 6. UVcc DC Characteristics (1) Note: (1) Data guaranteed by design. 5.6 Itrip comparator DC characteristics Unless specified, VDD=3.3V, Ta = 25˚C. Symbol Parameter Min Typ Max Itrip+ Itrip positive going 1.22V Threshold ItripItrip negative going 1.10V Threshold ItripH Itrip Hysteresys 120mV Table 7. Itrip DC Characteristics 5.7 Condition VDD = 3.3 V VDD = 3.3 V AREF Characteristics CAREF = 1nF. Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max VAREF Buffer Output Voltage 600 mV Load regulation (VDC-0.6) 1 mV ∆Vo PSRR Power Supply Rejection Ratio 75 db Table 8. CMEXT and AREF DC Characteristics Note: (1) Data guaranteed by design. 18 www.irf.com © 2015 International Rectifier Condition VVDD = 3.3 V (1) (1) February 20,2015 IRMCF588 6 AC Characteristics 6.1 Digital PLL AC Characteristics Symbol FCLKIN FPLL FLWPW JS D TLOCK Parameter Crystal input frequency Internal clock frequency Sleep mode output frequency Short time jitter Duty cycle PLL lock time Min 3.2 MHz Typ 4 MHz Max 60 MHz Condition 32 MHz 50 MHz 128 MHz (1) FCLKIN ÷ 256 - - (1) (1) (see figure below) 200 psec 50 % 500 μsec Table 9. PLL AC Characteristics (1) (1) (1) Note: (1) Data guaranteed by design. XTAL0 XTAL1 R1=1MΩ R2=1KΩ Xtal C1=15PF C2=15PF Figure 6. Crystal circuit example 19 www.irf.com © 2015 International Rectifier February 20,2015 IRMCF588 6.2 Analog to Digital Converter AC Characteristics Unless specified, Ta = 25˚C. Symbol Parameter TCONV Conversion time THOLD Sample/Hold maximum hold time Min - Typ - Max 2.05 μsec 10 μsec Condition (1) Voltage droop ≤ 15 LSB (see figure below) Table 10 . A/D Converter AC Characteristics Note: (1) Data guaranteed by design. Input Voltage Voltage droop S/H Voltage tSAMPLE THOLD Figure 7. Voltage droop and S/H hold time 20 www.irf.com © 2015 International Rectifier February 20,2015 IRMCF588 6.3 Op amp AC Characteristics Unless specified, Ta = 25˚C. Symbol Parameter OPSR OP amp slew rate OPIMP TSET OP input impedance Settling time Min - Typ 10 V/μsec Max - - 10 Ω 400 ns - 8 Condition VDD = 3.3 V, CL = (1) 33 pF (1) (2) VDD = 3.3 V, CL = (1) 33 pF Table 11 Current Sensing OP Amp AC Characteristics Note: (1) Data guaranteed by design. (2) To guarantee stability of the operational amplifier, it is recommended to load the output pin by a capacitor of 47pF, see Figure 8. Here typical OP amp connection is shown but all op amp outputs should be loaded with this capacitor value. IRMCF588 IC AVREF External components 47pF Figure 8. Op amp output capacitor 21 www.irf.com © 2015 International Rectifier February 20,2015 IRMCF588 6.4 SYNC to SVPWM and A/D Conversion AC Timing twSYNC SYNC tdSYNC1 IU,IV,IW tdSYNC2 AINx tdSYNC3 CPWMUx,CPWMVx,CPWMWx Figure 9. SYNC timing Unless specified, Ta = 25˚C. Symbol Parameter twSYNC SYNC pulse width tdSYNC1 SYNC to current feedback conversion time tdSYNC2 SYNC to AIN0-9 tdSYNC3 Min - Typ 32 - Max 100 Unit SYSCLK SYSCLK - - 200 SYSCLK 2 SYSCLK SYNC to PWM output delay time Table 12. SYNC AC Characteristics (1) Note: (1) Only any 3 AINx from the compressor AIN channels (AIN0 -AIN6) and any 2 AINx (AIN7 - AIN9) from the fan AIN channels are converted once every SYNC events at the same time and the rest of the channels will be sampled once every 5 SYNC events. 22 www.irf.com © 2015 International Rectifier February 20,2015 IRMCF588 6.5 GATEKILL to SVPWM AC Timing twGK CGATEKILL tdGK PWMUx,PWMVx,PWMWx Figure 10. Gatekill timing Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max twGK GATEKILL pulse width 32 tdGK GATEKILL to PWM 100 output delay Table 13. GATEKILL to SVPWM AC Timing 6.6 Unit SYSCLK SYSCLK Internal Overcurrent trip AC Timing Itrip CPWMUH,CPWMUL, CPWMVH,CPWMVH, CPWMWH,CPWMWL FPWMUH,FPWMUL, FPWMVH,FPWMVH, FPWMWH,FPWMWL tItrip Figure 11. ITRIP timing Unless specified, Ta = 25˚C. Symbol Parameter tITRIP Itrip propagation delay 23 www.irf.com Min Typ Max 100(sysclk)+1.0usec Table 14. Itrip AC Timing © 2015 International Rectifier Unit SYSCLK+usec February 20,2015 IRMCF588 6.7 Interrupt AC Timing twINT P3.2/INT0 tdINT Internal Program Counter Internal Vector Fetch Figure 12. Interrupt timing Unless specified, Ta = 25˚C. Symbol Parameter twINT INT0, NMI Interrupt Assertion Time tdINT INT0, NMI latency 24 www.irf.com Min 4 Typ - Max - 4 Table 15. Interrupt AC Timing Unit SYSCLK SYSCLK © 2015 International Rectifier February 20,2015 IRMCF588 6.8 I2C AC Timing TI2CLK TI2CLK SCL tI2ST1 tI2WSETUP tI2WHOLD tI2RSETUP tI2EN1 tI2RHOLD tI2ST2 tI2EN2 SDA 2 Figure 13. I C Timing Unless specified, Ta = 25˚C. Symbol Parameter 2 TI2CLK I C clock period 2 tI2ST1 I C SDA start time 2 tI2ST2 I C SCL start time 2 tI2WSETUP I C write setup time 2 tI2WHOLD I C write hold time 2 tI2RSETUP I C read setup time 2 tI2RHOLD I C read hold time Min Typ 10 0.25 0.25 0.25 0.25 2 (1) I C filter time 1 2 Table 16. I C AC Timing Max 8192 - Unit SYSCLK TI2CLK TI2CLK TI2CLK TI2CLK SYSCLK SYSCLK Note: 2 2 (1) I C read setup time is determined by the programmable filter time applied to I C communication. 25 www.irf.com © 2015 International Rectifier February 20,2015 IRMCF588 6.9 UART AC Timing TBAUD TXD Data and Parity Bit Start Bit Stop Bit RXD TUARTFIL Figure 14. UART timing Unless specified, Ta = 25˚C. Symbol Parameter TBAUD Baud Rate Period TUARTFIL UART sampling filter (1) period Min - Typ 57600 1/16 Max - Unit bit/sec TBAUD Table 17. UART AC Timing Note: (1) Each bit including start and stop bit is sampled three times at center of a bit at an interval of 1/16 TBAUD. If three sampled values do not agree, then UART noise error is generated. 26 www.irf.com © 2015 International Rectifier February 20,2015 IRMCF588 6.10 CAPTURE Input AC Timing TCAPCLK tCAPHIGH P4.5/CAP tCAPLOW tCRDELAY CREV(H,L) Internal register tCLDELAY CLAST(H,L) Internal register tINTDELAY Interrupt Vector Fetch Interrupt Figure 15. CAPTURE timing Unless specified, Ta = 25˚C. Symbol Parameter Min Typ TCAPCLK CAPTURE input period 8 tCAPHIGH CAPTURE input high time 4 tCAPLOW CAPTURE input low time 4 tCRDELAY CAPTURE falling edge to capture register latch time tCLDELAY CAPTURE rising edge to capture register latch time tINTDELAY CAPTURE input interrupt latency time Table 18. CAPTURE AC Timing 27 www.irf.com Max 4 Unit SYSCLK SYSCLK SYSCLK SYSCLK 4 SYSCLK 4 SYSCLK © 2015 International Rectifier February 20,2015 IRMCF588 6.11 JTAG AC Timing TJCLK TCK tJHIGH tJLOW tCO TDO tJSETUP tJHOLD TDI/TMS Figure 16. JTAG timing Unless specified, Ta = 25˚C. Symbol Parameter Min Typ TJCLK TCK Period tJHIGH TCK High Period 10 tJLOW TCK Low Period 10 tCO TCK to TDO propagation delay 0 time tJSETUP TDI/TMS setup time 4 tJHOLD TDI/TMS hold time 0 Table 19. JTAG AC Timing 28 www.irf.com Max 50 5 Unit MHz nsec nsec nsec - nsec nsec © 2015 International Rectifier February 20,2015 IRMCF588 7 I/O Structure The following figure shows the PWM output (CPWMUH/CPWMUL/CPWMVH/CPWMVL/CPWMWH/CPWMWL/PFCPWM/FPWMUL/FPWMUH/FPWMVL/FPW MVH/FPWMWL/FPWMWH) VDD1 (3.3V) Internal digital circuit High true logic 6.0V PIN 270 Ω 6.0V 58k Ω VSS Figure 17. Compressor, Fan and PFC PWM outputs The following figure shows the digital I/O structure except the PWM output VDD1 (3.3V) Internal digital circuit Low true logic 70k Ω 6.0V PIN 270 Ω 6.0V VSS Figure 18. All digital I/O except PWM output 29 www.irf.com © 2015 International Rectifier February 20,2015 IRMCF588 The following figure shows RESET and CGATEKILL, PFCGKILL I/O for structure. VDD1 (3.3V) RESET GATEKILL circuit 70k Ω 6.0V PIN 270 Ω 6.0V VSS Figure 19. RESET, GATEKILL I/O The following figure shows the analog input structure: VDDCAP(1.8V) Analog input 6.0V PIN 1 Ω Analog Circuit 6.0V AVSS Figure 20. Analog input The following figure shows all analog operational amplifier output pins and AREF pin I/O structure. VDDCAP(1.8V) Analog output 6.0V PIN Analog Circuit 6.0V AVSS Figure 21 Analog operational amplifier output and AREF I/O structure 30 www.irf.com © 2015 International Rectifier February 20,2015 IRMCF588 The following figure shows the VSS,AVSS pin I/O structure VDD AVDD PIN 6.0V Figure 22. VSS,AVSS pin I/O structure The following figure shows the VDD,VDDCAP pin I/O structure PIN 6.0V VSS Figure 23. VDD,VDDCAP pin I/O structure The following figure shows the XTAL0 and XTAL1 pins structure VDDCAP(1.8V) 6.0V PIN 1 Ω 6.0V VSS Figure 24. XTAL0/XTAL1 pins structure 31 www.irf.com © 2015 International Rectifier February 20,2015 IRMCF588 8 Pin List Pin Number 1 Pin Name IFBF2- Internal Pullup /Pull-down Pin Type I 2 3 4 5 P2.5 P2.6/AOPWM0 P2.7/AOPWM1 IFBF1O I/O I/O I/O O 6 IFBC2O O 7 IFBC2- I 8 IFBC2+ I 9 IFBF1- I 10 IFBF1+ I 11 AIN0 I 12 AIN1 I 13 AIN2 I 14 AIN3 I 15 16 VDDCAP AIN4 P I 17 AIN5 I 18 19 VDD IFBC- P I 20 IFBC+ I 21 IFBCO O 22 23 24 25 26 27 VSS VSS VPP AREF VSS IPFC- P P P O P I 32 www.irf.com Description nd Op amp positive input for 2 leg shunt resistor current sensing of Fan motor, 0-1.2V range Discrete programmable I/O Discrete programmable I/O or PWM 0 digital output Discrete programmable I/O or PWM 1 digital output st Op amp output for 1 leg or single shunt resistor current sensing of Fan motor, 0-1.2V range nd Op amp output 2 leg shunt current sensing of compressor motor, 0-1.2V range nd Op amp negative input 2 leg shunt current sensing of compressor motor, 0-1.2V range, needs to be pulled down to AVSS if unused nd Op amp positive input 2 leg shunt current sensing of compressor motor, 0-1.2V range, needs to be pulled down to AVSS if unused st Op amp negative input for 1 leg or single shunt resistor current sensing of Fan motor, 0-1.2V range st Op amp positive input for 1 leg or single shunt resistor current sensing of Fan motor, 0-1.2V range Analog input channel (0 – 1.2V) for DC voltage sensing, needs to be pulled down to AVSS if unused Analog input channel 1, 0-1.2V range, for AC voltage sensing, needs to be pulled down to AVSS if unused Analog input channel 2, 0-1.2V range, needs to be pulled down to AVSS if unused Analog input channel 3, 0-1.2V range, needs to be pulled down to AVSS if unused Internal 1.8V output, Capacitor(s) to be connected Analog input channel 4, 0-1.2V range, needs to be pulled down to AVSS if unused Analog input channel 5, 0 – 1.2V range, needs to be pulled down to AVSS if unused 3.3V digital power st Op amp negative input for 1 leg or single shunt current sensing of compressor motor, 0-1.2V range, needs to be pulled down to AVSS if unused st Op amp positive input for 1 leg or single shunt current sensing of compressor motor, 0-1.2V range, needs to be pulled down to AVSS if unused st Op amp output for 1 leg or single shunt current sensing of compressor motor, 0-1.2V range Analog and Digital Common Analog and Digital Common OTP programming voltage for Fan MCE Analog reference voltage output (0.6V) Analog and Digital Common Op amp negative input for application sensing, 0-1.2V range, needs to be pulled down to AVSS if unused © 2015 International Rectifier February 20,2015 IRMCF588 Pin Number 28 Pin Name IPFC+ 29 30 31 32 IPFCO AVSS VDDCAP FPWMUL 33 FPWMVL 34 FPWMWL 35 36 37 38 VDD VSS P3.1/AOPWM2 FPWMUH 39 FPWMVH 40 FPWMWH 41 CPWMWL 42 CPWMVL 43 CPWMUL 44 CPWMWH 45 46 47 48 P3.7 P2.1 P3.6 P4.0/ITRIP 49 50 51 P4.1/AOPWM3 P4.2/AOPWM4 CPWMVH 52 CPWMUH 53 54 55 56 57 58 P4.3 P1.5 PFCPWM PFCGKILL P4.4 CGATEKILL 59 60 61 62 P3.0 P4.5/CAP P5.2/TMS P4.6/RXD2 33 www.irf.com Internal Pullup /Pull-down 58 kΩ Pull down 58 kΩ Pull down 58 kΩ Pull down 58 kΩ Pull down 58 kΩ Pull down 58 kΩ Pull down 58 kΩ Pull down 58 kΩ Pull down 58 kΩ Pull down 58 kΩ Pull down 49 kΩ Pull up 58 kΩ Pull down 58 kΩ Pull down 70 kΩ Pull up 70 kΩ Pull up 70 kΩ Pull up Pin Type I O P P O O O P P I/O O O O O O O O I/O I/O I/O I/O I/O I/O O O I/O I/O I/O I I/O I I/O I/O I I/O Description Op amp positive input for application sensing, 0-1.2V range, needs to be pulled down to AVSS if unused Op amp output for application sensing, 0-1.2V range Analog common Internal 1.8V output, Capacitor(s) to be connected PWM gate drive for phase U low side of Fan motor, configurable either high or low true PWM gate drive for phase V low side of Fan motor, configurable either high or low true PWM gate drive for phase W low side of Fan motor, configurable either high or low true 3.3V power Analog and Digital common Discrete programmable I/O or PWM 2 digital output PWM gate drive for phase U high side of Fan, configurable either high or low true PWM gate drive for phase V high side of Fan motor, configurable either high or low true. PWM gate drive for phase W high side of Fan motor, configurable either high or low true PWM gate drive for phase W low side of compressor motor, configurable either high or low true. PWM gate drive for phase V low side of compressor motor, configurable either high or low true PWM gate drive for phase U low side of compressor motor, configurable either high or low true PWM gate drive for phase W high side of compressor motor, configurable either high or low true Discrete programmable I/O Discrete programmable I/O Discrete programmable I/O Discrete programmable I/O or Fan motor overcurrent trip input, active low Discrete programmable I/O or PWM 3 digital output Discrete programmable I/O or PWM 4 digital output PWM gate drive for phase V high side of compressor motor, configurable either high or low true PWM gate drive for phase U high side of compressor motor, configurable either high or low true Discrete programmable I/O Discrete programmable I/O PFC PWM gate drive , configurable either high or low PFCPWM shutdown input, active low input. Discrete programmable I/O PWM shutdown input, configurable digital filter, active low input. Discrete programmable I/O Discrete programmable I/O or Capture timer input JTAG test mode select or digital input port nd Discrete programmable I/O, 2 UART receive © 2015 International Rectifier February 20,2015 IRMCF588 Pin Number 63 64 65 66 67 68 69 70 71 Pin Name P5.3/TDO P5.1/TDI P4.7/TXD2 TCK RESET P1.1/RXD1 VSS P1.2/TXD1 P3.4/T0 Internal Pullup /Pull-down Pin Type O I I/O I I I/O P I/O I/O 72 73 74 75 76 77 78 79 80 81 82 83 84 85 FS4 FS4 FS3 FS3 XTAL0 XTAL1 P1.0/T2 SCL SDA FS2 FS1 FS1 FS2 AIN9 I/O I/O I/O I/O I O I/O I/O I/O I/O I/O I/O I/O I 86 AIN8 I 87 88 89 90 P2.4 P1.6 P1.7 AIN7 I/O I/O 91 92 93 94 95 VDD AIN6 VSS VDDCAP P2.0/NMI P I P P I/O 96 97 98 99 P3.2/INT0 P2.2 P2.3 IFB2O I/O I/O I/O O 100 IFB2- I I Description JTAG test data output JTAG test data input or digital input port nd Discrete programmable I/O, 2 UART transmit JTAG test clock Reset, low true, Schmitt trigger input UART receiver input or Discrete programmable I/O Analog and Digital common UART transmitter output or Discrete programmable I/O Discrete programmable I/O or Timer/Counter 2 input Factory use, need to be connected to pin73 Factory use, need to be connected to pin72 Factory use, need to be connected to pin75 Factory use, need to be connected to pin74 Crystal input Crystal output Discrete programmable I/O or Timer/Counter 2 input 2 I C clock output (open drain, need pull up) 2 I C data (open drain, need pull up) Factory use, need to be connected to pin84 Factory use, need to be connected to pin83 Factory use, need to be connected pin82 Factory use, need to be connected to pin81 Analog input channel (0 – 1.2V), needs to be pulled down to AVSS if unused Analog input channel (0 – 1.2V), needs to be pulled down to AVSS if unused Discrete programmable I/O Discrete programmable I/O Discrete programmable I/O Analog input channel (0 – 1.2V), needs to be pulled down to AVSS if unused 3.3V digital power Analog input channel (0 – 1.2V Digital common Internal 1.8V output, Capacitor(s) to be connected Discrete programmable I/O or Non-maskable Interrupt input Discrete programmable I/O or Interrupt 0 input Discrete programmable I/O Discrete programmable I/O nd Op amp output for 2 leg shunt resistor current sensing of Fan motor, 0-1.2V range nd Op amp negative input for 2 leg shunt resistor current sensing of Fan motor, 0-1.2V range Table 20. Pin List 34 www.irf.com © 2015 International Rectifier February 20,2015 IRMCF588 9 Package Dimensions 35 www.irf.com © 2015 International Rectifier February 20,2015 IRMCF588 10 Part Marking Information IR Logo Part Number Date Code IRMCF588 YWWP XXXXXX Production Lot Pin 1 Indentifier Part Marking 11 Qualification Information †† Qualification Level Industrial (per JEDEC JESD 47E) Moisture Sensitivity Level MSL3 (per IPC/JEDEC J-STD-020C) ††† Machine Model Class B (per JEDEC standard JESD22-A114D) Human Body Model Class 2 (per EIA/JEDEC standard EIA/JESD22-A115-A) ESD RoHS Compliant Yes † Qualification standards can be found at International Rectifier’s web site http://www.irf.com/ †† Higher qualification ratings may be available should the user have such requirements. Please contact your International Rectifier sales representative for further information. ††† Higher MSL ratings may be available for the specific package types listed here. Please contact your International Rectifier sales representative for further information. Note: Test condition for Temperature Cycling test is -40C to 125C. Revision History 36 www.irf.com © 2015 International Rectifier February 20,2015 IRMCF588 Data and Specifications are subject to change without notice IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information 37 www.irf.com © 2015 International Rectifier February 20,2015