ICST ICS2304NZGI-1LF Low skew pci/pci-x buffer Datasheet

ICS2304NZ-1
LOW SKEW PCI/PCI-X BUFFER
Description
Features
The ICS2304NZ-1 is a high-performance, low skew,
low jitter PCI/PCI-X clock driver. It is designed to
distribute high-speed signals in PCI/PCI-X applications
operating at speeds from 0 to 140 MHz.
•
•
•
•
•
•
•
The ICS2304NZ-1 is characterized for operation from
-40°C to +85°C for automotive and industrial
applications.
Packaged in 8-pin TSSOP (4.4 mm body)
Available in Pb (lead) free package
Frequency range of 0 to 140 MHz
Less than 100 ps skew between outputs
Distribute one clock input to one bank of four outputs
Operating voltage of 3.3 V ±10%
Available in commercial and industrial temperature
ranges
Block Diagram
OE
Logic
Control
CLK0
CLK1
CLK_IN
CLK2
CLK3
1
MDS 2304NZ-1 C
I n t e gra te d C i r c u i t S y s t e m s
●
525 Race Stre et, San Jo se, CA 9 5126
Revision 062105
●
te l (40 8) 2 97-12 01
●
w w w. i c st . c o m
ICS2304NZ-1
LOW SKEW PCI/PCI-X BUFFER
Pin Assignment
Functionality Table
Inputs
CLK_I N
1
8
CLK3
OE
2
7
CLK2
CLK0
3
6
VDD
GND
4
5
CLK1
Outputs
CLK_IN
OE
CLK(3:0)
0
0
Tristate
0
1
0
1
0
Tristate
1
1
1
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
1
CLK_IN
Input
Input reference frequency.
2
OE
Input
Output Enable. When OE is low, it tri-states clock outputs.
3
CLK0
Output
Buffered clock output.
4
GND
Power
Connect to ground.
5
CLK1
Output
Buffered clock output.
6
VDD
Power
Power supply for 3.3 V.
7
CLK2
Output
Buffered clock output.
8
CLK3
Output
Buffered clock output.
2
MDS 2304NZ-1 C
In te grated Circuit Systems
Pin Description
●
525 Ra ce Street, San Jose, CA 9512 6
Revision 062105
●
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
ICS2304NZ-1
LOW SKEW PCI/PCI-X BUFFER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS2304NZ-1. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage Range, VDD
-0.5 V to 4.3 V
Input Voltage Range, VI (see notes 1 and 2)
-0.5 V to VDD + 0.5 V
Output Voltage Range, VO (see notes 1 and 2)
-0.5 V to VDD + 0.5 V
Input Clamp Current, IIK (VI<0 or VI>VDD)
±50 mA
Output Clamp Current, IIK (VO<0 or VO)
±50 mA
Continuous Total Output Current, IO (VO = 0 to VDD)
±50 mA
Package Thermal Impedance, θJA (see note 3): PW
Package
230.5°C/W
Storage Temperature Range, Tstg
-65°C to 150°C
Notes:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current
ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
Recommended Operation Conditions
Parameter
Supply Voltage, VDD
High-level Input Voltage, VIH
Min.
Typ.
Max.
Units
3
3.3
3.6
V
0.7 x VDD
V
0.3 x VDD
V
VDD
V
High-level Output Current, IOH
-24
mA
Low-level Output Current, IOL
24
mA
+85
°C
Low-level Input Voltage, VIL
Input Voltage, VI
0
Operating Free-air Temperature, TA
-40
–
Timing Requirements Over Recommended Ranges of Supply Voltage and Operating
Free-air Temperature
Min.
Clock Frequency, fCLK
0
Max.
Units
140
MHz
3
MDS 2304NZ-1 C
In te grated Circuit Systems
Typ.
●
525 Ra ce Street, San Jose, CA 9512 6
Revision 062105
●
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
ICS2304NZ-1
LOW SKEW PCI/PCI-X BUFFER
Electrical Characteristics at 3.3 V over Recommended Free-air Temperature
Range
VDD = 3.3 V ±10%, TA = -40°C to +85°C (unless stated otherwise)
Parameter
Input Voltage
High-level Output Voltage
Low-level Output Voltage
Symbol
Conditions
VIK
VDD at 3.3 V, II = -18 mA
VOH
VOL
High-level Input Current
IOH
Low-level Input Current
IOL
Input Current
II
Min.
VDD = min to max,
IOH = -1 mA
Typ.
VDD-0.2
3.3
VDD = 3 V, IOH = -24 mA
2
2.3
VDD = 3 V, IOH = -12 mA
2.4
2.7
Max.
Units
-1.2
V
V
VDD = min to max,
IOH = 1 mA
0.222
0.2
VDD = 3 V, IOL = 24 mA
0.61
0.8
VDD = 3 V, IOL = 12 mA
0.31
0.55
VDD = 3 V, VO = 1 V
-53
-40
VDD = 3.3 V, VO = 1.65 V
-54
VDD = 3 V, VO = 2 V
40
VDD = 3.3 V, VO = 1.65 V
V = VDD or VO
53
V
mA
mA
57
0.1
50
µA
Dynamic Supply Current
IDD
Unloaded outputs at
66.67 MHz
13
37
mA
Input Capacitance
(Note 1)
CI
VDD = 3.3 V,
VI = 0V or 3.3 V
3
5
pF
Output Capacitance
(Note 1)
CO
VDD = 3.3 V,
VI = 0V or 3.3 V
3.2
pF
Note 1: Guaranteed by design, not 100% tested in production.
4
MDS 2304NZ-1 C
In te grated Circuit Systems
●
525 Ra ce Street, San Jose, CA 9512 6
Revision 062105
●
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
ICS2304NZ-1
LOW SKEW PCI/PCI-X BUFFER
Switching Characteristics at 3.3 V over Recommended Ranges of Supply
Voltage and Operating Free-air Temperature
VDD = 3.3 V ±10%, TA = -40°C to 85°C (unless stated otherwise)
Parameter
Symbol Conditions
Min.
Typ.
Max.
Units
High-to-Low Propagation Delay (Note 1)
tPLH
VO = VDD/2
1.8
3.1
3.8
ns
Low-to-High Propagation Delay (Note 1)
tPHL
VO = VDD/2
1.8
2.9
3.8
ns
Output Skew Window (Note 1)
TSK(o)
VO = VDD/2
50
100
ps
Pulse Skew = | tPLH - tPHL | (Note 1)
TSK(p)
VO = VDD/2
300
ps
Process Skew (Note 1)
TSK(pr)
VO = VDD/2
500
ps
CLKIN High Time (Note1)
Thigh
CLKIN Low Time (Note1)
Tlow
66 MHz
6
ns
140 MHz
3
ns
66 MHz
6
ns
140 MHz
3
ns
Rise Time (Note 1)
Tr
VOL=0.8 V,
VOH=2.0 V
1.2
2.0
ns
Fall Time (Note 1)
Tf
VOH=2.0 V,
VOL=0.8 V
1.2
2.0
ns
200
ps
40
ps
Cycle-to-Cycle Jitter
Tcyc-cyc
Tj1s
Jitter, 1-Sigma
Loaded
outputs
10,000 cycles
14
Note 1: Guaranteed by design, not 100% tested in production.
5
MDS 2304NZ-1 C
In te grated Circuit Systems
●
525 Ra ce Street, San Jose, CA 9512 6
Revision 062105
●
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
ICS2304NZ-1
LOW SKEW PCI/PCI-X BUFFER
Parameter Measurement Information
VDD
50% VDD
CLKIN
0V
tPLH
CLK0-CLK3
tPHL
2.0 V
50% VDD
0.8 V
2.0 V
50% VDD
0.8 V
tr
VOH
VOL
tf
Figure 2. Voltage Thresholds for Propagation Delay (tpd) Measurements
50% VDD
Any CLK
50% VDD
Any CLK
tSK(p)
Figure 3. Output Skew
Parameter
Value
Unit
VIH (MIN)
0.5 VDD
V
VIL (MAX)
0.35 VDD
V
0.4 VDD
V
VTEST
tCYC
tHIGH
0.5 VDD
VIH (MIN)
tLOW
VTEST
VIL (MAX)
0.2 VDD
0.4 VDD
Peak-to-Peak (minimum)
Figure 4. Clock Waveform
6
MDS 2304NZ-1 C
In te grated Circuit Systems
●
525 Ra ce Street, San Jose, CA 9512 6
Revision 062105
●
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
ICS2304NZ-1
LOW SKEW PCI/PCI-X BUFFER
VOH - High-level Output Voltage (V)
Figure 5. Supply Current vs. Frequency
Figure 6. High-level Output Voltage vs. High-level Output Current
7
MDS 2304NZ-1 C
In te grated Circuit Systems
●
525 Ra ce Street, San Jose, CA 9512 6
Revision 062105
●
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
ICS2304NZ-1
VOL - Low-level Output Voltage (V)
LOW SKEW PCI/PCI-X BUFFER
Figure 7. Low-level Output Voltage vs. Low-level Output Current
8
MDS 2304NZ-1 C
In te grated Circuit Systems
●
525 Ra ce Street, San Jose, CA 9512 6
Revision 062105
●
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
ICS2304NZ-1
LOW SKEW PCI/PCI-X BUFFER
Marking Diagram
5
1
BOTTOM
TOP
BOTTOM
Marking Diagram (Pb free/industrial)
5
5
$$##
####
YYWW
4NI1L
8
YYWW
04NI1
1
4
TOP
Marking Diagram (industrial)
8
4
1
BOTTOM
TOP
$$##
####
$$##
####
4
$$##
####
1
5
YYWW
04N1L
8
YYWW
304N1
8
Marking Diagram (Pb free)
4
BOTTOM
TOP
Notes:
1. ###### is the lot number.
2. YYWW is the last two digits of the year and week
that the part was assembled.
3. “LF” denotes Pb (lead) free package.
4. Bottom marking: (origin). Origin = country of origin if
not USA.
9
MDS 2304NZ-1 C
In te grated Circuit Systems
●
525 Ra ce Street, San Jose, CA 9512 6
Revision 062105
●
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
ICS2304NZ-1
LOW SKEW PCI/PCI-X BUFFER
Package Outline and Package Dimensions (8-pin TSSOP, 4.40 mm Body, 0.65 mm Pitch)
Package dimensions are kept current with JEDEC Publication No. 95, MO-153
8
Millimeters
Symbol
E1
INDEX
AREA
E
1 2
D
A
A2
Min
A
A1
A2
b
C
D
E
E1
e
L
α
aaa
Inches
Max
Min
-1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
2.90
3.10
6.40 BASIC
4.30
4.50
0.65 Basic
0.45
0.75
0°
8°
-0.10
Max
-0.047
0.002
0.006
0.032
0.041
0.007
0.012
0.0035 0.008
0.114
0.122
0.252 BASIC
0.169
0.177
0.0256 Basic
0.018
0.030
0°
8°
-0.004
A1
c
- Ce
SEATING
PLANE
b
L
aaa C
Ordering Information
Part / Order Number
ICS2304NZG-1
ICS2304NZG-1T
ICS2304NZG-1LF
ICS2304NZG-1LFT
ICS2304NZGI-1
ICS2304NZGI-1T
ICS2304NZGI-1LF
ICS2304NZGI-1LFT
Marking
Shipping Packaging
Package
Temperature
see page 8
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
8-pin TSSOP
8-pin TSSOP
8-pin TSSOP
8-pin TSSOP
8-pin TSSOP
8-pin TSSOP
8-pin TSSOP
8-pin TSSOP
0 to +70° C
0 to +70° C
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
Parts that are ordered with a “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
10
MDS 2304NZ-1 C
In te grated Circuit Systems
●
525 Ra ce Street, San Jose, CA 9512 6
Revision 062105
●
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
Similar pages