TI1 CY74FCT163244APAC 16-bit buffers/line driver Datasheet

Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT163244
CY74FCT163H244
16-Bit Buffers/Line Drivers
SCCS046 - December 1996 - Revised March 2000
Features
• Low power, pin-compatible replacement for LCX and
LPT families
• 5V tolerant inputs and outputs
• 24 mA balanced drive outputs
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for reduced noise
• FCT-C speed at 4.1 ns
• Latch-up performance exceeds JEDEC standard no. 17
• Typical output skew < 250 ps
• Industrial temperature range of –40˚C to +85˚C
• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)
• Typical Volp (ground bounce) performance exceeds Mil
Std 883D
• VCC = 2.7V to 3.6V
• ESD (HBM) > 2000V
CY74FCT163H244
• Bus hold on data inputs
• Eliminates the need for external pull-up or pull-down
resistors
• Devices with bus hold are not recommended for translating rail-to-rail CMOS signals to 3.3V logic levels
Functional Description
These 16-bit buffers/line drivers are designed for use in
memory driver, clock driver, or other bus interface applications,
where high-speed and low power are required. The three-state
controls are designed to allow 4-bit, 8-bit or combined 16-bit
operation. Flow-through pinout and small shrink packaging
simplifies board layout.
The CY74FCT163244 has 24-mA balanced output drivers
with current limiting resistors in the outputs.
The CY74FCT163H244 has “bus hold” on the data inputs,
which retains the last state of the input whenever the source
driving the input goes to high impedance. This eliminates the
need for pull-up/down resistors and prevents floating inputs.
Pin Configuration
Logic Block Diagrams CY74FCT163244, CY74FCT163H244
3OE
1OE
1A1
1A2
SSOP/TSSOP
Top View
1Y1
1Y2
3A1
3A2
3Y1
3Y2
1OE
1
48
1Y1
2
47
1A1
1Y2
3
46
1A2
GND
4
45
GND
1Y3
5
1Y4
1A3
1A4
1Y3
1Y4
2A2
2A3
2A4
3A4
3Y3
2Y1
4A1
2Y2
4A2
2Y3
4A3
2Y4
4A4
VCC
2Y1
2Y2
3Y4
4OE
2OE
2A1
3A3
4Y1
4Y2
4Y3
4Y4
Copyright
44
163244
6 163H244 43
42
7
8
41
2OE
1A3
1A4
VCC
2A1
9
40
2A2
GND
10
39
GND
2Y3
11
38
2A3
2Y4
37
36
2A4
3Y1
12
13
3Y2
14
35
3A2
GND
15
34
GND
3Y3
16
33
3A3
3Y4
17
32
3A4
VCC
4Y1
18
31
19
30
VCC
4A1
3A1
4Y2
20
29
4A2
GND
21
28
GND
4Y3
22
27
4A3
4Y4
23
26
4A4
4OE
24
25
3OE
© 2000, Texas Instruments Incorporated
CY74FCT163244
CY74FCT163H244
Maximum Ratings[3,4]
Pin Description
Name
Description
OE
Three-State Output Enable Inputs (Active LOW)
A
Y
(Above which the useful life may be impaired. For user guidelines, not tested.)
Data Inputs[1]
Storage Temperature ................................. –55°C to +125°C
Three-State Outputs
Ambient Temperature with
Power Applied............................................ –55°C to +125°C
Supply Voltage Range ..................................... 0.5V to +4.6V
Function Table[2]
Inputs
DC Input Voltage ........................................... –0.5V to +7.0V
Outputs
DC Output Voltage......................................... –0.5V to +7.0V
OE
A
Y
L
L
L
DC Output Current
(Maximum Sink Current/Pin) ........................–60 to +120 mA
L
H
H
Power Dissipation .......................................................... 1.0W
H
X
Z
Operating Range
Range
Industrial
Ambient
Temperature
VCC
–40°C to +85°C
2.7V to 3.6V
Electrical Characteristics for Non Bus Hold Devices Over the Operating Range VCC=2.7V to 3.6V
Parameter
Description
Test Conditions
VIH
Input HIGH Voltage
All Inputs
VIL
Input LOW Voltage
VH
Input
Hysteresis[6]
VIK
Input Clamp Diode Voltage
VCC=Min., IIN=–18 mA
IIH
Input HIGH Current
IIL
Min.
Typ.[5]
2.0
Max.
Unit
5.5
V
0.8
V
100
–0.7
mV
– 1.2
V
VCC=Max., VI=5.5
±1
µA
Input LOW Current
VCC=Max., VI=GND
±1
µA
IOZH
High Impedance Output Current
(Three-State Output pins)
VCC=Max., VOUT=5.5V
±1
µA
IOZL
High Impedance Output Current
(Three-State Output pins)
VCC=Max., VOUT=GND
±1
µA
IOS
Short Circuit Current[7]
VCC=Max., VOUT=GND
–240
mA
IOFF
Power-Off Disable
VCC=0V, VOUT≤4.5V
±100
µA
ICC
Quiescent Power Supply Current
VIN≤0.2V,
VIN>VCC–0.2V
VCC=Max.
0.1
10
µA
∆ICC
Quiescent Power Supply Current
(TTL inputs HIGH)
VIN=VCC–0.6V[8]
VCC=Max.
2.0
30
µA
–60
–135
Notes:
1. On the CY74FCT163H244, these pins have “bus hold.”
2. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. Z = High Impedance.
3. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature
range.
4. With the exception of inputs with bus hold, unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
5. Typical values are at VCC=3.3V, TA = +25˚C ambient.
6. This parameter is specified but not tested.
7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests should be performed last.
8. Per TTL driven input; all other inputs at VCC or GND.
2
CY74FCT163244
CY74FCT163H244
Electrical Characteristics For Bus Hold Devices Over the Operating Range VCC=2.7V to 3.6V
Parameter
Description
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
Test Conditions
All Inputs
Min.
Typ.[5]
2.0
[6]
VH
Input Hysteresis
VIK
Input Clamp Diode Voltage
VCC=Min., IIN=–18 mA
IIH
Input HIGH Current
VCC=Max., VI=VCC
IIL
Input LOW Current
IBBH
IBBL
Bus Hold Sustain Current on Bus Hold Input[9] VCC=Min.
IBHHO
IBHLO
Bus Hold Overdrive Current on Bus Hold Input[9]
VCC=Max., VI=1.5V
IOZH
High Impedance Output Current
(Three-State Output pins)
IOZL
Max.
Unit
VCC
V
0.8
V
100
–0.7
mV
–1.2
V
±100
µA
±100
µA
VI=2.0V
–50
µA
VI=0.8V
+50
µA
±500
µA
VCC=Max., VOUT=VCC
±1
µA
High Impedance Output Current
(Three-State Output pins)
VCC=Max., VOUT=GND
±1
µA
IOS
Short Circuit Current[7]
VCC=Max., VOUT=GND
–240
mA
IOFF
Power-Off Disable
VCC=0V, VOUT≤4.5V
±100
µA
ICC
Quiescent Power Supply Current
VIN≤0.2V,
VIN>VCC–0.2V
VCC=Max.
+40
µA
∆ICC
Quiescent Power supply Current
(TTL inputs HIGH)
VIN=VCC–0.6V[8] VCC=Max.
+350
µA
–60
–135
Electrical Characteristics For Balanced Drive Devices Over the Operating Range VCC=2.7V to 3.6V
Parameter
Max.
Unit
IODL
Output LOW Dynamic
VCC=3.3V, VIN=VIH
or VIL, VOUT=1.5V
45
180
mA
IODH
Output HIGH Dynamic Current[7]
VCC=3.3V, VIN=VIH
or VIL, VOUT=1.5V
–45
–180
mA
VOH
Output HIGH Voltage
VCC=Min., IOH= –0.1 mA
Output LOW Voltage
Test Conditions
Min.
Typ.[5]
Current[7]
VOL
Description
VCC–0.2
V
VCC=3.0V, IOH= –8 mA
2.4[10]
3.0
VCC=3.0V, IOH= –24 mA
2.0
3.0
VCC=Min., IOL= 0.1mA
VCC=Min., IOL= 24 mA
Notes:
9. Pins with bus hold are described in Pin Description.
10. VOH = VCC – 0.6V at rated current.
3
V
V
0.2
0.3
0.55
V
CY74FCT163244
CY74FCT163H244
Capacitance[6](TA = +25˚C, f = 1.0 MHz)
Parameter
Description
Test Conditions
Typ.[5]
Max.
Unit
CIN
Input Capacitance
VIN = 0V
4.5
6.0
pF
COUT
Output Capacitance
VOUT = 0V
5.5
8.0
pF
Typ.[5]
Max.
Unit
Power Supply Characteristics
Parameter
Description
Test Conditions
ICCD
Dynamic Power Supply
Current[10]
VCC=Max., One Input Toggling, VIN=VCC or
50% Duty Cycle,
VIN=GND
Outputs Open, OE=GND
50
75
µA/MHz
IC
Total Power Supply
Current[11]
VCC=Max., f1=10 MHz, 50%
VIN=VCC or
Duty Cycle, Outputs Open, One VIN=GND
Bit Toggling, OE=GND
VIN=VCC–0.6V or
VIN=GND
0.5
0.8
mA
0.5
0.8
mA
VCC=Max., f1=2.5 MHz, 50%
VIN=VCC or
Duty Cycle, Outputs Open, Six- VIN=GND
teen Bits Toggling, OE=GND
VIN=VCC–0.6V or
VIN=GND
2.0
3.0[12]
mA
2.0
3.3[12]
mA
Notes:
11. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
12. IC
= IQUIESCENT + IINPUTS + IDYNAMIC
IC
= ICC+∆ICCDHNT+ICCD(f0/2 + f1N1)
ICC = Quiescent Current with CMOS input levels
∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V)
DH = Duty Cycle for TTL inputs HIGH
NT = Number of TTL inputs at DH
ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)
= Clock frequency for registered devices, otherwise zero
f0
= Input signal frequency
f1
N1 = Number of inputs changing at f1
All currents are in milliamps and all frequencies are in megahertz.
13. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
4
CY74FCT163244
CY74FCT163H244
Switching Characteristics Over the Operating Range VCC=3.0V to 3.6V[14,15]
CY74FCT163244A
CY74FCT163H244A
CY74FCT163244C
CY74FCT163H244C
Description
Min.
Max.
Min.
Max.
Unit
Fig. No.[16]
tPLH
tPHL
Propagation Delay Data to
Output
1.5
4.8
1.5
4.1
ns
1, 3
tPZH
tPZL
Output Enable Time
1.5
6.2
1.5
5.8
ns
1, 7, 8
tPHZ
tPLZ
Output Disable Time
1.5
5.6
1.5
5.2
ns
1, 7, 8
tSK(O)
Output Skew[17]
0.5
ns
—
Parameter
0.5
Notes:
14. Minimum limits are specified but not tested on Propagation Delays.
15. For VCC =2.7, propagation delay, output enable and output disable times should be degraded by 20%.
16. See “Parameter Measurement Information” in the General Information section.
17. Skew between any two outputs of the same package switching in the same direction. This parameter is ensured by design.
Ordering Information CY74FCT163244
Speed
(ns)
4.1
4.8
Ordering Code
Package
Name
Package Type
CY74FCT163244CPACT
Z48
48-Lead (240-Mil) TSSOP
CY74FCT163244CPVC/PVCT
O48
48-Lead (300-Mil) SSOP
CY74FCT163244APACT
Z48
48-Lead (240-Mil) TSSOP
CY74FCT163244APVC/PVCT
O48
48-Lead (300-Mil) SSOP
Operating
Range
Industrial
Industrial
Ordering Information CY74FCT163H244
Speed
(ns)
4.1
Ordering Code
Package
Name
Package Type
74FCT163H244CPACT
Z48
48-Lead (240-Mil) TSSOP
CY74FCT163H244CPVC
O48
48-Lead (300-Mil) SSOP
74FCT163H244CPVCT
O48
48-Lead (300-Mil) SSOP
5
Operating
Range
Industrial
CY74FCT163244
CY74FCT163H244
Package Diagrams
48-Lead Shrunk Small Outline Package O48
48-Lead Thin Shrunk Small Outline Package Z48
6
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
74FCT163H244CPACT
OBSOLETE
TSSOP
DGG
48
TBD
Call TI
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74FCT163H244CPVCT
OBSOLETE
SSOP
DL
48
TBD
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Lead/Ball Finish
MSL Peak Temp (3)
CY74FCT163244APAC
OBSOLETE
TSSOP
DGG
48
TBD
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CY74FCT163244APACT
OBSOLETE
TSSOP
DGG
48
TBD
Call TI
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CY74FCT163244APVC
OBSOLETE
SSOP
DL
48
TBD
Call TI
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CY74FCT163244APVCT
OBSOLETE
SSOP
DL
48
TBD
Call TI
Call TI
CY74FCT163244CPAC
OBSOLETE
TSSOP
DGG
48
TBD
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CY74FCT163244CPACT
OBSOLETE
TSSOP
DGG
48
TBD
Call TI
Call TI
CY74FCT163244CPVC
OBSOLETE
SSOP
DL
48
TBD
Call TI
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CY74FCT163244CPVCT
OBSOLETE
SSOP
DL
48
TBD
Call TI
Call TI
CY74FCT163H244CPAC
OBSOLETE
TSSOP
DGG
48
TBD
Call TI
Call TI
CY74FCT163H244CPVC
OBSOLETE
SSOP
DL
48
TBD
Call TI
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(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
0.0135 (0,343)
0.008 (0,203)
48
0.005 (0,13) M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°–ā8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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