Cypress CY62136EV30LL 2-mbit (128k x 16) static ram Datasheet

CY62136EV30 MoBL®
2-Mbit (128K x 16) Static RAM
Features
Functional Description
■
Very high speed: 45 ns
The CY62136EV30[1] is a high performance CMOS static RAM
organized as 128 K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. The device can
also be put into standby mode reducing power consumption by
more than 99% when deselected (CE HIGH). The input/output
pins (I/O0 through I/O15) are placed in a high impedance state
when: deselected (CE HIGH), outputs are disabled (OE HIGH),
both Byte High Enable and Byte Low Enable are disabled (BHE,
BLE HIGH), or during a write operation (CE LOW and WE LOW).
■
Wide voltage range: 2.20 V to 3.60 V
■
Pin compatible with CY62136CV30
■
Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 7 A
■
Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
■
Easy memory expansion with CE and OE features
■
Automatic power down when deselected
■
Complementary metal oxide semiconductor (CMOS) for
optimum speed/power
■
Offered in a Pb-free 48-ball very fine ball grid array (VFBGA)
and 44-pin thin small outline package (TSOP II) packages
Writing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is
LOW, then data from I/O pins (I/O0 through I/O7), is written into
the location specified on the address pins (A0 through A16). If
Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8
through I/O15) is written into the location specified on the address
pins (A0 through A16).
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory appear on I/O8 to I/O15. See the Truth Table on page 10
for a complete description of read and write modes.
Logic Block Diagram
128K x 16
RAM Array
SENSE AMPS
ROW DECODER
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
I/O0–I/O7
I/O8–I/O15
BHE
WE
CE
OE
BLE
A13
A14
A15
A16
A11
A12
COLUMN DECODER
Note
1. For best practice recommendations, refer to the Cypress application note “SRAM System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05569 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 17, 2011
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CY62136EV30 MoBL®
Contents
Pin Configuration .............................................................. 3
Product Portfolio ............................................................... 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics.................................................. 4
Capacitance ...................................................................... 4
Thermal Resistance .......................................................... 5
Data Retention Characteristics ....................................... 5
Data Retention Waveform ................................................ 5
Switching Characteristics................................................. 6
Switching Waveforms ...................................................... 7
Document #: 38-05569 Rev. *D
Truth Table ...................................................................... 10
Ordering Information ...................................................... 11
Ordering Code Definition ........................................... 11
Package Diagrams .......................................................... 12
Acronyms ........................................................................ 13
Document Conventions ................................................. 13
Units of Measure ....................................................... 13
Document History Page ................................................. 14
Sales, Solutions, and Legal Information ...................... 15
Worldwide Sales and Design Support ....................... 15
Products .................................................................... 15
PSoC Solutions ......................................................... 15
Page 2 of 15
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CY62136EV30 MoBL®
Pin Configuration[2, 3]
VFBGA (Top View)
44 TSOP II (Top View)
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
I/O8
BHE
A3
A4
CE
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
D
E
VSS
I/O11
NC
A7
I/O3
Vcc
VCC
I/O12
NC
A16
I/O4
Vss
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
NC
A12
A13
WE
I/O7
G
NC
A8
A9
A10
A11
NC
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
H
1
44
2
3
43
42
4
41
40
39
38
5
6
7
8
9
10
11
12
37
36
35
34
33
32
31
30
29
28
27
13
14
15
16
17
18
19
20
21
22
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
Product Portfolio[4]
Power Dissipation
Product
Speed
(ns)
VCC Range (V)
Operating ICC (mA)
f = 1 MHz
CY62136EV30LL
Min
Typ[4]
Max
2.2
3.0
3.6
45
f = fmax
Standby ISB2 (A)
Typ[4]
Max
Typ[4]
Max
Typ[4]
Max
2
2.5
15
20
1
7
Notes
2. NC pins are not connected on the die.
3. Pins D3, H1, G2, H6 and H3 in the VFBGA package are address expansion pins for 4 Mb, 8 Mb, 16 Mb, and 32 Mb and 64 Mb respectively
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C.
Document #: 38-05569 Rev. *D
Page 3 of 15
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CY62136EV30 MoBL®
Maximum Ratings
DC input voltage[5,6] ........... –0.3 V to 3.9 V (VCC MAX + 0.3 V)
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature with
power applied ......................................... –55 °C to + 125 °C
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage ......................................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch up current ..................................................... > 200 mA
Operating Range
Supply voltage to ground
potential ........................... –0.3 V to 3.9 V (VCC MAX + 0.3 V)
DC voltage applied to outputs
in High-Z state[5,6] .............. –0.3 V to 3.9 V (VCC MAX + 0.3 V)
Device
Range
CY62136EV30LL Industrial
Ambient
Temperature
VCC[7]
–40 °C to
+85 °C
2.2 V - 3.6 V
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
45 ns
Min
Typ[8]
Max
VCC = 2.20 V
2.0
–
–
Unit
VOH
Output HIGH voltage
IOH = –0.1 mA
IOH = –1.0 mA
VCC = 2.70 V
2.4
–
–
V
VOL
Output LOW voltage
IOL = 0.1 mA
VCC = 2.20 V
–
–
0.4
V
IOL = 2.1 mA
VCC = 2.70 V
–
–
0.4
V
1.8
–
VCC + 0.3
V
VIH
Input HIGH voltage
VIL
Input LOW voltage
VCC = 2.2V to 2.7 V
V
VCC= 2.7 V to 3.6 V
2.2
–
VCC + 0.3
V
VCC = 2.2 V to 2.7 V
–0.3
–
0.6
V
VCC= 2.7 V to 3.6 V
–0.3
–
0.8
V
–1
–
+1
A
IIX
Input leakage current
IOZ
Output leakage current
GND < VO < VCC, output disabled
–1
–
+1
A
ICC
VCC operating supply
current
f = fmax = 1/tRC
–
15
20
mA
–
2
2.5
ISB1
[9]
ISB2 [9]
GND < VI < VCC
f = 1 MHz
VCC = VCCmax, IOUT = 0 mA
CMOS levels
Automatic CE
power-down current —
CMOS
inputs
CE > VCC0.2 V,
VIN>VCC–0.2 V, VIN<0.2 V)
f = fmax (address and data only),
f = 0 (OE, and WE),
VCC = 3.60 V
–
1
7
A
Automatic CE
power-down current —
CMOS inputs
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2V, f = 0,
VCC = 3.60 V
–
1
7
A
Capacitance
Parameter[10]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz,
VCC = VCC(typ)
Max
Unit
10
pF
10
pF
Notes
5. VIL(min.) = –2.0 V for pulse durations less than 20 ns.
6. VIH(max)=VCC+0.75 V for pulse durations less than 20 ns.
7. Full Device AC operation assumes a 100 s ramp time from 0 to Vcc(min) and 200 s wait time after VCC stabilization.
8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C
9. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR specification. Other inputs can be left floating.
10. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05569 Rev. *D
Page 4 of 15
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CY62136EV30 MoBL®
Thermal Resistance
Parameter[11]
Test Conditions
VFBGA
Package
TSOP II
Package
Unit
Still air, soldered on a 3 × 4.5 inch, two-layer printed
circuit board
75
77
C / W
10
13
C / W
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Figure 1. AC Test Loads and Waveforms
R1
VCC
OUTPUT
VCC
R2
30 pF
INCLUDING
JIG AND
SCOPE
10%
GND
Rise Time = 1 V/ns
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
2.50 V
3.0 V
Unit
R1
R2
16667
1103

15385
1554

RTH
VTH
8000
645

1.20
1.75
V
Data Retention Characteristics
(Over the Operating Range)
Parameter
Conditions
VCC for data retention
VDR
ICCDR
Description
[13]
Data retention current
VCC= 1.0 V
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
Min
Typ[12]
Max
Unit
1.0
–
–
V
–
0.8
3
A
–
–
ns
–
ns
tCDR[11]
Chip deselect to data
retention time
0
tR[14]
Operation recovery time
45
Data Retention Waveform[15]
VCC
VCC(min)
tCDR
DATA RETENTION MODE
VDR > 1.0 V
VCC(min)
tR
CE
Notes
11. Tested initially and after any design or process changes that may affect these parameters.
12. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C
13. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR specification. Other inputs can be left floating
14. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.) > 100 s.
15. BHE.BLE is the AND of both BHE and BLE. The chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document #: 38-05569 Rev. *D
Page 5 of 15
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CY62136EV30 MoBL®
Switching Characteristics Over the Operating Range
Parameter[16, 17]
Description
45 ns
Min
Max
Unit
Read Cycle
tRC
Read cycle time
45
–
ns
tAA
Address to data valid
–
45
ns
tOHA
Data hold from address change
10
–
ns
tACE
CE LOW to data valid
–
45
ns
tDOE
OE LOW to data valid
–
22
ns
tLZOE
OE LOW to LOW Z[18]
5
–
ns
tHZOE
OE HIGH to High Z
–
18
ns
tLZCE
CE LOW to Low Z
10
–
ns
tHZCE
CE HIGH to High Z
–
18
ns
tPU
CE LOW to power-up
0
–
ns
tPD
CE HIGH to power-down
–
45
ns
tDBE
BLE/BHE LOW to data valid
–
22
ns
tLZBE
BLE/BHE LOW to Low Z
5
–
ns
tHZBE
BLE/BHE HIGH to HIGH Z[18, 19]
–
18
ns
tWC
Write cycle time
45
–
ns
[18, 19]
[18]
[18, 19]
[18]
Write Cycle[20]
tSCE
CE LOW to write end
35
–
ns
tAW
Address setup to write end
35
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
35
–
ns
tBW
BLE/BHE LOW to write end
35
–
ns
tSD
Data setup to write end
25
–
ns
tHD
Data hold from write end
0
–
ns
tHZWE
WE LOW to High Z
–
18
ns
tLZWE
WE HIGH to Low Z[18]
10
–
ns
[18, 19]
Notes
16. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of VCC(typ)/2, input
pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in AC Test Loads and Waveforms.
17. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Refer application note AN13842 for more information.
18. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device.
19. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state.
20. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and BLE = VIL. All signals must be ACTIVE to initiate a write and any of
these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the
write.
Document #: 38-05569 Rev. *D
Page 6 of 15
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CY62136EV30 MoBL®
Switching Waveforms
Figure 2. Read Cycle 1: Address Transition Controlled [21, 22]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 3. Read Cycle No. 2 : OE Controlled[22, 23]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
BHE/BLE
tLZOE
tHZBE
tDBE
tLZBE
DATA OUT
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPU
50%
50%
ICC
ISB
.
Notes
21. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL.
22. WE is HIGH for read cycle.
23. Address valid prior to or coincident with CE and BHE, BLE transition LOW.
Document #: 38-05569 Rev. *D
Page 7 of 15
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CY62136EV30 MoBL®
Switching Waveforms (continued)
Figure 4. Write Cycle No. 1: WE Controlled [24, 25, 26]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
WE
tPWE
tBW
BHE/BLE
OE
tSD
DATA I/O
NOTE 27
tHD
DATAIN
tHZOE
Figure 5. Write Cycle No. 2: CE Controlled [24, 25, 26]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
DATAIN
NOTE 27
tHZOE
Notes
24. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and BLE = VIL. All signals must be ACTIVE to initiate a write and any of
these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the
write.
25. Data I/O is high impedance if OE = VIH.
26. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
27. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05569 Rev. *D
Page 8 of 15
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CY62136EV30 MoBL®
Switching Waveforms (continued)
Figure 6. Write Cycle No. 3: WE Controlled, OE LOW [28]
tWC
ADDRESS
tSCE
CE
tBW
BHE/BLE
tAW
tHA
tSA
tPWE
WE
tSD
DATAI/O
NOTE 29
tHD
DATAIN
tHZWE
tLZWE
Figure 7. Write Cycle No. 4: BHE/BLE Controlled, OE LOW [28]
tWC
ADDRESS
CE
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tHZWE
DATA I/O
NOTE 29
tSD
tHD
DATAIN
tLZWE
Notes
28. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state
29. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05569 Rev. *D
Page 9 of 15
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CY62136EV30 MoBL®
Truth Table
CE
H[30]
WE
X
OE
X
BHE
X[30]
BLE
X[30]
Inputs/Outputs
High Z
Mode
Deselect/power-down
Power
Standby (ISB)
L
X
X
H
H
High Z
Output disabled
Active (ICC)
L
H
L
L
H
L
L
L
Data out (I/OO–I/O15)
Read
Active (ICC)
H
L
Data out (I/OO–I/O7);
I/O8–I/O15 in High Z
Read
Active (ICC)
L
H
L
L
H
Data Out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read
Active (ICC)
L
H
H
L
L
High Z
Output disabled
Active (ICC)
L
L
H
H
H
L
High Z
Output disabled
Active (ICC)
H
H
L
H
High Z
Output disabled
Active (ICC)
L
L
X
L
L
Data in (I/OO–I/O15)
Write
Active (ICC)
L
L
X
H
L
Data in (I/OO–I/O7);
I/O8–I/O15 in High Z
Write
Active (ICC)
L
L
X
L
H
Data in (I/O8–I/O15);
I/O0–I/O7 in High Z
Write
Active (ICC)
Note
30. Chip enable (CE) and Byte enables (BHE and BLE) must be at fixed CMOS levels (not floating). Intermediate voltage levels on these pins is not permitted
Document #: 38-05569 Rev. *D
Page 10 of 15
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CY62136EV30 MoBL®
Ordering Information
Speed
(ns)
45
Package
Diagram
Ordering Code
Package Type
CY62136EV30LL-45BVXI
51-85150
48-Ball Very Fine Pitch Ball Grid Array (Pb-free)
CY62136EV30LL-45ZSXI
51-85087
44-Pin Thin Small Outline Package II (Pb-free)
Operating
Range
Industrial
Contact your local Cypress sales representative for availability of other parts
Ordering Code Definition
CY
621
3
6E
V30
LL
45
XXX
I
Temperature Grades
I = Industrial
Package Type BVX: VFBGA (Pb-free)
ZSX : TSOP II (Pb-free)
Speed Grade
Low Power
Wide Voltage Range (3 V and 5 V)
Bus Width = X16
E = 90nm Technology
Density = 2 Mbit
MoBL SRAM Family
Company ID: CY = Cypress
Document #: 38-05569 Rev. *D
Page 11 of 15
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CY62136EV30 MoBL®
Package Diagrams
Figure 8. 48-Pin VFBGA (6 x 8 x 1 mm) (51-85150)
51-85150-*F
Document #: 38-05569 Rev. *D
Page 12 of 15
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CY62136EV30 MoBL®
Package Diagrams (continued)
Figure 9. 44-Pin TSOP II (51-85087)
51-85087-*C
Acronyms
Document Conventions
Description
Units of Measure
CMOS
complementary metal oxide semiconductor
Symbol
I/O
input/output
°C
degrees Celsius
SRAM
static random access memory
A
microamperes
VFBGA
very fine ball gird array
mA
milliampere
TSOP
thin small outline package
MHz
megahertz
Acronym
Document #: 38-05569 Rev. *D
Unit of Measure
ns
nanoseconds
pF
picofarads
V
volts

ohms
W
watts
Page 13 of 15
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CY62136EV30 MoBL®
Document History Page
Document Title: CY62136EV30 MoBL® 2-Mbit (128K x 16) Static RAM
Document Number: 38-05569
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
237432
AJU
See ECN
New Data Sheet
*A
419988
RXU
See ECN
Converted from Advanced Information to Final.
Changed the address of Cypress Semiconductor Corporation on Page #1
from “3901 North First Street” to “198 Champion Court”
Removed 35ns Speed Bin
Removed “L” version of CY62136EV30
Changed ICC (Max) value from 2 mA to 2.5 mA and ICC (Typ) value from
1.5 mA to 2 mA at f=1 MHz
Changed ICC (Typ) value from 12 mA to 15 mA at f = fmax
Changed ISB1 and ISB2 Typ. values from 0.7 A to 1 A and Max. values from
2.5 A to 7 A.
Changed the AC test load capacitance from 50pF to 30pF on Page# 4
Changed VDR from 1.5V to 1V on Page# 4.
Changed ICCDR from 2.5 A to 3 A.
Added ICCDR typical value.
Changed tOHA , tLZCE and tLZWE from 6 ns to 10 ns
Changed tLZBE from 6 ns to 5 ns
Changed tLZOE from 3 ns to 5 ns
Changed tHZOE, tHZCE, tHZBE and tHZWE from 15 ns to 18 ns
Changed tSCE,tAW and tBW from 40 ns to 35 ns
Changed tPWE from 30 ns to 35 ns
Changed tSD from 20 ns to 25 ns
Corrected typo in the Truth Table on Page# 9
Updated the package diagram 48-pin VFBGA from *B to *D
Updated the ordering Information table and replaced the Package Name
column with Package Diagram.
*B
427817
NXR
See ECN
Minor change: Moved datasheet to external web
*C
2604685
VKN/PYRS
11/12/08
Added footnote 8 related to ISB2 and ICCDR
Added footnote 12 related to AC timing parameters
*D
3144174
RAME
01/17/2011
Added Acronyms and Units of Measure table
Added Ordering Code Definition
Update Package Diagrams 51-85150 from *D to *F
Converted all tablenotes into footnotes
Added TOC
Updated datasheet as per new template.
Document #: 38-05569 Rev. *D
Page 14 of 15
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CY62136EV30 MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
psoc.cypress.com/solutions
cypress.com/go/clocks
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2007-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05569 Rev. *D
Revised January 17, 2011
Page 15 of 15
All products and company names mentioned in this document may be the trademarks of their respective holders.
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