Integrated Circuit Systems, Inc. ICSSSTV16857 DDR 14-Bit Registered Buffer Recommended Application: DDR Memory Modules Product Features: • Differential clock signal • Meets SSTL_2 signal data • Supports SSTL_2 class I & II specifications • low-voltage operation VDD = 2.3V to 2.7V • 48 pin TSSOP package Pin Configuration Truth Table1 Inputs Q Outputs 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 ICSSSTV16857 Q1 Q2 GND VDDQ Q3 Q4 Q5 GND VDDQ Q6 Q7 VDDQ GND Q8 Q9 VDDQ GND Q10 Q11 Q12 VDDQ GND Q13 Q14 D1 D2 GND VDD D3 D4 D5 D6 D7 CLK# CLK VDD GND VREF RESET# D8 D9 D10 D11 D12 VDD GND D13 D14 RESET# CLK CLK# D Q L X or Floating X or Floating X or Floating L H ↑ ↓ H H H ↑ ↓ L L 48-Pin TSSOP & TVSOP Q0(2) 6.10 mm. Body, 0.50 mm. pitch = TSSOP 4.40 mm. Body, 0.40 mm. pitch = TSSOP (TVSOP) H L or H L or H X Notes: 1. H = High Signal Level L = Low Signal Level ↑ = Transition LOW-to-HIGH ↓ = Transition HIGH -to LOW X = Irrelevant 2. Output level before the indicated steady state input conditions were established. Block Diagram CLK CLK# RESET# D1 VREF 38 39 34 48 35 R CLK D1 1 Q1 To 13 Other Channels 16857 Rev D 07/09/01 Third party brands and names are the property of their respective owners. ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICSSSTV16857 General Description The 14-bit ICSSTV16857 is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/O Levels except for the RESET# input which is LVCMOS. Data flow from D to Q is controlled by the differential clock, CLK, CLK# and RESET#. Data is triggered on the positive edge of CLK. CLK# must be used to maintain noise margins. RESET# must be supported with LVCMOS levels as VREF may not be stable during power-up. RESET# is asynchronous and is intended for power-up only and when low assures that all of the registers reset to the Low State, Q outputs are low, and all input receivers, data and clock are switched off. Pin Configuration PIN NUMBER 24, 23, 20, 19, 18, 15, 14, 11, 10, 7, 6, 5, 2, 1 3, 8, 13, 22, 27, 36, 46 4, 9, 12, 16, 21 25, 26, 29, 30, 31, 32, 33, 40, 41, 42, 43, 44, 47, 48 38 39 28, 37, 45 34 35 PIN NAME TYPE DESCRIPTION Q (14:1) OUTPUT GND PWR Ground VDDQ PWR Output supply voltage D (14:1) INPUT Data input CLK CLK# VDD RESET# VREF INPUT INPUT PWR INPUT INPUT Positive clock input Negative clock input Core supply voltage Reset (active low) Input reference voltage Data output Third party brands and names are the property of their respective owners. 2 ICSSSTV16857 Absolute Maximum Ratings Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Voltage 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Voltage 1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Clamp Current . . . . . . . . . . . . . . . . . . . . . . . Output Clamp Current . . . . . . . . . . . . . . . . . . . . . Continuous Output Current . . . . . . . . . . . . . . . . . VDD, VDDQ or GND Current/Pin . . . . . . . . . . . . –65°C to +150°C -0.5 to 3.6V -0.5 to VDD +0.5 -0.5 to VDDQ +0.5 ±50 mA ±50mA ±50mA ±100mA Package Thermal Impedance3 55°C/W .................... Notes: 1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. This current will flow only whtn the output is in the high state level V0 >VDDQ. 3. The package thermal impedance is calculated in accordance with JESD 51. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Recommended Operating Conditions PARAM ETER VDD V DDQ VREF VTT VI VIH VIH VIL VIL VIH VIL VICR VID 1 DESCRIPTION Supply Voltage I/O Supply Voltage M IN 2.3 2.3 1.15 VREF -0.04 0 VREF +0.15 VREF +0.31 Reference Voltage VREF = 0.5X VDDQ Termination Voltage V IX Input Voltage DC Input High Voltage AC Input High Voltage Data Inputs DC Input Low Voltage AC Input Low Voltage Input High Voltage Level 1.7 RESET# Input Low Voltage Level Common mode Input Range 0.97 CLK, CLK# Differential Input Voltage 0.36 Cross Point Voltage of Differential Clock (VDDQ/2) -0.2 Pair IOH High-Level Output Current IOL TA Low-Level Output Current Operating Free-Air Temperature 0 Guarenteed by design, not 100% tested in production. Third party brands and names are the property of their respective owners. 3 TYP 2.5 2.5 1.25 VREF M AX 2.7 2.7 1.35 V REF -0.04 VDD UNITS V REF -0.15 V REF -0.31 V 0.7 1.53 (VDDQ/2) +0.2 -20 20 70 mA °C ICSSSTV16857 Electrical Characteristics - DC TA = 0 - 70º C; VDD = 2.5 V +/-200mV, VDDQ=2.5V 200mV; (unless otherwise stated) SYMBOL VIK PARAMETERS VOH VOL II All Inputs Standby (Static) IDD Operating (Static) Dynamic operating clock only IDDD Dynamic Operating per each data input rOH rOL rO(∆) Ci Output High Output Low [rOH - rOL] each separate bit Data Inputs CK and CK# CONDITIONS II = -18mA IOH = -100µA IOH= -16mA IOL = 100µA IOL = 16mA VI = VDD or GND RESET# = GND VI = VIH (AC#) or VIL (AC), RESET# = VDD RESET = VDD, VI = VIH(AC) or VIL (AC), CK and CK# switching 50% duty cycle. RESET# = VDD, VI = VIH(AC) or VIL (AC), CK and CK# switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle IOH = -20mA IOL = 20mA VDD 2.3V 2.3V-2.7 2.3V 2.3-2.7V 2.3V 2.7V IO = 0 TYP VDD -0.2 1.95 2.5 2 0 0.16 7 7 2.5V 2.5V Notes: 1 - Guaranteed by design, not 100% tested in production. Third party brands and names are the property of their respective owners. 4 MAX -1.2 UNITS 0.2 0.35 ±5 0.01 V µA µA TBD mA TBD µA/clock MHz TBD µA/ clock MHz/data 20 20 Ω Ω 4 3.5 3.5 Ω 2.7V 2.3-2.7V 2.3-2.7V IO = 20mA, TA = 25° C VI = VREF ±310mV VICR = 1.25V, VI(PP) = 360mV MIN 2.5 2.5 15 10 pF ICSSSTV16857 Timing Requirements (over recommended operating free-air temperature range, unless otherwise noted) SYMBOL PARAMETERS VDD=2.5±0.2V MIN TYP MAX fclock Clock frequency 133 200 tPD Clock to output time 1.1 2.4 2.8 tRST Reset to output time 3.1 5 tSL Output slew rate 1 1.5 4 Setup time, fast slew rate 2, 4 Data before CKD , CK#E 0.75 0.018 3, 4 Setup time, slow slew rate 0.9 tSU Hold time, fast slew rate 2,4 Data after CKD , CK#E 0.75 0.145 Hold time, slow slew rate 3, 4 Th 0.9 Notes: 1 - Guaranteed by design, not 100% tested in production. 2 - For data signal input slew rate =1V/ns. 4 - CLK, CLK# signals input slew rates are =1V/ns. 3 - For data signal input slew rate =0.5V/ns and < 1V/ns. Sw itching Characteristics (over recom m ended operating free-air tem perature range, unles s otherwis e noted) SYMBOL fclock tPD tph1 From (Input) To (Output) MIN VDD=2.5±0.2V TYP 133 MAX 200 MHz CLK, CLK# Q 1.1 2.4 2.8 ns RESET# Q 3.1 5 ns Third party brands and names are the property of their respective owners. 5 UNITS UNITS MHz ns ns V/ns ns ns ns ns ICSSSTV16857 VTT RL= From Output Under Test Test Point CL = 30 pF (see Note 1) Load Circuit LVCMOS RESET# Input VDD/2 VDD VDD/2 tinact VI(pp) 0V Timing Input tact IDD (see note 2) tPHL 90% IDDH 10% IDDL Voltage and Current Waveforms Inputs Active and Inactive Times tw VREF Input VREF Voltage Waveforms - Pulse Duration Output Input VREF VTT VTT VOH VOL VIH VIL LVCMOS RESET# Input VICR tSU tPHL Voltage Waveforms - Propagation Delay Times VI(pp) Timing Input VICR VICR VIH VDD/2 VIL tPHL Output th VREF Voltage Waveforms - Setup and Hold Times VTT VIH VOH VOL Voltage Waveforms - Propagation Delay Times VIL Parameter Measurement Information (VDD = 2.5V ±0.2V) Notes: 1. CL incluces probe and jig capacitance. 2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA. 3. All input pulses are supplied by generators having the following chareacteristics: PRR ≤10 MHz, Zo=50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. VTT = VREF = VDDQ/2 6. VIH = VREF + 310mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 7. VIL = VREF -310mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input. 8. tPLH and tPHL are the same as tpd Third party brands and names are the property of their respective owners. 6 ICSSSTV16857 c N L E1 INDEX AREA E 1 2 D A A2 A1 In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 8.10 BASIC 0.319 BASIC E1 6.00 6.20 .236 .244 e 0.50 BASIC 0.020 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS α 0° 8° 0° 8° aaa -0.10 -.004 VARIATIONS -Ce SEATING PLANE b aaa C D mm. N MIN 12.40 48 D (inch) MAX 12.60 MIN .488 MAX .496 Reference Doc.: JEDEC Publication 95, MO-153 10-0039 6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil) (240 mil) Ordering Information ICSSSTV16857yG-T Example: ICS XXXX y G - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type G=TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device Third party brands and names are the property of their respective owners. 7 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICSSSTV16857 c N L E1 INDEX AREA SYMBOL A A1 A2 b c D E E1 e L N α aaa E 1 2 α D A A2 A1 VARIATIONS -C- e In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX -1.20 -.047 0.05 0.15 .002 .006 0.80 1.05 .032 .041 0.13 0.23 .005 .009 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS 6.40 BASIC 0.252 BASIC 4.30 4.50 .169 .177 0.40 BASIC 0.016 BASIC 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS 0° 8° 0° 8° -0.08 -.003 SEATING PLANE b D mm. N MIN 9.60 48 D (inch) MAX 9.80 MIN .378 MAX .386 Reference Doc.: JEDEC Publication 95, MO-153 aaa C 10-0037 4.40 mm. Body, 0.40 mm. pitch TSSOP (173 mil) (16 mil) Ordering Information ICSSSTV16857yL-T Example: ICS XXXX y L - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type L=TSSOP (TVSOP) Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device Third party brands and names are the property of their respective owners. 8 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.