STMicroelectronics M24C32S-FCU6T 32-kbit serial ic bus eeprom 4 balls csp Datasheet

M24C32S-FCU
32-Kbit serial I²C bus EEPROM 4 balls CSP
Datasheet - production data
Features
• Compatible with the 400 kHz I²C protocol
• High speed 1MHz transfer rate
• Memory array:
– 32 Kbit (4 Kbyte) of EEPROM
– Page size: 32 byte
WLCSP (CU)
• Supply voltage range:
– 1.7 V to 5.5 V
• Operating temperature range
– -40°C / +85°C
• Write
– Byte Write within 5 ms
– Page Write within 5 ms
• Random and sequential Read modes
• Software Write protect
– Upper quarter memory array
– Upper half memory array
– Upper 3/4 memory array
– Whole memory array
• ESD protection
– Human Body Model: 4 kV
• More than 4 million Write cycles
• More than 200-years data retention
• Package
– WLCSP, RoHS and Halogen free compliant
(ECOPACK2®)
October 2015
This is information on a product in full production.
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Contents
M24C32S-FCU
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3
VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4.1
Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4.2
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4.3
Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4.4
Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
4.1
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.2
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.3
Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.4
Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.5
Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1
5.2
6
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Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.1
Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.2
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.3
Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.4
Minimizing Write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 17
Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2.1
Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2.2
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2.3
Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2.4
Read the Write Protect register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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Contents
7
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.1
Ultra Thin WLCSP package information . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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List of tables
M24C32S-FCU
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
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Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write Protect register (Address = 1xxx.xxxx.xxxx.xxxxb) . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
High frequency clock AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Ultra Thin WLCSP- 4-bump, 0.833 x 0.833 mm, wafer level chip scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Ultra Thin WLCSP- 4-bump, 0.833 x 0.833 mm, wafer level chip scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4-bump WLCSP connections
(top view, marking side, with balls on the underside) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write mode sequence (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write mode sequence (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Maximum Rbus value versus bus parasitic capacitance (Cbus) for
an I2C bus at maximum frequency fC = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Maximum Rbus value versus bus parasitic capacitance (Cbus)
for an I2C bus at high clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Ultra Thin WLCSP- 4-bump, 0.833 x 0.833 mm, wafer level chip scale
package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Ultra Thin WLCSP- 4-bump, 0.833 x 0.833 mm, wafer level chip scale
package outline with BSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Thin WLCSP- 4-bump, 0.833 x 0.833 mm, wafer level chip scale
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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Description
1
M24C32S-FCU
Description
The M24C32S-FCU is a 32-Kbit I2C-compatible EEPROM (Electrically Erasable
PROgrammable Memory) organized as 4 K × 8 bits
The M24C32S-FCU can operate with a supply voltage from 1.7 V to 5.5 V, over an ambient
temperature range of -40 °C/+85 °C.
The M24C32S-FCU is delivered in a 4-ball WLCSP package.
Figure 1. Logic diagram
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Table 1. Signal names
Signal name
Function
Direction
SDA
Serial Data
I/O
SCL
Serial Clock
Input
VCC
Supply voltage
-
VSS
Ground
-
Figure 2. 4-bump WLCSP connections
(top view, marking side, with balls on the underside)
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M24C32S-FCU
Signal description
2
Signal description
2.1
Serial Clock (SCL)
SCL is an input. The signal applied on the SCL input is used to strobe the data available on
SDA(in) and to output the data on SDA(out).
2.2
Serial Data (SDA)
SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an
open drain output that may be wire-OR’ed with other open drain or open collector signals on
the bus. A pull-up resistor must be connected from Serial Data (SDA) to VCC (Figure 9
indicates how to calculate the value of the pull-up resistor).
2.3
VSS (ground)
VSS is the reference for the VCC supply voltage.
2.4
Supply voltage (VCC)
2.4.1
Operating supply voltage (VCC)
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions
in Section 8: DC and AC parameters). In order to secure a stable DC supply voltage, it is
recommended to decouple the VCC line with a suitable capacitor (usually from10 nF to
100 nF) close to the VCC/VSS package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a write instruction, until the completion of the internal write cycle (tW).
2.4.2
Power-up conditions
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
(see Operating conditions in Section 8: DC and AC parameters) and the rise time must not
vary faster than 1 V/µs.
2.4.3
Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included.
At power-up, the device does not respond to any instruction until VCC has reached the
internal reset threshold voltage. This threshold is lower than the minimum VCC operating
voltage (see Operating conditions in Section 8: DC and AC parameters). When VCC passes
over the POR threshold, the device is reset and enters the Standby Power mode; however,
the device must not be accessed until VCC reaches a valid and stable DC voltage within the
specified [VCC(min), VCC(max)] range (see Operating conditions in Section 8: DC and AC
parameters).
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Signal description
M24C32S-FCU
In a similar way, during power-down (continuous decrease in VCC), the device must not be
accessed when VCC drops below VCC(min). When VCC drops below the power-on-reset
threshold voltage, the device stops responding to any instruction sent to it.
2.4.4
Power-down conditions
During power-down (continuous decrease in VCC), the device must be in the Standby Power
mode (mode reached after decoding a Stop condition, assuming that there is no internal
write cycle in progress).
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Memory organization
The memory is organized as shown below.
Figure 3. Block diagram
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Memory organization
PAGE
8 DECODER
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Device operation
4
M24C32S-FCU
Device operation
The device supports the I2C protocol. This is summarized in Figure 4. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The device is always a slave in all
communications.
Figure 4. I2C bus protocol
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4.1
Device operation
Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer instruction. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition.
4.2
Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and
driven high. A Stop condition terminates communication between the device and the bus
master. A Read instruction that is followed by NoAck can be followed by a Stop condition to
force the device into the Standby mode.
A Stop condition at the end of a Write instruction triggers the internal Write cycle.
4.3
Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.
4.4
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to
acknowledge the receipt of the eight data bits.
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Device operation
4.5
M24C32S-FCU
Device addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Table 2 (on Serial Data (SDA), most significant bit first).
Table 2. Device select code
Device type identifier(1)
Chip Enable address
RW
b7
b6
b5
b4
b3
b2
b1
b0
1
0
1
0
0
0
1
RW
1. The most significant bit, b7, is sent first.
The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9th bit time.
If the device does not match the device select code, the device deselects itself from the bus,
and goes into Standby mode (therefore will not acknowledge the device select code).
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Instructions
5
Instructions
5.1
Write operations
Following a Start condition the bus master sends a device select code with the R/W bit (RW)
reset to 0. The device acknowledges this, as shown in Figure 5, and waits for two address
bytes. The device responds to each address byte with an acknowledge bit, and then waits
for the data byte.
Table 3. Most significant address byte
A15
A14
A13
A12
A11
A10
A9
A8
A1
A0
Table 4. Least significant address byte
A7
A6
A5
A4
A3
A2
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write
cycle tW is triggered. A Stop condition at any other time slot does not trigger the internal
Write cycle.
After the Stop condition and the successful completion of an internal Write cycle (tW), the
device internal address counter is automatically incremented to point to the next byte after
the last modified byte.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
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Instructions
5.1.1
M24C32S-FCU
Byte Write
After the device select code and the address bytes, the bus master sends one data byte. If
the addressed location is Write-protected, the device replies with NoAck, and the location is
not modified, as shown in Figure 6. If, instead, the addressed location is not Writeprotected, the device replies with Ack, as shown in Figure 5. The bus master shall terminate
the transfer by generating a Stop condition.
Figure 5. Write mode sequence (data write enabled)
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M24C32S-FCU
Page Write
The Page Write mode allows up to 32 bytes to be written in a single Write cycle, provided
that they are all located in the same page in the memory: that is, the most significant
memory address bits, A15/A5, are the same. If more bytes are sent than will fit up to the end
of the page, a “roll-over” occurs, i.e. the bytes exceeding the page end are written on the
same page, from location 0.
The bus master sends from 1 to 32 bytes of data, each of which is acknowledged by the
device if the page is not write-protected, as shown in Figure 5. If the page is write-protected,
the contents of the addressed memory location are not modified, and each data byte is
followed by a NoAck, as shown in Figure 6. After each transferred byte, the internal page
address counter is incremented.
The transfer is terminated by the bus master generating a Stop condition.
Figure 6. Write mode sequence (data write inhibited)
ACK
ACK
Byte addr
Dev sel
Data in
ACK
Byte addr
ACK
Byte addr
NO ACK
Data in 1
Data in 2
R/W
NO ACK
NO ACK
Data in N
Stop
Page Write (cont'd)
Byte addr
NO ACK
R/W
ACK
Page Write
ACK
Stop
Dev sel
Start
Byte Write
Start
5.1.2
Instructions
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Instructions
5.1.3
M24C32S-FCU
Write protection
By writing specific values in a register (Table 5) located at address 1xxx.xxxx.xxxx.xxxxb,
the memory array can be write-protected by blocks, which size can be defined as:
•
the upper quarter memory array
•
the upper half memory array
•
the upper 3/4 memory array
•
the whole memory array
Table 5. Write Protect register (Address = 1xxx.xxxx.xxxx.xxxxb)
b7
b6
b5
b4
Write
x
x
x
x
Read
0
0
0
0
Note:
b3
b2
b1
b0
Write protect
activation
Size of write
protected block
Size of write
protected
block
Write protect
lock
Location 1xxx.xxxx.xxxx.xxxxb is outside of the addressing field of the EEPROM memory
(16 Kbytes are addressed within the 00xx.xxxx.xxxx.xxxx range)
•
•
•
•
Bit b3 enables or disables the Write protection
–
b3=0: the whole memory can be written (no Write protection)
–
b3=1: the concerned block is write-protected
Bits b2 and b1 define the size of the memory block to be protected against write
instructions
–
b2,b1=0,0: the upper quarter of memory is write-protected
–
b2,b1=0,1: the upper half memory is write-protected
–
b2,b1=1,0: the upper 3/4 of memory are write-protected
–
b2,b1=1,1: the whole memory is write-protected
bit b0 locks the write protect status
–
b0=0: bits b3,b2,b1,b0 can be modified
–
b0=1: bits b3,b2,b1,b0 cannot be modified and therefore the memory write
protection is frozen.
b7, b6, b5, b4 bits are Don't Care bits.
Writing the Write Protect register
Writing in the Write protect register is performed with a Byte Write instruction at address
1xxx.xxxx.xxxx.xxxxb. Bits b7,b6,b5,b4 of the data byte are not significant (Don't Care).
Writing more than one byte will discard the write cycle (Write protect register content will not
be changed).
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5.1.4
Instructions
Minimizing Write delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (tw) is
shown in AC characteristics tables in Section 8: DC and AC parameters, but the typical time
is shorter. To make use of this, a polling sequence can be used by the bus master.
The sequence, as shown in Figure 7, is:
•
Initial condition: a Write cycle is in progress.
•
Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
•
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Figure 7. Write cycle polling flowchart using ACK
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1. The seven most significant bits of the Device Select code of a Random Read (bottom right box in the
figure) must be identical to the seven most significant bits of the Device Select code of the Write (polling
instruction in the figure).
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Instructions
5.2
M24C32S-FCU
Read operations
Read operations are performed independently of the Write protection state.
After the successful completion of a Read operation, the device internal address counter is
incremented by one, to point to the next byte address.
For the Read instructions, after each byte read (data out), the device waits for an
acknowledgment (data in) during the 9th bit time. If the bus master does not acknowledge
during this 9th time, the device terminates the data transfer and switches to its Standby
mode.
Figure 8. Read mode sequences
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5.2.1
!)D
Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure 8) but without sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the device select code, with the RW bit set to 1. The device
acknowledges this, and outputs the contents of the addressed byte. The bus master must
not acknowledge the byte, and terminates the transfer with a Stop condition.
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5.2.2
Instructions
Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the R/W bit set to 1. The device acknowledges this, and
outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure 8, without acknowledging the byte.
5.2.3
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in Figure 8.
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter “rolls-over”, and the device continues to output data from memory address
00h.
5.2.4
Read the Write Protect register
Reading the Write Protect register is performed with a Random Read instruction at address
1xxx.xxxx.xxxx.xxxxb. Bits b7, b6, b5, b4 of the Write Protect register content are read as
0, 0, 0, 0. The signification of the Protect Register lower bits b3, b2, b1, b0 are defined in
Section 5.1.3: Write protection.
Reading more than one byte will loop on reading the Write Protect Register value.
The Write Protect register cannot be read while a write cycle (tw) is ongoing.
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Initial delivery state
6
M24C32S-FCU
Initial delivery state
The device is delivered with all the memory array bits set to 1 (each byte contains FFh) and
the Write Protect register set to 0 (00h).
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7
Maximum rating
Maximum rating
Stressing the device outside the ratings listed in Table 6 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 6. Absolute maximum ratings
Symbol
TSTG
TLEAD
Parameter
Min.
Max.
Unit
Ambient operating temperature
–40
130
°C
Storage temperature
–65
150
°C
note(1)
°C
–0.50
6
V
-
5
mA
–0.50
6
V
-
4000
V
Lead temperature during soldering
VIO
Input or output range
IOL
DC output current (SDA = 0)
VCC
Supply voltage
VESD
Electrostatic pulse (Human Body model)
see
1. Compliant with JEDEC standard J-STD-020D (for small-body, Sn-Pb or Pb free assembly), the ST
ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances
(RoHS directive 2011/65/EU of July 2011).
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DC and AC parameters
8
M24C32S-FCU
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device.
Table 7. Test conditions
Symbol
Data
retention(1)
Cycling
Parameter
Min.
Unit
TA = 55 °C
200
year
TA = 25 °C
4 million
cycle
1. The data retention behavior is checked in production. The 200-year limit is defined from characterization
and qualification results.
Table 8. Operating conditions
Symbol
VCC
TA
fC
22/35
Parameter
Min.
Supply voltage
1.60
1.70
Ambient operating temperature: READ
–40
–40
Ambient operating temperature: WRITE
0
–40
Max.
Unit
5.5
V
85
°C
Operating clock frequency, VCC = 1.6 V
-
400
Operating clock frequency, VCC = 1.7 V
-
1000
DocID026427 Rev 5
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M24C32S-FCU
DC and AC parameters
Table 9. DC characteristics
Symbol
Parameter
ILI
Input leakage current
(SCL, SDA)
ILO
Output leakage
current
ICC
Supply current (Read)
Test conditions
Min.
Max.
Unit
VIN = VSS or VCC
device in Standby mode
-
±2
µA
SDA in Hi-Z, external voltage applied
on SDA: VSS or VCC
-
±2
µA
VCC < 1.8 V, fC = 400 kHz
-
0.8
mA
VCC >= 1.8 V, fC = 400 kHz
-
2
mA
(1)
-
2.5
mA
During tW
-
2
mA
Device not selected (3),
VIN = VSS or VCC, VCC = 1.8 V
-
1
µA
Device not selected (3),
VIN = VSS or VCC, VCC = 2.5 V
-
2
µA
Device not selected (3),
VIN = VSS or VCC, VCC = 5.5 V
-
3
µA
VCC >= 1.8 V, fC = 1 MHz
ICC0
ICC1
Supply current
(Write)(2)
Standby supply
current
VIL
Input low voltage
(SCL, SDA)
–0.45
0.25 VCC
V
VIH
Input high voltage
(SCL, SDA)
0.75 VCC
VCC + 1
V
IOL = 1 mA, VCC < 1.8 V
-
0.2
V
IOL = 2.1 mA, VCC = 2.5 V
-
0.4
V
IOL = 3 mA, VCC = 5.5 V
-
0.4
V
VOL
Output low voltage
1. Only for devices operating at fcMax = 1 MHz (See Table 8)
2. Characterized value, not tested in production.
3. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
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DC and AC parameters
M24C32S-FCU
Table 10. 400 kHz AC characteristics
Symbol
Alt.
fC
fSCL
Clock frequency
tCHCL
tHIGH
tCLCH
tLOW
tQL1QL2(1)
tF
tXH1XH2
tR
Parameter
Min.
Max.
Unit
-
400
kHz
Clock pulse width high
600
-
ns
Clock pulse width low
1300
-
ns
SDA (out) fall time
20 (2)
300
ns
Input signal rise time
(3)
(3)
ns
(3)
(3)
ns
100
-
ns
tXL1XL2
tF
Input signal fall time
tDXCH
tSU:DAT
Data in set up time
tCLDX
tHD:DAT
Data in hold time
0
-
ns
50
-
ns
-
900
ns
tCLQX
(4)
tDH
Data out hold time
tCLQV
(5)
tAA
Clock low to next data valid (access time)
tCHDL
tSU:STA
Start condition setup time
600
-
ns
tDLCL
tHD:STA
Start condition hold time
600
-
ns
tCHDH
tSU:STO
Stop condition set up time
600
-
ns
tDHDL
tBUF
Time between Stop condition and next Start
condition
1300
-
ns
tW
tWR
Write time
-
5
ms
tNS(1)
-
Pulse width ignored (input filter on SCL and
SDA) - single glitch
-
50
ns
1. Characterized only, not tested in production.
2. With CL = 10 pF.
3. There is no min. or max. value for the input signal rise and fall times. It is however recommended by the I²C
specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
fC < 400 kHz.
4. The min value for tCLQX (Data out hold time) offers a safe timing to bridge the undefined region of the falling
edge SCL.
5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or
0.7VCC, assuming that Rbus × Cbus time constant is less than 400 ns.
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DC and AC parameters
Table 11. High frequency clock AC characteristics
Symbol
Alt.
Parameter
fC
fSCL
Clock frequency
tCHCL
tHIGH
Clock pulse width high
Min.
Max.
Unit
0
1
MHz
-
ns
-
ns
260
tCLCH
tLOW
Clock pulse width low
tXH1XH2
tR
Input signal rise time
(2)
(2)
ns
Input signal fall time
(2)
(2)
ns
120
ns
tXL1XL2
(3)
tF
700
(1)
tF
SDA (out) fall time
tDXCH
tSU:DAT
Data in setup time
50
-
ns
tCLDX
tHD:DAT
Data in hold time
0
-
ns
50
-
ns
-
650
ns
tQL1QL2
tCLQX
(5)
tDH
Data out hold time
tCLQV
(6)
tAA
Clock low to next data valid (access time)
20
(4)
tCHDL
tSU:STA
Start condition setup time
250
-
ns
tDLCL
tHD:STA
Start condition hold time
250
-
ns
tCHDH
tSU:STO
Stop condition setup time
250
-
ns
tDHDL
tBUF
Time between Stop condition and next Start
condition
500
-
ns
tW
tWR
Write time
-
5
ms
tNS (3)
-
Pulse width ignored (input filter on SCL and
SDA)
-
50
ns
1. 600ns when -20°C ≤ t°≤ +85°C. Characterized only, not tested in production.
2. There is no min. or max. values for the input signal rise and fall times. However, it is recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 120 ns when
fC < 1 MHz.
3. Characterized only, not tested in production.
4. With CL = 10 pF.
5. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
6. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or
0.7 VCC, assuming that the Rbus × Cbus time constant is within the values specified in Figure 9.
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DC and AC parameters
M24C32S-FCU
Figure 9. Maximum Rbus value versus bus parasitic capacitance (Cbus) for
an I2C bus at maximum frequency fC = 400 kHz
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DC and AC parameters
Figure 11. AC waveforms
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DocID026427 Rev 5
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34
Package information
9
M24C32S-FCU
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
9.1
Ultra Thin WLCSP package information
Figure 12. Ultra Thin WLCSP- 4-bump, 0.833 x 0.833 mm, wafer level chip scale
package outline
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1. Drawing is not to scale.
28/35
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Package information
Table 12. Ultra Thin WLCSP- 4-bump, 0.833 x 0.833 mm, wafer level chip scale
package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
0.2400
0.2700
0.3000
0.0094
0.0106
0.0118
A1
-
0.0950
-
-
0.0037
-
A2
-
0.1750
-
-
0.0069
-
(2)
-
0.1850
-
-
0.0073
-
D
-
0.8330
0.8530
-
0.0328
0.0336
E
-
0.8330
0.8530
-
0.0328
0.0336
e
-
0.4000
-
-
0.0157
-
e1
-
0.5000
-
-
0.0197
-
F
-
0.2170
-
-
0.0085
-
G
0.1670
-
-
0.0066
-
aaa
0.1100
0.0043
bbb
0.1100
0.0043
ccc
0.1100
0.0043
ddd
0.0600
0.0024
eee
0.0600
0.0024
b
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension is measured at the maximum bump diameter parallel to primary datum Z
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Package information
M24C32S-FCU
Figure 13. Ultra Thin WLCSP- 4-bump, 0.833 x 0.833 mm, wafer level chip scale
package outline with BSC
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1. Drawing is not to scale.
2. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
30/35
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Package information
Table 13. Ultra Thin WLCSP- 4-bump, 0.833 x 0.833 mm, wafer level chip scale
package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
0.265
0.295
0.330
0.0104
0.0116
0.0130
A1
-
0.095
-
-
0.0037
-
A2
-
0.200
-
-
0.0079
-
A3 (BSC)
-
0.025
-
-
0.0010
-
-
0.185
-
-
0.0073
-
D
-
0.833
0.853
-
0.0328
0.0336
E
-
0.833
0.853
-
0.0328
0.0336
e
-
0.400
-
-
0.0157
-
e1
-
0.500
-
-
0.0197
-
F
-
0.217
-
-
0.0085
-
G
-
0.167
-
-
0.0066
-
aaa
-
-
0.110
-
-
0.0043
bbb
-
-
0.110
-
-
0.0043
ccc
-
-
0.110
-
-
0.0043
ddd
-
-
0.060
-
-
0.0024
eee
-
-
0.060
-
-
0.0024
(2) (3)
b
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
Figure 14. Thin WLCSP- 4-bump, 0.833 x 0.833 mm, wafer level chip scale
package recommended footprint
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Part numbering
10
M24C32S-FCU
Part numbering
Table 14. Ordering information scheme
Example:
M24 C32S -F CU 6
T
/T
F
Device type
M24 = I2C serial access EEPROM
Device function
C32S = 32 Kbits (4 K x 8 bits)
Operating voltage
F = VCC = 1.7 V to 5.5 V
Package(1)
CU = ultra-thin 4-bump WLCSP
Device grade
6 = device tested with standard test flow over –40 to 85 °C
Packing
T = Tape and reel packing
Process technology(2)
/T = Process letter
Option
blank = no Back Side Coating (WLCSP height = 0.300mm)
F = Back Side Coating (WLCSP height = 0.330mm)
1. The package is ECOPACK2® (RoHS compliant and free of brominated, chlorinated and antimony oxide
flame retardants).
2. The process letter appears on the device package (marking) and on the shipment box. Please contact
your nearest ST Sales Office for further information.
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Part numbering
Engineering samples
Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are
not yet qualified and therefore not yet ready to be used in production and any consequences
deriving from such usage will not be at ST charge. In no event, ST will be liable for any
customer usage of these engineering samples in production. ST Quality has to be contacted
prior to any decision to use these Engineering samples to run qualification activity.
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Revision history
11
M24C32S-FCU
Revision history
Table 15. Document revision history
Date
Revision
05-Jun-2014
1
Initial release
2
Updated Features
Updated Table 8: Operating conditions
Added Table 11: High frequency clock AC characteristics
Updated Table 12: Ultra Thin WLCSP- 4-bump, 0.833 x 0.833 mm,
wafer level chip scale package mechanical data
Added Table 13: Ultra Thin WLCSP- 4-bump, 0.833 x 0.833 mm, wafer
level chip scale package mechanical data
Added Figure 10: Maximum Rbus value versus bus parasitic
capacitance (Cbus) for an I2C bus at high clock frequency
Added Figure 12: Ultra Thin WLCSP- 4-bump, 0.833 x 0.833 mm, wafer
level chip scale package outline
Added Figure 13: Ultra Thin WLCSP- 4-bump, 0.833 x 0.833 mm, wafer
level chip scale package outline with BSC
Added Figure 14: Thin WLCSP- 4-bump, 0.833 x 0.833 mm, wafer level
chip scale package recommended footprint
Added option F inside Table 14: Ordering information scheme
Added note after Table 14: Ordering information scheme.
3
Change from Preliminary to Production data status
Updated Icc(read) value in Table 9: DC characteristics
Updated Figure 10: Maximum Rbus value versus bus parasitic
capacitance (Cbus) for an I2C bus at high clock frequency
27-Jul-2015
4
Updated:
– Features in cover page
– Figure 2
– Note 1 on Table 6
– Table 7 and its note 1.
– Figure 13
– Table 13
14-Oct-2015
5
Added:
– Note 1 on Table 11.
– notes 1 and 2 on Table 14
13-Jan-2015
30-Apr-2015
34/35
Changes
DocID026427 Rev 5
M24C32S-FCU
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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