MOTOROLA MPC7450EC Freescale semiconductor, inc. Datasheet

Freescale Semiconductor, Inc.
Advance Information
MPC7450EC/D
Rev. 4, 11/2001
MPC7450
RISC Microprocessor
Hardware Specifications
Freescale Semiconductor, Inc...
C
IN
.
R,
O
The MPC7450 is a reduced instruction set computing (RISC)
CT microprocessor that implements
U
the PowerPC instruction set architecture. This document
describes pertinent electrical and
ND characteristics of the processor, refer
physical characteristics of the MPC7450. For functional
O
ICUser’s Manual.
to the MPC7450 RISC Microprocessor Family
M
SE
This document contains the following
topics:
E
AL
Topic
Page
C
S
Section 1.1, “Overview”
1
EE
R
Section 1.2, “Features”
3
F
Y
Section 1.3, “Comparison
with the MPC7400”
7
B
D
E “General Parameters”
Section
9
V1.4,
I
Section
9
CH 1.5, “Electrical and Thermal Characteristics”
R
30
A Section 1.6, “Pin Assignments”
Section 1.7, “Pinout Listings for the 483 CBGA Package”
Section 1.8, “Package Description”
Section 1.9, “System Design Information”
Section 1.10, “Document Revision History”
Section 1.11, “Ordering Information”
31
34
36
48
49
To locate any published updates for this document, refer to the website at
http://www.motorola.com/semiconductors
1.1
Overview
The MPC7450 is the third implementation of the fourth generation (G4) microprocessors from
Motorola. The MPC7450 implements the full PowerPC 32-bit architecture and is targeted at
networking and computing systems applications. The MPC7450 consists of a processor core,
a 256-Kbyte L2, and an internal L3 tag and controller which support a glueless backside L3
cache through a dedicated high bandwidth interface.
Figure 1 shows a block diagram of the MPC7450. The core is a high-performance superscalar
design supporting a double-precision floating-point unit and a SIMD multimedia unit. The
memory storage subsystem supports the MPX bus interface to main memory and other system
resources. The L3 interface supports 1 or 2 Mbytes of external SRAM for L3 cache data.
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MPC7450 RISC Microprocessor Hardware Specifications
Completes up to three instructions per clock
64-Bit Data
(8-Bit Parity)
External SRAM
(1 or 2 Mbytes)
Push
36-Bit Address Bus
Bus Accumulator
Castout
Queue
(9)
Bus Store Queue
L2 Prefetch (3)
32-Bit
Completed
Stores
Load Miss
L1 Castout
EA
64-Bit Data Bus
FPR File
Tags
64-Bit
FPSCR
+ x÷
FloatingPoint Unit
Reservation
Stations (2)
Instruction Fetch (2)
Cacheable Store
Request (1)
L1 Load Miss (5)
L1 Load Queue (LLQ)
L1 Service Queues
L1 Store Queue
(LSQ)
64-Bit
32-Kbyte
I Cache
32-Kbyte
D Cache
Tags
128-Bit (4 Instructions)
16 Rename
Buffers
PA
.
L2 Store Queue (L2SQ)
Snoop Push/
Interventions
L1 Castouts
(4)
256-Kbyte Unified L2 Cache/Cache Controller
Line Block 0 (32-Byte)
Block 1 (32-Byte)
Tags Status
Status
Memory Subsystem
System Bus Interface
128-Bit
32-Bit
L1 Push
Finished
Stores
+ (EA Calculation)
Vector Touch Engine
Load/Store Unit
Reservation
Stations (2-Entry)
DBAT Array
128-Entry
DTLB
Data MMU
SRs
(Original)
C
IN
18-Bit
Address
L3CR
128-Bit
+++
x÷
32-Bit
Integer
Integer
Integer
Unit
122
Unit
Unit
(3)
Integer
Unit 2
GPR File
16 Rename
Buffers
128-Entry
ITLB
IBAT Array
SRs
(Shadow)
Instruction MMU
R,
O
CT
U
ND
Bus Accumulator
Line Block 0/1
Tags Status
L3 Cache Controller
Vector
FPU
Reservation
Reservation
Reservation
Station
Station
Station
S
Completion Unit
Vector
Integer
Unit 1
Vector
Touch
Queue
LE
A
SC
O
IC
EM
Completion Queue
(16-Entry)
Vector
Integer
Unit 2
BY
Vector
Permute
Unit
VR File
Instruction Queue
(12-Word)
FPR Issue
(2-Entry/1-Issue)
ED
V
I
EE
R
F
16 Rename
Buffers
Dispatch
Unit
Fetcher
GPR Issue
(6-Entry/3-Issue)
Reservation
Stations (2)
LR
BHT (2048-Entry)
VR Issue
(4-Entry/2-Issue)
CTR
BTIC (128-Entry)
Branch Processing Unit
Instruction Unit
CH
R
A
Reservation Reservation Reservation Reservation
Station
Station
Station
Station
96-Bit (3 Instructions)
Additional Features
• Time Base
Counter/Decrementer
• Clock Multiplier
• JTAG/COP Interface
• Thermal/Power Management
• Performance Monitor
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Overview
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Figure 1. MPC7450 Block Diagram
MOTOROLA
Freescale Semiconductor, Inc.
Features
1.2
Features
This section summarizes features of the MPC7450 implementation of the PowerPC architecture. Major
features of the MPC7450 are as follows:
Major features of the MPC7450 are as follows:
•
High-performance, superscalar microprocessor
— As many as 4 instructions can be fetched from the instruction cache at a time
— As many as 3 instructions can be dispatched to the issue queues at a time
— As many as 12 instructions can be in the instruction queue (IQ)
C
IN
.
— As many as 16 instructions can be at some stage of execution simultaneously
R,
TO
C
— One instruction per clock cycle throughput for most instructions
DU
N
O
— Seven-stage pipeline control
IC
M
Eleven independent execution units and three register
files
SE
— Branch processing unit (BPU) features static
LE and dynamic branch prediction
A
– 128-entry (32-set, four-way set-associative)
branch target instruction cache (BTIC), a
C
S
E
cache of branch instructionsEthat have been encountered in branch/loop code sequences. If
RBTIC, it is fetched into the instruction queue a cycle sooner
a target instruction is in F
the
Y
than it can be madeBavailable
from the instruction cache. Typically, a fetch that hits the
BTIC provides the
first four instructions in the target stream.
D
VE history table (BHT) with two bits per entry for four levels of
I
– 2048-entry
branch
CH
prediction—
R
A
not-taken,
strongly not-taken, taken, strongly taken
Freescale Semiconductor, Inc...
— Single-cycle execution for most instructions
•
– Up to three outstanding speculative branches
– Branch instructions that do not update the count register (CTR) or link register (LR) are
often removed from the instruction stream.
– 8-entry link register stack to predict the target address of Branch Conditional to Link
Register (bclr) instructions.
— Four integer units (IUs) that share 32 GPRs for integer operands
– Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except
multiply, divide, and move to/from special-purpose register instructions.
– IU2 executes miscellaneous instructions including the CR logical operations, integer
multiplication and division instructions, and move to/from special-purpose register
instructions.
— Five-stage FPU and a 32-entry FPR file
– Fully IEEE 754-1985-compliant FPU for both single- and double-precision operations
– Supports non-IEEE mode for time-critical operations
– Hardware support for denormalized numbers
– Thirty-two 64-bit FPRs for single- or double-precision operands
— Four vector units and 32-entry vector register file (VRs)
– Vector permute unit (VPU)
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MPC7450 RISC Microprocessor Hardware Specifications
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Features
– Vector integer unit 1 (VIU1) handles short-latency AltiVec integer instructions, such as
vector add instructions (vaddsbs, vaddshs, and vaddsws, for example)
– Vector integer unit 2 (VIU2) handles longer -latency AltiVec integer instructions, such as
vector multiply add instructions (vmhaddshs, vmhraddshs, and vmladduhm, for
example).
– Vector floating-point unit (VFPU)
— Three-stage load/store unit (LSU)
– Supports integer, floating-point and vector instruction load/store traffic
. stream
– Four-entry vector touch queue (VTQ) supports all four architected AltiVecCdata
N
operations
,I
R
– Three-cycle GPR and AltiVec load latency (byte, half-word, word,
O vector) with 1-cycle
CT
throughput
U
Freescale Semiconductor, Inc...
– Four-cycle FPR load latency (single, double) with 1-cycle
ND throughput
O
– No additional delay for misaligned access withinIC
double-word boundary
M
– Dedicated adder calculates effective addresses
SE (EAs)
LE
A
SC and precision conversion for floating-point data
– Performs alignment, normalization,
E
E
– Executes cache control and
FRTLB instructions
Y padding, and sign extension for integer data
– Performs alignment,
Bzero
D
– Supports hits under
VE misses (multiple outstanding misses)
I
– Supports
CHboth big- and little-endian modes, including misaligned little-endian accesses
R
Aqueues FIQ, VIQ, and GIQ can accept as many as one, two, and three instructions,
Three issue
– Supports store gathering
•
respectively, in a cycle. Instruction dispatch requires the following:
— Instructions can be dispatched only from the three lowest IQ entries—IQ0, IQ1, and IQ2.
— A maximum of three instructions can be dispatched to the issue queues per clock cycle.
— Space must be available in the CQ for an instruction to dispatch (this includes instructions that
are assigned a space in the CQ but not in an issue queue).
•
Rename buffers
— 16 GPR rename buffers
— 16 FPR rename buffers
— 16 VR rename buffers
•
Dispatch unit
— The decode/dispatch stage fully decodes each instruction.
•
Completion unit
— The completion unit retires an instruction from the 16-entry completion queue (CQ) when all
instructions ahead of it have been completed, the instruction has finished execution, and no
exceptions are pending.
— Guarantees sequential programming model (precise exception model)
— Monitors all dispatched instructions and retires them in order
4
MPC7450 RISC Microprocessor Hardware Specifications
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Features
— Tracks unresolved branches and flushes instructions after a mispredicted branch
— Retires as many as three instructions per clock cycle
•
Separate on-chip L1 instruction and data caches (Harvard architecture)
— 32-Kbyte, eight-way set-associative instruction and data caches
— Pseudo least-recently-used (PLRU) replacement algorithm
— 32-byte (eight-word) L1 cache block
— Physically indexed/physical tags
— Cache write-back or write-through operation programmable on a per-page or per-block
basis
.
C
— Instruction cache can provide four instructions per clock cycle; data cacheIN
, can provide four
R
words per clock cycle
O
Freescale Semiconductor, Inc...
— Caches can be disabled in software
— Caches can be locked in software
O
— MESI data cache coherency maintained in hardwareIC
M
CT
U
ND
E
— Separate copy of data cache tags for efficient S
snooping
LE
A
— No snooping of instruction cache except
SC for icbi instruction
E
E
— Data cache supports AltiVec LRU
FR and transient instructions
Y
— Critical double- and/orBquad-word
forwarding is performed as needed. Critical quad-word
D
forwarding is usedEfor AltiVec loads and instruction fetches. Other accesses use critical
double-word forwarding.
IV
H
C interface
Level 2 (L2)Rcache
A
— Parity support on cache and tags
•
— On-chip, 256-Kbyte, 8-way set associative unified instruction and data cache
— Fully pipelined to provide 32 bytes per clock cycle to the L1 caches
— A total 9-cycle load latency for an L1 data cache miss that hits in L2
— Pseudo least-recently-used (PLRU) replacement algorithm
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— 64-byte, two-sectored line size
— Parity support on cache
•
Level 3 (L3) cache interface
— Provides critical double-word forwarding to the requesting unit
— Internal L3 cache controller and tags
— External data SRAMs
— Support for 1- and 2-Mbyte L3 caches
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— 64-byte (1 M) or 128-byte (2 M) sectored line size
— Private memory capability for half (1-Mbyte minimum) or all of the L3 SRAM space
— Supports MSUG2 dual data rate (DDR) synchronous Burst SRAMs, PB2 pipelined
synchronous Burst SRAMs, and pipelined (register-register) Late Write synchronous Burst
SRAMs
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MPC7450 RISC Microprocessor Hardware Specifications
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Features
— Supports parity on cache and tags
— Configurable core-to-L3 frequency divisors
— 64-bit external L3 data bus sustains 64 bits per L3 clock cycle
•
Separate memory management units (MMUs) for instructions and data
— 52-bit virtual address; 32- or 36-bit physical address
— Address translation for 4-Kbyte pages, variable-sized blocks, and 256-Mbyte segments
— Memory programmable as write-back/write-through, caching-inhibited/caching-allowed, and
memory coherency enforced/memory coherency not enforced on a page or block basis
— Separate IBATs and DBATs (four each) also defined as SPRs
C
IN
.
R,
O
– Both TLBs are 128-entry, two-way set associative, and use LRU
CT replacement algorithm
U
– TLBs are hardware- or software-reloadable (that is, onNaDTLB miss a page table search is
performed in hardware or by system software) ICO
M
Efficient data flow
SE
— Although the VR/LSU interface is 128 bits,
LEthe L1/L2/L3 bus interface allows up to 256 bits.
A
C provide 128 bits/cycle to or from the VRs
— The L1 data cache is fully pipelinedSto
E
E
— L2 cache is fully pipelined toRprovide
256 bits per processor clock cycle to the L1 cache.
F
— As many as 8 outstanding,
Y out-of-order, cache misses are allowed between the L1 data cache
B
and L2/L3 bus.
ED
V
— As many as 16Iout-of-order transactions can be present on the MPX bus
CH for multiple store misses to the same line. Only coherency action taken
— Store merging
R
A
(address-only)
for store misses merged to all 32 bytes of a cache block (no data tenure
Freescale Semiconductor, Inc...
— Separate instruction and data translation lookaside buffers (TLBs)
•
needed).
— Three-entry finished store queue and five-entry completed store queue between the LSU and
the L1 data cache
— Separate additional queues for efficient buffering of outbound data (such as cast outs and write
through stores) from the L1 data cache and L2 cache
•
Multiprocessing support features include the following:
— Hardware-enforced, MESI cache coherency protocols for data cache
— Load/store with reservation instruction pair for atomic memory references, semaphores, and
other multiprocessor operations
•
Power and thermal management
— 1.6-V processor core (1.8-V processor core still supported)
— The following three power-saving modes are available to the system:
– Nap—Instruction fetching is halted. Only those clocks for the thermal assist unit (TAU),
time base, decrementer, and JTAG logic remain running. The part goes into the doze state
to snoop memory operations on the bus and then back to nap using a QREQ/QACK
processor-system handshake protocol.
– Sleep—Power consumption is further reduced by disabling bus snooping, leaving only the
PLL in a locked and running state. All internal functional units are disabled.
– Deep sleep—When the part is in the sleep state, the system can disable the PLL resulting.
6
MPC7450 RISC Microprocessor Hardware Specifications
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Comparison with the MPC7400
The system can then disable the SYSCLK source for greater system power savings.
Power-on reset procedures for restarting and relocking the PLL must be followed on
exiting the deep sleep state.
— Thermal management facility provides software-controllable thermal management. Thermal
management is performed through the use of three supervisor-level registers and an
MPC7451-specific thermal management exception.
— Instruction cache throttling provides control of instruction fetching to limit power
consumption.
•
Performance monitor can be used to help debug system designs and improve software
. efficiency.
In-system testability and debugging features through JTAG boundary-scan capability
IN
•
Testability
— LSSD scan design
Freescale Semiconductor, Inc...
C
•
— IEEE 1149.1 JTAG interface
O
IC
EM
R,
O
CT
U
ND
— Array built-in self test (ABIST)—factory test only
S
E
L
— Parity checking on system bus and L3 cache
A bus
C
— Parity checking on L1, L2, and L3
EScache arrays
E
FR
Y
1.3 ComparisonBwith
the MPC7400
D
Table 1 compares the key features
VE of the MPC7450 with the key features of the earlier MPC7400. To achieve
I
H
a higher frequency, theCnumber
of logic levels per cycle is reduced. Also, to achieve this higher frequency,
R
the pipeline of the A
MPC7450 is extended (compared to the MPC7400), while maintaining the same level of
•
Reliability and serviceability
performance as measured by the number of instructions executed per cycle (IPC).
Table 1. Microarchitecture Comparison
Microarchitectural Specs
MPC7450
MPC7400/MPC7410
Basic Pipeline Functions
Logic Inversions per Cycle
18
28
Pipeline Stages up to Execute
5
3
Total Pipeline Stages (Minimum)
7
4
3 + Branch
2 + Branch
Instruction Buffer Size
12
6
Completion Buffer Size
16
8
16, 16, 16
6, 6, 6
Pipeline Maximum Instruction Throughput
Pipeline Resources
Renames (Integer, Float, Vector)
Maximum Execution Throughput
SFX
Vector
Scalar Floating-Point
MOTOROLA
3
2
2 (Any 2 of 4 Units)
2 (Permute/Fixed)
1
1
MPC7450 RISC Microprocessor Hardware Specifications
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Comparison with the MPC7400
Table 1. Microarchitecture Comparison (continued)
Microarchitectural Specs
MPC7450
MPC7400/MPC7410
Out-of-Order Window Size in Execution Queues
SFX Integer Units
1 Entry × 3 Queues
1 Entry × 2 Queues
Vector Units
In Order, 4 Queues
In Order, 2 Queues
In Order
In Order
Scalar Floating-Point Unit
Branch Processing Resources
Prediction Structures
BTIC, BHT, Link Stack
BTIC Size, Associativity
BHT Size
Freescale Semiconductor, Inc...
R,
O
2K-Entry
CT
U
8 D
N
3
O
IC 1
M
E
128-Entry, 4-Way
Link Stack Depth
Unresolved Branches Supported
Branch Taken Penalty (BTIC Hit)
S
LE
A
Execution Unit Timings
C (Latency-Throughput)
S
Aligned Load (Integer, Float, Vector)
3-1, 4-1, 3-1
EE
R
F
Misaligned Load (Integer, Float, Vector)
4-2, 5-2, 4-2
Y
B
L1 Miss, L2 Hit Latency
6 (9)
D
E
SFX (aDd Sub, Shift, Rot, Cmp,
1-1
IVLogicals)
H
32 × 16, 32 × 32)
3-1, 3-1, 4-2
Integer Multiply (32 × 8, C
R
A
Scalar Float
5-1
Minimum Misprediction Penalty
6
BTIC,
C. BHT
N
I
64-Entry, 4-Way
512-Entry
None
2
0
4
2-1, 2-1, 2-1
3-2, 3-2, 3-2
9 (11)1
1-1
2-1, 3-2, 5-4
3-1
VSFX (Vector Simple)
1-1
1-1
VCFX (Vector Complex)
4-1
3-1
VFPU (Vector Float)
4-1
4-1
VPER (Vector Permute)
2-1
1-1
128-Entry, 2-Way
128-Entry, 2-Way
Hardware + Software
Hardware
MMUs
MMUs (Instruction and Data)
Tablewalk Mechanism
L1 I Cache/D Cache Features
Size
32K/32K
32K/32K
8-Way
8-Way
4-Kbyte/Way
Full Cache
Parity on I Cache
Word
None
Parity on D Cache
Byte
None
5/1
8 (Any Combination)
4 Streams
4 Streams
Associativity
Locking Granularity/Style
Number of D Cache Misses (Load/Store)
Data Stream Touch Engines
On-Chip Cache Features
Cache Level
8
L2
MPC7450 RISC Microprocessor Hardware Specifications
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None (Except L1)
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Freescale Semiconductor, Inc.
General Parameters
Table 1. Microarchitecture Comparison (continued)
Microarchitectural Specs
Size/Associativity
MPC7450
MPC7400/MPC7410
256-Kbyte/8-Way
N/A
256 Bits
N/A
2
N/A
Byte
N/A
L3
C. L2
N
I
0.5MB,
1MB, 2MB
Access Width
Number of 32-Byte Sectors/Line
Parity
Off-Chip Cache Support
Cache Level
On-Chip Tag Logical Size
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Associativity
8-Way
Number of 32-Byte Sectors/Line
Off-Chip Data SRAM Support
Data Path Width
Direct Mapped SRAM Sizes
Parity
1
R,
O
2-Way
T
C
2, 4
1, 2, 4
DU
N
MSUG2 DDR, LW, PB2
LW, PB2, PB3
O
IC64
64
M
E
0.5 Mbyte, 1 Mbyte,
S 1 Mbyte, 2 Mbytes
1MB, 2MB
EE
R
F
Numbers in parentheses are for 2:1 SRAM.
LE
A
SC
2 Mbytes
Byte
Byte
BY
D
1.4 General Parameters
VE
I
The following list provides
CH a summary of the general parameters of the MPC7450:
R
A
Technology
0.18 µm CMOS, six-layer metal
Die size
8.69 mm × 12.17 mm (106 mm2)
Transistor count
33 million
Logic design
Fully static
Packages
MPC7450: Surface mount 483 ceramic ball grid array (CBGA)
Core power supply
1.6 V ± 50 mV DC nominal; (operation up to 1.8 V is supported; see Table 4 for
the recommended operating conditions)
I/O power supply
1.8 V ± 5% DC or
2.5 V ± 5% DC or
1.5 V ± 5% DC (L3 interface only)
1.5
Electrical and Thermal Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the MPC7450.
1.5.1
DC Electrical Characteristics
The tables in this section describe the MPC7450 DC electrical characteristics. Table 2 provides the absolute
maximum ratings.
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Electrical and Thermal Characteristics
Table 2. Absolute Maximum Ratings1
Characteristic
Symbol
Maximum Value
Unit
Notes
Core supply voltage
VDD
–0.3 to 1.95
V
4
PLL supply voltage
AVDD
–0.3 to 1.95
V
4
BVSEL = 0
OVDD
–0.3 to 1.95
V
3, 6
BVSEL = HRESET or OVDD
OVDD
–0.3 to 2.7
V
3, 7
L3VSEL = ¬HRESET
GVDD
–0.3 to 1.65
V
3, 8
V
3, 9
V
3, 10
V
2, 5
V
2, 5
Processor bus supply voltage
L3 bus supply voltage
L3VSEL = 0
L3VSEL = HRESET or GVDD
Freescale Semiconductor, Inc...
Input voltage
Processor bus
L3 bus
JTAG signals
Storage temperature range
IN
,
GVDD
–0.3 to 2.7
OR
T
–0.3 to
Vin
COVDD + 0.3
U
D to GVDD + 0.3
Vin
N–0.3
O
Vin
IC –0.3 to OVDD + 0.3
M
–55 to 150
SE Tstg
GVDD
–0.3 to 1.95
C.
V
°C
Notes:
LE
A
1. Functional and tested operating conditions are given
SC in Table 4. Absolute maximum ratings are stress ratings
only, and functional operation at the maximums
is not guaranteed. Stresses beyond those listed may affect device
E
E
reliability or cause permanent damage toR
the device.
F
2. Caution: Vin must not exceed OVDDY
or GVDD by more than 0.3 V at any time including during power-on reset.
B VDD/AVDD by more than 2.0 V at any time including during power-on
3. Caution: OVDD/GVDD must not exceed
reset.
ED
V
4. Caution: VDD/AVDD mustInot exceed OVDD/GVDD by more than 0.4 V at any time including during power-on
reset.
CH
R
5. Vin may overshoot/undershoot
to a voltage and for a maximum duration as shown in Figure 2.
A
6.
7.
8.
9.
10.
10
BVSEL must be set to 0, such that the bus is in 1.8 V mode.
BVSEL must be set to HRESET or 1, such that the bus is in 2.5 V mode.
L3VSEL must be set to ¬HRESET (inverse of HRESET), such that the bus is in 1.5 V mode.
L3VSEL must be set to 0, such that the bus is in 1.8 V mode.
L3VSEL must be set to HRESET or 1, such that the bus is in 2.5 V mode.
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Electrical and Thermal Characteristics
Figure 2 shows the undershoot and overshoot voltage on the MPC7450.
OVDD/GVDD + 20%
OVDD/GVDD + 5%
OVDD/GVDD
VIH
R,
O
CT
U
ND
Freescale Semiconductor, Inc...
VIL
GND
GND – 0.3 V
C
IN
.
O
IC
Not to Exceed
EM 10%
ofStSYSCLK
LE
A
Figure 2. Overshoot/Undershoot
Voltage
SC
E
The MPC7450 provides several I/O voltages
RE to support both compatibility with existing systems and
F
migration to future systems. The MPC7450
core voltage must always be provided at nominal 1.6 V (see
BY voltage). Voltage to the L3 I/Os and processor interface I/Os are
Table 4 for actual recommended
core
D
Eof
provided through separate sets
supply pins and may be provided at the voltages shown in Table 3. The
V
I
Heach
input voltage thresholdC
for
bus is selected by sampling the state of the voltage select pins at the negation
of the signal HRESET.
AR The output voltage will swing from GND to the maximum voltage applied to the
GND – 0.7 V
OVDD or GVDD power pins.
Table 3. Input Threshold Voltage Setting
BVSEL Signal
Processor Bus Input
Threshold is Relative to:
L3VSEL Signal
L3 Bus Input Threshold is
Relative to:
Notes
0
1.8 V
0
1.8 V
1, 4
¬HRESET
Not Available
¬HRESET
1.5 V
1, 3
HRESET
2.5 V
HRESET
2.5 V
1, 2
1
2.5 V
1
2.5 V
1
Notes:
1. Caution: The input threshold selection must agree with the OVDD/GVDD voltages supplied. See notes in Table 2.
2. To select the 2.5-V threshold option for the processor bus, BVSEL should be tied to HRESET so that the two
signals change state together. Similarly, to select 2.5 V for the L3 bus, tie L3VSEL to HRESET. This is the preferred
method for selecting this mode of operation.
3. Applicable to L3 bus interface only. ¬HRESET is the inverse of HRESET.
4. If used, pulldown resistors should be less than 250 Ω .
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Electrical and Thermal Characteristics
Table 4 provides the recommended operating conditions for the MPC7450.
Table 4. Recommended1 Operating Conditions
Recommended Value
Characteristic
Min
Max
Unit
Notes
Core supply voltage
VDD
1.55
1.85
V
3
PLL supply voltage
AVDD
1.55
1.85
V
2, 3
Processor bus supply voltage
L3 bus supply voltage
Freescale Semiconductor, Inc...
Symbol
BVSEL = 0
OVDD
1.8 V ± 5%
BVSEL = HRESET or OVDD
OVDD
2.5 V ± 5%,
L3VSEL = 0
GVDD
L3VSEL = HRESET or GVDD
GVDD
L3VSEL = ¬HRESET
Input voltage
Processor bus
L3 bus
JTAG signals
Die-junction temperature
EE
R
F
LE
A
SC
O
IC
Vin
EM
GVDD
S
R
O
1.8 V
± 5%
T
U2.5CV ± 5%
D
N
C
IN
.
V
V
V
V
1.5 V ± 5%
V
GND
OVDD
V
Vin
GND
GVDD
V
Vin
GND
OVDD
V
Tj
0
105
°C
Notes:
BY
1. These are the recommended and
tested operating conditions. Proper device operation outside of these conditions
D
is not guaranteed.
VE
2. This voltage is the inputH
toIthe filter discussed in Section 1.9.2, “PLL Power Supply Filtering” and not necessarily
C
the voltage at the AV
DD pin which may be reduced from VDD by the filter.
AR at core voltages up to 1.8 V is supported, but the power consumption given in Table 7
3. 1.6 V nominal. Operation
must be adjusted correspondingly by the formula: P = C V 2 f, where P is the power consumption, C is a constant,
V is the core voltage, and f is the core frequency.
Table 5 provides the package thermal characteristics for the MPC7450.
Table 5. Package Thermal Characteristics
Characteristic
Symbol
Value
Rating
CBGA package thermal resistance, junction-to-case thermal resistance
(typical)
θJC
<0.1
°C/W
CBGA package thermal resistance, die junction-to-lead thermal resistance
(typical)
θJB
2.2
°C/W
Note: Refer to Section 1.9, “System Design Information,” for more details about thermal management.
12
MPC7450 RISC Microprocessor Hardware Specifications
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Freescale Semiconductor, Inc.
Electrical and Thermal Characteristics
Table 6 provides the DC electrical characteristics for the MPC7450.
Table 6. DC Electrical Specifications
At recommended operating conditions. See Table 4.
Characteristic
Nominal
Bus
Voltage1
Symbol
Min
Max
Unit
Notes
1.5
VIH
GVDD × 0.65
GVDD + 0.3
V
6
1.8
VIH
OVDD/GVDD × 0.65
OVDD/GVDD + 0.3
2.5
VIH
1.7
1.5
VIL
–0.3
1.8
VIL
–0.3
2.5
VIL
—
CVIH
Input high voltage
(all inputs except SYSCLK)
Freescale Semiconductor, Inc...
Input low voltage
(all inputs except SYSCLK)
SYSCLK input high voltage
SYSCLK input low voltage
Input leakage current,
Vin = GVDD/OVDD + 0.3 V
High impedance (off-state) leakage
current, Vin = GVDD/OVDD + 0.3 V
Output high voltage, IOH = –5 mAED
IV
H
C
AR
Output low voltage, IOL = 5 mA
Capacitance,
Vin = 0 V,
f = 1 MHz
L3 interface
All other inputs
LE
A
—
Iin C
S
E
E
— FR ITSI
BY
—
CVIL
CO
I
M
E1.4
–0.3
C
OVDD/GVDD I+N
0.3
,
R
GVDD
× 0.35
O
CT/GV × 0.35
OV
U
DD
DD
ND
.
V
V
V
6
V
0.7
V
OVDD + 0.3
V
0.4
V
—
10
µA
2, 3
—
10
µA
2, 3, 5
6
S –0.3
1.5
VOH
OVDD/GVDD – 0.45
—
V
1.8
VOH
OVDD/GVDD – 0.45
—
V
2.5
VOH
1.7
—
V
1.5
VOL
—
0.45
V
1.8
VOL
—
0.45
V
2.5
VOL
—
0.7
V
—
Cin
—
9.5
pF
4
—
8.0
pF
4
6
Notes:
1. Nominal voltages; see Table 4 for recommended operating conditions.
2. For processor bus signals, the reference is OVDD while GVDD is the reference for the L3 bus signals.
3. Excludes test signals and IEEE 1149.1 boundary scan (JTAG) signals.
4. Capacitance is periodically sampled rather than 100% tested.
5. The leakage is measured for nominal OVDD/GVDD and VDD, or both OVDD/GVDD and VDD must vary in the same
direction (for example, both OVDD and VDD vary by either +5% or –5%).
6. Applicable to L3 bus interface only.
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Freescale Semiconductor, Inc.
Electrical and Thermal Characteristics
Table 7 provides the power consumption for the MPC7450.
Table 7. Power Consumption for MPC7450
Processor (CPU) Frequency
533 MHz
600 MHz
667 MHz
Unit
Notes
W
1, 3
W
1, 2
W
1, 3, 4
W
1, 3
Full-Power Mode
Typical
11.6
13.0
14.5
Maximum
15.2
17.5
19.0
Doze Mode
Freescale Semiconductor, Inc...
Typical
—
Nap Mode
Typical
Typical
1.3
S
Sleep Mode
LE
A
0.6
SC
IN
,
OR
T
—
C —
U
ND
O
IC1.4
1.7
M
E
0.7
0.8
W
1, 3
460
510
mW
1, 3
Deep Sleep
EE Mode (PLL Disabled)
FR
Typical
BY
1.5.2
AC Electrical Characteristics
410
C.
D
Notes:
VEprocessor bus and L3 bus ratios. The values do not include I/O supply power
1. These values apply for all Ivalid
Hsupply power (AVDD). OVDD and GVDD power is system dependent, but is typically
(OVDD and GVDD) or C
PLL
<20% of VDD power.RWorst case power consumption for AVDD < 3 mW.
A
2. Maximum power is measured at nominal VDD (see Table 4) while running an entirely cache-resident, contrived
sequence of instructions which keep the execution units, with or without AltiVec, maximally busy.
3. Typical power is an average value measured at the nominal recommended VDD (see Table 4) in a system while
running a typical code sequence.
4. Doze mode is not a user-definable state; it is an intermediate state between full-power and either nap or sleep
mode. As a result, power consumption for this mode is not tested.
This section provides the AC electrical characteristics for the MPC7450. After fabrication, functional parts
are sorted by maximum processor core frequency as shown in Section 1.5.2.1, “Clock AC Specifications,”
and tested for conformance to the AC specifications for that frequency. The processor core frequency is
determined by the bus (SYSCLK) frequency and the settings of the PLL_EXT and PLL_CFG[0:3] signals.
Parts are sold by maximum processor core frequency; see Section 1.11, “Ordering Information.”
1.5.2.1
Clock AC Specifications
Table 8 provides the clock AC timing specifications as defined in Figure 3.
14
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Electrical and Thermal Characteristics
Table 8. Clock AC Timing Specifications
At recommended operating conditions. See Table 4.
Maximum Processor Core Frequency
Characteristic
Symbol
600 MHz
667 MHz
Min
Max
Min
Max
Min
Max
Unit
Notes
Processor frequency
fcore
500
533
500
600
500
667
MHz
1
VCO frequency
fVCO
1000
1066
1000
1200
1000
1333
. MHz
1
SYSCLK frequency
fSYSCLK
33
133
MHz
1
SYSCLK cycle time
tSYSCLK
7.5
30
tKR and tKF
—
1.0
tKHKL/tSYSCLK
40
60
SYSCLK jitter
—
±150
Internal PLL relock time
—
SYSCLK rise and fall time
Freescale Semiconductor, Inc...
533 MHz
SYSCLK duty cycle
measured at OVDD/2
100
LE
A
SC
S
NC
33
133
33
133
I
,
7.5
30
7.5 OR 30
T
—
1.0 UC
—
1.0
D
N
40
60
40
60
O
IC
—
±150
E—M ±150
—
100
—
100
ns
ns
2
%
3
ps
4, 6
µs
5
Notes:
E PLL_CFG[0:3] settings must be chosen such that the resulting
1. Caution: The SYSCLK frequency, PLL_EXT E
and
R
SYSCLK (bus) frequency, CPU (core) frequency,
and PLL (VCO) frequency do not exceed their respective
F Refer
maximum or minimum operating frequencies.
to the PLL_EXT, PLL_CFG[0:3] signal description in
Y
Section 1.9.1, “PLL Configuration,” B
for valid PLL_EXT and PLL_CFG[0:3] settings.
2. Rise and fall times for the SYSCLK
ED input measured from 0.4 V to 1.4 V.
V
3. Timing is guaranteed by design
and characterization.
HIjitter—short
4. This represents total input
term and long term combined—and is guaranteed by design.
C
5. Relock timing is guaranteed
by design and characterization. PLL-relock time is the maximum amount of time
AR
required for PLL lock after a stable VDD and SYSCLK are reached during the power-on reset sequence. This
specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also
note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the
power-on reset sequence.
6. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low
to allow cascade connected PLL-based devices to track SYSCLK drivers with the specified jitter.
Figure 3 provides the SYSCLK input timing diagram.
SYSCLK
VM
VM
VM
CVIH
CVIL
tKHKL
tKR
tKF
tSYSCLK
VM = Midpoint Voltage (OVDD/2)
Figure 3. SYSCLK Input Timing Diagram
1.5.2.2
Processor Bus AC Specifications
Table 9 provides the processor bus AC timing specifications for the MPC7450 as defined in Figure 4 and
Figure 5. Timing specifications for the L3 bus are provided in Section 1.5.2.3, “L3 Clock AC
Specifications.”
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Freescale Semiconductor, Inc.
Electrical and Thermal Characteristics
Table 9. Processor Bus AC Timing Specifications
At recommended operating conditions. See Table 4.
All Speed Grades
Symbol2
Freescale Semiconductor, Inc...
Parameter
Min
Max
Unit
Notes
Mode select input setup to HRESET
tMVRH
8
—
tsysclk
3, 4, 5, 6
HRESET to mode select input hold
tMXRH
0
—
ns
3, 5
tAVKH
2.0
—
Input setup times:
A[0:35], AP[0:4], GBL, TBST, TSIZ[0:2], WT, CI,
D[0:63], DP[0:7]
AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3],
HRESET, INT, MCP, QACK, SMI, SRESET, TA,
TBEN, TEA, TS, EXT_QUAL, PMON_IN, SHD[0:1]
tIVKH
Input hold times:
CO
A[0:35], AP[0:4], GBL, TBST, TSIZ[0:2], WT, CI,
tAXKH I
D[0:63], DP[0:7]
EM
S
AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3],
E tIXKH
L
HRESET, INT, MCP, QACK, SMI, SRESET, TA,
A
TBEN, TEA, TS, EXT_QUAL, PMON_IN, SHD[0:1]SC
R,
—
O
CT
U
ND
ns
.
C
IN
2.0
ns
0
—
0
—
—
—
—
—
—
2.5
2.5
2.8
2.5
2.5
Output hold times: A
A[0:35], AP[0:4], GBL, TBST, TSIZ[0:2], WT, CI
TS
D[0:63], DP[0:7]
ARTRY/SHD0/SHD1
BR, CKSTP_OUT, DRDY, HIT, PMON_OUT, QREQ
tKHAV
tKHTSV
tKHDV
tKHARV
tKHOV
tKHAX
tKHTSX
tKHDX
tKHARX
tKHOX
0.5
0.5
0.5
0.5
0.5
—
—
—
—
—
SYSCLK to output enable
tKHOE
0.5
—
ns
SYSCLK to output high impedance (all except TS, ARTRY,
SHD0, SHD1)
tKHOZ
—
3.5
ns
SYSCLK to TS high impedance after precharge
tKHTSPZ
—
1
tsysclk
5, 7, 10
Maximum delay to ARTRY/SHD0/SHD1 precharge
tKHARP
—
1
tsysclk
5, 8,
9, 10
E
E
Output valid times:
FRCI
A[0:35], AP[0:4], GBL, TBST, TSIZ[0:2], WT,
TS
BY
D
D[0:63], DP[0:7]
ARTRY/SHD0/SHD1
VE
I
BR, CKSTP_OUT, DRDY,HHIT, PMON_OUT, QREQ]
RC
16
ns
ns
MPC7450 RISC Microprocessor Hardware Specifications
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Freescale Semiconductor, Inc.
Electrical and Thermal Characteristics
Table 9. Processor Bus AC Timing Specifications (continued)
At recommended operating conditions. See Table 4.
All Speed Grades
Symbol2
Parameter
Freescale Semiconductor, Inc...
SYSCLK to ARTRY/SHD0/SHD1 high impedance after
precharge
tKHARPZ
Min
Max
—
2
Unit
Notes
tsysclk
5, 8,
9, 10
Notes:
1. All input specifications are measured from the midpoint of the signal in question to the midpoint of. the rising edge
C of SYSCLK to
of the input SYSCLK. All output specifications are measured from the midpoint of the rising N
edge
I
the midpoint of the signal in question. All output timings assume a purely resistive 50-Ω load
(see
Figure 4). Input
,
R
and output timings are measured at the pin; time-of-flight delays must be added for trace
lengths,
vias, and
O
T
connectors in the system.
UC
2. The symbology used for timing specifications herein follows the pattern of t(signal)(state)(reference)(state)
for inputs
D
and t(reference)(state)(signal)(state) for outputs. For example, tIVKH symbolizesN
the time input signals (I) reach the valid
O or input setup time. And tKHOV
state (V) relative to the SYSCLK reference (K) going to the high (H)C
state
I
symbolizes the time from SYSCLK(K) going high (H) until outputs
M(O) are valid (V) or output valid time. Input hold
time can be read as the time that the input signal (I) went invalid
SE (X) with respect to the rising clock edge (KH)
(note the position of the reference and its state for inputs)
LEand output hold time can be read as the time from the
rising edge (KH) until the output went invalid (OX). A
3. The setup and hold time is with respect to the rising
SC edge of HRESET (see Figure 5).
E
4. This specification is for configuration mode E
Rselect only.
5. tsysclk is the period of the external clockF(SYSCLK)
in nanoseconds (ns). The numbers given in the table must be
multiplied by the period of SYSCLK Y
to compute the actual time duration (in ns) of the parameter in question.
B
6. Mode select signals are: BVSEL,
L3VSEL, PLL_CFG[0:3], PLL_EXT, BMODE[0:1].
D
E
7. According to the bus protocol,
IV TS is driven only by the currently active bus master. It is asserted low then
precharged high beforeHreturning to high impedance as shown in Figure 6. The nominal precharge width for TS is
C than the minimum tSYSCLK period, to ensure that another master asserting TS on the
0.5 × tSYSCLK, i.e.,R
less
A
following clock will not contend with the precharge. Output valid and output hold timing is tested for the signal
asserted. Output valid time is tested for precharge.The high impedance behavior is guaranteed by design.
8. According to the bus protocol, ARTRY can be driven by multiple bus masters through the clock period
immediately following AACK. Bus contention is not an issue because any master asserting ARTRY will be driving
it low. Any master asserting it low in the first clock following AACK will then go to high impedance for one clock
before precharging it high during the second cycle after the assertion of AACK. The nominal precharge width for
ARTRY is 1.0 tsysclk; that is, it should be high impedance as shown in Figure 6 before the first opportunity for
another master to assert ARTRY. Output valid and output hold timing is tested for the signal asserted.The
high-impedance behavior is guaranteed by design.
9. According to the MPX bus protocol, SHD0 and SHD1 can be driven by multiple bus masters beginning the cycle
of TS. Timing is the same as ARTRY, i.e., the signal is high impedance for a fraction of a cycle, then negated for
up to an entire cycle (crossing a bus cycle boundary) before being three-stated again. The nominal precharge
width for SHD0 and SHD1 is 1.0 tsysclk. The edges of the precharge vary depending on the programmed ratio of
core to bus (PLL configurations).
10. Guaranteed by design and not tested.
Figure 4 provides the AC test load for the MPC7450.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 4. AC Test Load
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Freescale Semiconductor, Inc.
Electrical and Thermal Characteristics
Figure 5 provides the mode select input timing diagram for the MPC7450.
VM
HRESET
tMVRH
tMXRH
Mode Signals
VM = Midpoint Voltage (OVDD/2)
Figure 5. Mode Input Timing Diagram
Freescale Semiconductor, Inc...
Figure 6 provides the input/output timing diagram for the MPC7450.
SYSCLK
VM
VM
tAVKH
LE
A
SC
tIVKH
All Inputs
All Outputs
(Except TS, CH
ARTRY, SHD0, SHD1)
AR
ED
V
I
BY
Et E
R
F KHAV
tKHDV
tKHOV
tKHOE
S
C
IN
.
R,
O
CT
U
VM
ND
O
ICtAXKH
EM
tIXKH
tKHAX
tKHDX
tKHOX
tKHOZ
All Outputs
(Except TS,
ARTRY, SHD0, SHD1)
tKHTSPZ
tKHTSV
tKHTSX
tKHTSV
TS
tKHARPZ
tKHARV
ARTRY,
SHD0,
SHD1
tKHARP
tKHARX
VM = Midpoint Voltage (OVDD/2)
Figure 6. Input/Output Timing Diagram
18
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Electrical and Thermal Characteristics
1.5.2.3
L3 Clock AC Specifications
The L3_CLK frequency is programmed by the L3 configuration register (L3CR[6:8]) core-to-L3 divisor
ratio. See Table 17 for example core and L3 frequencies at various divisors. Table 10 provides the potential
range of L3_CLK output AC timing specifications as defined in Figure 7.
Freescale Semiconductor, Inc...
The maximum L3_CLK frequency is the core frequency divided by two. However, very few SRAM designs
will be able to operate in this mode and most designs will select a greater core-to-L3 divisor to provide a
longer L3_CLK period for read and write access to the L3 SRAMs. Therefore, the maximum L3_CLK
frequency shown in Table 10 is considered to be the practical maximum in a typical system. The maximum
L3_CLK frequency for any application of the MPC7450 will be a function of the AC .timings of the
MPC7450, the AC timings for the SRAM, bus loading, and printed circuit board trace length.
NC
,I
R
Motorola is similarly limited by system constraints and cannot perform testsOof the L3 interface on a
socketed part on a functional tester at the maximum frequencies of Table 10. Therefore,
functional operation
CT
U
and AC timing information are tested at core-to-L3 divisors which result
in
L3
frequencies
at 200 MHz or
D
N
less.
O
IC
Table 10. L3_CLK Output AC Timing
EM Specifications
S
At recommended operating conditions. See Table 4.
LE
A
All Speed Grades
SC
Parameter
Symbol
Unit
Notes
E
E
Min
Max
R
F
L3 clock frequency
fL3_CLK
75
266
MHz
1
BY
D
3.75
13.3
ns
L3 clock cycle time
tL3_CLK
E
V
I
50
%
2
L3 clock duty cycle
tCHCL/tL3_CLK
H
C
—
200
ps
3
L3 clock output-to-output
tL3CSKW1
AR skew (L1_CLK0 to L1_CLK1)
L3 clock output-to-output skew (L1_CLK[0:1] to
L1_ECHO_CLK[1:3])
L3 clock jitter
tL3CSKW2
—
100
ps
4
—
±50
ps
5
Notes:
1. The maximum L3 clock frequency will be system dependent. See Section 1.5.2.3, “L3 Clock AC Specifications” for
an explanation that this maximum frequency is not functionally tested at speed by Motorola.
2. The nominal duty cycle of the L3 output clocks is 50% measured at midpoint voltage.
3. Maximum possible skew between L3_CLK0 and L3_CLK1. This parameter is critical to the address and control
signals which are common to both SRAM chips in the L3.
4. Maximum possible skew between L3_CLK0 and L3_ECHO_CLK1 or between L3_CLK1 and L3_ECHO_CLK3 for
PB2 or Late Write SRAM. This parameter is critical to the write data signals which are separately latched onto each
SRAM part by these pairs of signals.
5. Guaranteed by design and not tested. The input jitter on SYSCLK affects L3 output clocks and the L3 address/data/
control signals equally and, therefore, is already comprehended in the AC timing and does not have to be
considered in the L3 timing analysis. The clock-to-clock jitter shown here is uncertainty in the internal clock period
caused by supply voltage noise or thermal effects. This must be accounted for, along with clock skew, in any L3
timing analysis.
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Freescale Semiconductor, Inc.
Electrical and Thermal Characteristics
The L3_CLK timing diagram is shown in Figure 7.
.
tL3CF
tL3CR
tL3_CLK
tCHCL
L3_CLK0
VM
VM
VM
L3_CLK1
VM
VM
VM
VM
tL3CSKW1
For PB2 or Late Write:
Freescale Semiconductor, Inc...
L3_ECHO_CLK1
L3_ECHO_CLK3
VM
VM
VM
VM
LE
C
IN
.
R,
O
CT VM
VM
U
D
tN
L3CSKW2
O
VM
VM
IC
M
tL3CSKW2
SE
Figure 7. L3_CLK_OUT
A Output Timing Diagram
SC
E
E
1.5.2.4
L3 Bus AC Specifications
FR
BYthree different types of SRAM: source-synchronous, double data rate
The MPC7450 L3 interface supports
D
(DDR) MSUG2 SRAM, LateEWrite SRAMs, and pipeline burst (PB2) SRAMs. Each requires a different
IV and a different routing of the L3 clock signals. The type of SRAM is
protocol on the L3 interface
H
programmed in L3CR[22:23]
and the MPC7450 then follows the appropriate protocol for that type. The
RC
A
designer must connect and route the L3 signals appropriately for each type of SRAM. Following are some
observations about the chip-to-SRAM interface.
•
The routing for the point-to-point signals (L3_CLK[0:1], L3DATA[0:63], L3DP[0:7], and
L3_ECHO_CLK[0:3]) to a particular SRAM must be delay matched.
•
For a 1-Mbyte L3, use address bits 0:16 (bit 0 is LSB).
•
No pull-up resistors are required for the L3 interface.
•
For high speed operations, L3 interface address and control signals should be a “T” with minimal
stubs to the two loads; data and clock signals should be point-to-point to their single load. Figure 8
shows the AC test load for the L3 interface.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 8. AC Test Load for the L3 Interface
In general, if routing is short, delay-matched, and designed for incident wave reception and minimal
reflection, there is a high probability that the AC timing of the MPC7450 L3 interface will meet the
maximum frequency operation of appropriately chosen SRAMs. This is despite the pessimistic,
guard-banded AC specifications (see Table 12, Table 13, and Table 14), the limitations of functional testers
described in Section 1.5.2.3, “L3 Clock AC Specifications,” and the uncertainty of clocks and signals which
inevitably make worst-case critical path timing analysis pessimistic.
20
MPC7450 RISC Microprocessor Hardware Specifications
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Freescale Semiconductor, Inc.
Electrical and Thermal Characteristics
Freescale Semiconductor, Inc...
More specifically, certain signals within groups should be delay-matched with others in the same group
while intergroup routing is less critical. Only the address and control signals are common to both SRAMs
and additional timing margin is available for these signals. The double-clocked data signals are grouped
with individual clocks as shown in Figure 9 or Figure 11, depending on the type of SRAM. For example,
for the MSUG2 DDR SRAM (see Figure 9); L3DATA[0:31], L3DP[0:3], and L3_CLK[0] form a closely
coupled group of outputs from the MPC7450; while L3DATA[0:15], L3DP[0:1], and L3_ECHO_CLK[0]
form a closely coupled group of inputs.
The MPC7450 RISC Microprocessor Family User’s Manual refers to logical settings called “Sample
Points” used in the synchronization of reads from the receive FIFO. The computation of the correct value
for this setting is system-dependent and is described in the MPC7450 RISC Microprocessor
C. Family User’s
N
Manual. Three specifications are used in this calculation and are given in Table 11. ItI is essential that all
,
three specifications are included in the calculations to determine the sample points,Ras incorrect settings can
O
result in errors and unpredictable behavior. For more information, see the MPC7450
RISC Microprocessor
CT
U
Family User’s Manual.
D
N
O
Table 11. Sample Points CalculationCParameters
I
M
E
Max
Unit
Notes
S Symbol
E
L
Delay from processor clock to internal_L3_CLK
tAC
3/4
tL3_CLK
1
A
C
S
Delay from internal_L3_CLK to L3_CLK[n] output
tCO
3
ns
2
EE pins
R
Delay from L3_ECHO_CLK[n] to receiveFlatch
tECI
3
ns
3
Y
B
Notes:
1. This specification describes
a logical offset between the internal clock edge used to launch the L3 address
ED
V
I
and control signals (this
clock edge is phase-aligned with the processor clock edge) and the internal clock
edge used to launch
CHthe L3_CLK[n] signals. With proper board routing, this offset ensures that the
R
L3_CLK[n] edge
A will arrive at the SRAM within a valid address window and provide adequate setup and
Parameter
hold time. This offset is reflected in the L3 bus interface AC timing specifications, but must also be
separately accounted for in the calculation of sample points and, thus, is specified here.
2. This specification is the delay from a rising or falling edge on the internal_L3_CLK signal to the
corresponding rising or falling edge at the L3CLK[n] pins.
3. This specification is the delay from a rising or falling edge of L3_ECHO_CLK[n] to data valid and ready to
be sampled from the FIFO.
1.5.2.4.1
L3 Bus AC Specifications for DDR MSUG2 SRAMs
When using DDR MSUG2 SRAMs at the L3 interface, the parts should be connected as shown in Figure 9.
Outputs from the MPC7450 are actually launched on the edges of an internal clock phase-aligned to
SYSCLK (adjusted for core and L3 frequency divisors). L3_CLK0 and L3_CLK1 are this internal clock
output with 90° phase delay, so outputs are shown synchronous to L3_CLK0 and L3_CLK1. Output valid
times are typically negative when referenced to L3_CLKn because the data is launched one-quarter period
before L3_CLKn to provide adequate setup time at the SRAM after the delay-matched address, control,
data, and L3_CLKn signals have propagated across the printed wiring board.
Inputs to the MPC7450 are source-synchronous with the CQ clock generated by the DDR MSUG2 SRAMs.
These CQ clocks are received on the L3_ECHO_CLKn inputs of the MPC7450. An internal circuit delays
the incoming L3_ECHO_CLKn signal such that it is positioned within the valid data window at the internal
receiving latches. This delayed clock is used to capture the data into these latches which comprise the
receive FIFO. This clock is asynchronous to all other processor clocks. This latched data is subsequently
read out of the FIFO synchronously to the processor clock. The time between writing and reading the data
is set by the using the sample point settings defined in the L3CR register.
MOTOROLA
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Freescale Semiconductor, Inc.
Electrical and Thermal Characteristics
Table 12 provides the L3 bus interface AC timing specifications for the configuration as shown in Figure 9,
assuming the timing relationships shown in Figure 10 and the loading shown in Figure 8.
Table 12. L3 Bus Interface AC Timing Specifications for MSUG2
At recommended operating conditions. See Table 4.
All Speed Grades
Parameter
Symbol
Min
Max
tL3CR and tL3CF
—
1.0
Setup times:Data and parity
tL3DVEH and tL3DVEL
–(tL3_ECHO_CLK/4
– 0.35)
Input hold times:Data and parity
tL3DXEH and tL3DXEL
Valid times:Data and parity
All other outputs
tL3CHDV and tL3CLDV
tL3CHOV
Output hold times:
Data and parity
All other outputs
tL3CHDX and tL3CLDX
tL3CHOX
Freescale Semiconductor, Inc...
L3_CLK rise and fall time
L3_CLK to high impedance:
Data and parity
All other outputs
Y
tL3CLDZ
RE
tFL3CHOZ
IN
,
O—R
tL3_ECHO_CLK/4
T
+ 0.35
UC
D
—
N –tL3_CLK/4 + 0.5
— CO
tL3_CLK/4 + 1.0
I
M
SE
—
tL3_CLK/4 – 0.35
LE tL3_CLK/4 + 0.5
CA
S
E
C.
Unit
Notes
ns
1
ns
2, 3, 4
ns
2, 4
ns
5, 6, 7
5, 7
ns
5, 6, 7
5, 7
—
—
ns
—
—
tL3_CLK/2
tL3_CLK/4 + 2.0
B
Notes:
D
1. Rise and fall times for the L3_CLK
output
are measured from 20% to 80% of GVDD.
VE are measured from the midpoint of the signal in question to the midpoint voltage
2. For DDR, all input specifications
I
H of the input L3_ECHO_CLKn (see Figure 10). Input timings are measured at the pins.
of the rising or falling C
edge
R
3. For DDR, the input
data
will typically follow the edge of L3_ECHO_CLKn as shown in Figure 10. For consistency
A
with other input setup time specifications, this will be treated as negative input setup time.
4. tL3_ECHO_CLK/4 is one-fourth the period of L3_ECHO_CLKn. This parameter indicates that the MPC7450 can latch
an input signal that is valid for only a short time before and a short time after the midpoint between the rising and
falling (or falling and rising) edges of L3_ECHO_CLKn at any frequency.
5. All output specifications are measured from the midpoint voltage of the rising (or for DDR write data, also the
falling) edge of L3_CLK to the midpoint of the signal in question. The output timings are measured at the pins. All
output timings assume a purely resistive 50-Ω load (see Figure 8).
6. For DDR, the output data will typically lead the edge of L3_CLKn as shown in Figure 10. For consistency with other
output valid time specifications, this will be treated as negative output valid time.
7. tL3_CLK/4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually
launched by an internal clock delayed in phase by 90°. Therefore, there is a frequency component to the output
valid and output hold times such that the specified output signal will be valid for approximately one L3_CLK period
starting three-fourths of a clock prior to the edge on which the SRAM will sample it and ending one-fourth of a clock
period after the edge it will be sampled.
22
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Electrical and Thermal Characteristics
Figure 9 shows the typical connection diagram for the MPC7450 interfaced to MSUG2 SRAMs such as the
Motorola MCM64E836.
SRAM 0
SA[0:17]
L3ADDR[0:17]
MPC7450
L3_CNTL[0]
L3_CNTL[1]
Denotes
Receive (SRAM
to MPC7450)
Aligned Signals
L3_ECHO_CLK[0]
CQ
{L3DATA[0:15], L3DP[0:1]}
D[0:17]
L3_CLK[0]
Freescale Semiconductor, Inc...
LE
A
{L3_DATA[32:47], L3DP[4:5]}
SC
E
E
L3_CLK[1]
FR
{L3DATA[48:63],
L3DP[6:7]}
BY
D
L3_ECHO_CLK[3]
VE
IN
,
D[18:35]
OR
T
C CQ
U
ND
CK
L3_ECHO_CLK[1]
L3ECHO_CLK[2]
GND
G
GND
LBO
GND
CQ
NC
B2
{L3DATA[16:31], L3DP[2:3]}
Denotes
Transmit
(MPC7450 to
SRAM)
Aligned Signals
B3
B1
S
O
IC
EM
C.CQ
CK
NC
GVDD/2
SRAM 1
SA[0:17]
B3
B1
G
B2
GND
CQ
LBO
GND
D[0:17]
CQ
NC
CK
CQ
NC
D[18:35]
CK
GVDD/2
GND
HI
C
AR9. Typical Source Synchronous 2-Mbyte L3 Cache DDR Interface
Figure
MOTOROLA
CQ
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Electrical and Thermal Characteristics
Figure 10 shows the L3 bus timing diagrams for the MPC7450 interfaced to MSUG2 SRAMs.
Outputs
L3_CLK[0,1]
VM
VM
tL3CHOV
VM
VM
VM
tL3CHOZ
tL3CHOX
ADDR, L3CNTL
tL3CLDV
tL3CHDV
C
IN
tL3CLDZ
.
R,
O
CTt
tL3CHDX
U
D valid L3CLDX
N
Note: tL3CHDV and tL3CLDV as drawn here will be negative numbers, i.e., output
time will be
O
time before the clock edge.
IC
M
Inputs
SE
E
L
L3_ECHO_CLK[0,1,2,3]
VM CA
VM
VM
VM
S
E
E
tL3DXEL
tL3DVEL
FR
tL3DVEH
BY
L3 Data and Data
D
Parity Inputs
VE
I
tL3DXEH
H
C
Note: tL3DVEH and
L3DVEL as drawn here will be negative numbers, i.e., input setup time will be
AtR
Freescale Semiconductor, Inc...
L3DATA WRITE
VM
time after the clock edge.
VM = Midpoint Voltage (GVDD/2)
Figure 10. L3 Bus Timing Diagrams for L3 Cache DDR SRAMs
1.5.2.4.2
L3 Bus AC Specifications for PB2 and Late Write SRAMs
When using PB2 or Late Write SRAMs at the L3 interface, the parts should be connected as shown in
Figure 11. These SRAMs are synchronous to the MPC7450; one L3_CLKn signal is output to each SRAM
to latch address, control, and write data. Read data is launched by the SRAM synchronous to the delayed
L3_CLKn signal it received. The MPC7450 needs a copy of that delayed clock which launched the SRAM
read data to know when the returning data will be valid. Therefore, L3_ECHO_CLK1 and
L3_ECHO_CLK3 must be routed halfway to the SRAMs and then returned to the MPC7450 inputs
L3_ECHO_CLK0 and L3_ECHO_CLK2 respectively. Thus, L3_ECHO_CLK0 and L3_ECHO_CLK2 are
phase-aligned with the input clock received at the SRAMs. The MPC7450 will latch the incoming data on
the rising edge of L3_ECHO_CLK0 and L3_ECHO_CLK2.
Table 13 provides the L3 bus interface AC timing specifications for the configuration shown in Figure 11,
assuming the timing relationships of Figure 12 and the loading of Figure 8.
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Electrical and Thermal Characteristics
Table 13. L3 Bus Interface AC Timing Specifications for PB2 and Late Write SRAMs
At recommended operating conditions. See Table 4.
All Speed Grades
Parameter
Symbol
Notes
1.0
ns
1, 5
—
ns
2, 5
ns
2, 5
ns
3, 4, 5
4
ns
3, 4, 5
4, 5
ns
5
5
Max
tL3CR and tL3CF
—
Setup times:Data and parity
tL3DVEH
1.5
Input hold times:Data and parity
tL3DXEH
Valid times:Data and parity
All other outputs
tL3CHDV
tL3CHOV
Output hold times:Data and parity
All other outputs
tL3CHDX
tL3CHOX
L3_CLK to high impedance:Data and parity
All other outputs
tL3CHDZ
tL3CHOZ
L3_CLK rise and fall time
Freescale Semiconductor, Inc...
Unit
Min
C.
—
tL3_CLK/4 +N
1.0
—
tL3_CLK/4
, +I 1.0
R
tL3_CLK/4 + 0.5
TO —
tL3_CLK/4 + 0.5UC
—
D
N
—
2.0
O
2.0
IC—
M
SE
—
0.5
Notes:
1. Rise and fall times for the L3_CLK output are measured from
E 20% to 80% of GVDD.
L
2. All input specifications are measured from the midpoint
of
the
signal in question to the midpoint voltage of the rising
A
C
edge of the input L3_ECHO_CLKn (see Figure 10).
Input
timings
are measured at the pins.
S
E
3. All output specifications are measured from the
midpoint
voltage
of
the rising edge of L3_CLKn to the midpoint of
REmeasured at the pins. All output timings assume a purely resistive
the signal in question. The output timingsFare
50-Ω load (see Figure 10).
Y
4. tL3_CLK/4 is one-fourth the period ofBL3_CLKn. This parameter indicates that the specified output signal is actually
D
launched by an internal clock E
V delayed in phase by 90°. Therefore, there is a frequency component to the output
valid and output hold timesI such that the specified output signal will be valid for approximately one L3_CLK period
H
starting three-fourths C
of a clock prior to the edge on which the SRAM will sample it and ending one-fourth of a clock
R
period after the edge
A it will be sampled.
5. Timing behavior and characterization are currently being evaluated.
MOTOROLA
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Electrical and Thermal Characteristics
Figure 11 shows the typical connection diagram for the MPC7450 interfaced to PB2 SRAMs, such as the
Motorola MCM63R737, or Late Write SRAMs, such as the Motorola MCM63R836A.
SRAM 0
SA[0:17]
SS
SW,
SBWa, SBWb,
SBWc, SBWd
DQ[0:17]
ZZ
L3_ADDR[0:17]
MPC7450
L3_CNTL[0]
L3_CNTL[1]
L3_ECHO_CLK[0]
Denotes
Receive (SRAM
to MPC7450)
Aligned Signals
{L3_DATA[0:15], L3_DP[0:1]}
L3_CLK[0]
Freescale Semiconductor, Inc...
L3_ECHO_CLK[1]
Denotes
Transmit
(MPC7450 to
SRAM)
Aligned Signals
L3_ECHO_CLK[2]
LE
IN
,
R
]
ODQ[18:36
T
UC
D
N
K
{L3_DATA[16:31], L3_DP[2:3]}
S
O
IC
EM
A
{L3_DATA[32:47],
SC L3_DP[4:5]}
EE
R
L3_CLK[1]
F
ED
V
I
C.
Y
{L3_DATA[48:63],
L3_DP[6:7]}
B
GND
G
GND
K
GVDD/2
SRAM 1
SA[0:17]
SS
SW,
SBWa, SBWb,
SBWc, SBWd
DQ[0:17]
ZZ
GND
K
G
GND
DQ[18:36]
K
GVDD/2
CH
R
A
Figure 11. Typical Synchronous 1-MByte L3 Cache Late Write or PB2 Interface
26
L3_ECHO_CLK[3]
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Electrical and Thermal Characteristics
Figure 12 shows the L3 bus timing diagrams for the MPC7450 interfaced to PB2 or Late Write SRAMs.
Outputs
L3_CLK[0,1]
L3_ECHO_CLK[1,3]
VM
VM
tL3CHOV
tL3CHOX
ADDR, L3_CNTL
tL3CHOZ
tL3CHDV
Freescale Semiconductor, Inc...
L3DATA WRITE
Inputs
L3_ECHO_CLK[0,2]
EE
R
F
Parity Inputs
L3 Data and Data
1.5.2.5
R,
O
CT
tL3CHDZ
U
ND
tL3CHDX
LE
A
SC
O
IC
M
VME
S
C
IN
.
tL3DVEH
tL3DXEH
BYVM = Midpoint Voltage (GVDD/2)
D
Figure 12.
L3 Bus Timing Diagrams for Late Write or PB2 SRAMs
VE
I
H
RC
A
IEEE 1149.1 AC Timing Specifications
Table 14 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 14, Figure 15,
Figure 16, and Figure 17.
Table 14. JTAG AC Timing Specifications (Independent of SYSCLK)1
At recommended operating conditions. See Table 4.
Parameter
Symbol
Min
Max
Unit
TCK frequency of operation
fTCLK
0
33.3
MHz
TCK cycle time
t TCLK
30
—
ns
TCK clock pulse width measured at 1.4 V
tJHJL
15
—
ns
tJR and tJF
0
2
ns
TRST assert time
tTRST
25
—
ns
Input setup times:
Boundary-scan data
TMS, TDI
tDVJH
tIVJH
4
0
—
—
Input hold times:
Boundary-scan data
TMS, TDI
tDXJH
tIXJH
20
25
—
—
TCK rise and fall times
MOTOROLA
Notes
2
ns
3
ns
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Freescale Semiconductor, Inc.
Electrical and Thermal Characteristics
Table 14. JTAG AC Timing Specifications (Independent of SYSCLK)1 (continued)
At recommended operating conditions. See Table 4.
Parameter
Symbol
Min
Max
Valid times:
Boundary-scan data
TDO
tJLDV
tJLOV
4
4
20
25
Output hold times:
Boundary-scan data
TDO
tJLDX
tJLOX
TBD
TBD
TBD
TBD
Notes
ns
4
ns
C.
4
IN ns
,
tJLDZ
3
19R
4, 5
O
3
9
5
tJLOZ
T
C
U
Notes:
NDof TCLK to the midpoint of the signal
1. All outputs are measured from the midpoint voltage of the falling/rising edge
O
in question. The output timings are measured at the pins. All output timings
IC assume a purely resistive 50-Ω load
M
(see Figure 13). Time-of-flight delays must be added for trace lengths,
vias, and connectors in the system.
SEis for test purposes only.
2. TRST is an asynchronous level sensitive signal. The setup time
3. Non-JTAG signal input timing with respect to TCK.
LE
A
4. Non-JTAG signal output timing with respect to TCK.C
5. Guaranteed by design and characterization. ES
RE
F
Figure 13 provides the AC test load for
TDO and the boundary-scan outputs of the MPC7450.
BY
ED
V
OutputI
OVDD/2
Z0 = 50 Ω
H
RL = 50 Ω
C
AR
TCK to output high impedance:
Boundary-scan data
TDO
Freescale Semiconductor, Inc...
Unit
Figure 13. Alternate AC Test Load for the JTAG Interface
Figure 14 provides the JTAG clock input timing diagram.
TCLK
VM
VM
VM
tJHJL
tJR
tJF
tTCLK
VM = Midpoint Voltage (OVDD/2)
Figure 14. JTAG Clock Input Timing Diagram
Figure 15 provides the TRST timing diagram.
TRST
VM
VM
tTRST
VM = Midpoint Voltage (OVDD/2)
Figure 15. TRST Timing Diagram
28
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Electrical and Thermal Characteristics
Figure 16 provides the boundary-scan timing diagram.
TCK
VM
VM
tDVJH
Boundary
Data Inputs
tDXJH
Input
Data Valid
tJLDV
tJLDX
NC
Output Data Valid
I
R,
O
CT
tJLDZ
U
Boundary
ND
Output
Data
Valid
O
Data Outputs
IC
MDD/2)
VM = Midpoint Voltage E
(OV
S
E Timing Diagram
Figure 16. Boundary-Scan
L
A
SC
Figure 17 provides the test access port timingEdiagram.
E
FR
TCK
VMY
VM
B
D
tIVJH
VE
I
tIXJH
H
C
Input
TDI, TMS
AR
Data Valid
Freescale Semiconductor, Inc...
Boundary
Data Outputs
.
tJLOV
tJLOX
Output Data Valid
TDO
tJLOZ
TDO
Output Data Valid
VM = Midpoint Voltage (OVDD/2)
Figure 17. Test Access Port Timing Diagram
MOTOROLA
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Pin Assignments
1.6
Pin Assignments
Figure 18 (in Part A) shows the pinout of the MPC7450, 483 CBGA package as viewed from the top surface.
Part B shows the side profile of the CBGA package to indicate the direction of the top surface view.
Part A
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
A
B
C
D
E
Freescale Semiconductor, Inc...
F
G
H
J
K
L
M
N
P
R
T
U
CH
R
A
ED
V
I
BY
EE
R
F
LE
A
SC
S
O
IC
EM
R,
O
CT
U
ND
C
IN
.
V
W
Y
AA
AB
Not to Scale
Part B
Substrate Assembly
Encapsulant
View
Die
Figure 18. Pinout of the MPC7450, 483 CBGA Package as Viewed from the Top Surface
30
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Pinout Listings for the 483 CBGA Package
1.7
Pinout Listings for the 483 CBGA Package
Table 15 provides the pinout listing for the MPC7450, 483 CBGA package.
Table 15. Pinout Listing for the MPC7450, 483 CBGA Package
Signal Name
Freescale Semiconductor, Inc...
A[0:35]
Pin Number
E10, N4, E8, N5, C8, R2, A7, M2, A6, M1,
A10, U2, N2, P8, M8, W4, N6, U6, R5, Y4,
P1, P4, R6, M7, N7, AA3, U4, W2, W1, W3,
V4, AA1, D10, J4, G10, D9
AACK
U1
AP[0:4]
L5, L6, J1, H2, G5
ARTRY
T2
AVDD
B2
BG
R3
BMODE0
C6
BMODE1
C4
BR
K1
BVSEL
G6
CI
R1
CKSTP_IN
F3
CKSTP_OUT
CLK_OUT
K6
CH
R
A N1
ED
V
I
BY
EE
R
F
LE
A
SC
S
Active
I/O
I/F Select1
Notes
High
I/O
BVSEL
11
Low
Input
C.
N
IBVSEL
High
I/O
BVSEL
R,
O
T
C
Low
I/O
U
ND Input
—
O
IC
Low
Input
M
E
BVSEL
8
N/A
BVSEL
Low
Input
BVSEL
5
Low
Input
BVSEL
6
Low
Output
BVSEL
High
Input
N/A
3, 7
Low
Output
BVSEL
8
Low
Input
BVSEL
Low
Output
BVSEL
High
Output
BVSEL
D[0:63]
AB15, T14, R14, AB13, V14, U14, AB14,
W16, AA11, Y11, U12, W13, Y14, U13, T12,
W12, AB12, R12, AA13, AB11, Y12, V11,
T11, R11, W10, T10, W11, V10, R10, U10,
AA10, U9, V7, T8, AB4, Y6, AB7, AA6, Y8,
AA7, W8, AB10, AA16, AB16, AB17, Y18,
AB18, Y16, AA18, W14, R13, W15, AA14,
V16, W6, AA12, V6, AB9, AB6, R7, R9, AA9,
AB8, W9
High
I/O
BVSEL
DBG
V1
Low
Input
BVSEL
DP[0:7]
AA2, AB3, AB2, AA8, R8, W5, U8, AB5
High
I/O
BVSEL
DRDY
T6
Low
Output
BVSEL
4
DTI[0:3])
P2, T5, U3, P6
High
Input
BVSEL
4, 13
EXT_QUAL
B9
High
Input
BVSEL
9
GBL
M4
Low
I/O
BVSEL
MOTOROLA
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Freescale Semiconductor, Inc.
Pinout Listings for the 483 CBGA Package
Table 15. Pinout Listing for the MPC7450, 483 CBGA Package (continued)
Pin Number
Active
I/O
I/F Select1
A22, B1, B5, B12, B14, B16, B18, B20, C3,
C9, C21, D7, D13, D15, D17, D19, E2, E5,
E21, F10, F12, F14, F16, F19, G4, G7, G17,
G21, H13, H15, H19, H5, J3, J10, J12, J14,
J17, J21, K5, K9, K11, K13, K15, K19, L10,
L12, L14, L17, L21, M3, M6, M9, M11, M13,
M19, N10, N12, N14, N17, N21, P3, P9, P11,
P13, P15, P19, R17, R21, T13, T15, T19, T4,
T7, T9, U17, U21, V2, V5, V8, V12, V15, V19,
W7, W17, W21, Y3, Y9, Y13, Y15, Y20, AA5,
AA17, AB1, AB22
—
—
N/A
Signal Name
Freescale Semiconductor, Inc...
GND
GVDD
HIT
HRESET
INT
L1_TSTCLK
L2_TSTCLK
L3VSEL
L3ADDR[0:17]
R,
O
T
C
—
—
B13, B15, B17, B19, B21, D12, D14, D16,
U
D18, D21, E19, F13, F15, F17, F21, G19,
ND
H12, H14, H17, H21, J19, K17, K21, L19,
O
M17, M21, N19, P17, P21, R15, R19, T17,
IC
M
T21, U19, V17, V21, W19, Y21
SE
E
K2
Low
Output
L
A
A3
Low
Input
SC
E
J6
Low
Input
RE
F
H4
High
Input
BY
J2
High
Input
ED
V
A4 I
High
Input
H
C
L18, K22, L16, K20, K18, J22, J20, H22, J18,
High
Output
ARK16,
H20, G22, F22, G20, H18, E22, J16,
C
IN
Notes
.
N/A
15
BVSEL
4
BVSEL
BVSEL
BVSEL
9
BVSEL
12
N/A
3, 7
L3VSEL
F20
L3_CLK[0:1]
V22, C17
High
Output
L3VSEL
L3_CNTL[0:1]
L20, L22
Low
Output
L3VSEL
L3DATA[0:63]
AA19, AB20, U16, W18, AA20, AB21, AA21,
T16, W20, U18, Y22, R16, V20, W22, T18,
U20, N18, N20, N16, N22, M16, M18, M20,
M22, R18, T20, U22, T22, R20, P18, R22,
M15, G18, D22, E20, H16, C22, F18, D20,
B22, G16, A21, G15, E17, A20, C19, C18,
A19, A18, G14, E15, C16, A17, A16, C15,
G13, C14, A14, E13, C13, G12, A13, E12,
C12
High
I/O
L3VSEL
L3DP[0:7]
AB19, AA22, P22, P16, C20, E16, A15, A12
High
I/O
L3VSEL
L3_ECHO_CLK[0:3]
V18, P20, E18, E14
High
Input
L3VSEL
LSSD_MODE
F6
Low
Input
BVSEL
MCP
B8
Low
Input
BVSEL
No Connect
A8, A11, B6, B11, C11, D11, D3, D5, E11, E7,
F2, F11, G11, G2, H11, H9, J8
—
—
N/A
32
MPC7450 RISC Microprocessor Hardware Specifications
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MOTOROLA
Freescale Semiconductor, Inc.
Pinout Listings for the 483 CBGA Package
Table 15. Pinout Listing for the MPC7450, 483 CBGA Package (continued)
Pin Number
Active
I/O
I/F Select1
OVDD
B3, C5, C7, C10, D2, E3, E9, F5, G3, G9, H7,
J5, K3, L7, M5, N3, P7, R4, T3, U5, U7, U11,
U15, V3, V9, V13, Y2, Y5, Y7, Y10, Y17, Y19,
AA4, AA15
—
—
N/A
PLL_CFG[0:3]
A2, F7, C2, D4
High
Input
BVSEL
PLL_EXT
H8
High
Input
BVSEL
PMON_IN
E6
Low
Input
PMON_OUT
B4
QACK
K7
QREQ
Y1
SHD[0:1]
L4, L8
SMI
G8
SRESET
G1
SYSCLK
D6
TA
N8
TBEN
L3
TBST
B7
TCK
CH
E4
R
A
Freescale Semiconductor, Inc...
Signal Name
LE
A
SC
S
BVSEL
C.
N
IBVSEL
Low
Output
,
OR BVSEL
Low
Input
T
C
Low DU
Output
BVSEL
N
O
Low
I/O
BVSEL
IC
Input
BVSEL
EM Low
Notes
10
8
Low
Input
BVSEL
—
Input
BVSEL
Low
Input
BVSEL
High
Input
BVSEL
Low
Output
BVSEL
High
Input
BVSEL
High
Input
BVSEL
H1
High
Output
BVSEL
TEA
T1
Low
Input
BVSEL
TEST[0:5]
B10, H6, H10, D8, F9, F8
—
Input
BVSEL
2
TEST[6]
A9
—
Input
BVSEL
9
TMS
K4
High
Input
BVSEL
7
TRST
C1
Low
Input
BVSEL
7, 14
TS
P5
Low
I/O
BVSEL
8
TSIZ[0:2]
L1,H3,D1
High
Output
BVSEL
TT[0:4]
F1, F4, K8, A5, E1
High
I/O
BVSEL
WT
L2
Low
Output
BVSEL
TDI
TDO
MOTOROLA
J7
ED
V
I
BY
EE
R
F
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7
8
33
Freescale Semiconductor, Inc.
Package Description
Table 15. Pinout Listing for the MPC7450, 483 CBGA Package (continued)
Signal Name
Freescale Semiconductor, Inc...
VDD
Pin Number
Active
I/O
I/F Select1
—
—
N/A
J9, J11, J13, J15, K10, K12, K14, L9, L11,
L13, L15, M10, M12, M14, N9, N11, N13,
N15, P10, P12, P14
Notes
Notes:
1. OVDD supplies power to the processor bus, JTAG, and all control signals except the L3 cache controls
(L3CTL[0:1]); GVDD supplies power to the L3 cache interface (L3ADDR[0:17], L3DATA[0:63], L3DP[0:7],
L3_ECHO_CLK[0:3], and L3_CLK[0:1]) and the L3 control signals L3_CNTL[0:1]; and VDD supplies power to the
processor core and the PLL (after filtering to become AVDD). For actual recommended value of
CV.in or supply
N
voltages, see Table 4.
, I operation.
2. These input signals are for factory use only and must be pulled up to OVDD for normalR
machine
3. To program the processor interface I/O voltage, connect BVSEL to either GND (selects
TO 1.8 V) or to HRESET
C
(selects 2.5 V). To program the L3 interface, connect L3VSEL to either GND (selects
1.8 V) or to HRESET
U be less
D
(selects 2.5 V) or to HRESET (selects 1.5 V). If used, pulldown resistors should
than 250 Ω .
N
4. Ignored in 60x bus mode.
O
5. This signal selects between MPX bus mode (asserted) and 60x bus
ICmode (negated) and will be sampled at
M
HRESET going high.
SE
6. This signal must be negated during reset, by pull-up to OVDD
or negation by ¬HRESET (inverse of HRESET), to
E
L
ensure proper operation.
7. Internal pull-up on die.
CA
S
8. These pins require weak pull-up resistors (forE
4.7 kΩ) to maintain the control signals in the negated
Eandexample,
state after they have been actively negated
released by the MPC7450 and other bus masters.
R
9. These input signals for factory use onlyFand must be pulled down to GND for normal machine operation.
Y
10. This pin can externally enable theBperformance monitor counters (PMC) if they are internally enabled by the
D
software. If it will not be usedEto control the PMC, it should be pulled down to GND so that the software can
enable the PMC.
IV
H
11. Unused address pins
must
be pulled down to GND.
C
12. This test signal A
is R
recommended to be tied to HRESET; however, other configurations will not adversely affect
performance.
13. These signals must be pulled down to GND if unused or if the MPC7450 is in 60x bus mode.
14. This signal must be asserted during reset, by pull-down to GND or assertion by HRESET, to ensure proper
operation.
15. Power must be supplied to GVDD, even when the L3 interface is disabled or unused.
1.8
Package Description
The following sections provide the package parameters and mechanical dimensions for the CBGA package.
1.8.1
Package Parameters for the MPC7450, 483 CBGA
The package parameters are as provided in the following list. The package type is 29 × 29 mm, 483-lead
ceramic ball grid array (CBGA).
34
Package outline
29 × 29 mm
Interconnects
483 (22 × 22 ball array – 1)
Pitch
1.27 mm (50 mil)
Minimum module height
—
Maximum module height
3.22 mm
Ball diameter
0.89 mm (35 mil)
MPC7450 RISC Microprocessor Hardware Specifications
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Freescale Semiconductor, Inc.
Package Description
1.8.2
Mechanical Dimensions for the MPC7450, 483 CBGA
Figure 19 provides the mechanical dimensions and bottom surface nomenclature for the MPC7450, 483
CBGA package.
2X
0.2
D
B
D1
D3
A1 CORNER
Capacitor Region
D2
C
IN
1
A
R,
O
NOTES:T
C
1. U
DIMENSIONING
AND TOLERANCING
PER ASME Y14.5M, 1994.
D
N2. DIMENSIONS IN MILLIMETERS.
O
TOP SIDE A1 CORNER INDEX IS A
IC 3. METALIZED
FEATURE WITH VARIOUS
M
E
SHAPES. BOTTOM SIDE. A1 CORNER
Freescale Semiconductor, Inc...
0.2 A
E3
E
E1
E2
EE
R
F
LE
A
SC
BY
1 2 3 4 5 6 7 8 9 10 111213141516
171819 2021 22
D
E
IV
H
C
AR
2X
0.2
C
e
483X
S
.
IS DESIGNATED WITH A BALL
MISSING FROM THE ARRAY.
Millimeters
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
DIM
MIN
MAX
A
--
3.22
A1
0.80
1.00
A2
1.08
1.32
A3
A2
A1
A
b
0.3 A B C
0.15 A
A3
--
0.60
b
0.82
0.93
D
29.00 BSC
D1
—
D2
8.94
—
D3
—
6.9
11.6
e
1.27 BSC
E
29.00 BSC
E1
—
11.6
E2
8.94
—
E3
—
6.9
Figure 19. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7450, 483 CBGA
MOTOROLA
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Freescale Semiconductor, Inc.
System Design Information
1.9
System Design Information
This section provides system and thermal design recommendations for successful application of the
MPC7450.
1.9.1
PLL Configuration
Freescale Semiconductor, Inc...
The MPC7450 PLL is configured by the PLL_EXT and PLL_CFG[0:3] signals. For a given SYSCLK (bus)
frequency, the PLL configuration signals set the internal CPU and VCO frequency of operation. PLL_EXT
will normally be pulled low but can be asserted for extended modes of operation. The PLL
configuration
C. shaded cells
for the MPC7450 is shown in Table 16 for a set of example frequencies. In this example,
N
,I
represent settings that, for a given SYSCLK frequency, result in core and/or VCORfrequencies
that do not
comply with the 600-MHz column in Table 8.
TO
UC
D for 600 MHz Parts
Table 16. MPC7450 Microprocessor PLL Configuration Example
PLL_EXT
0
0
0
0
36
N
O
CMHz (VCO Frequency in MHz)
Example Bus-to-Core FrequencyIin
M
PLL_CFG Bus-toSE Bus
Core-toBus
Bus
Bus
Bus
Bus
[0:3]
E
Core
VCO
33.3 MHzAL
50 MHz 66.6 MHz 75 MHz 83 MHz 100 MHz
Multiplier Multiplier
SC
E
0000
0.5x
2x
25
33
37
47
50
E 16
R
(33)
(50)
(66)
(75)
(83)
(100)
F
Y
0100
2x
66
100
133
150
166
200
B2x
D
(133)
(200)
(266)
(300)
(333)
(400)
VE 2x
I
0110
2.5x
83
125
166
187
208
250
H
C
(166)
(250)
(333)
(375)
(415)
(500)
AR
Bus
133 MHz
66
(133)
266
(533)
333
(666)
1000
3x
2x
100
(200)
150
(300)
200
(400)
225
(450)
250
(500)
300
(600)
400
(800)
0
1110
3.5x
2x
116
(233)
175
(350)
233
(466)
262
(525)
291
(581)
350
(700)
466
(933)
0
1010
4x
2x
133
(266)
200
(400)
266
(533)
300
(600)
333
(666)
400
(800)
533
(1066)
0
0111
4.5x
2x
150
(300)
225
(450)
300
(600)
337
(675)
374
(747)
450
(900)
600
(1200)
0
1011
5x
2x
166
(333)
250
(500)
333
(666)
375
(750)
415
(830)
500
(1000)
667
(1333)
0
1001
5.5x
2x
183
(366)
275
(550)
366
(733)
412
(825)
457
(913)
550
(1100)
733
(1466)
0
1101
6x
2x
200
(400)
300
(600)
400
(800)
450
(900)
498
(996)
600
(1200)
0
0101
6.5x
2x
216
(433)
325
(630)
433
(866)
488
(975)
540
(1080)
650
(1300)
0
0010
7x
2x
233
(466)
350
(700)
466
(933)
525
(1050)
581
(1162)
700
(1400)
0
0001
7.5x
2x
250
(500)
375
(750)
500
(1000)
563
(1125)
623
(1245)
750
(1500)
0
1100
8x
2x
266
(533)
400
(800)
533
(1066)
600
(1200)
664
(1328)
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Freescale Semiconductor, Inc.
System Design Information
Table 16. MPC7450 Microprocessor PLL Configuration Example for 600 MHz Parts (continued)
Freescale Semiconductor, Inc...
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
PLL_EXT
PLL_CFG
[0:3]
1
0111
9x
2x
300
(600)
450
(900)
600
(1200)
675
(1350)
1
1010
10x
2x
333
(666)
500
(1000)
667
(1333)
750
(1500)
733
(1466)
Bus-toCore-toBus
Bus
Bus
Bus
Bus
Bus
Bus
Core
VCO
33.3 MHz 50 MHz 66.6 MHz 75 MHz 83 MHz 100 MHz 133 MHz
Multiplier Multiplier
1
1001
11x
2x
366
(733)
550
(1100)
1
1011
12x
2x
400
(800
600
(1200)
1
0101
13x
2x
433
(866)
650
(1300)
1
1100
14x
2x
466
(933)
700S
(1400)
E
1
0001
15x
2x
1
1101
16x
2x
0
0011
PLL off/bypass
D
BY
L
2.
3.
4.
.
E
533
FR (1066)
E
IVPLL off
1111
R,
O
CT
U
ND
C
IN
500CA 750
(1000)
ES (1500)
PLL off, SYSCLK clocks core circuitry directly
CH
Notes:
R
A
1. PLL_CFG[0:3] settings
not listed are reserved.
0
O
IC
EM
747
(1494)
PLL off, no core clocking occurs
The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core,
or VCO frequencies which are not useful, not supported, or not tested for by the MPC7450; see Section 1.5.2.1,
“Clock AC Specifications,” for valid SYSCLK, core, and VCO frequencies.
In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly and the PLL is disabled.
However, the bus interface unit requires a 2x clock to function. Therefore, an additional signal, EXT_QUAL, must
be driven at one-half the frequency of SYSCLK and offset in phase to meet the required input setup tIVKH and hold
time tIXKH (see Table 9). The result will be that the processor bus frequency will be one-half SYSCLK while the
internal processor is clocked at SYSCLK frequency. This mode is intended for factory use and emulator tool use
only.
Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.
In PLL-off mode, no clocking occurs inside the MPC7450 regardless of the SYSCLK input.
The MPC7450 generates the clock for the external L3 synchronous data SRAMs by dividing the core clock
frequency of the MPC7450. The core-to-L3 frequency divisor for the L3 PLL is selected through the
L3_CLK bits of the L3CR register. Generally, the divisor must be chosen according to the frequency
supported by the external RAMs, the frequency of the MPC7450 core, and timing analysis of the circuit
board routing. Table 17 shows various example L3 clock frequencies that can be obtained for a given set of
core frequencies.
Table 17. Sample Core-to-L3 Frequencies
Core Frequency (MHz)
÷2
÷2.5
÷3
÷3.5
÷4
÷5
÷6
500
250
200
167
143
125
100
83
533
266
213
178
152
133
107
89
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Freescale Semiconductor, Inc.
System Design Information
Freescale Semiconductor, Inc...
Table 17. Sample Core-to-L3 Frequencies (continued)
Core Frequency (MHz)
÷2
÷2.5
÷3
÷3.5
÷4
÷5
÷6
5502
275
220
183
157
138
110
92
6002
300
240
200
171
150
120
100
6502
325
260
217
186
163
130
108
6662
333
266
222
190
167
133
111
7002
350
280
233
200
175
140
117
7332
367
293
244
209
183
C
IN
147 .
122
Notes:
1. The core and L3 frequencies are for reference only. Some examples may represent coreR
or, L3 frequencies which
O
are not useful, not supported, or not tested for the MPC7450; see Section 1.5.2.3, “L3
Clock
AC Specifications,” for
T
C
valid L3_CLK frequencies. (Shaded cells do not comply with Table 10.)
U
2. These core frequencies are not supported by all speed grades; see Table 8. D
N
O
IC
1.9.2 PLL Power Supply FilteringSEM
LEto provide power to the clock generation PLL. To
The AVDD power signal is provided on the MPC7450
A
C
ensure stability of the internal clock, the power S
supplied
to the AVDD input signal should be filtered of any
E
noise in the 500 kHz to 10 MHz resonant frequency
range
of the PLL. A circuit similar to the one shown in
RE minimum effective series inductance (ESL) is recommended.
Figure 20 using surface mount capacitorsFwith
BYas possible to the AVDD pin to minimize noise coupled from nearby
The circuit should be placed as D
close
circuits. It is often possible to
VEroute directly from the capacitors to the AVDD pin, which is on the periphery
I
of the 360 CBGA footprint
CH and very close to the periphery of the 483 CBGA footprint, without the
inductance of vias. R
A
10 Ω
VDD
AVDD
2.2 µF
2.2 µF
Low ESL Surface Mount Capacitors
GND
Figure 20. PLL Power Supply Filter Circuit
1.9.3
Power Supply Voltage Sequencing
The notes in Table 2 contain cautions about the sequencing of the external bus voltages and core voltage of
the MPC7450 (when they are different). These cautions are necessary for the long-term reliability of the
part. If they are violated, the electrostatic discharge (ESD) protection diodes will be forward-biased and
excessive current can flow through these diodes. If the system power supply design does not control the
voltage sequencing, the circuit shown in Figure 21 can be added to meet these requirements. The 30BF10
38
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diodes (see Figure 21) control the maximum potential difference between the external bus and core power
supplies on power-up and the 1N5820 diodes regulate the maximum potential difference on power-down.
2.5 V
1.6 V
30BF10
30BF10
1N5820
1N5820
R,
O
CT
U
ND
C
IN
.
Freescale Semiconductor, Inc...
Figure 21. Example Voltage Sequencing Circuit
1.9.4
Decoupling Recommendations O
C
I
Due to the MPC7450 dynamic power management feature, large
address and data buses, and high operating
EM
frequencies, the MPC7450 can generate transient powerSsurges and high frequency noise in its power
supply, especially while driving large capacitive loads.
LEThis noise must be prevented from reaching other
A
components in the MPC7450 system, and the MPC7450
itself requires a clean, tightly regulated source of
SC
E
power. Therefore, it is recommended that theEsystem designer place at least one decoupling capacitor at each
VDD, OVDD, and GVDD pin of the MPC7450.
It is also recommended that these decoupling capacitors
FR
Y
receive their power from separate V
,
OV
/GV
DD
DD, and GND power planes in the PCB, utilizing short
BDD
traces to minimize inductance.ED
V
I a value of 0.01 µF or 0.1 µF. Only ceramic surface mount technology (SMT)
These capacitors should H
have
C
capacitors should beR used to minimize lead inductance, preferably 0508 or 0603 orientations where
A
connections are made along the length of the part. Consistent with the recommendations of Dr. Howard
Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993) and contrary to
previous recommendations for decoupling Motorola microprocessors, multiple small capacitors of equal
value are recommended over using multiple values of capacitance.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the VDD, GVDD, and OVDD planes, to enable quick recharging of the smaller chip capacitors. These
bulk capacitors should have a low equivalent series resistance (ESR) rating to ensure the quick response
time necessary. They should also be connected to the power and ground planes through two vias to minimize
inductance. Suggested bulk capacitors: 100–330 µF (AVX TPS tantalum or Sanyo OSCON).
1.9.5
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to OVDD. Unused active high inputs should be connected to
GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external VDD, OVDD, GVDD, and GND pins in the
MPC7450. If the L3 interface is not used, GVDD should be connected to the OVDD power phase, and
L3VSEL should be connected to BVSEL.
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1.9.6
Output Buffer DC Impedance
The MPC7450 processor bus and L3 I/O drivers are characterized over process, voltage, and temperature.
To measure Z0, an external resistor is connected from the chip pad to OVDD or GND. Then, the value of
each resistor is varied until the pad voltage is OVDD/2 (see Figure 22).
The output impedance is the average of two components, the resistances of the pull-up and pull-down
devices. When data is held low, SW2 is closed (SW1 is open), and RN is trimmed until the voltage at the
pad equals OVDD/2. RN then becomes the resistance of the pull-down devices. When data is held high, SW1
is closed (SW2 is open), and RP is trimmed until the voltage at the pad equals OVDD/2. RP then becomes
. Then, Z0 =
the resistance of the pull-up devices. RP and RN are designed to be close to each other in value.
C
N
(RP + RN)/2.
I
Freescale Semiconductor, Inc...
OVDD
O
IC
EM
RN
Data
CH
R
A
ED
V
I
BY
EE
R
F
LE
A
SC
S
R,
O
CT
U
ND
SW2
Pad
SW1
RP
OGND
Figure 22. Driver Impedance Measurement
Table 18 summarizes the signal impedance results. The impedance increases with junction temperature and
is relatively unaffected by bus voltage.
Table 18. Impedance Characteristics
VDD = 1.5 V, OVDD = 1.8 V ± 5%, Tj = 5°–85°C
Impedance
Z0
1.9.7
Processor Bus
L3 Bus
Unit
Typical
33–42
34–42
Ω
Maximum
31–51
32–44
Ω
Pull-Up/Pull-Down Resistor Requirements
The MPC7450 requires high-resistive (weak: 4.7 kΩ) pull-up resistors on several control pins of the bus
interface to maintain the control signals in the negated state after they have been actively negated and
released by the MPC7450 or other bus masters. These pins are: TS, ARTRY, SHDO, and SHD1.
Some pins designated as being for factory test must be pulled up to OVDD or down to GND to ensure proper
device operation. For the MPC7450, 483 BGA, the pins that must be pulled up to OVDD are: LSSD_MODE
and TEST[0:5]; the pins that must be pulled down are: L1_TSTCLK and TEST[6].
40
MPC7450 RISC Microprocessor Hardware Specifications
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In addition, the MPC7450 has one open-drain style output that requires a pull-up resistor (weak or stronger:
4.7 kΩ–1 kΩ) if it is used by the system. This pin is CKSTP_OUT.
If pull-down resistors are used to configure BVSEL or L3VSEL, the resistors should be less than 250 Ω (see
Table 15).
During inactive periods on the bus, the address and transfer attributes may not be driven by any master and
may, therefore, float in the high-impedance state for relatively long periods of time. Because the MPC7450
must continually monitor these signals for snooping, this float condition may cause excessive power draw
by the input receivers on the MPC7450 or by other receivers in the system. It is recommended that these
signals be pulled up through weak (4.7 kΩ) pull-up resistors by the system, or that they may
. be otherwise
C
driven by the system during inactive periods of the bus. The snooped address and transfer
N attribute inputs
I
,
are: A[0:35], AP[0:4], TT[0:4], CI, WT, and GBL.
Freescale Semiconductor, Inc...
OR
If extended addressing is not used, A[0:3] are unused and must be be pulled
CTlow to GND through weak
U
pull-down resistors. If the MPC7450 is in 60x bus mode, DTI[0:3] must be
D pulled low to GND through weak
N
pull-down resistors.
O
C
I operation is in progress and, therefore,
The data bus input receivers are normally turned off when noM
read
do not require pull-up resistors on the bus. Other data bus
receivers in the system, however, may require
SE
E
pull-ups, or that those signals be otherwise driven by the
system during inactive periods by the system. The
L
data bus signals are: D[0:63] and DP[0:7].
CA
ES
E
If address or data parity is not used by the
system, and the respective parity checking is disabled through
FR
HID0, the input receivers for those pins
are
disabled, and those pins do not require pull-up resistors and
Y
B
should be left unconnected by the system. If all parity generation is disabled through HID0, then all parity
EDthrough HID0, and all parity pins may be left unconnected by the system.
checking should also be disabled
IV
H
The L3 interface does C
not normally require pull-up resistors.
AR
1.9.8
JTAG Configuration Signals
Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE 1149.1 specification, but is provided on all processors that implement the PowerPC architecture.
While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more
reliable power-on reset performance will be obtained if the TRST signal is asserted during power-on reset.
Because the JTAG interface is also used for accessing the common on-chip processor (COP) function,
simply tying TRST to HRESET is not practical.
The COP function of these processors allows a remote computer system (typically, a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The COP
interface connects primarily through the JTAG port of the processor, with some additional status monitoring
signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control
the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers,
power supply failures, or push-button switches, then the COP reset signals must be merged into these signals
with logic.
The arrangement shown in Figure 23 allows the COP to independently assert HRESET or TRST, while
ensuring that the target can drive HRESET as well. An optional pull-down resistor on TRST can be
populated to ensure that the JTAG scan chain is initialized during power-on if the JTAG interface and COP
header will not be used; otherwise, this resistor should be unpopulated and TRST is asserted when the
system reset signal (HRESET) is asserted and the JTAG interface is responsible for driving TRST when
needed.
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The COP header shown in Figure 23 adds many benefits—breakpoints, watchpoints, register and memory
examination/modification, and other standard debugger features are possible through this interface—and
can be as inexpensive as an unpopulated footprint for a header to be added when needed.
The COP interface has a standard header for connection to the target system, based on the 0.025"
square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has
pin 14 removed as a connector key.
There is no standardized way to number the COP header shown in Figure 23; consequently, many different
pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then
left-to-right, while others use left-to-right then top-to-bottom, while still others number the
. pins counter
C
clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement
recommended
in
N
I
,
Figure 23 is common to all known emulators.
Freescale Semiconductor, Inc...
OR
T in a system and is an input
The QACK signal shown in Figure 23 is usually connected to the PCI bridge C
chip
U
to the MPC7450 informing it that it can go into the quiescent state. Under
normal operation this occurs
ND must see this signal asserted
during a low-power mode selection. In order for COP to work, the O
MPC7450
(pulled down). While shown on the COP header, not all emulator
ICproducts drive this signal. If the product
M Additionally, some emulator products
does not, a pull-down resistor can be populated to assert thisEsignal.
S
implement open-drain type outputs and can only drive QACK
E asserted; for these tools, a pull-up resistor can
L
be implemented to ensure this signal is deassertedAwhen it is not being driven by the tool. Note that the
C are mutually exclusive and it is never necessary to
Ssignal
pull-up and pull-down resistors on the QACK
E
populate both in a system. To preserve correct
RE power down operation, QACK should be merged via logic
F
so that it also can be driven by the PCI
Y bridge.
CH
R
A
42
ED
V
I
B
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System Design Information
From Target
Board Sources
(if any)
SRESET
SRESET
HRESET
HRESET
QACK
13
11
10 kΩ
HRESET
OVDD
SRESET
OVDD
10 kΩ
,I
R
OOVDD
T
10 kΩ
UC TRST
D
N
Freescale Semiconductor, Inc...
10 kΩ
1
2
3
4
5
6
7
8
9
10
4
6
51
15
Key
TRST
VDD_SENSE
LE
SE
10 kΩ
ES
E
FR
C
10
NC
12
NC
.
GND
OVDD
OVDD
CHKSTP_OUT
10 kΩ
10 kΩ
OVDD
OVDD
CHKSTP_IN
COP Header
12
M
2 kΩ3
CHKSTP_OUTA
142Y
B CHKSTP_IN
KEY
13 No
pin
D
VE 8 TMS
15
16
I
9
CH
TDO
R
A
1
COP Connector
Physical Pin Out
TDI
3
TCK
7
QACK
2
11
O
2
ICkΩ
OVDD NC
TMS
TDO
TDI
TCK
QACK
2 kΩ4
10 kΩ5
OVDD
16
Notes:
1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the MPC7450.
Connect pin 5 of the COP header to OVDD with a 10 KΩ pull-up resistor.
2. Key location; Pin 14 is not physically present on the COP header.
3. .Component not populated. Populate only if JTAG interface is unused.
4. Component not populated. Populate only if debug tool does not drive QACK.
5. Populate only if debug tool uses an open-drain type output and does not actively deassert QACK.
Figure 23. JTAG Interface Connection
1.9.9
Thermal Management Information
This section provides thermal management information for the ceramic ball grid array (CBGA) package for
air-cooled applications. Proper thermal control design is primarily dependent on the system-level
design—the heat sink, airflow, and thermal interface material. To reduce the die-junction temperature, heat
MOTOROLA
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System Design Information
sinks may be attached to the package by several methods—spring clip to holes in the printed-circuit board
or package, and mounting clip and screw assembly (see Figure 24); however, due to the potential large mass
of the heat sink, attachment through the printed circuit board is suggested. If a spring clip is used, the spring
force should not exceed 5.5 pounds.
CBGA Package
Heat Sink
Heat Sink
Clip
Freescale Semiconductor, Inc...
Thermal Interface Material
EE
R
F
LE
A
SC
S
O
IC
EM
R,
O
CT
U
ND
C
IN
.
Printed-Circuit Board
Y Cross-Sectional View with Several Heat Sink Options
Figure 24. Package Exploded
B
D
The board designer can choose
VE between several types of heat sinks to place on the MPC7450. There are
I
several commercially available
heat sinks for the MPC7450 provided by the following vendors:
CH
R
Chip Coolers Inc.
800-227-0254 (USA/Canada)
A
44
333 Strawberry Field Rd.
Warwick, RI 02887-6979
Internet: www.chipcoolers.com
401-739-7600
International Electronic Research Corporation (IERC)
135 W. Magnolia Blvd.
Burbank, CA 91502
Internet: www.ctscorp.com
818-842-7277
Thermalloy
2021 W. Valley View Lane
Dallas, TX 75234-8993
Internet: www.thermalloy.com
972-243-4321
Wakefield Engineering
100 Cummings Center, Suite 157H
Beverly, MA 01915
Internet: www.wakefield.com
781-406-3000
Aavid Engineering
250 Apache Trail
Terrell, TX 75160
Internet: www.aavid.com
972-551-7330
MPC7450 RISC Microprocessor Hardware Specifications
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System Design Information
Cool Innovations Inc.
260 Spinnaker Way, Unit 8
Concord, Ontario L4K 4P9
Canada
Internet: www.coolinnovations.com
905-760-1992
Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal
performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost.
C.
N
For the exposed-die packaging technology, shown in Table 3, the intrinsic conduction
, I thermal resistance
R
paths are as follows:
TO
• The die junction-to-case (or top-of-die for exposed silicon) thermal C
resistance
DU
• The die junction-to-ball thermal resistance
N
CO
Iwith
Figure 25 depicts the primary heat transfer path for a package
an attached heat sink mounted to a
M
E
printed-circuit board.
S
E
L
Radiation
Convection
External Resistance
CA
S
E
E
FR
BY
D
Heat Sink
VE
Thermal Interface Material
I
H
C
Die/Package
Internal
Resistance
Die Junction
AR
Freescale Semiconductor, Inc...
1.9.9.1
Internal Package Conduction Resistance
Package/Leads
Printed-Circuit Board
Radiation
Convection
External Resistance
(Note the internal versus external package resistance)
Figure 25. C4 Package with Heat Sink Mounted to a Printed-Circuit Board
Heat generated on the active side of the chip is conducted through the silicon, then through the heat sink
attach material (or thermal interface material), and finally to the heat sink where it is removed by forced-air
convection.
Because the silicon thermal resistance is quite small, for a first-order analysis, the temperature drop in the
silicon may be neglected. Thus, the thermal interface material and the heat sink conduction/convective
thermal resistances are the dominant terms.
1.9.9.2
Thermal Interface Materials
A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the
thermal contact resistance. For those applications where the heat sink is attached by spring clip mechanism,
Figure 26 shows the thermal performance of three thin-sheet thermal-interface materials (silicone,
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Freescale Semiconductor, Inc.
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graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure.
As shown, the performance of these thermal interface materials improves with increasing contact pressure.
The use of thermal grease significantly reduces the interface thermal resistance. That is, the bare joint results
in a thermal resistance approximately 7 times greater than the thermal grease joint.
Often, heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board
(see Figure 24). Therefore, the synthetic grease offers the best thermal performance, considering the low
interface pressure and is recommended due to the high power dissipation of the MPC7450. Of course, the
selection of any thermal interface material depends on many factors—thermal performance requirements,
manufacturability, service temperature, dielectric properties, cost, etc.
Specific Thermal Resistance (Kin2/W)
Freescale Semiconductor, Inc...
2
1.5
1
0.5
C
IN
.
Silicone Sheet (0.006 inch)
Bare Joint
Floroether Oil Sheet (0.007 inch)
Graphite/Oil Sheet (0.005 inch)
Synthetic Grease
CH
R
A
ED
V
I
BY
EE
R
F
LE
A
SC
S
O
IC
EM
R,
O
CT
U
ND
0
0
10
20
30
40
50
60
70
80
Contact Pressure (psi)
Figure 26. Thermal Performance of Select Thermal Interface Material
The board designer can choose between several types of thermal interface. Heat sink adhesive materials
should be selected based upon high conductivity, yet adequate mechanical strength to meet equipment
shock/vibration requirements. There are several commercially available thermal interfaces and adhesive
materials provided by the following vendors:
46
Dow-Corning Corporation
Dow-Corning Electronic Materials
PO Box 0997
Midland, MI 48686-0997
Internet: www.dow.com
800-248-2481
Chomerics, Inc.
77 Dragon Court
Woburn, MA 01888-4014
Internet: www.chomerics.com
781-935-4850
MPC7450 RISC Microprocessor Hardware Specifications
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System Design Information
Thermagon Inc.
3256 West 25th Street
Cleveland, OH 44109-1668
Internet: www.thermagon.com
888-246-9050
Loctite Corporation
1001 Trout Brook Crossing
Rocky Hill, CT 06067-3910
Internet: www.loctite.com
860-571-5100
Freescale Semiconductor, Inc...
The following section provides a heat sink selection example using one of the commercially. available heat
sinks.
NC
,I
R
TO
1.9.9.3 Heat Sink Selection Example
C
DU as follows:
For preliminary heat sink sizing, the die-junction temperature can be expressed
N
O
Tj = Ta + Tr + (θjc + θint + θsa) × Pd
IC
M
where:
SE
Tj is the die-junction temperature
LE
A
Ta is the inlet cabinet ambient temperature
SC
E
Ethe computer cabinet
Tr is the air temperature rise within
FR
θjc is the junction-to-case thermal
BY resistance
D
interface material thermal resistance
θint is the adhesive or E
V
I
θsa is the heat sink
H base-to-ambient thermal resistance
C
Pd is the power
AR dissipated by the device
During operation, the die-junction temperatures (Tj) should be maintained less than the value specified in
Table 4. The temperature of the air cooling the component greatly depends upon the ambient inlet air
temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air
temperature (Ta) may range from 30° to 40°C. The air temperature rise within a cabinet (Tr) may be in the
range of 5° to 10°C. The thermal resistance of the thermal interface material (θint) is typically about
1.5°C/W. For example, assuming a Ta of 30°C, a Tr of 5°C, a CBGA package θjc = 0.1, and a typical power
consumption (Pd) of 13.0 W, the following expression for Tj is obtained:
Die-junction temperature:
Tj = 30°C + 5°C + (0.1°C/W + 1.5°C/W + θsa) × 13.0 W
For this example, a θsa value of 3.7°C/W or less is required to maintain the die junction temperature below
the maximum value of Table 4.
Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common
figure-of-merit used for comparing the thermal performance of various microelectronic packaging
technologies, one should exercise caution when only using this metric in determining thermal management
because no single parameter can adequately describe three-dimensional heat flow. The final die-junction
operating temperature is not only a function of the component-level thermal resistance, but the system-level
design and its operating conditions. In addition to the component's power consumption, a number of factors
affect the final operating die-junction temperature—airflow, board population (local heat flux of adjacent
components), heat sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology,
system air temperature rise, altitude, etc.
Due to the complexity and the many variations of system-level boundary conditions for today's
microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection,
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Document Revision History
and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models
for the board, as well as system-level designs.
1.10 Document Revision History
Table 19 provides a revision history for this hardware specification.
Table 19. Document Revision History
Document Revision
Rev 0
Freescale Semiconductor, Inc...
Rev 1
Substantive Change(s)
Initial release.
,
C
IN
.
Removed CHKS, DX, HPR, IARTRY0, OSHD, SRW[0:1], WAITR
from spec and added to
TEST signal group; corrected Tables 16 and 17 and respective
TO Notes.
Reformatted Table 16.
UC
D
N
O pull-up resistors.
Added CI and WT to list of signals requiring C
weak
I
Updated power consumption specifications
EM in Table 7.
Rev 1.1
S
Corrected Notes in Table 21 and E
Table 15 for L1_TSTCLK, L2TSTCLK, BVSEL, and
L3VSEL.
AL
SC
Added pullup/pulldownErequirements for factory test signals to Section 1.9.7,
E
“Pull-Up/Pull-Down
Requirements”.
RResistor
Rev 2
Rev 3
F
Y core voltage to 1.6 V; 1.8 V core voltage still supported.
Changed nominal
B
Updated
EDpower consumption specifications in Table 7 and changed low power modes
V
(Doze,
I Nap, Sleep) to specify ‘Typical’ values.
CHRevised Table 6 to clarify Cin specifications.
R
A
Removed Table 6, “Thermal Sensor Specifications” and accompanying text; TAU is
non-functional on MPC7450.
Corrected Parameter names and Notes in Table 9.
Corrected Table 21 and Table 15 and added Notes 13 and 14.
Removed 25 MHz column from Table 16 and added 83 MHz column.
Changed all references to inverted HRESET from HRESET to ¬HRESET for clarity and
to be consistent with the MPC7450 RISC Microprocessor Family User’s Manual.
Moved Table 11 (Table 13 in prior revisions) to Section 1.5.2.4, “L3 Bus AC
Specifications” because these specifications apply to all supported SRAM types, added
specification for tAC and all Notes.
Corrected Figure 23.
Removed Section 1.9.9, “MPX Outstanding Data Tenures (ODT)”. This information is now
provided in an Application Note.
48
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Ordering Information
Table 19. Document Revision History (continued)
Document Revision
Substantive Change(s)
Rev 4
Updated document template.
Changed “Full-on Mode” to “Full-Power Mode” and “Sleep - PLL disabled” to “Deep Sleep
Mode” in Table 7 to be consistent with User’s Manual.
Removed specifcation for Doze mode power since this is not tested (see Table 7, Note 4).
Removed Deep Sleep Mode-Max power specification since this is not tested.
Revised Figure 23 and removed Table 23 (information is now included in .figure).
Revised format and content of Section 1.11, “Ordering Information.”IN
R,
C
Freescale Semiconductor, Inc...
Removed rows for unsupported core frequencies from TableO
17.
1.11 Ordering Information
CT
U
ND
O
IC
M specification
this
E
Ordering information for the parts fully covered by
document is provided in
S
Section 1.11.1, “Part Numbers Fully Addressed by This
Document.”
Section
1.11.2,
“Part Numbers Not
E
L
Fully Addressed by This Document,” lists the part numbers
which
do
not
fully
conform
to the specifications
A
C
of this document. These special part numbers
ES require an additional document called a part number
E
specification.
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BY
F
1.11.1 Part Numbers
ED Fully Addressed by This Document
IV
Table 20 provides the Motorola
part numbering nomenclature for the MPC7450. Note that the individual
CHto a maximum
R
part numbers correspond
processor core frequency. For available frequencies, contact your
A
local Motorola sales office. In addition to the processor frequency, the part numbering scheme also includes
an application modifier which may specify special application conditions. Each part number also contains
a revision level code which refers to the die mask revision number.
Table 20. Part Numbering Nomenclature
XPC
7450
RX
nnn
x
x
Product
Code
Part
Identifier
Package
Processor
Frequency1
Application Modifier
Revision Level
XPC2
7450
RX = CBGA
533
600
667
L: 1.6 to 1.8 V ± 50 mV
0 to 105°C
E: 2.1; PVR = 8000 0201
Notes:
1. Processor core frequencies supported by parts addressed by this specification only. Parts addressed by Part
Number Specifications may support other maximum core frequencies.
2. The X prefix in a Motorola part number designates a “Pilot Production Prototype” as defined by Motorola SOP
3-13. These are from a limited production volume of prototypes manufactured, tested, and Q.A. inspected on a
qualified technology to simulate normal production. These parts have only preliminary reliability and
characterization data. Before pilot production prototypes may be shipped, written authorization from the customer
must be on file in the applicable sales office acknowledging the qualification status and the fact that product
changes may still occur while shipping pilot production prototypes.
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Ordering Information
1.11.2 Part Numbers Not Fully Addressed by This Document
Parts with application modifiers or revision levels not fully addressed in this specification document are
described in separate part number specifications which supplement and supersede this document; see
Table 21.
Freescale Semiconductor, Inc...
Table 21. Part Numbers with Separate Documentation
Part Number Series
Operating Conditions
Document Order Number of
Applicable Specification
XPC7450RXnnnLD
1.8 V ± 50 mV, 0 to 105°C
.
MPC7450RXLDPNS/D
XPC7450RXnnnQx
1.9 V ± 50 mV, 0 to 65°C
XPC7450RXnnnPD
1.9 V ± 50 mV, 0 to 65°C
Note: For other differences, see applicable specifications.
1.11.3 Part Marking
LE
A
SC
Parts are marked as the example shown in Figure 27.
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EE
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EM
NC
MPC7450RXQXPNS/D
,I
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MPC7450RXPDPNS/D
TO
UC
D
N
XPC7450
RX600LE
MMMMMM
ATWLYYWWA
7450
Notes:
BGA
MMMMMM is the 6-digit mask number.
ATWLYYWWA is the traceability code.
CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States.
Figure 27. Part Marking for BGA Device
50
MPC7450 RISC Microprocessor Hardware Specifications
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MOTOROLA
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Ordering Information
CH
R
A
MOTOROLA
ED
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EE
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F
LE
A
SC
S
O
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EM
R,
O
CT
U
ND
MPC7450 RISC Microprocessor Hardware Specifications
For More Information On This Product,
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IN
.
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Motorola reserves the right to make
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can and do vary in different applications and actual
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Freescale Semiconductor, Inc...
Information in this document is provided solely to enable system and software
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MPC7450EC/D
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