LM3677 www.ti.com SNVS502E – MARCH 2007 – REVISED OCTOBER 2008 LM3677 3MHz, 600mA Miniature Step-Down DC-DC Converter for Ultra Low Voltage Circuits Check for Samples: LM3677 FEATURES APPLICATIONS • • • • • • • • • • • • 1 2 • • • • • • 16 µA typical quiescent current 600 mA maximum load capability 3 MHz PWM fixed switching frequency (typ.) Automatic PFM/PWM mode switching Available in 5-bump micro SMD package and 6-pin LLP package Internal synchronous rectification for high efficiency Internal soft start 0.01 µA typical shutdown current Operates from a single Li-Ion cell battery Only three tiny surface-mount external components required (solution size less than 20 mm2) Current overload and thermal shutdown protection Mobile Phones PDAs MP3 Players W-LAN Portable Instruments Digital Still Cameras Portable Hard Disk Drives DESCRIPTION The LM3677 step-down DC-DC converter is optimized for powering ultra-low voltage circuits from a single Li-Ion cell battery and input voltage rails from 2.7V to 5.5V. It provides up to 600 mA load current over the entire input voltage range. The LM3677 is configured to different fixed voltage output options as well as an adjustable output voltage version range from 1.2V to 3.3V. The device offers superior features and performance for mobile phones and similar portable applications with complex power management systems. Automatic intelligent switching between PWM low-noise and PFM lowcurrent mode offers improved system control. During PWM mode operation, the device operates at a fixed frequency of 3 MHz (typ). PWM mode drives loads from ~ 80 mA to 600 mA max. Hysteretic PFM mode extends the battery life by reducing the quiescent current to 16 µA (typ.) during light load and standby operation. Internal synchronous rectification provides high efficiency. In shutdown mode (Enable pin pulled down), the device turns off and reduces battery consumption to 0.01 µA (typ.). The LM3677 is available in a lead-free (NOPB) 5-bump micro SMD package and 6-pin LLP package. A switching frequency of 3 MHz (typ.) allows use of tiny surface-mount components. Only three external surface-mount components, an inductor and two ceramic capacitors, are required. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2008, Texas Instruments Incorporated LM3677 SNVS502E – MARCH 2007 – REVISED OCTOBER 2008 www.ti.com TYPICAL APPLICATION CIRCUITS VIN 2.7V to 5.5V L1: 1.0 PH VIN CIN 4.7 PF VOUT SW 1 5 COUT 10 PF LM3677 GND 2 EN FB 3 4 Figure 1. Typical Application Circuit VIN 2.7V to 5.5V L1: 1.0 PH VIN 1 CIN 4.7 PF GND EN 2 3 5 LM3677ADJ 4 VOUT SW C1 R1 C2 R2 COUT 10 PF FB Figure 2. Typical Application Circuit - ADJ. Version Figure 3. Efficiency vs. Output Current (VOUT = 1.8V) 2 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Links: LM3677 LM3677 www.ti.com SNVS502E – MARCH 2007 – REVISED OCTOBER 2008 CONNECTION DIAGRAM AND PACKAGE MARK INFORMATION Figure 4. 5-Bump micro SMD Package NS Package Number TLA05FEA Vin A1 B2 EN C1 GND GND A3 C3 SW SW FB FB Top View A3 A1 Vin C1 EN B2 C3 Bottom View Figure 5. 5 Bump Micro SMD Package 6 GND VIN 1 5 SW 5 SW SW 2 4 FB 4 FB EN 3 VIN 1 6 GND SW 2 EN 3 BOTTOM VIEW TOP VIEW Figure 6. 6 Pin LLP Package Table 1. PIN DESCRIPTIONS (1) Pin # (1) Name Description A1 1 VIN A3 6 GND Power supply input. Connect to the input filter capacitor (Figure 1). C1 3 EN Enable pin. The device is in shutdown mode when voltage to this pin is < 0.4V and enabled when > 1.0V. Do not leave this pin floating. Ground pin. C3 4 FB Feedback analog input. Connect directly to the output filter capacitor ( FIGURE 1). B2 2, 5 SW Switching node connection to the internal PFET switch and NFET synchronous rectifier. For output voltage 1.2V or lower, input voltage needs to be derated to the range of 2.7V to 5.0V in order to perform within specification. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Links: LM3677 3 LM3677 SNVS502E – MARCH 2007 – REVISED OCTOBER 2008 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributor for availability and specifications. VIN Pin: Voltage to GND −0.2V to 6.0V FB, SW, EN Pin: (GND−0.2V) to (VIN + 0.2V) Continuous Power Dissipation (2) Internally Limited Junction Temperature (TJ-MAX) +125°C Storage Temperature Range −65°C to +150°C Maximum Lead Temperature (Soldering, 10 sec.) 260°C ESD Rating (1) (2) (3) (3) Human Body Model: All Pins 2.0 kV Machine Model: All Pins 200V Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ= 150°C (typ.) and disengages at TJ= 130°C (typ.). The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each pin. MIL-STD-883 3015.7 OPERATING RATINGS (1), (2) Input Voltage Range 2.7V to 5.5V Recommended Load Current 0 mA to 600 mA −30°C to +125°C Junction Temperature (TJ) Range Ambient Temperature (TA) Range (1) (2) (3) (3) −30°C to +85°C Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. All voltages are with respect to the potential at the GND pin. In Applications where high power dissipation and/or poor package resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX), the maximum power dissipation of the device in the application (PD-MAX) and the junction to ambient thermal resistance of the package (θJA) in the application, as given by the following equation: TA-MAX= TJ-MAX− (θJAx PD-MAX). Refer to Dissipation rating table for PD-MAX values at different ambient temperatures. THERMAL PROPERTIES Junction-to-Ambient Thermal Resistance (θJA) (1) 4 (1) 85°C/W Junction to ambient thermal resistance is highly application and board layout dependent. In applications where high power dissipation exists, special care must be given to thermal dissipation issues in board design. Value specified here 85 °C/W is based on measurement results using a 4 layer board as per JEDEC standards. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Links: LM3677 LM3677 www.ti.com SNVS502E – MARCH 2007 – REVISED OCTOBER 2008 ELECTRICAL CHARACTERISTICS (1) (2) (3) Limits in standard typeface are for TJ = TA = 25°C. Limits in boldface type apply over the operating ambient temperature range (−30°C ≤ TA ≤ +85°C). Unless otherwise noted, specifications apply to the LM3677 with VIN = EN = 3.6V. Symbol VIN Parameter Input Voltage Condition (4) Feedback Voltage (TL) VFB PWM mode Feedback Voltage (LE) Min Max Units 2.7 Typ 5.5 V -2.5 +2.5 -4.0 +4.0 VREF Internal Reference Voltage ISHDN Shutdown Supply Current EN = 0V IQ DC Bias Current into VIN No load, device is not switching 16 35 µA RDSON (P) Pin-Pin Resistance for PFET VIN= VGS= 3.6V, ISW= 100mA 350 450 mΩ RDSON (N) Pin-Pin Resistance for NFET VIN= VGS= 3.6V, ISW= -100mA 150 250 mΩ 1220 1375 mA ILIM Switch Peak Current Limit VIH Logic High Input VIL Logic Low Input IEN Enable (EN) Input Current FOSC Internal Oscillator Frequency (1) (2) (3) (4) (5) 0.5 % Open Loop 0.01 (5) 1085 V 1 1.0 V 0.4 PWM Mode 2.5 µA V 0.01 1 µA 3 3.5 MHz All voltages are with respect to the potential at the GND pin. Min and Max limits are guaranteed by design, test or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm. The parameters in the electrical characteristic table are tested under open loop conditions at VIN= 3.6V unless otherwise specified. For performance over the input voltage range and closed loop condition, refer to the datasheet curves. For output voltage 1.2V or lower, input voltage needs to be derated to the range of 2.7V to 5.0V in order to perform within specification. Refer to datasheet curves for closed loop data and its variation with regards to supply voltage and temperature. Electrical Characteristic table reflects open loop data (FB=0V and current drawn from SW pin ramped up until cycle by cycle current limit is activated). Closed loop current limit is the peak inductor current measured in the application circuit by increasing output current until output voltage drops by 10%. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Links: LM3677 5 LM3677 SNVS502E – MARCH 2007 – REVISED OCTOBER 2008 www.ti.com DISSIPATION RATING TABLE θJA TA≤ 25°C Power Rating TA= 60°C Power Rating TA= 85°C Power Rating 85°C/W (4-layer board) micro SMD 1178 mW 785 mW 470 mW 117°C/W (4-layer board) LLP 855 mW 556 mW 342 mW BLOCK DIAGRAM VIN EN SW Current Limit Comparator Undervoltage Lockout Ramp Generator Soft Start + - Ref1 PFM Current Comparator Thermal Shutdown + - 3 MHz Oscillator Bandgap Ref2 PWM Comparator Error Amp + Control Logic Driver - pfm_low VREF 0.5V + - pfm_hi Vcomp 1.0V + - + - Zero Crossing Comparator Frequency Compensation Fixed Ver FB GND Figure 7. Simplified Functional Diagram 6 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Links: LM3677 LM3677 www.ti.com SNVS502E – MARCH 2007 – REVISED OCTOBER 2008 TYPICAL PERFORMANCE CHARACTERISTICS LM3677, Circuit of Figure 1, VIN = 3.6V, VOUT = 1.8V, TA = 25°C, unless otherwise noted. Quiescent Supply Current vs. Supply Voltage (Switching) Shutdown Current vs. Temp Switching Frequency vs. Temperature RDS(ON) vs. Temperature Open/Closed Loop Current Limit vs. Temperature Output Voltage vs. Supply Voltage (VOUT = 1.8V) Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Links: LM3677 7 LM3677 SNVS502E – MARCH 2007 – REVISED OCTOBER 2008 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) LM3677, Circuit of Figure 1, VIN = 3.6V, VOUT = 1.8V, TA = 25°C, unless otherwise noted. 8 Output Voltage vs. Supply Voltage (VOUT = 2.5V) Output Voltage vs. Temperature (VOUT = 1.3V) Output Voltage vs. Temperature (VOUT = 1.8V) Output Voltage vs. Temperature (VOUT = 2.5V) Output Voltage vs. Output Current (VOUT = 1.8V) Output Voltage vs. Output Current (VOUT = 2.5V) Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Links: LM3677 LM3677 www.ti.com SNVS502E – MARCH 2007 – REVISED OCTOBER 2008 TYPICAL PERFORMANCE CHARACTERISTICS (continued) LM3677, Circuit of Figure 1, VIN = 3.6V, VOUT = 1.8V, TA = 25°C, unless otherwise noted. Efficiency vs. Output Current (VOUT = 1.3V) Efficiency vs. Output Current (VOUT = 1.8V) Efficiency vs. Output Current (VOUT = 2.5V) Output Current vs. Input Voltage at Mode Change Point (VOUT = 1.3V) Output Current vs. Input Voltage at Mode Change Point (VOUT = 1.8V) Output Current vs. Input Voltage at Mode Change Point (VOUT = 2.5V) Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Links: LM3677 9 LM3677 SNVS502E – MARCH 2007 – REVISED OCTOBER 2008 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) LM3677, Circuit of Figure 1, VIN = 3.6V, VOUT = 1.8V, TA = 25°C, unless otherwise noted. 10 Line Transient Response VOUT = 1.3V (PWM Mode) Line Transient Response VOUT = 1.8V (PWM Mode) Line Transient Response VOUT = 1.8V (PWM Mode) Line Transient Response VOUT = 2.5V (PWM Mode) Load Transient Response (VOUT = 1.3V) (PFM Mode 1mA to 50mA) Load Transient Response (VOUT = 1.3V) (PFM Mode 50mA to 1mA) Load Transient Response (VOUT = 1.8V) (PFM Mode 1mA to 50mA) Load Transient Response (VOUT = 1.8V) (PFM Mode 50mA to 1mA) Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Links: LM3677 LM3677 www.ti.com SNVS502E – MARCH 2007 – REVISED OCTOBER 2008 TYPICAL PERFORMANCE CHARACTERISTICS (continued) LM3677, Circuit of Figure 1, VIN = 3.6V, VOUT = 1.8V, TA = 25°C, unless otherwise noted. Load Transient Response (VOUT = 2.5V) (PFM Mode 1mA to 50mA) Load Transient Response (VOUT = 2.5V) (PFM Mode 50mA to 1mA) Mode Change by Load Transients VOUT = 1.3V (PFM to PWM) Mode Change by Load Transients VOUT = 1.3V (PWM to PFM) Mode Change by Load Transients VOUT = 1.8V (PFM to PWM) Mode Change by Load Transients VOUT = 1.8V (PWM to PFM) Load Transient Response VOUT = 1.3V (PWM Mode) Load Transient Response VOUT = 1.8V (PWM Mode) Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Links: LM3677 11 LM3677 SNVS502E – MARCH 2007 – REVISED OCTOBER 2008 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) LM3677, Circuit of Figure 1, VIN = 3.6V, VOUT = 1.8V, TA = 25°C, unless otherwise noted. Load Transient Response VOUT = 2.5V (PWM Mode) Start Up into PWM Mode VOUT = 1.3V (Output Current= 300mA) Start Up into PFM Mode VOUT = 1.3V (Output Current= 1mA) Start Up into PWM Mode VOUT = 1.8V (Output Current= 300mA) Start Up into PFM Mode VOUT = 1.8V (Output Current= 1mA) Start Up into PWM Mode VOUT = 2.5V (Output Current= 300mA) Start Up into PFM Mode VOUT = 2.5V (Output Current= 1mA) 12 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Links: LM3677 LM3677 www.ti.com SNVS502E – MARCH 2007 – REVISED OCTOBER 2008 OPERATION DESCRIPTION DEVICE INFORMATION The LM3677, a high-efficiency step-down DC-DC switching buck converter, delivers a constant voltage from a single Li-Ion battery and input voltage rails from 2.7V to 5.5V to devices such as cell phones and PDAs. Using a voltage-mode architecture with synchronous rectification, the LM3677 has the ability to deliver up to 600 mA depending on the input voltage and output voltage, ambient temperature, and the inductor chosen. There are three modes of operation depending on the current required: PWM (Pulse Width Modulation), PFM (Pulse Frequency Modulation), and shutdown. The device operates in PWM mode at load current of approximately 80 mA or higher, having a voltage precision of ±2.5% with 90% efficiency or better. Lighter load current causes the device to automatically switch into PFM mode for reduced current consumption (IQ = 16 µA typ.) and a longer battery life. Shutdown mode turns off the device, offering the lowest current consumption (ISHUTDOWN = 0.01 µA (typ.). Additional features include soft-start, under voltage protection, current overload protection, and thermal shutdown protection. As shown in Figure 1, only three external power components are required for implementation. The part uses an internal reference voltage of 0.5V. It is recommended to keep the part in shutdown until the input voltage exceeds 2.7V. CIRCUIT OPERATION The LM3677 operates as follows. During the first portion of each switching cycle, the control block in the LM3677 turns on the internal PFET switch. This allows current to flow from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a ramp with a slope of (VIN–VOUT)/L, by storing energy in a magnetic field. During the second portion of each cycle, the controller turns the PFET switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor draws current from ground through the NFET to the output filter capacitor and load, which ramps the inductor current down with a slope of - VOUT/L. The output filter stores charge when the inductor current is high, and releases it when inductor current is low, smoothing the voltage across the load. The output voltage is regulated by modulating the PFET switch-on time to control the average current sent to the load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and synchronous rectifier at the SW pin to a low-pass filter formed by the inductor and output filter capacitor. The output voltage is equal to the average voltage at the SW pin. PWM OPERATION During PWM operation, the converter operates as a voltage-mode controller with input voltage feed forward. This allows the converter to achieve good load and line regulation. The DC gain of the power stage is proportional to the input voltage. To eliminate this dependence, feed forward inversely proportional to the input voltage is introduced. While in PWM mode, the output voltage is regulated by switching at a constant frequency and then modulating the energy per cycle to control power to the load. At the beginning of each clock cycle the PFET switch is turned on and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The current limit comparator can also turn off the switch in case the current limit of the PFET is exceeded. Then the NFET switch is turned on and the inductor current ramps down. The next cycle is initiated by the clock turning off the NFET and turning on the PFET. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Links: LM3677 13 LM3677 SNVS502E – MARCH 2007 – REVISED OCTOBER 2008 www.ti.com Figure 8. Typical PWM Operation INTERNAL SYNCHRONOUS RECTIFICATION While in PWM mode, the LM3677 uses an internal NFET as a synchronous rectifier to reduce rectifier forward voltage drop and associated power loss. Synchronous rectification provides a significant improvement in efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier diode. CURRENT LIMITING A current limit feature allows the LM3677 to protect itself and external components during overload conditions. PWM mode implements current limiting using an internal comparator that trips at 1220 mA (typ.). If the output is shorted to ground the device enters a timed current limit mode where the NFET is turned on for a longer duration until the inductor current falls below a low threshold, ensuring inductor current has more time to decay, thereby preventing runaway. PFM OPERATION At very light loads, the converter enters PFM mode and operates with reduced switching frequency and supply current to maintain high efficiency. The part will automatically transition into PFM mode when either of the following conditions occurs for a duration of 32 or more clock cycles: A. The NFET current reaches zero. B. The peak PMOS switch current drops below the IMODE level, (Typically IMODE < 75 mA + VIN/55Ω ). Figure 9. Typical PFM Operation 14 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Links: LM3677 LM3677 www.ti.com SNVS502E – MARCH 2007 – REVISED OCTOBER 2008 During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage during PWM operation allowing additional headroom for voltage drop during a load transient from light to heavy load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output FETs such that the output voltage ramps between ~0.2% and ~1.8% above the nominal PWM output voltage. If the output voltage is below the ‘high’ PFM comparator threshold, the PMOS power switch is turned on. It remains on until the output voltage reaches the ‘high’ PFM threshold or the peak current exceeds the IPFM level set for PFM mode. The typical peak current in PFM mode is: IPFM = 112 mA + VIN/20Ω . Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output voltage is below the ‘high’ PFM comparator threshold (see Figure 10), the PMOS switch is again turned on and the cycle is repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero, and then both output switches are turned off and the part enters an extremely low-power mode. Quiescent supply current during this ‘sleep’ mode is 16 µA (typ.), which allows the part to achieve high efficiencies under extremely light load conditions. If the load current should increase during PFM mode (Figure 10) causing the output voltage to fall below the ‘low2’ PFM threshold, the part will automatically transition into fixed-frequency PWM mode. When VIN =2.7V the part transitions from PWM to PFM mode at ~ 35 mA output current and from PFM to PWM mode at ~ 95 mA , when VIN=3.6V, PWM to PFM transition occurs at ~ 42 mA and PFM to PWM transition occurs at ~ 115 mA, when VIN =4.5V, PWM to PFM transition occurs at ~ 60 mA and PFM to PWM transition occurs at ~ 135 mA. High PFM Threshold ~1.018*Vout PFM Mode at Light Load Load current increases ZAx is High PFM Voltage Threshold reached, go into sleep mode Low PFM Threshold, turn on PFET Low2 PFM Threshold, switch back to PWMmode xis Z-A Pfet on until Ipfm limit reached Nfet on drains conductor current until I inductor=0 Current load increases, draws Vout towards Low2 PFM Threshold Low1 PFM Threshold ~1.002*Vout Low2 PFM Threshold Vout PWM Mode at Moderate to Heavy Loads Figure 10. Operation in PFM Mode and Transfer to PWM Mode SHUTDOWN MODE Setting the EN input pin low (<0.4V) places the LM3677 in shutdown mode. During shutdown the PFET switch, NFET switch, reference, control and bias circuitry of the LM3677 are turned off. Setting EN high (>1.0V) enables normal operation. It is recommended to set EN pin low to turn off the LM3677 during system power up and undervoltage conditions when the supply is less than 2.7V. Do not leave the EN pin floating. SOFT START The LM3677 has a soft-start circuit that limits in-rush current during start-up. During start-up the switch current limit is increased in steps. Soft start is activated only if EN goes from logic low to logic high after VIN reaches 2.7V. Soft start is implemented by increasing switch current limit in steps of 200 mA, 400 mA, 600 mA and 1220 mA (typical switch current limit). The start-up time thereby depends on the output capacitor and load current demanded at start-up. Typical start-up times with a 10 µF output capacitor and 300 mA load is 300 µs and with 1 mA load is 200 µs. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Links: LM3677 15 LM3677 SNVS502E – MARCH 2007 – REVISED OCTOBER 2008 www.ti.com APPLICATION INFORMATION INDUCTOR SELECTION There are two main considerations when choosing an inductor: the inductor should not saturate, and the inductor current ripple should be small enough to achieve the desired output voltage ripple. Different saturation current rating specifications are followed by different manufacturers so attention must be given to details. Saturation current ratings are typically specified at 25°C. However, ratings at the maximum ambient temperature of application should be requested form the manufacturer. The minimum value of inductance to guarantee good performance is 0.7 µH at ILIM (typ.) DC current over the ambient temperature range. Shielded inductors radiate less noise and should be preferred. There are two methods to choose the inductor saturation current rating. Method 1: The saturation current is greater than the sum of the maximum load current and the worst case average to peak inductor current. This can be written as ISAT ! IOUTMAX + IRIPPLE where IRIPPLE = • • • • • • § VIN - VOUT · § VOUT · § 1 · ¨ 2 L ¸ ¨ VIN ¸ ¨ f ¸ ¹ © ¹ ¹ © © (1) IRIPPLE: average to peak inductor current IOUTMAX: maximum load current (600 mA) VIN: maximum input voltage in application L : min inductor value including worst case tolerances (30% drop can be considered for method 1) f : minimum switching frequency (2.5 MHz) VOUT: output voltage Method 2: A more conservative and recommended approach is to choose an inductor that has saturation current rating greater than the max current limit of 1375 mA. A 1.0 µH inductor with a saturation current rating of at least 1375 mA is recommended for most applications. The inductor’s resistance should be less than 0.15Ω for good efficiency. Table 2 lists suggested inductors and suppliers. For low-cost applications, an unshielded bobbin inductor could be considered. For noise critical applications, a toroidal or shielded-bobbin inductor should be used. A good practice is to lay out the board with overlapping footprints of both types for design flexibility. This allows substitution of a low-noise shielded inductor in the event that noise from low-cost bobbin models is unacceptable. INPUT CAPACITOR SELECTION A ceramic input capacitor of 4.7 µF, 6.3V is sufficient for most applications. Place the input capacitor as close as possible to the VIN pin of the device. A larger value may be used for improved input voltage filtering. Use X7R or X5R types; do not use Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0603 and 0805. The minimum input capacitance to guarantee good performance is 2.2 µF at 3V DC bias; 1.5 µF at 5V DC bias including tolerances and over ambient temperature range. The input filter capacitor supplies current to the PFET switch of the LM3677 in the first half of each cycle and reduces voltage ripple imposed on the input power source. A ceramic capacitor’s low ESR provides the best noise filtering of the input voltage spikes due to this rapidly changing current. Select a capacitor with sufficient ripple current rating. The input current ripple can be calculated as: VOUT IRMS = IOUTMAX VIN §1¨ © VOUT VIN + r 2 12 · ¸ ¹ (VIN - VOUT) VOUT r= L f IOUTMAX VIN The worst case is when VIN = 2 VOUT 16 (2) Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Links: LM3677 LM3677 www.ti.com SNVS502E – MARCH 2007 – REVISED OCTOBER 2008 Table 2. Suggested Inductors and Their Suppliers Model Vendor Dimensions LxWxH(mm) D.C.R (max) MIPSA2520D 1R0 FDK 2.5 x 2.0 x 1.2 100 mΩ LQM2HP 1R0 Murata 2.5 x 2.0 x 0.95 100 mΩ BRL2518T1R0M Taiyo Yuden 2.5x 1.8 x 1.2 80 mΩ OUTPUT CAPACITOR SELECTION A ceramic output capacitor of 10 µF, 6.3V is sufficient for most applications. Use X7R or X5R types; do not use Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0603 and 0805. DC bias characteristics vary from manufacturer to manufacturer and dc bias curves should be requested from them as part of the capacitor selection process. The minimum output capacitance to guarantee good performance is 5.75 µF at 2.5V DC bias including tolerances and over ambient temperature range. The output filter capacitor smooths out current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR to perform these functions. The output voltage ripple is caused by the charging and discharging of the output capacitor and by the RESR and can be calculated as: Voltage peak-to-peak ripple due to capacitance can be expressed as follows VPP-C = IRIPPLE 4*f*C (3) Voltage peak-to-peak ripple due to ESR can be expressed as follows VPP-ESR = (2 * IRIPPLE) * RESR Because these two components are out of phase the rms (root mean squared) value can be used to get an approximate value of peak-to-peak ripple. Voltage peak-to-peak ripple, rms can be expressed as follow: VPP-RMS = VPP-C2 + VPP-ESR2 (4) Note that the output voltage ripple is dependent on the inductor current ripple and the equivalent series resistance of the output capacitor (RESR). The RESR is frequency dependent (as well as temperature dependent); make sure the value used for calculations is at the switching frequency of the part. Table 3. Suggested Capacitors and Their Suppliers Type Vendor Voltage Rating Case Size Inch (mm) C1608X5R0J475 Ceramic, X5R TDK 6.3V 0603 (1608) Model 4.7 µF for CIN C2012X5R0J475 Ceramic, X5R TDK 6.3V 0805 (2012) GRM21BR60J475 Ceramic, X5R muRata 6.3V 0805 (2012) JMK212BJ475 Ceramic, X5R Taiyo-Yuden 6.3V 0805 (2012) C1608X5R0J106 Ceramic, X5R TDK 6.3V 0603 (1608) C2012X5R0J106 Ceramic, X5R TDK 6.3V 0805 (2012) GRM21BR60J106 Ceramic, X5R muRata 6.3V 0805 (2012) JMK212BJ106 Ceramic, X5R Taiyo-Yuden 6.3V 0805 (2012) 10 µF for COUT Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Links: LM3677 17 LM3677 SNVS502E – MARCH 2007 – REVISED OCTOBER 2008 www.ti.com OUTPUT VOLTAGE SELECTION FOR LM3677-ADJ The output voltage of the adjustable parts can be programmed through the resistor network connected from VOUT to FB to GND. The resistor and FB to GND (R2) should be 200 kΩ to keep the current drawn through this network well below 16 µA quiescent current level (PFM mode) but large enough that it is not susceptible to noise. If R2 is 200 kΩ, and given the VFB is 0.5V, then the current through the resistor feedback network will be 2.5 µA. The output voltage of the adjustable parts ranges from 1.2V and 3.3V. The output voltage formula is: VOUT = VFB R1 +1 R2 VOUT: output voltage (V) VFB: feedback voltage (0.5V typical) R1: feedback resistor from VOUT to FB (Ω) R2: feedback resistor from to FB to GND (Ω) For the fixed output voltage parts the feedback resistors are internal and R1 is 0Ω. The bypass capacitors C1 and C2 (labeled C3 and C4 on Evaluation Board) in parallel with the feedback resistors are chosen for increased stability. Below are the formulas for C1 and C2: C1 = 1 2 x S x R1 x 70 kHz C2 = 1 2 x S x R2 x 70 kHz Table 4. LM3677–ADJ Configurations for Various VOUT (Circuit of Figure 2) VOUT (V) R1(kΩ ) R2(kΩ ) C1(pF) C2(pF) L (µH) CIN (µF) COUT (µF) 1.2 280 200 8.2 none 1.0 4.7 10 1.3 320 200 8.2 none 1.0 4.7 10 1.5 357 178 6.8 none 1.0 4.7 10 1.6 442 200 5.6 none 1.0 4.7 10 1.8 464 178 5.6 none 1.0 4.7 10 2.5 402 100 6.0 none 1.0 4.7 10 2.8 464 100 5.6 24 1.0 4.7 10 3.3 562 100 5.6 24 1.0 4.7 10 MICRO SMD PACKAGE ASSEMBLY AND USE Use of the micro SMD package requires specialized board layout, precision mounting and careful re-flow techniques, as detailed in National Semiconductor Application Note 1112. Refer to the section "Surface Mount Technology (SMD) Assembly Considerations". For best results in assembly, alignment ordinals on the PC board should be used to facilitate placement of the device. The pad style used with micro SMD package must be the NSMD (non-solder mask defined typ.). This means that the solder-mask opening is larger than the pad size. This prevents a lip that otherwise forms if the solder-mask and pad overlap, from holding the device off the surface of the board and interfering with mounting. See Application Note 1112 for specific instructions how to do this. The 5-bump package used for LM3677 has 300–micron solder balls and requires 10.82 mils pads for mounting on the circuit board. The trace to each pad should enter the pad with a 90° entry angle to prevent debris from being caught in deep corners. Initially, the trace to each pad should be 7 mil wide, for a section approximately 7 mil long or longer, as a thermal relief. Then each trace should neck up or down to its optimal width. The important criteria is symmetry. This ensures the solder bumps on the LM3677 re-flow evenly and that the device solders level to the board. In particular, special attention must be paid to the pads for bumps A1 and A3, because GND and VIN are typically connected to large copper planes, inadequate thermal relief can result in late or inadequate re-flow of these bumps. 18 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Links: LM3677 LM3677 www.ti.com SNVS502E – MARCH 2007 – REVISED OCTOBER 2008 The micro SMD package is optimized for the smallest possible size in applications with red or infrared opaque cases. Because the micro SMD package lacks the plastic encapsulation characteristic of larger devices, it is vulnerable to light. Backside metallization and/or epoxy coating, along with front-side shading by the printed circuit board, reduce this sensitivity. However, the package has exposed die edges. In particular, micro SMD devices are sensitive to light, in the red and infrared range, shining on the package’s exposed die edges. BOARD LAYOUT CONSIDERATIONS PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces. These can send erroneous signals to the DC-DC converter IC, resulting in poor regulation or instability. Poor layout can also result in re-flow problems leading to poor solder joints between the micro SMD package and board pads. Poor solder joints can result in erratic or degraded performance. Figure 11. Board Layout Design Rules for the LM3677 Good layout for the LM3677 can be implemented by following a few simple design rules. 1. Place the LM3677 on 10.82 mil pads. As a thermal relief, connect to each pad with a 7 mil wide, approximately 7 mil long trace, and then incrementally increase each trace to its optimal width. The important criterion is symmetry to ensure the solder bumps on the re-flow evenly (see Micro SMD Package Assembly and Use). 2. Place the LM3677, inductor and filter capacitors close together and make the traces short. The traces between these components carry relatively high switching currents and act as antennas. Following this rule reduces radiated noise. Special care must be given to place the input filter capacitor very close to the VIN and GND pin. 3. Arrange the components so that the switching current loops curl in the same direction. During the first half of each cycle, current flows from the input filter capacitor, through the LM3677 and inductor to the output filter capacitor and back through ground, forming a current loop. In the second half of each cycle, current is pulled up from ground, through the LM3677 by the inductor, to the output filter capacitor and then back through ground, forming a second current loop. Routing these loops so the current curls in the same direction prevents magnetic field reversal between the two half-cycles and reduces radiated noise. 4. Connect the ground pins of the LM3677, and filter capacitors together using generous component-side copper fill as a pseudo-ground plane. Then connect this to the ground-plane (if one is used) with several vias. This reduces ground-plane noise by preventing the switching currents from circulating through the ground plane. It also reduces ground bounce at the LM3677 by giving it a low-impedance ground connection. 5. Use wide traces between the power components and for power connections to the DC-DC converter circuit. This reduces voltage errors caused by resistive losses across the traces Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Links: LM3677 19 LM3677 SNVS502E – MARCH 2007 – REVISED OCTOBER 2008 www.ti.com 6. Route noise sensitive traces such as the voltage feedback path away from noisy traces between the power components. The voltage feedback trace must remain close to the LM3677 circuit and should be routed directly from FB to VOUT at the output capacitor and should be routed opposite to noise components. This reduces EMI radiated onto the DC-DC converter’s own voltage feedback trace. 7. Place noise sensitive circuitry, such as radio IF blocks, away from the DC-DC converter, CMOS digital blocks and other noisy circuitry. Interference with noise-sensitive circuitry in the system can be reduced through distance. In mobile phones, for example, a common practice is to place the DC-DC converter on one corner of the board, arrange the CMOS digital circuitry around it (since this also generates noise), and then place sensitive preamplifiers and IF stages on the diagonally opposing corner. Often, the sensitive circuitry is shielded with a metal pan and power to it is post-regulated to reduce conducted noise, using low-dropout linear regulators. 20 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Links: LM3677 PACKAGE OPTION ADDENDUM www.ti.com 12-Nov-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Samples (3) (Requires Login) LM3677LE-1.2/NOPB ACTIVE USON NGE 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LM3677LE-1.5/NOPB ACTIVE USON NGE 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LM3677LE-1.8/NOPB ACTIVE USON NGE 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LM3677LE-1.82/NOPB ACTIVE USON NGE 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LM3677LEE-1.2/NOPB ACTIVE USON NGE 6 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LM3677LEE-1.5/NOPB ACTIVE USON NGE 6 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LM3677LEE-1.8/NOPB ACTIVE USON NGE 6 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LM3677LEE-1.82/NOPB ACTIVE USON NGE 6 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LM3677LEX-1.2/NOPB ACTIVE USON NGE 6 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LM3677LEX-1.5/NOPB ACTIVE USON NGE 6 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LM3677LEX-1.8/NOPB ACTIVE USON NGE 6 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LM3677LEX-1.82/NOPB ACTIVE USON NGE 6 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LM3677TL-1.2/NOPB ACTIVE DSBGA YZR 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM LM3677TL-1.3/NOPB ACTIVE DSBGA YZR 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM LM3677TL-1.5/NOPB ACTIVE DSBGA YZR 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM LM3677TL-1.8/NOPB ACTIVE DSBGA YZR 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM LM3677TL-1.82/NOPB ACTIVE DSBGA YZR 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 12-Nov-2012 Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Samples (3) (Requires Login) LM3677TL-1.875/NOPB ACTIVE DSBGA YZR 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM LM3677TL-2.5/NOPB ACTIVE DSBGA YZR 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM LM3677TL-ADJ/NOPB ACTIVE DSBGA YZR 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM LM3677TLX-1.2/NOPB ACTIVE DSBGA YZR 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM LM3677TLX-1.3/NOPB ACTIVE DSBGA YZR 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM LM3677TLX-1.5/NOPB ACTIVE DSBGA YZR 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM LM3677TLX-1.8/NOPB ACTIVE DSBGA YZR 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM LM3677TLX-1.82/NOPB ACTIVE DSBGA YZR 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM LM3677TLX-1.875/NOPB ACTIVE DSBGA YZR 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM LM3677TLX-2.5/NOPB ACTIVE DSBGA YZR 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM LM3677TLX-ADJ/NOPB ACTIVE DSBGA YZR 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 12-Nov-2012 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 15-Nov-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM3677LE-1.2/NOPB USON NGE 6 1000 178.0 12.4 1.7 2.2 0.8 8.0 12.0 Q1 LM3677LE-1.5/NOPB USON NGE 6 1000 178.0 12.4 1.7 2.2 0.8 8.0 12.0 Q1 LM3677LE-1.8/NOPB USON NGE 6 1000 178.0 12.4 1.7 2.2 0.8 8.0 12.0 Q1 LM3677LE-1.82/NOPB USON NGE 6 1000 178.0 12.4 1.7 2.2 0.8 8.0 12.0 Q1 LM3677LEE-1.2/NOPB USON NGE 6 250 178.0 12.4 1.7 2.2 0.8 8.0 12.0 Q1 LM3677LEE-1.5/NOPB USON NGE 6 250 178.0 12.4 1.7 2.2 0.8 8.0 12.0 Q1 LM3677LEE-1.8/NOPB USON NGE 6 250 178.0 12.4 1.7 2.2 0.8 8.0 12.0 Q1 LM3677LEE-1.82/NOPB USON NGE 6 250 178.0 12.4 1.7 2.2 0.8 8.0 12.0 Q1 LM3677LEX-1.2/NOPB USON NGE 6 4500 330.0 12.4 1.7 2.2 0.8 8.0 12.0 Q1 LM3677LEX-1.5/NOPB USON NGE 6 4500 330.0 12.4 1.7 2.2 0.8 8.0 12.0 Q1 LM3677LEX-1.8/NOPB USON NGE 6 4500 330.0 12.4 1.7 2.2 0.8 8.0 12.0 Q1 LM3677LEX-1.82/NOPB USON NGE 6 4500 330.0 12.4 1.7 2.2 0.8 8.0 12.0 Q1 LM3677TL-1.2/NOPB DSBGA YZR 5 250 178.0 8.4 1.24 1.7 0.76 4.0 8.0 Q1 LM3677TL-1.3/NOPB DSBGA YZR 5 250 178.0 8.4 1.24 1.7 0.76 4.0 8.0 Q1 LM3677TL-1.5/NOPB DSBGA YZR 5 250 178.0 8.4 1.24 1.7 0.76 4.0 8.0 Q1 LM3677TL-1.8/NOPB DSBGA YZR 5 250 178.0 8.4 1.24 1.7 0.76 4.0 8.0 Q1 LM3677TL-1.82/NOPB DSBGA YZR 5 250 178.0 8.4 1.24 1.7 0.76 4.0 8.0 Q1 LM3677TL-1.875/NOPB DSBGA YZR 5 250 178.0 8.4 1.24 1.7 0.76 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 15-Nov-2012 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM3677TL-2.5/NOPB DSBGA YZR 5 250 178.0 8.4 1.24 1.7 0.76 4.0 8.0 Q1 LM3677TL-ADJ/NOPB DSBGA YZR 5 250 178.0 8.4 1.24 1.7 0.76 4.0 8.0 Q1 LM3677TLX-1.2/NOPB DSBGA YZR 5 3000 178.0 8.4 1.24 1.7 0.76 4.0 8.0 Q1 LM3677TLX-1.3/NOPB DSBGA YZR 5 3000 178.0 8.4 1.24 1.7 0.76 4.0 8.0 Q1 LM3677TLX-1.5/NOPB DSBGA YZR 5 3000 178.0 8.4 1.24 1.7 0.76 4.0 8.0 Q1 LM3677TLX-1.8/NOPB DSBGA YZR 5 3000 178.0 8.4 1.24 1.7 0.76 4.0 8.0 Q1 LM3677TLX-1.82/NOPB DSBGA YZR 5 3000 178.0 8.4 1.24 1.7 0.76 4.0 8.0 Q1 LM3677TLX-1.875/NOPB DSBGA YZR 5 3000 178.0 8.4 1.24 1.7 0.76 4.0 8.0 Q1 LM3677TLX-2.5/NOPB DSBGA YZR 5 3000 178.0 8.4 1.24 1.7 0.76 4.0 8.0 Q1 LM3677TLX-ADJ/NOPB DSBGA YZR 5 3000 178.0 8.4 1.24 1.7 0.76 4.0 8.0 Q1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM3677LE-1.2/NOPB USON NGE 6 1000 203.0 190.0 41.0 LM3677LE-1.5/NOPB USON NGE 6 1000 203.0 190.0 41.0 LM3677LE-1.8/NOPB USON NGE 6 1000 203.0 190.0 41.0 LM3677LE-1.82/NOPB USON NGE 6 1000 203.0 190.0 41.0 LM3677LEE-1.2/NOPB USON NGE 6 250 203.0 190.0 41.0 LM3677LEE-1.5/NOPB USON NGE 6 250 203.0 190.0 41.0 LM3677LEE-1.8/NOPB USON NGE 6 250 203.0 190.0 41.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 15-Nov-2012 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM3677LEE-1.82/NOPB USON NGE 6 250 203.0 190.0 41.0 LM3677LEX-1.2/NOPB USON NGE 6 4500 349.0 337.0 45.0 LM3677LEX-1.5/NOPB USON NGE 6 4500 349.0 337.0 45.0 LM3677LEX-1.8/NOPB USON NGE 6 4500 349.0 337.0 45.0 LM3677LEX-1.82/NOPB USON NGE 6 4500 349.0 337.0 45.0 LM3677TL-1.2/NOPB DSBGA YZR 5 250 203.0 190.0 41.0 LM3677TL-1.3/NOPB DSBGA YZR 5 250 203.0 190.0 41.0 LM3677TL-1.5/NOPB DSBGA YZR 5 250 203.0 190.0 41.0 LM3677TL-1.8/NOPB DSBGA YZR 5 250 203.0 190.0 41.0 LM3677TL-1.82/NOPB DSBGA YZR 5 250 203.0 190.0 41.0 LM3677TL-1.875/NOPB DSBGA YZR 5 250 203.0 190.0 41.0 LM3677TL-2.5/NOPB DSBGA YZR 5 250 203.0 190.0 41.0 LM3677TL-ADJ/NOPB DSBGA YZR 5 250 203.0 190.0 41.0 LM3677TLX-1.2/NOPB DSBGA YZR 5 3000 206.0 191.0 90.0 LM3677TLX-1.3/NOPB DSBGA YZR 5 3000 206.0 191.0 90.0 LM3677TLX-1.5/NOPB DSBGA YZR 5 3000 206.0 191.0 90.0 LM3677TLX-1.8/NOPB DSBGA YZR 5 3000 206.0 191.0 90.0 LM3677TLX-1.82/NOPB DSBGA YZR 5 3000 206.0 191.0 90.0 LM3677TLX-1.875/NOPB DSBGA YZR 5 3000 206.0 191.0 90.0 LM3677TLX-2.5/NOPB DSBGA YZR 5 3000 206.0 191.0 90.0 LM3677TLX-ADJ/NOPB DSBGA YZR 5 3000 206.0 191.0 90.0 Pack Materials-Page 3 MECHANICAL DATA NGE0006A LEB06A (Rev B) www.ti.com MECHANICAL DATA YZR0005xxx TLA05XXX (Rev C) D: Max = 1.534 mm, Min =1.434 mm E: Max = 1.153 mm, Min =1.053 mm www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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