MOTOROLA MPC962309 Low-cost 3.3 v zero delay buffer Datasheet

Freescale Semiconductor, Inc.
MOTOROLA
Order number: MPC962305
Rev 5, 08/2004
SEMICONDUCTOR TECHNICAL DATA
Low-Cost 3.3 V Zero Delay Buffer
The MPC962309 is a zero delay buffer designed to distribute high-speed
clocks. Available in a 16-pin SOIC or TSSOP package, the device accepts one
reference input and drives nine low-skew clocks. The MPC962305 is the 8-pin
version of the MPC962309 which drives five outputs with one reference input.
The -1H versions of these devices have higher drive than the -1 devices and
can operate up to 100/-133 MHz frequencies. These parts have on-chip PLLs
which lock to an input clock presented on the REF pin. The PLL feedback is
on-chip and is obtained from the CLOCKOUT pad.
MPC962305
MPC962309
D SUFFIX
8-LEAD SOIC PACKAGE
CASE 751-06
Freescale Semiconductor, Inc...
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1:5 LVCMOS zero-delay buffer (MPC962305)
1:9 LVCMOS zero-delay buffer (MPC962309)
Zero input-output propagation delay
Multiple low-skew outputs
250 ps max output-output skew
700 ps max device-device skew
Supports a clock I/O frequency range of 10 MHz to 133 MHz,
compatible with CPU and PCI bus frequencies
Low jitter, 200 ps max cycle-cycle, and compatible with Pentium® based
systems
Test Mode to bypass PLL (MPC962309 only. See “Select Input Decoding”)
8-pin SOIC or 8-pin TSSOP package (MPC962305);16-pin SOIC or 16-pin
TSSOP package (MPC962309)
Single 3.3 V supply
Ambient temperature range: –40°C to +85°C
Compatible with the CY2305, CY23S05, CY2309, CY23S09
Spread spectrum compatible
DT SUFFIX
8-LEAD TSSOP PACKAGE
CASE 948J-01
D SUFFIX
16-LEAD SOIC PACKAGE
CASE 751B-05
DT SUFFIX
16-LEAD TSSOP PACKAGE
CASE 948F-01
Functional Description
The MPC962309 has two banks of four outputs each, which can be controlled by the Select Inputs as shown in Table 3.Select Input Decoding for
MPC962309. Bank B can be tri-stated if all of the outputs are not required. Select inputs also allow the input clock to be directly applied
to the outputs for chip and system testing purposes.
The MPC962305 and MPC962309 PLLs enters a power down state when there are no rising edges on the REF input. During this
state, all of the outputs are in tristate, the PLL is turned off, and there is less than 25.0 µA of current draw for the device. The PLL
shuts down in one additional case as shown in Table 3.Select Input Decoding for MPC962309.
Multiple MPC962305 and MPC962309 devices can accept the same input clock and distribute it throughout the system. In this
situation, the difference between the output skews of two devices will be less than 700 ps.
All outputs have less than 200 ps of cycle-cycle jitter. The input-to-output propagation delay on both devices is guaranteed to be
less than 350 ps and the output-to-output skew is guaranteed to be less than 250 ps.
The MPC962305 and MPC962309 are available in two/three different configurations, as shown on the ordering information page.
The MPC962305-1/MPC962309-1 are the base parts. High drive versions of those devices, MPC962305-1H and MPC962309-1H,
are available to provide faster rise and fall times of the base device.
© Motorola, Inc. 2004
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Freescale Semiconductor, Inc.
MPC962305 MPC962309
Block Diagram
Pin Configuration
CLKOUT
PLL
MUX
REF
REF
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
S2
CLKB2
Select Input
Decoding
S1
REF
CLK2
CLK1
GND
CLKB3
Freescale Semiconductor, Inc...
CLKB4
SOIC/TSSOP
Top View
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
SOIC/TSSOP
Top View
1
8
2
7
3
6
4
5
CLKOUT
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
CLKOUT
CLK4
VDD
CLK3
Table 1. Pin Description for MPC962309
Pin
Signal
Description
1
REF1
Input reference frequency, 5 V-tolerant input
2
CLKA12
Buffered clock output, Bank A
3
CLKA22
Buffered clock output, Bank A
4
VDD
3.3 V supply
5
GND
Ground
6
CLKB1
2
Buffered clock output, Bank B
7
CLKB22
Buffered clock output, Bank B
8
Select input, bit 2
Select input, bit 1
S2
3
9
S1
3
10
CLKB32
11
CLKB4
2
12
GND
Ground
13
VDD
3.3 V supply
14
CLKA32
15
2
16
CLKA4
Buffered clock output, Bank B
Buffered clock output, Bank B
Buffered clock output, Bank A
Buffered clock output, Bank A
Buffered output, internal feedback on this pin
2
CLKOUT
Table 2. Pin Description for MPC962305
Pin
Signal
Description
1
Input reference frequency, 5 V-tolerant input
REF
2
CLK22
Buffered clock output
3
CLK12
Buffered clock output
4
GND
Ground
1
5
CLK3
Buffered clock output
6
VDD
3.3 V supply
7
CLK42
Buffered clock output
8
CLKOUT2
Buffered clock output, internal feedback on this pin3
2
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-ups on these inputs.
TIMING SOLUTIONS
2
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Freescale Semiconductor, Inc.
MPC962305 MPC962309
Table 3. Select Input Decoding for MPC962309
S2
S1
CLOCK A1–A4
CLOCK B1–B4
CLKOUT1
Output Source
PLL Shutdown
0
0
Three-State
Three-State
Driven
PLL
N
0
1
Driven
Three-State
Driven
PLL
N
1
0
Driven
Driven
Driven
Reference
Y
1
1
Driven
Driven
Driven
PLL
N
1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference
and output.
Table 4. Maximum Ratings
Characteristics
Freescale Semiconductor, Inc...
Supply Voltage to Ground Potential
DC Input Voltage (Except Ref)
Value
Unit
−0.5 to +3.9
V
−0.5 to VDD+0.5
V
DC Input Voltage REF
−0.5 to 5.5
V
Storage Temperature
−65 to +150
°C
Junction Temperature
150
°C
>2000
V
Static Discharge Voltage (per MIL-STD-883, Method 3015)
Table 5. Operating Conditions for MPC962305-X and MPC962309-X Industrial Temperature Devices
Parameter
Min
Max
Unit
Supply Voltage
3.0
3.6
V
TA
Operating Temperature (Ambient Temperature)
−40
85
°C
CL
Load Capacitance, below 100 MHz
30
pF
CL
Load Capacitance, from 100 MHz to 133 MHz
10
pF
CIN
Input Capacitance
7
pF
VDD
Description
Table 6. Electrical Characteristics for MPC962305-X and MPC962309-X Industrial Temperature Devices1
Parameter
Description
Test Conditions
Min
Max
Unit
0.8
V
VIL
Input LOW Voltage2
VIH
Input HIGH Voltage2
IIL
Input LOW Current
VIN = 0 V
50.0
µA
IIH
Input HIGH Current
VIN = VDD
100.0
µA
VOL
Output LOW Voltage3
IOL = 8 mA (−1)
IOH = 12 mA (−1H)
0.4
V
VOH
Output HIGH Voltage3
IOH = −8 mA (−1)
IOL = −12 mA (−1H)
Power Down Supply Current
REF = 0 MHz
25.0
µA
Supply Current
Unloaded outputs at 66.67 MHz,
SEL inputs at VDD
35.0
mA
IDD (PD mode)
IDD
2.0
V
2.4
V
1. All parameters are specified with loaded outputs.
2. REF input has a threshold voltage of VPP/2.
3. Parameter is guaranteed by design and characterization. Not 100% tested in production.
MOTOROLA
3
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TIMING SOLUTIONS
Freescale Semiconductor, Inc.
MPC962305 MPC962309
Table 7. Switching Characteristics for MPC962305-1 and MPC962309-1 Industrial Temperature Devices1
Parameter
Test Conditions
Min
Typ
Unit
100
133.33
MHz
MHz
60.0
%
30-pF load
10-pF load
Duty Cycle2 = t2 ÷ t1
Measured at 1.4 V, FOUT = 66.67 MHz
t3
Rise Time2
Measured between 0.8 V and 2.0 V
2.50
ns
t4
Fall Time2
Measured between 0.8 V and 2.0 V
2.50
ns
t5
Output to Output Skew2
All outputs equally loaded
250
ps
t6A
Delay, REF Rising Edge to
Measured at VDD/2
0
±350
ps
t6B
Delay, REF Rising Edge to
5
8.7
ns
0
700
ps
CLKOUT Rising Edge2
CLKOUT Rising Edge2
10
10
Max
Output Frequency
t1
Freescale Semiconductor, Inc...
Name
40.0
Measured at VDD/2. Measured in PLL Bypass Mode,
50.0
1
MPC962309 device only
t7
Device to Device Skew
tJ
Cycle to Cycle Jitter2
Measured at 66.67 MHz, loaded outputs
200
ps
PLL Lock Time2
Stable power supply, valid clock presented on REF pin
1.0
ms
tLOCK
2
Measured at VDD/2 on the CLKOUT pins of devices
1. All parameters are specified with loaded outputs.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Table 8. Switching Characteristics for MPC962305-1H and MPC962309-1H Industrial Temperature Devices1
Parameter
Name
Test Conditions
Min
Typ
Unit
100
133.33
MHz
MHz
Output Frequency
30-pF load
10-pF load
Duty Cycle2 = t2 ÷ t1
Measured at 1.4 V, FOUT = 66.67 MHz
40.0
50.0
60.0
%
Duty Cycle2 = t2 ÷ t1
Measured at 1.4 V, FOUT < 50 MHz
45.0
55.0
55.0
%
t3
Rise Time2
Measured between 0.8 V and 2.0 V
1.50
ns
t4
Fall Time2
Measured between 0.8 V and 2.0 V
1.50
ns
t5
Output to Output Skew2
All outputs equally loaded
250
ps
t6A
Delay, REF Rising Edge to Measured at V /2
DD
CLKOUT Rising Edge2
0
±350
ps
t6B
Delay, REF Rising Edge to Measured at VDD/2. Measured in PLL Bypass Mode,
5
8.7
ns
0
700
ps
t1
10
10
Max
1
CLKOUT Rising Edge2
MPC962309 device only
t7
Device to Device Skew2
Measured at VDD/2 on the CLKOUT pins of devices
t8
Output Slew Rate2
Measured between 0.8 V and 2.0 V using Test Circuit #2
tJ
Cycle to Cycle Jitter2
Measured at 66.67 MHz, loaded outputs
200
ps
PLL Lock Time2
Stable power supply, valid clock presented on REF pin
1.0
ms
tLOCK
1
V/ns
1. All parameters are specified with loaded outputs.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
TIMING SOLUTIONS
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Freescale Semiconductor, Inc.
MPC962305 MPC962309
APPLICATIONS INFORMATION
VCC
1.4 V
GND
VCC
VCC ÷ 2
CCLK
GND
VCC
VCC
VCC ÷ 2
1.4 V
GND
FB_IN
GND
t5
t6
The pin-to-pin skew is defined as the worst case difference in propagation
delay between any similar delay path within a single device
Freescale Semiconductor, Inc...
Figure 1. Output-to-Output Skew tSK(O)
Figure 2. Static Phase Offset Test Reference
VCC
1.4 V
GND
VCC
VCC ÷ 2
DEVICE 1
GND
t2
t1
VCC
VCC ÷ 2
DEVICE 2
DC = t2/t1 x 100%
GND
t7
The time from the PLL controlled edge to the non-controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
Figure 4. Device-to-Device Skew
Figure 3. Output Duty Cycle (DC)
VCC = 3.3 V
2.0
tN
tN+1
0.8
tJ = |tN–tN+1|
t4
t3
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs
Figure 5. Cycle-to-Cycle Jitter
MOTOROLA
Figure 6. Output Transition Time Test Reference
5
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TIMING SOLUTIONS
Freescale Semiconductor, Inc.
MPC962305 MPC962309
Test Circuit #1
Test Circuit #2
VDD
0.1 µF
VDD
OUTPUTS
CLKOUT
0.1 µF
1KΩ
OUTPUTS
1KΩ
CLOAD
VDD
0.1 µF
GND
10 pF
VDD
GND
Test Circuit for all parameters except t8
Freescale Semiconductor, Inc...
CLKOUT
0.1 µF
GND
GND
Test Circuit for t8, Output slew rate on –1H, –5 device
Table 9. Ordering Information
Ordering Code
Package Type
MPC962305D-1
8-pin 150-mil SOIC
MPC962305D-1R2
8-pin 150-mil SOIC-Tape and Reel
MPC962305D-1H
8-pin 150-mil SOIC
MPC962305D-1HR2
8-pin 150-mil SOIC-Tape and Reel
MPC962305DT-1H
8-pin 150-mil TSSOP
MPC962305DT-1HR2
8-pin 150-mil TSSOP-Tape and Reel
MPC962309D-1
16-pin 150-mil SOIC
MPC962309D-1R2
16-pin 150-mil SOIC-Tape and Reel
MPC962309D-1H
16-pin 150-mil SOIC
MPC962309D-1HR2
16-pin 150-mil SOIC-Tape and Reel
MPC962309DT-1H
16-pin 4.4-mm TSSOP
MPC962309DT-1HR2
16-pin 4.4-mm TSSOP-Tape and Reel
TIMING SOLUTIONS
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MOTOROLA
Freescale Semiconductor, Inc.
MPC962305 MPC962309
PACKAGE DIMENSIONS
D SUFFIX
8-LEAD SOIC PACKAGE
CASE 751-06
ISSUE T
D
A
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETER.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
C
5
0.25
H
E
M
B
M
1
4
h
Freescale Semiconductor, Inc...
B
X 45˚
e
θ
DIM
A
A1
B
C
D
E
e
H
h
L
q
A
C
SEATING
PLANE
L
0.10
A1
B
0.25
STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
PIN'S
NUMBER
EMITTER
COLLECTOR
COLLECTOR
EMITTER
EMITTER
BASE
BASE
EMITTER
C B
M
0.25
8X
M
6.2
5.8
S
B
A
S
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
COLLECTOR, DIE, #1
COLLECTOR, #1
COLLECTOR, #2
COLLECTOR, #2
BASE, #2
EMITTER, #2
BASE, #1
EMITTER,
A #1
STYLE 6:
16
PIN 1.
2.
3.
4.
5.
6.
7.
8.
STYLE 5:
1
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
PIN 1 INDEX
5. GATE
6. GATE
7. SOURCE
8. SOURCE
SOURCE
DRAIN
DRAIN
SOURCE
SOURCE
GATE
GATE
SOURCE
4
STYLE 9:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
A
EMITTER, COMMON
COLLECTOR, DIE #1
COLLECTOR, DIE #2
EMITTER, COMMON
EMITTER, COMMON
8 DIE #2
BASE,
BASE, DIE #1
EMITTER, COMMON
4.0
3.8
STYLE 13:
PIN 1.
2.
3.
4.
5.
0.50
6.
7.
0.25
8.
N.C.
SOURCE
SOURCE
GATE
DRAIN
DRAIN
X45˚
DRAIN
DRAIN
5
STYLEA
10:
PIN 1.
2.
3.
4.
5.
9
6.
7.
8.
10.0
9.8
D SUFFIX
STYLE 3:SOIC PACKAGE
16-LEAD
PIN 1. DRAIN, DIE #1
CASE
751B-05
2. DRAIN,
#1
3. DRAIN,K
#2
ISSUE
4. DRAIN, #2
5.
6.
7.
8.
1.75
1.35
GROUND
BIAS 1
OUTPUT
GROUND
GROUND
BIAS 2
INPUT
GROUND
STYLE 11:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
N-SOURCE
N-GATE
P-SOURCE
P-GATE
P-DRAIN
P-DRAIN
N-DRAIN
N-DRAIN
STYLE 15:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
B
STYLE 14:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
STYLE 4:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
GATE, #2
SOURCE, #2
GATE, #1
SOURCE,
0.25 #1
0.10
STYLE 7:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
16X
0.49
0.35
0.25
INPUT
EXTERNAL BYPASS
THIRD STAGE SOURCE
14X
GROUND
DRAIN 1.27
GATE 3
SECOND STAGE Vd
FIRST STAGE Vd
SOURCE 1
GATE 1
SOURCE 2
GATE 2
DRAIN 2
DRAIN 2
DRAIN 1 SEATING
T 1 PLANE
DRAIN
16X
0.1 T
ANODE 1
ANODE 1
ANODE 1
ANODE 1
CATHODE, COMMON
CATHODE, COMMON
CATHODE, COMMON
CATHODE, 0.25
COMMON
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.35
0.49
0.19
0.25
4.80
5.00
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0˚
7˚
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
COMMON CATHODE
6
M
STYLE 8:
T PIN
A 1.B COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7.NOTES:
EMITTER, #1
8. 1.COLLECTOR,
#1 ARE IN MILLIMETERS.
DIMENSIONS
2. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
3. DATUMS A AND B TO BE DETERMINED AT THE
STYLE 12: PLANE WHERE THE BOTTOM OF THE LEADS
PIN 1. SOURCE
EXIT THE PLASTIC BODY.
2.4.SOURCE
THIS DIMENSION DOES NOT INCLUDE MOLD
3. SOURCE
FLASH, PROTRUSION OR GATE BURRS. MOLD
4. GATE
FLASH, PROTRUSION OR GATE BURRS SHALL
5. DRAIN
NOT EXCEED 0.15MM PER SIDE. THIS
6. DRAIN
DIMENSION IS DETERMINED AT THE PLANE
7. DRAIN
WHERE THE BOTTOM OF THE LEADS EXIT
8. DRAIN
THE PLASTIC BODY.
5. THIS DIMENSION DOES NOT INCLUDE
INTER-LEAD FLASH OR PROTRUSIONS.
INTER-LEAD FLASH AND PROTRUSIONS
STYLE 16: SHALL NOT EXCEED 0.25MM PER SIDE. THIS
PIN 1. EMITTER,
DIE #1
DIMENSION
IS DETERMINED AT THE PLANE
2. BASE,
DIETHE
#1 BOTTOM OF THE LEADS EXIT
WHERE
3. EMITTER,
DIE #2BODY.
THE PLASTIC
4.6.BASE,
#2
THIS DIE
DIMENSION
DOES NOT INCLUDE
5. COLLECTOR,
DIE #2
DAMBAR PROTRUSION.
ALLOWABLE
6. COLLECTOR,
DIE #2
DAMBAR PROTRUSION
SHALL NOT CAUSE
7. COLLECTOR,
DIE #1TO EXCEED 0.62MM.
THE LEAD WIDTH
8. COLLECTOR, DIE #1
0.19
STYLE 17:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
VCC
V2OUT
V1OUT
TXE
RXE
VEE
GND
ACC
MOTOROLA
STYLE 18:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
ANODE
ANODE
SOURCE
GATE
DRAIN
DRAIN
CATHODE
CATHODE
1.25
0.40
SECTION A-A
7˚
0˚
7
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TIMING SOLUTIONS
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MPC962305 MPC962309
PACKAGE DIMENSIONS
DT SUFFIX
8-LEAD TSSOP PACKAGE
CASE 948J-01
ISSUE O
K
0.15 (0.006) T U
8x
REF
0.10 (0.004)
S
M
T U
S
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH
OR PROTRUSION SHALL NOT EXCEED 0.25
(0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
S
K
2X L/2
K1
8
5
Freescale Semiconductor, Inc...
J J1
B
-U-
L
PIN 1
IDENT.
SECTION N-N
4
1
N
0.25 (0.010)
0.15 (0.006) T U
S
A
-V-
M
N
F
DETAIL E
-W-
C
0.10 (0.004)
-T-
SEATING
PLANE
D
G
SEE DETAIL E
H
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
2.90
3.10
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0˚ _
8˚_
INCHES
MIN
MAX
0.114
0.122
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.020
0.024
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0˚ _
8˚_
CASE 948J-01
ISSUE O
DATE 08/21/95
TIMING SOLUTIONS
8
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MOTOROLA
Freescale Semiconductor, Inc.
MPC962305 MPC962309
PACKAGE DIMENSIONS
DT SUFFIX
16-LEAD TSSOP PACKAGE
CASE 948F-01
ISSUE O
K
16X
REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH
OR PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
K
K1
Freescale Semiconductor, Inc...
2X
L/2
16
9
J1
B
-U-
L
SECTION N-N
J
PIN 1
IDENT.
8
1
N
0.25 (0.010)
0.15 (0.006) T U
S
A
-V-
M
N
F
DETAIL E
-W-
C
0.10 (0.004)
-T-
SEATING
PLANE
H
D
DETAIL E
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0˚
8˚
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.007
0.011
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0˚
8˚
G
CASE 948F-01
ISSUE O
MOTOROLA
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
9
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On This Product,
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DATE 12/20/
TIMING SOLUTIONS
Freescale Semiconductor, Inc.
MPC962305 MPC962309
Freescale Semiconductor, Inc...
NOTES
TIMING SOLUTIONS
10
For More Information
On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
MPC962305 MPC962309
Freescale Semiconductor, Inc...
NOTES
MOTOROLA
11
For More Information
On This Product,
Go to: www.freescale.com
TIMING SOLUTIONS
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
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