Dallas DS1553 64kb, nonvolatile, year-2000-compliant timekeeping ram Datasheet

DS1553
64kB, Nonvolatile, Year-2000-Compliant
Timekeeping RAM
www.maxim-ic.com
GENERAL DESCRIPTION
FEATURES
The DS1553 is a full-function, year-2000-compliant
(Y2KC) real-time clock/calendar (RTC) with an RTC
alarm, watchdog timer, power-on reset, battery
monitor, and 8k x 8 nonvolatile static RAM. User
access to all registers within the DS1553 is
accomplished with a bytewide interface as shown in
Figure 1. The RTC registers contain century, year,
month, date, day, hours, minutes, and seconds data in
24-hour BCD format. Corrections for day of month and
leap year are made automatically.
§
ORDERING INFORMATION
PART
PIN-PACKAGE
DS1553-100
DS1553-70
DS1553P-100
DS1553P-70
DS1553W-120
DS1553W-150
DS1553WP-120
DS1553WP-150
DS9034PCX*
VCC (V)
28 EDIP
28 EDIP
34 PowerCap®
34 PowerCap
28 EDIP
28 EDIP
34 PowerCap
34 PowerCap
—
5.0
5.0
5.0
5.0
3.3
3.3
3.3
3.3
—
§
§
Totally Nonvolatile with Over 10 Years of
Operation in the Absence of Power
§
Precision Power-On Reset
§
Programmable Watchdog Timer and RTC Alarm
§
BCD-Coded Year, Month, Date, Day, Hours,
Minutes, and Seconds with Automatic Leap Year
Compensation Valid Up to the Year 2100
§
Battery Voltage Level Indicator Flag
§
Power-Fail Write Protection Allows for ±10% VCC
Power-Supply Tolerance
§
Lithium Energy Source is Electrically
Disconnected to Retain Freshness Until Power is
Applied for the First Time
TOP MARK
DS1553-100
DS1553-070
DS1553P-100
DS1553P-70
DS1553W-120
DS1553W-150
DS1553WP-120
DS1553WP-150
DS9034PCX
Integrated NV SRAM, RTC, Crystal, Power-Fail
Control Circuit, and Lithium Energy Source
Clock Registers are Accessed Identically to the
Static RAM; These Registers are Resident in the 16
Top RAM Locations
*PowerCap required, must be ordered separately.
PIN CONFIGURATIONS
TOP VIEW
RST
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
28
2
27
DS1553
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
VCC
WE
IRQ/FT
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
28-Pin Encapsulated Package
(700-mil Extended)
IRQ/FT
N.C.
N.C.
RST
VCC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
DS1553
X1
GND VBAT
X2
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
N.C.
N.C.
N.C.
N.C.
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
34-Pin PowerCap Module Board
(Uses DS9034PCX PowerCap)
PowerCap is a registered trademark of Dallas Semiconductor.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 022304
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
PIN DESCRIPTION
A0–A12
DQ0–DQ7
IRQ /FT
- Address Input
- Data Input/Outputs
- Interrupt, Frequency Test Output
(Open Drain)
RST
- Power-On Reset Output (Open Drain)
- Chip Enable
- Output Enable
- Write Enable
- Power-Supply Input
- Ground
- No Connection
CE
OE
WE
VCC
GND
N.C.
DETAILED DESCRIPTION
The RTC registers in the DS1553 are double-buffered into an internal and external set. The user has direct
access to the external set. Clock/calendar updates to the external set of registers can be disabled and
enabled to allow the user to access static data. Assuming the internal oscillator is turned on, the internal
set of registers is continuously updated. This occurs regardless of external registers settings to guarantee
that accurate RTC information is always maintained.
The DS1553 has interrupt ( IRQ /FT) and reset ( RST ) outputs that can be used to control CPU activity.
The IRQ /FT interrupt output can be used to generate an external interrupt when the RTC register values
match user-programmed alarm values. The interrupt is always available while the device is powered from
the system supply, and it can be programmed to occur when in the battery-backed state to serve as a
system wakeup. Either the IRQ /FT or RST outputs can also be used as a CPU watchdog timer. CPU
activity is monitored and an interrupt or reset output is activated if the correct activity is not detected
within programmed limits. The DS1553 power-on reset can be used to detect a system power-down or
failure and can hold the CPU in a safe reset state until normal power returns and stabilizes. The RST
output is used for this function.
The DS1553 also contains its own power-fail circuitry, which automatically deselects the device when the
VCC supply enters an out-of-tolerance condition. This feature provides a high degree of data security
during unpredictable system operation brought on by low VCC levels.
PACKAGES
The DS1553 is available in a 28-pin DIP and a 34-pin PowerCap module. The 28-pin DIP module
integrates the crystal, lithium energy source, and silicon in one package. The 34-pin PowerCap module
board is designed with contacts for connection to a separate PowerCap (DS9034PCX) that contains the
crystal and battery. This design allows the PowerCap to be mounted on top of the DS1553P after
completion of the surface-mount process. Mounting the PowerCap after the surface-mount process
prevents damage to the crystal and battery due to the high temperatures required for solder reflow. The
PowerCap is keyed to prevent reverse insertion. The PowerCap module board and PowerCap are ordered
separately and shipped in separate containers. The part number for the PowerCap is DS9034PCX.
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DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
Figure 1. Block Diagram
Table 1. Operating Modes
CE
OE
WE
DQ0–DQ7
MODE
POWER
VIH
X
X
High-Z
Deselect
Standby
VIL
X
VIL
DIN
Write
Active
VIL
VIL
VIH
DOUT
Read
Active
VIL
VIH
VIH
High-Z
Read
Active
VSO < VCC <VPF
X
X
X
High-Z
Deselect
CMOS Standby
<VBAT
X
X
X
High-Z
Data Retention
Battery Current
VCC
VCC > VPF
DATA READ MODE
The DS1553 is in read mode whenever CE (chip enable) is low and WE (write enable) is high. The
device architecture allows ripple-through access to any valid address location. Valid data is available at
the data input/output (DQ) pins within tAA after the last address input is stable, provided that CE and OE
access times are satisfied. If CE or OE access times are not met, valid data is available at the latter of
chip-enable access (tCEA) or at output-enable access time (tOEA). The state of the DQ pins is controlled by
CE and OE . If the outputs are activated before tAA, the data lines are driven to an intermediate state until
tAA. If the address inputs are changed while CE and OE remain valid, output data remains valid for
output data hold time (tOH) but will then go indeterminate until the next address access.
DATA WRITE MODE
The DS1553 is in write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout
the cycle. CE and WE must return inactive for a minimum of tWR prior to the initiation of a subsequent
read or write cycle. Data in must be valid tDS prior to the end of the write and remain valid for tDH
afterward. In a typical application, the OE signal is high during a write cycle. However, OE can be active
provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE
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DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
transitioning low, the data bus can become active with read data defined by the address inputs. A low
transition on WE will then disable the outputs tWEZ after WE goes active.
DATA RETENTION MODE
The 5V device is fully accessible, and data can be written and read only when VCC is greater than VPF.
However, when VCC is below the power-fail point (VPF)—the point at which write protection occurs—the
internal clock registers and SRAM are blocked from any access. When VCC falls below the battery switch
point VSO (battery supply level), device power is switched from the VCC pin to the internal backup lithium
battery. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal
levels.
The 3.3V device is fully accessible and data can be written and read only when VCC is greater than VPF.
When VCC falls below VPF, access to the device is inhibited. If VPF is less than VSO, the device power is
switched from VCC to the internal backup lithium battery when VCC drops below VPF. If VPF is greater
than VSO, the device power is switched from VCC to the internal backup lithium battery when VCC drops
below VSO. RTC operation and SRAM data are maintained from the battery until VCC is returned to
nominal levels.
All control, data, and address signals must be powered down when VCC is powered down.
BATTERY LONGEVITY
The DS1553 has a lithium power source that is designed to provide energy for the clock activity and
clock and RAM data retention when the VCC supply is not present. The capability of this internal power
supply is sufficient to power the DS1553 continuously for the life of the equipment in which it is
installed. For specification purposes, the life expectancy is 10 years at +25°C with the internal clock
oscillator running in the absence of VCC. Each DS1553 is shipped from Dallas Semiconductor with its
lithium energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a
level greater than VPF, the lithium energy source is enabled for battery backup operation.
INTERNAL BATTERY MONITOR
The DS1553 constantly monitors the battery voltage of the internal battery. The Battery Low Flag (BLF)
bit of the Flags register (B4 of 1FF0h) is not writeable and should always be 0 when read. If a 1 is ever
present, an exhausted lithium energy source is indicated, and both the contents of the RTC and RAM are
questionable.
POWER-ON RESET
A temperature-compensated comparator circuit monitors the VCC level. When VCC falls to the power-fail
trip point, the RST signal (open drain) is pulled low. When VCC returns to nominal levels, the RST signal
continues to be pulled low for 40ms to 200ms. The power-on reset function is independent of the RTC
oscillator and is therefore operational whether or not the oscillator is enabled.
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DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
CLOCK OPERATIONS
Table 2 and the following paragraphs describe the operation of RTC, alarm, and watchdog functions.
Table 2. Register Map
ADDRESS
DATA
B7
B6
1FFFh
B5
B4
B3
B2
10 Year
X
10 M
B1
B0
FUNCTION/RANGE
Year
Year
00-99
Month
Month
01-12
Date
Date
01-31
Day
01-07
Hour
Hour
00-23
1FFEh
X
X
1FFDh
X
X
1FFCh
X
FT
1FFBh
X
X
1FFAh
X
10 Minutes
Minutes
Minutes
00-59
1FF9h
OSC
10 Seconds
Seconds
Seconds
00-59
1FF8h
W
R
Century
Control
00-39
1FF7h
WDS
BMB4
BMB3
BMB2
BMB1
BMB0
RB1
RB0
Watchdog
1FF6h
AE
Y
ABE
Y
Y
Y
Y
Y
Interrupts
1FF5h
AM4
Y
10 Date
Date
Alarm Date
01-31
1FF4h
AM3
Y
10 Hours
Hours
Alarm Hours
00-23
1FF3h
AM2
10 Minutes
Minutes
Alarm Minutes
00-59
1FF2h
AM1
10 Seconds
Seconds
Alarm Seconds
00-59
1FF1h
Y
Y
Y
Y
Y
Y
Y
Y
Unused
1FF0h
WF
AF
0
BLF
0
0
0
0
Flags
10 Date
X
X
X
Day
10 Hour
10 Century
X = Unused, Read/Writable Under Write and Read Bit Control
FT = Frequency Test Bit
AE = Alarm Flag Enable
Y = Unused, Read/Writable Without Write and Read Bit Control
OSC = Oscillator Start/Stop Bit
ABE = Alarm in Battery-Backup Mode Enable
W = Write Bit
AM1–AM4 = Alarm Mask Bits
R = Read Bit
WF = Watchdog Flag
WDS = Watchdog Steering Bit
AF = Alarm Flag
BMB0–BMB4 = Watchdog Multiplier Bits
0 = 0 Read Only
RB0–RB1 = Watchdog Resolution Bits
BLF = Battery Low Flag
CLOCK OSCILLATOR CONTROL
The clock oscillator may be stopped at any time. To increase the shelf life of the backup lithium battery
source, the oscillator can be turned off to minimize current drain from the battery. The OSC bit is the
MSB of the Seconds register (B7 of 1FF9h). Setting it to 1 stops the oscillator; setting it to 0 starts the
oscillator. The DS1553 is shipped from Dallas Semiconductor with the clock oscillator turned off, with
the OSC bit set to 1.
READING THE CLOCK
When reading the RTC data, it is recommended to halt updates to the external set of double-buffered RTC
registers. This puts the external registers into a static state, allowing data to be read without register
values changing during the read process. Normal updates to the internal registers continue while in this
state. External updates are halted when a 1 is written into the read bit, B6 of the Control register (1FF8h).
As long as a 1 remains in the Control register read bit, updating is halted. After a halt is issued, the
registers reflect the RTC count (day, date, and time) that was current at the moment the halt command
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DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
was issued. Normal updates to the external set of registers resume within 1 second after the read bit is set
to 0 for a minimum of 500ms. The read bit must be 0 for a minimum of 500ms to ensure the external
registers are updated.
SETTING THE CLOCK
The 8th bit, B7 of the Control register, is the write bit. Setting the write bit to 1, like the read bit, halts
updates to the DS1553 (1FF8h–1FFFh) registers. After setting the write bit to 1, RTC registers can be
loaded with the desired RTC count (day, date, and time) in 24-hour BCD format. Setting the write bit to 0
then transfers the values written to the internal RTC registers and allows normal operation to resume.
CLOCK ACCURACY (DIP MODULE)
The DS1553 is guaranteed to keep time accuracy to within ±1 minute per month at +25°C. The RTC is
calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements and does not require
additional calibration. For this reason, methods of field clock calibration are not available and not
necessary. The electrical environment also affects clock accuracy and caution should be taken to place the
RTC in the lowest level EMI section of the PC board layout. For additional information, refer to
Application Note 58: Crystal Considerations with Dallas Real-Time Clocks on our website at
www.maxim-ic.com/appnoteindex.com.
CLOCK ACCURACY (PowerCap MODULE)
The DS1553 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module typically keeps time accuracy to within ±1.53 minutes per month (35ppm) at +25°C. The
electrical environment affects clock accuracy and caution should be taken to place the RTC in the lowest
level EMI section of the PC board layout. For additional information, refer to Application Note 58:
Crystal Considerations with Dallas Real-Time Clocks on our website at www.maximic.com/appnoteindex.com.
FREQUENCY TEST MODE
The DS1553 frequency test mode uses the open-drain IRQ /FT output. With the oscillator running, the
IRQ /FT output toggles at 512Hz when the FT bit is 1, the Alarm Flag Enable bit (AE) is 0, and the
Watchdog Steering bit (WDS) is 1 or the Watchdog register is reset (Register 1FF7h = 00h). The IRQ /FT
output and the frequency test mode can be used as a measure of the actual frequency of the 32.768kHz
RTC oscillator. The IRQ /FT pin is an open-drain output that requires a pullup resistor for proper
operation. The FT bit is cleared to 0 on power-up.
USING THE CLOCK ALARM
The alarm settings and control for the DS1553 reside within registers 1FF2h–1FF5h. Register 1FF6h
contains two alarm-enable bits: Alarm Enable (AE) and Alarm in Backup Enable (ABE). The AE and
ABE bits must be set as described below for the IRQ /FT output to be activated for a matched alarm
condition.
The alarm can be programmed to activate on a specific day of the month or repeat every day, hour,
minute, or second. It can also be programmed to go off while the DS1553 is in the battery-backed state of
operation to serve as a system wakeup. Alarm mask bits AM1–AM4 control the alarm mode. Table 3
shows the possible settings. Configurations not listed in the table default to the once-per-second mode to
notify the user of an incorrect alarm setting.
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DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
Table 3. Alarm Mask Bits
AM4
AM3
AM2
AM1
1
1
1
1
0
1
1
1
0
0
1
1
0
0
0
1
0
0
0
0
ALARM RATE
Once per second
When seconds match
When minutes and seconds match
When hours, minutes, and seconds match
When date, hours, minutes, and seconds match
When the RTC register values match Alarm register settings, the Alarm Flag bit (AF) is set to 1. If the
Alarm Flag Enable (AE) is also set to 1, the alarm condition activates the IRQ /FT pin. The IRQ /FT signal
is cleared by a read or write to the Flags register (Address 1FF0h) as shown in Figures 2 and 3. When CE
is active, the IRQ /FT signal may be cleared by having the address stable for as short as 15ns and either
OE or WE active, but it is not guaranteed to be cleared unless tRC is fulfilled. The alarm flag is also
cleared by a read or write to the Flags register, but the flag does not change states until the end of the
read/write cycle and the IRQ /FT signal has been cleared.
Figure 2. Clearing IRQ Waveforms
CE ,
0V
Figure 3. Clearing IRQ Waveforms
CE = Ø
The IRQ /FT pin can also be activated in the battery-backed mode. The IRQ /FT goes low if an alarm
occurs and both ABE and AE are set. The ABE and AE bits are cleared during the power-up transition,
however, an alarm generated during power-up sets AF. Therefore, the AF bit can be read after system
power-up to determine if an alarm was generated during the power-up sequence. Figure 4 illustrates alarm
timing during the battery-backup mode and power-up states.
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DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
Figure 4. Backup Mode Alarm Waveforms
USING THE WATCHDOG TIMER
The watchdog timer can be used to detect an out-of-control processor. The user programs the watchdog
timer by setting the desired amount of timeout into the 8-bit Watchdog register (Address 1FF7h). The five
Watchdog register bits BMB4–BMB0 store a binary multiplier and the two lower-order bits
RB1–RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and
11 = 4 seconds. The watchdog timeout value is then determined by the multiplication of the 5-bit
multiplier value with the 2-bit resolution value. (For example: writing 00001110 in the Watchdog register
= 3 x 1 second or 3 seconds.) If the processor does not reset the timer within the specified period, the
Watchdog Flag (WF) is set and a processor interrupt is generated and stays active until either the
Watchdog Flag (WF) is read or the Watchdog register (1FF7) is read or written.
The most significant bit of the Watchdog register is the Watchdog Steering Bit (WDS). When set to 0, the
watchdog activates the IRQ /FT output when the watchdog times out.
When WDS is set to 1, the watchdog outputs a negative pulse on the RST output for 40ms to 200ms. The
Watchdog register (1FF7) and the FT bit are reset to 0 at the end of a watchdog timeout when the WDS
bit is set to 1.
The watchdog timer resets when the processor performs a read or write of the Watchdog register. The
timeout period then starts over. Writing a value of 00h to the Watchdog register disables the watchdog
timer. The watchdog function is automatically disabled upon power-up and the Watchdog register is
cleared. If the watchdog function is set to output to the IRQ /FT output and the frequency test function is
activated, the watchdog function prevails and the frequency test function is denied.
POWER-ON DEFAULT STATES
Upon application of power to the device, the following register bits are set to 0:
WDS = 0, BMB0–BMB4 = 0, RB0–RB1 = 0, AE = 0, and ABE = 0.
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DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground
Storage Temperature Range
Soldering Temperature
-0.3V to +6.0V
-40°C to +85°C
260°C for 10 seconds (DIP Package) (Note 8)
See IPC/JEDEC Standard J-STD-020A for
Surface Mount Devices
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
OPERATING RANGE
Range
Commercial
Temperature
0°C to +70°C
VCC
3.3V ±10% or 5V ±10%
RECOMMENDED DC OPERATING CONDITIONS
(Over the operating range)
PARAMETER
SYMBOL
MIN
VIH
2.2
VIH
2.0
VIL
-0.3
+0.8
1
VIL
-0.3
+0.6
1
Logic 1 Voltage All Inputs
VCC = 5V ±10%
VCC = 3.3V ±10%
Logic 0 Voltage All Inputs
VCC = 5V ±10%
VCC = 3.3V ±10%
TYP
MAX
VCC x
+0.3V
VCC x
+0.3V
UNITS
NOTES
V
1
V
1
DC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V ±10%, over the operating range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Active Supply Current
ICC
15
50
mA
2, 3
TTL Standby Current (CE = VIH)
ICC1
1
3
mA
2, 3
CMOS Standby Current
(CE ³ VCC - 0.2V)
ICC2
1
3
mA
2, 3
Input Leakage Current (Any Input)
IIL
-1
+1
mA
Output Leakage Current (Any Output)
IOL
-1
+1
mA
VOH
2.4
Output Logic 1 Voltage
(IOUT = -1.0mA)
Output Logic 0 Voltage
(IOUT = 2.1mA, DQ0-7 Outputs);
(IOUT = 7.0mA, IRQ/FT and RST
Outputs)
VOL1
VOL2
Write Protection Voltage
VPF
Battery Switchover Voltage
VSO
4.20
VBAT
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V
1
0.4
V
1
0.4
V
1, 5
4.50
V
1
V
1, 4
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.3V ±10%, over the operating range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Active Supply Current
ICC
10
30
mA
2, 3
TTL Standby Current (CE = VIH)
ICC1
0.7
2
mA
2, 3
CMOS Standby Current
(CE ³ VCC - 0.2V)
ICC2
0.7
2
mA
2, 3
Input Leakage Current (Any Input)
IIL
-1
+1
mA
Output Leakage Current (Any Output)
IOL
-1
+1
mA
VOH
2.4
Output Logic 1 Voltage
(IOUT = -1.0mA)
Output Logic 0 Voltage
(IOUT = 2.1mA, DQ0–7 Outputs)
V
1
VOL1
0.4
V
1
(IOUT = 7.0mA, IRQ/FT and RST Outputs)
VOL2
0.4
V
1, 5
Write Protection Voltage
VPF
2.97
V
1
Battery Switchover Voltage
VSO
V
1, 4
2.75
VBAT
or VPF
Figure 5. Read Cycle Timing Diagram
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DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
READ CYCLE, AC CHARACTERISTICS
(VCC = 5.0V ±10%, over the operating range.)
PARAMETER
70ns ACCESS
SYMBOL
MIN
MAX
70
100ns ACCESS
MIN
MAX
100
UNITS
Read Cycle Time
tRC
Address Access Time
tAA
CE to DQ Low-Z
tCEL
CE Access Time
tCEA
70
100
ns
CE Data Off Time
tCEZ
25
35
ns
OE to DQ Low-Z
tOEL
OE Access Time
tOEA
35
55
ns
OE Data Off Time
tOEZ
25
35
ns
Output Hold from Address
tOH
70
5
ns
100
5
5
ns
ns
5
5
NOTES
ns
5
ns
READ CYCLE, AC CHARACTERISTICS
(VCC = 3.3V ±10%, over the operating range.)
PARAMETER
120ns ACCESS
SYMBOL
MIN
MAX
120
150ns ACCESS
MIN
MAX
150
UNITS
Read Cycle Time
tRC
Address Access Time
tAA
CE to DQ Low-Z
tCEL
CE Access Time
tCEA
120
150
ns
CE Data Off Time
tCEZ
40
50
ns
OE to DQ Low-Z
tOEL
OE Access Time
tOEA
100
130
ns
OE Data Off Time
tOEZ
35
35
ns
Output Hold from Address
tOH
120
5
ns
150
5
5
ns
ns
5
5
NOTES
ns
5
ns
WRITE CYCLE, AC CHARACTERISTICS
(VCC = 5.0V ±10%, over the operating range.)
PARAMETER
SYMBOL
70ns ACCESS
MIN
MAX
100ns ACCESS
MIN
MAX
UNITS
Write Cycle Time
tWC
70
100
ns
Address Access Time
tAS
0
0
ns
WE Pulse Width
tWEW
50
70
ns
CE Pulse Width
tCEW
60
75
ns
Data Setup Time
tDS
30
40
ns
Data Hold time
tDH
0
0
ns
Address Hold Time
WE Data Off Time
tAH
tWEZ
5
Write Recovery Time
tWR
5
5
25
11 of 19
35
5
ns
ns
ns
NOTES
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
WRITE CYCLE, AC CHARACTERISTICS
(VCC = 3.3V ±10%, over the operating range.)
PARAMETER
SYMBOL
120ns ACCESS
MIN
MAX
150ns ACCESS
MIN
MAX
UNITS
Write Cycle Time
tWC
120
150
ns
Address Setup Time
tAS
0
0
ns
WE Pulse Width
tWEW
100
130
ns
CE Pulse Width
tCEW
110
140
ns
Data Setup Time
tDS
80
90
ns
Data Hold Time
tDH
0
0
ns
Address Hold Time
tAH
0
0
ns
WE Data Off Time
tWEZ
Write Recovery Time
tWR
40
10
Figure 6. Write Cycle Timing, Write-Enable Controlled
Figure 7. Write Cycle Timing, Chip-Enable Controlled
12 of 19
50
10
ns
ns
NOTES
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
POWER-UP/DOWN CHARACTERISTICS
(VCC = 5.0V ±10%, over the operating range.)
PARAMETER
SYMBOL
MIN
CE or WE at VIH, Before Power-Down
tPD
0
ms
VCC Fall Time: VPF(MAX) to VPF(MIN)
tF
300
ms
VCC Fall Time: VPF(MIN) to VSO
tFB
10
ms
VCC Rise Time: VPF(MIN) to VPF(MAX)
tR
0
ms
VPF to RST High
tREC
40
Expected Data Retention Time
(Oscillator On)
tDR
10
Figure 8. Power-Up/Down Waveform Timing 5V Device
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TYP
MAX
200
UNITS
NOTES
ms
years
6, 7
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
POWER-UP/DOWN CHARACTERISTICS
(VCC = 3.3V ±10%, over the operating range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
CE or WE at VIH, Before Power-Down
tPD
0
ms
VCC Fall Time: VPF(MAX) to VPF(MIN)
tF
300
ms
VCC Rise Time: VPF(MIN) to VPF(MAX)
tR
0
ms
VPF to RST High
tREC
40
Expected Data Retention Time
(Oscillator On)
tDR
10
200
UNITS
NOTES
ms
years
6, 7
MAX
UNITS
NOTES
Figure 9. Power-Up/Down Waveform Timing 3.3V Device
CAPACITANCE
(TA = +25°C)
PARAMETER
SYMBOL
MIN
TYP
Capacitance on All Input Pins
CIN
7
pF
1
Capacitance on IRQ/FT, RST, and
DQ Pins
CIO
10
pF
1
14 of 19
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
AC TEST CONDITIONS
Output Load:
100 pF + 1TTL Gate
Input Pulse Levels: 0.0 to 3.0V
Timing Measurement Reference Levels:
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5ns
NOTES:
1)
2)
3)
4)
5)
6)
7)
Voltage referenced to ground.
Typical values are at +25°C and nominal supplies.
Outputs are open.
Battery switch over occurs at the lower of either the battery voltage or VPF.
The IRQ /FT and RST outputs are open drain.
Data retention time is at +25°C.
Each DS1553 has a built-in switch that disconnects the lithium source until VCC is first applied by the
user. The expected tDR is defined for DIP modules as a cumulative time in the absence of VCC starting
from the time power is first applied by the user.
8) Real Time Clock Modules (DIP) can be successfully processed through conventional wave-soldering
techniques as long as temperature exposure to the lithium energy source contained within does not
exceed +85°C. Post solder cleaning with water-washing techniques is acceptable, provided that
ultrasonic vibration is not used.
In addition, for the PowerCap:
a. Dallas Semiconductor recommends that PowerCap Module bases experience one pass through
solder reflow oriented with the label side up (“live-bug”).
b. Hand soldering and touch-up: Do not touch or apply the soldering iron to leads for more than
3 seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder. To remove
the part, apply flux, heat the lead frame pad until the solder reflow and use a solder wick to
remove solder.
15 of 19
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package
outline information, go to www.maxim-ic.com/DallasPackInfo.)
PKG
16 of 19
28-PIN
DIM
A IN.
MM
B IN.
MM
C IN.
MM
D IN.
MM
E IN.
MM
F IN.
MM
G IN.
MM
H IN.
MM
J IN.
MM
MIN
1.470
37.34
0.675
17.75
0.315
8.51
0.075
1.91
0.015
0.38
0.140
3.56
0.090
2.29
0.590
14.99
0.010
0.25
MAX
1.490
37.85
0.740
18.80
0.335
9.02
0.105
2.67
0.030
0.76
0.180
4.57
0.110
2.79
0.630
16.00
0.018
0.45
K IN.
MM
0.015
0.43
0.025
0.58
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
PACKAGE INFORMATION (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package
outline information, go to www.maxim-ic.com/DallasPackInfo.)
PKG
DIM
A
B
C
D
E
F
G
MIN
0.920
0.980
—
0.052
0.048
0.015
0.025
DS1553P
INCHES
NOM
0.925
0.985
—
0.055
0.050
0.020
0.027
MAX
0.930
0.990
0.080
0.058
0.052
0.025
0.030
NOTE: Dallas Semiconductor recommends that PowerCap
Module bases experience one pass through solder reflow
oriented with the label side up (“live-bug”).
Hand Soldering and Touch-Up: Do not touch or apply the
soldering iron to leads for more than 3 seconds. To solder,
apply flux to the pad, heat the lead frame pad and apply solder.
To remove the part, apply flux, heat the lead frame pad until the
solder reflows and use a solder wick to remove solder.
17 of 19
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
PACKAGE INFORMATION (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package
outline information, go to www.maxim-ic.com/DallasPackInfo.)
PKG
DIM
A
B
C
D
E
F
G
18 of 19
DS1553P WITH
DS9034PCX ATTACHED
INCHES
MIN
NOM
MAX
0.920
0.925
0.930
0.955
0.960
0.965
0.240
0.245
0.250
0.052
0.055
0.058
0.048
0.050
0.052
0.015
0.020
0.025
0.020
0.025
0.030
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM
PACKAGE INFORMATION (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package
outline information, go to www.maxim-ic.com/DallasPackInfo.)
Recommended PowerCap Module Land Pattern
PKG
DIM
A
B
C
D
E
MIN
—
—
—
—
—
INCHES
NOM
1.050
0.826
0.050
0.030
0.112
MAX
—
—
—
—
—
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products · Printed USA
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