ETC2 FAN4822IN Built-in zvs switch control with fast response for high efficiency at high power level Datasheet

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FAN4822
ZVS Average Current PFC Controller
Features
General Description
• Average current sensing, continuous boost, leading edge
PFC for low total harmonic distortion and near unity
power factor
• Built-in ZVS switch control with fast response for high
efficiency at high power levels
• Average line voltage compensation with brownout control
• Current fed gain modulator improves noise immunity and
provides universal input operation
• Overvoltage comparator eliminates output “runaway” due
to load removal
• UVLO, current limit, and soft-start
• Precision 1.3% reference
The FAN4822 is a PFC controller designed specifically for
high power applications. The controller contains all of the
functions necessary to implement an average current boost
PFC converter, along with a Zero Voltage Switch (ZVS) controller to reduce diode recovery and MOSFET turn-on
losses.
The average current boost PFC circuit provides high power
factor (>98%) and low Total Harmonic Distortion (THD).
Built-in safety features include undervoltage lockout, overvoltage protection, peak current limiting, and input voltage
brownout protection.
The ZVS control section drives an external ZVS MOSFET
which, combined with a diode and inductor, soft switches the
boost regulator. This technique reduces diode reverse recovery and MOSFET switching losses to reduce EMI and maximize efficiency.
Block Diagram
VEAO
FB
–
14
2.5V
IAC
4
+
1
8
2
GND
FB
R+
+
GAIN
MODULATOR
+
VCC
OVP
12
VCCZ
13.5V
IEA
2.7V
–
+
–
–
VRMS
5
IEAO
VEA
S
Q
I LIMIT
R–
–1V
ISENSE
+
R
–
3
PFC OUT
11
RTCT
6
OSC
S
Q
R
Q
VCCZ
REF
13
ZV SENSE
7
ZVS OUT
REF
10
+
––
S
Q
R
Q
PWR GND
9
REV. 1.0.1 8/10/01
FAN4822
PRODUCT SPECIFICATION
Pin Configuration
FAN4822
FAN4822
14-Pin DIP (P14)
16-Pin SOIC (S16W)
VEAO
1
14
FB
VEAO
1
16
FB
IEAO
2
13
REF
IEAO
2
15
REF
ISENSE
3
12
VCC
ISENSE
3
14
VCC
IAC
4
11
PFC OUT
IAC
4
13
PFC OUT
VRMS
5
10
ZVS OUT
VRMS
5
12
ZVS OUT
RTCT
6
9
PWR GND
RTCT
6
11
PWR GND
ZV SENSE
7
8
GND
ZV SENSE
7
10
GND
N/C
8
9
N/C
TOP VIEW
TOP VIEW
Pin Description (Pin numbers is parentheses are for 16-pin package)
Pin
Name
Function
1 (1)
VEAO
Transconductance voltage error amplifier output.
2 (2)
IEAO
Transconductance current error amplifier output.
3 (3)
ISENSE
4 (4)
IAC
5 (5)
VRMS
Input for RMS line voltage compensation.
6 (6)
RTCT
Connection for oscillator frequency setting components.
7 (7)
ZV SENSE
8 (10)
GND
9 (11)
PWR GND
Return for the PFC and ZVS driver outputs.
10 (12)
ZVS OUT
ZVS MOSFET driver output.
11 (13)
PFC OUT
12 (14)
VCC
Shunt-regulated supply voltage.
13 (15)
REF
Buffered output for the internal 7.5V reference.
14 (16)
FB
Transconductance voltage error amplifier input.
Current sense input to the PFC current limit comparator.
PFC gain modulator reference input.
Input to the high speed zero voltage crossing comparator.
Analog signal ground.
PFC MOSFET driver output.
Absolute Maximum Ratings
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied.
Parameter
Min
Max
Unit
55
mA
±500
mA
7
V
150
°C
150
°C
Lead Temperature (Soldering, 10 sec)
150
°C
Thermal Resistance (θJA)
Plastic DIP
Plastic SOIC
80
110
°C/W
°C/W
Shunt Regulator Current (ICC)
Peak Driver Output Current
Analog Inputs
–0.3
Junction Temperature
Storage Temperature Range
2
–65
REV. 1.0.1 8/10/01
PRODUCT SPECIFICATION
FAN4822
Operating Conditions
Temperature Range
Min.
Max.
Units
FAN4822IX
–40
85
°C
Electrical Characteristics
Unless otherwise specified, RT = 52.3kΩ, CT = 470pF, TA = Operating Temperature Range (Note 1)
Parameter
Conditions
Min.
Typ.
Max.
Units
7
V
Voltage Error Amplifier
Transconductance
0
50
70
120
µ
Feedback Reference Voltage VEAO = VFB
2.4
2.5
2.6
V
Open Loop Gain
60
75
dB
60
75
dB
PSRR
VNON-INV = VINV, VEAO = 3.75V
Ω
Input Voltage Range
VCCZ – 3V < VCC < VCCZ – 0.5V
Output Low
0.65
Output High
1
V
6.0
6.7
V
Source Current
∆VIN = ±0.5V, VOUT = 6V
–40
–80
µA
Sink Current
∆VIN = ±0.5V, VOUT = 1.5V
40
80
mA
Current Error Amplifier
Transconductance
–1.5
VNON-INV = VINV, IEAO = 3.75V
130
Input Offset Voltage
Open Loop Gain
PSRR
VCCZ – 3V < VCC < VCCZ – 0.5V
2
195
310
µ
±3
±15
mV
60
75
dB
60
75
dB
Output Low
0.65
Output High
V
Ω
Input Voltage Range
1
V
6.0
6.7
V
Source Current
∆VIN = ±0.5V, VOUT = 6V
–30
–80
µA
Sink Current
∆VIN = ±0.5V, VOUT = 1.5V
40
80
µA
Threshold Voltage
2.6
2.7
2.8
V
Hysteresis
80
120
150
mV
–0.8
–1.0
–1.15
V
150
300
ns
50
ns
7.5
7.65
V
OVP Comparator
ISENSE Comparator
Threshold Voltage
Delay to Output
ZV Sense Comparator
Propagation Delay
Threshold Voltage
Input Capacitance
REV. 1.0.1 8/10/01
100mV Overdrive
7.35
6
pF
3
FAN4822
PRODUCT SPECIFICATION
Electrical Characteristics (Continued)
Unless otherwise specified, RT = 52.3kΩ, CT = 470pF, TA = Operating Temperature Range (Note 1)
Parameter
Conditions
Min.
Typ.
Max.
IIAC = 100mA, VVRMS = 0V,
VFB = 0V
0.36
0.51
0.66
IIAC = 50mA, VVRMS = 1.2V,
VFB = 0V
1.20
1.72
2.24
IIAC = 100µA, VVRMS = 1.8V,
VFB = 0V
0.55
0.78
1.01
IIAC = 100µA, VVRMS = 3.3V,
VFB = 0V
0.14
0.20
0.26
Units
Gain Modulator
Gain (Note 2)
Bandwidth
IIAC = 250µA
Output Voltage
VFB = 0V, VVRMS = 1.15V, IIAC =
250µA
10
MHz
0.72
0.8
0.9
V
74
80
87
kHz
Oscillator
Initial Accuracy
TA = 25°C
Voltage Stability
VCCZ – 3V < VCC < VCCZ – 0.5V
Temperature Stability
Total Variation
Line, temperature
1
%
2
%
72
Ramp Valley to Peak Voltage
89
kHz
2.5
V
Dead Time
100
300
450
ns
CT Discharge Current
4.5
7.5
9.5
mA
7.4
7.5
7.6
V
Reference
Output Voltage
TA = 25°C, IREF = 1mA
Line Regulation
VCCZ – 3V < VCC < VCCZ – 0.5V
2
10
mV
Load Regulation
1mA < IREF, < 20mA
2
15
mV
Temperature Stability
0.4
Total Variation
Line, load, and temperature
Long Term Stability
Tj = 125°C, 1000 hours
Short Circuit Current
VCC < VCCZ – 0.5V, VREF = 0V
7.35
–15
%
7.65
V
5
25
mV
–40
–100
mA
0
%
PFC Comparator
Minimum Duty Cycle
VIEAO > 6.7V
Maximum Duty Cycle
VIEAO < 1.2V
90
95
%
MOSFET Driver Outputs
Output Low Voltage
Output High Voltage
Output Rise/Fall Time
IOUT = –20mA
0.4
1.0
V
IOUT = –100mA
1.5
3.5
V
IOUT = –10mA, VCC = 8V
0.8
1.5
V
IOUT = 20mA
9.5
10.3
V
IOUT = 100mA
9
10.3
V
40
ns
CL = 1000pF
Undervoltage Lockout
Threshold Voltage
Hysteresis
4
VCCZ –
0.9
VCCZ –
0.6
VCCZ –
0.2
V
2.4
2.9
3.45
V
REV. 1.0.1 8/10/01
PRODUCT SPECIFICATION
FAN4822
Electrical Characteristics (Continued)
Unless otherwise specified, RT = 52.3kΩ, CT = 470pF, TA = Operating Temperature Range (Note 1)
Parameter
Conditions
Min.
Typ.
Max.
Units
Supply
Shunt Voltage (VCCZ)
ICC =25mA
Load Regulation
25mA < ICC < 55mA
Total Variation
Load and temperature
Start-up Current
VCC < 12.3V
Operating Current
VCC = VCCZ – 0.5V
12.8
13.5
14.2
V
±150
±300
mV
14.6
V
0.7
1.1
mA
22
28
mA
12.4
Notes
1. Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
2. Gain = K x 5.3 V; K = (IGAINMOD – IOFFSET) x IAC x (VEAO – 1.5)–1.
REV. 1.0.1 8/10/01
5
FAN4822
PRODUCT SPECIFICATION
Functional Description
bined parasitic capacitance of D1 and Q1 (or optional ZVS
capacitor CZVS). At t3, the voltage across Q1 is sufficiently
low that the controller turns Q2 off and Q1 on. Q1 then
behaves as an ordinary PFC switch, storing energy in the
boost inductor L1. The energy stored in L2 is completely discharged into the boost capacitor via D2 during the Q1 offtime and the value of L2 must be selected for discontinuousmode operation.
Switching losses of wide input voltage range PFC boost converters increase dramatically as power levels increase above
200 watts. The use of zero-voltage switching (ZVS) techniques improves the efficiency of high power PFCs by significantly reducing the turn-on losses of the boost MOSFET.
ZVS is accomplished by using a second, smaller MOSFET,
together with a storage element (inductor) to convert the
turn-on losses of the boost MOSFET into useful output
power.
Component Selection
Q1 Turn-Off
Because the FAN4822 uses leading edge modulation, the
PFC MOSFET (Q1) is always turned off at the end of each
oscillator ramp cycle. For proper operation, the internal ZVS
flip-flop must be reset every cycle during the oscillator discharge time. This is done by automatically resetting the ZVS
comparator a short time after the drain voltage of the main Q
has reached zero (refer to Figure 1 sense circuit). This sense
circuit terminates the ZVS on time by sensing the main Q
drain voltage reaching zero. It is then reset by way of a resistor pull-up to VCC (R6). The advantage of this circuit is that
the ZVS comparator is not reset at the main Q turn off which
occurs at the end of the clock cycle. This avoids the potential
for improper reset of the internal ZVS flip-flop.
The basic function of the FAN4822 is to provide a power
factor corrected, regulated DC bus voltage using continuous,
average current-mode control. Like Micro Linear’s family of
PFC/PWM controllers, the FAN4822 employs leading-edge
pulse width modulation to reduce system noise and permit
frequency synchronization to a trailing edge PWM stage for
the highest possible DC bus voltage bandwidth. For minimization of switching losses, circuitry has been incorporated to
control the switching of the ZVS FET.
Theory of Operation
Figure 1 shows a simplified schematic of the output and control sections of a high power PFC circuit. Figure 2 shows the
relationship of various waveforms in the circuit. Q1 functions as the main switching FET and Q2 provides the ZVS
action. During each cycle, Q2 turns on before Q1, diverting
the current in L1 away from D1 into L2. The current in L2
increases linearly until at t2 it equals the current through L1.
When these currents are equal, L1 ceases discharging current
and is now charged through L2 and Q2. At time t2, the drain
voltage of Q1 begins to fall. The shape of the voltage waveform is sinusoidal due to the interaction of L2 and the com-
Another concern is the proper operation of the ZVS comparator during discontinuous mode operation (DCM), which
will occur at the cusps of the rectified AC waveform and at
light loads. Due to the nature of the voltage seen at the drain
of the main boost Q during DCM operation, the ZVS comparator can be fooled into forcing the ZVS Q on for the
entire period. By adding a circuit which limits the maximum
on time of the ZVS Q, this problem can be avoided. Q3 in
Figure 1 provides this function.
L1
D1
+
C1
VREF
13 VREF
L2
FAN4822
CZVS(OPT)
12 VCC
D2
Q1
R3
22k
R5
220
R6
22k
PFC OUT 11
C4
330pF
C2
Q2
7
ZV SENSE
8
GND
C3
33pF
R4
51k
R1
ZVS OUT 10
PWR GND 9
MAX ZVS
ON TIME LIMIT
R2
Q3
C5
Figure 1. Simplified PFC/ZVS Schematic.
6
REV. 1.0.1 8/10/01
PRODUCT SPECIFICATION
FAN4822
Q1 Turn-On
The turn-on event consists of the time it takes for the current
through L2 to ramp to the L1 current plus the resonant event
of L2 and the ZVS capacitor. The total event should occur in
a minimum of 350–450ns, but can be longer at the risk of
increasing the total harmonic distortion. Setting these times
equal should minimize conducted and radiated emissions.
t Q1 ( OFF ) = t IL2 + t RES = 400ns
A. SYSTEM
CLOCK
(INTERNAL)
(1)
B. RTCT
Where IL2 is equal to IL1.
The value of L2 is calculated to remain in discontinuousmode:
V BUS × V RMS ( MIN ) × t IL2
L2 = ---------------------------------------------------------------2 × P OUT
C. ZVS GATE (Q2)
(2)
The resonant event occurs in 1/4 of a full sinusoidal cycle.
For example, when a 1/4 cycle occurs in 200ns, the frequency is 1.25MHz.
D. VDS (Q2)
1
1
f RES = ----------------------------------- = --------------------×
4
t RES
2π L2 × C
ZVS
(3)
Rearranging and solving for L2:
4 × t RES 2
L2 = -------------------------2
π × C ZVS
E. PFC GATE (Q1)
(4)
The resonant capacitor (CZVS) value is found by setting
equations 2 and 4 equal to each other and solving for CZVS.
4 × t RES 2 × 2 × P OUT
C ZVS = ---------------------------------------------------------------------------2
π × V BUS × V RMS ( MIN ) × t IL2
F. VDS (Q1)
(5)
Application
Figure 3 displays a typical application circuit for a 500W
ZVS PFC supply. Full design details are covered in application note 33, FAN4822 Power Factor Correction With Zero
Voltage Resonant Switching.
G. IL2
t1
t3
t2
Figure 2. Timing Diagrams
REV. 1.0.1 8/10/01
7
8
R25
51kΩ
R24
22kΩ
NEUTRAL
C19
330pF
50V
R16
8.25kΩ
1%
R27
220
D10
UF4005
C14
0.47µF
250VAC
LINE 8AMP
250VAC
F1
C20
2.2nF
50V
GBU6G
D13
1N5401
R26
22kΩ
C13
100pF
50V
C18
33pF
50V
R15
16.2kΩ
1%
R23
402kΩ
1%
R13
402kΩ
1%
R19
10kΩ
C11
68nF
50V
C12
2.2nF
50V
D7
1N5401
R18
0.0732 5W 1%
B1
C6
0.47µF
16V
ISENSE
IEAO
C22
100pF
ZVS OUT
PFC OUT
VCC
REF
FB
R4
10kΩ
1N4148
R29
10kΩ
GND
PWR GND
ZV SENSE
RTCT
VRMS
IAC
C4
0.1µF
50V
FAN4822
VEAO
Q3
2N7000
7
6
5
4
3
2
1
R17
220kΩ
C7
0.68µF 50V
R14
100kΩ 1%
R22
453kΩ 1%
R12
453kΩ 1%
8
9
10
11
12
13
14
D5
1N4747A
Q1
FQA24N50
L1
420uH @ 10A
n = 57
C5
1µF
50V
D8
1N5819
D9
1N5819
C8
2.2µF
50V
C2
470pF
1600V
D6
1N4747A
R3
10
L2
8.5m @ 14A
FESI6JT
D1
4
3
2
1
R1
3.3kΩ
3W
IN B
NC
OUT B
VS
OUT A
VS RTN
IN A
NC
TC4427
R6
10kΩ
Q2
FQP6N50
D3
MUR460
R7
47
C9
1µF
50V
C15
1500µF
25V
5
6
7
8
C1
330µF
450V
D4
UF4005
C21
0.1µF
200V
MUR860
D2
C17
1µF
50V
C3
1000pF
50V
400VDC
C10
1µF
50V
D12
EGP20A
D11
EGP20A
R21
39kΩ
2W
400VDC RTN
R11
2.37kΩ
1%
R2
10Ω
C16
1µF
50V
+
R20
93.1kΩ 1%
R9
93.1kΩ 1%
R8
93.1kΩ 1%
R10
102kΩ 1%
L1
n = 2.5
R5
39kΩ
2W
FAN4822
PRODUCT SPECIFICATION
Figure 3. FAN4822 Schematic.
REV. 1.0.1 8/10/01
PRODUCT SPECIFICATION
FAN4822
Mechanical Dimensions inches (millimeters)
Package: P14
14-Pin PDIP
0.740 - 0.760
(18.79 - 19.31)
14
0.240 - 0.260 0.295 - 0.325
(6.09 - 6.61) (7.49 - 8.25)
PIN 1 ID
0.070 MIN
(1.77 MIN)
(4 PLACES)
1
0.050 - 0.065 0.100 BSC
(1.27 - 1.65) (2.54 BSC)
0.015 MIN
(0.38 MIN)
0.170 MAX
(4.32 MAX)
0.016 - 0.022 SEATING PLANE
(0.40 - 0.56)
0.125 MIN
(3.18 MIN)
0º - 15º
0.008 - 0.012
(0.20 - 0.31)
Package: S16W
16-Pin Wide SOIC
0.400 - 0.414
(10.16 - 10.52)
16
0.291 - 0.301 0.398 - 0.412
(7.39 - 7.65) (10.11 - 10.47)
PIN 1 ID
1
0.024 - 0.034
(0.61 - 0.86)
(4 PLACES)
0.050 BSC
(1.27 BSC)
0.095 - 0.107
(2.41 - 2.72)
0º - 8º
0.090 - 0.094
(2.28 - 2.39)
REV. 1.0.1 8/10/01
0.012 - 0.020
(0.30 - 0.51)
SEATING PLANE 0.005 - 0.013
(0.13 - 0.33)
0.022 - 0.042
(0.56 - 1.07)
0.009 - 0.013
(0.22 - 0.33)
9
FAN4822
PRODUCT SPECIFICATION
Ordering Information
Part Number
FAN4822IN
FAN4822IM
PFC/PWM Frequency
Package
-40°C to 85°C
-40°C to 85°C
14-Pin PDIP (P14)
16-Pin Wide SOIC (S16W)
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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2001 Fairchild Semiconductor Corporation
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