Maxim MAX5941BESE Ieee 802.3af-compliant power-over-ethernet interface/pwm controller for power device Datasheet

19-3069; Rev 0; 10/03
IEEE 802.3af-Compliant Power-Over-Ethernet
Interface/PWM Controller for Power Devices
Applications
Features
♦ Powered Device Interface
Fully Integrated IEEE 802.3af-Compliant PD
Interface
PD Detection and Programmable Classification
Signatures
Less than 10µA Leakage Current Offset During
Detection
Integrated MOSFET for Isolation and Inrush
Current Limiting
Gate Output Allows External Control of the
Internal Isolation FET
Programmable Inrush Current Control
Programmable Undervoltage Lockout
♦ PWM Controller
Wide Input Range: 18V to 67V
Current-Mode Control
Leading-Edge Blanking
Internally Trimmed 275kHz ±10% Oscillator
Soft-Start
Ordering Information
PART
TEMP RANGE
PINPACKAGE
MAX DUTY
CYCLE (%)
MAX5941AESE
-40°C to +85°C
16 SO
85
MAX5941ACSE
0°C to +70°C
16 SO
85
MAX5941BESE
-40°C to +85°C
16 SO
50
MAX5941BCSE
0°C to +70°C
16 SO
50
IP Phones
Wireless Access Nodes
Pin Configuration
Internet Appliances
Computer Telephony
Security Cameras
Power Devices in Power-Over-Ethernet/
Power-Over-MDI
TOP VIEW
V+ 1
15 NDRV
14 V-
OPTO 3
SS_SHDN 4
ULVO 5
Typical Operating Circuit appears at end of data sheet.
16 VCC
VDD 2
MAX5941A
MAX5941B
13 CS
12 GND
RCL 6
11 PGOOD
GATE 7
10 PGOOD
VEE 8
9
OUT
SO
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX5941A/MAX5941B
General Description
The MAX5941A/MAX5941B integrate a complete power
IC for powered devices (PD) in a power-over-ethernet
(PoE) system. The MAX5941A/MAX5941B provide a PD
interface and a compact DC-DC PWM controller suitable
for flyback and forward converters in either isolated or
nonisolated designs.
The MAX5941A/MAX5941B PD interface complies with
the IEEE 802.3af standard, providing the PD with a detection signature, a classification signature, and an integrated isolation switch with programmable inrush current
control. These devices also feature power-mode undervoltage lockout (UVLO) with wide hysteresis and powergood status outputs.
The MAX5941A/MAX5941B also integrate all the building
blocks necessary for implementing DC-DC fixedfrequency isolated power supplies. These devices are a
current-mode controller with an integrated high startup
circuit suitable for isolated telecom/industrial voltagerange power supplies. A high-voltage startup circuit
allows the PWM controller to draw power directly from the
18V to 67V input supply during startup. The switching frequency is internally trimmed to 275kHz ±10%, thus
reducing magnetics and filter components. The
MAX5941A allows an 85% operating duty cycle and can
be used to implement flyback converters. The MAX5941B
limits the operating duty cycle to less than 50% and can
be used in single-ended forward converters. The
MAX5941A/MAX5941B are designed to work with or without an external diode bridge in front of the PD.
The MAX5941A/MAX5941B are available in 16-pin SO
packages.
MAX5941A/MAX5941B
IEEE 802.3af-Compliant Power-Over-Ethernet
Interface/PWM Controller for Power Devices
ABSOLUTE MAXIMUM RATINGS
UVLO, PGOOD, PGOOD to VEE .....................................20mA
GATE to VEE ....................................................................80mA
VDD, VCC .........................................................................20mA
NDRV Continuous ...........................................................25mA
NDRV (Pulsed for less than 1µs) .......................................±1A
Continuous Power Dissipation (TA = +70°C)
16-Pin SO (derate 9.1mW/°C above +70°C)................727mW
Operating Temperature Range
MAX5941_CSE ..................................................0°C to +70°C
MAX5941_ESE ...............................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature ......................................................+150°C
Lead Temperature (soldering, 10s) ................................+300°C
(All voltages are referenced to VEE, unless otherwise noted.)
GND........................................................................-0.3V to +80V
OUT, PGOOD ...........................................-0.3V to (GND + 0.3V)
RCL, GATE .............................................................-0.3V to +12V
UVLO ........................................................................-0.3V to +8V
PGOOD to OUT.........................................-0.3V to (GND + 0.3V)
V+ to V-...................................................................-0.3V to +80V
VDD to V-.................................................................-0.3V to +40V
VCC to V-..............................................................-0.3V to +12.5V
OPTO, NDRV, SS_SHDN, CS to V-.............-0.3V to (VCC + 0.3V)
Maximum Input/Output Current (Continuous)
OUT to VEE ...................................................................500mA
GND, RCL to VEE ............................................................70mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = (GND - VEE) = 48V, GATE = PGOOD = PGOOD = OPEN, V- tied to OUT, V+ tied to GND, UVLO = VEE, TA = TMIN to +TMAX,
unless otherwise noted. Typical values are at TA = +25°C. All voltages are referenced to VEE, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
IOFFSET
VIN = 1.4V to 10.1V, GND = V- = OUT = V+
(Note 2)
dR
VIN = 1.4V up to 10.1V with 1V step, OUT =
PGOOD = GND = OUT = V+ (Note 3)
550
VIN rising (Note 4)
20.8
TYP
MAX
UNITS
10
µA
PD INTERFACE
DETECTION MODE
Input Offset Current
Effective Differential Input
Resistance
kΩ
CLASSIFICATION MODE
Classification Current Turn-Off
Threshold
VTH,CLSS
Class 0, RCL = 10kΩ
Classification Current (Notes 5, 6)
ICLASS
21.8
22.5
0
2
Class 1, RCL = 732Ω
VIN = 12.6V
to 20V, RDISC Class 2, RCL = 392Ω
= 25.5kΩ
Class 3, RCL = 255Ω
9.17
11.83
17.29
19.71
26.45
29.55
Class 4, RCL = 178Ω
36.6
41.4
V
mA
POWER MODE
Operating Supply Voltage
VIN
VIN = (GND - VEE)
Operating Supply Current
IIN
Measure at GND, not including RDISC
Default Power Turn-On Voltage
VUVLO, ON
Default Power Turn-Off Voltage
VUVLO, OFF VIN decreasing, UVLO = VEE
Default Power Turn-On/Off
Hysteresis
External UVLO Programming
Range
UVLO External Reference Voltage
2
VIN increasing, UVLO = VEE
VHYST,
UVLO
VIN,EX
Set UVLO externally (Note 7)
VREF, UVLO VUVLO increasing
37.4
67
V
0.4
1
mA
38.6
40.1
V
30
V
7.4
V
12
2.400
2.460
_______________________________________________________________________________________
67
V
2.522
V
IEEE 802.3af-Compliant Power-Over-Ethernet
Interface/PWM Controller for Power Devices
(VIN = (GND - VEE) = 48V, GATE = PGOOD = PGOOD = OPEN, V- tied to OUT, V+ tied to GND, UVLO = VEE, TA = TMIN to +TMAX,
unless otherwise noted. Typical values are at TA = +25°C. All voltages are referenced to VEE, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
20
20.9
%
UVLO External Reference Voltage
Hysteresis
HYST
Ratio to VREF,UVLO
19.2
UVLO Bias Current
IUVLO
UVLO = 2.460V
-1.5
+1.5
µA
50
440
mV
UVLO Input Ground Sense
Threshold
VTH,G,UVLO (Note 8)
UVLO Input Ground Sense Glitch
Rejection
Power Turn-Off Voltage,
Undervoltage Lockout Deglitch
Time
Isolation Switch N-Channel
MOSFET On-Resistance
Isolation Switch N-Channel
MOSFET Off-Threshold Voltage
GATE Pulldown Switch Resistance
GATE Charging Current
GATE High Voltage
PGOOD, PGOOD Assertion VOUT
Threshold
7
UVLO = VEE
tOFF_DLY
RON
VIN, VUVLO falling (Note 9)
Output current =
300mA, VGATE = 5.6V,
measured between
OUT and VEE
0.32
TA = +25°C
(Note 11)
0.6
1.1
TA = +85°C
0.8
1.5
Ω
OUT = GND, VGATE - VEE, output current
< 1µA
RG
Power-off mode, VIN = 12V, UVLO = VEE
IG
VGATE = 2V
5
VGATE
IGATE = 1µA
5.58
VOUT - VEE, |VOUT - VEE| decreasing,
VGATE = 5.75V
1.15
1.23
0.5
VGSEN
PGOOD Output Low Voltage
PGOOD Output Low Voltage
VOLDCDC
V
80
Ω
10
15
µA
5.76
5.93
V
1.31
V
38
Hysteresis
PGOOD, PGOOD Assertion VGATE
Threshold
ms
VGSTH
VOUTEN
µs
70
(GATE - VEE) increasing, OUT = VEE
4.62
Hysteresis
4.76
mV
4.91
80
V
mV
ISINK = 2mA (Note 10)
0.4
V
ISINK = 2mA, OUT ≤ (GND - 5V) (Note 10)
0.2
V
PGOOD Leakage Current
GATE = high, GND - VOUT = 67V (Note 10)
1
µA
PGOOD Leakage Current
GATE = VEE, PGOOD - VEE = 67V (Note 10)
1
µA
ELECTRICAL CHARACTERISTICS (PWM Controller)
(All voltages referenced to V-. VDD = 13V, a 10µF capacitor connects VCC to V-, VCS = V-, V+ = 48V, 0.1µF capacitor connected to
SS_SHDN, NDRV = open circuit, OPTO = V-, TA = TMIN to +TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SUPPLY CURRENT
V+ Supply Current
IV+(NS)
VDD = 0V, V+ = 67V, driver not switching
0.85
1.3
IV+(S)
V+ = 67V, VDD = 0V, VOPTO = 4V, driver
switching
1.4
2.6
V+ Supply Current After Startup
VDD Supply Current
IVDD(NS)
IVDD(S)
V+ = 67V, VDD = 13V, VOPTO = 4V
11
VDD = 36V, driver not switching
0.9
1.3
VDD = 36V, driver switching, VOPTO = 4V
1.9
2.7
mA
µA
mA
_______________________________________________________________________________________
3
MAX5941A/MAX5941B
ELECTRICAL CHARACTERISTICS (continued)
MAX5941A/MAX5941B
IEEE 802.3af-Compliant Power-Over-Ethernet
Interface/PWM Controller for Power Devices
ELECTRICAL CHARACTERISTICS (PWM Controller) (continued)
(All voltages referenced to V-. VDD = 13V, a 10µF capacitor connects VCC to V-, VCS = V-, V+ = 48V, 0.1µF capacitor connected to
SS_SHDN, NDRV = open circuit, OPTO = V-, TA = TMIN to +TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
V+ Shutdown Current
VSS_SHDN = 0V, V+ = 67V
VDD Shutdown Current
VSS_SHDN = 0V
MIN
TYP
MAX
UNITS
190
290
µA
8
20
µA
PREREGULATORS/STARTUP
V+ Input Voltage
18
67
V
VDD Supply Voltage
13
36
V
INTERNAL REGULATORS
VCC Output Voltage
VCC Undervoltage Lockout
VCC_UVLO
Powered from V+, ICC = 7.5mA, VDD = 0V
7.5
9.8
12
Powered from VDD, ICC = 7.5mA
9.0
10.0
11.0
VCC falling
V
6.6
V
OUTPUT DRIVER
Peak Source Current
VCC = 11V (externally forced)
570
mA
Peak Sink Current
VCC = 11V (externally forced)
1000
mA
NDRV High-Side Driver
Resistance
ROH
VCC = 11V, externally forced, NDRV
sourcing 50mA
NDRV Low-Side Driver
Resistance
ROL
VCC = 11V, externally forced, NDRV sinking
50mA
4
12
Ω
1.6
4
Ω
-1.00
+1.00
µA
2
3
PWM COMPARATOR
OPTO Input Bias Current
VOPTO = VSS_SHDN
OPTO Control Range
Slope Compensation
VSCOMP
MAX5941A
26
V
mV/µs
THERMAL SHUTDOWN
Thermal Shutdown Temperature
150
°C
Thermal Hysteresis
25
°C
CURRENT LIMIT
CS Threshold Voltage
VILIM
VOPTO = 4V
419
465
510
mV
+1
µA
CS Input Bias Current
0V ≤ VCS ≤ 2V, VOPTO = 4V
Current-Limit Comparator
Propagation Delay
25mV overdrive on CS, VOPTO = 4V
180
ns
CS Blanking Time
VOPTO = 4V
70
ns
-1
OSCILLATOR
Clock Frequency Range
Max Duty Cycle
VOPTO = 4V
235
MAX5941A, VOPTO = 4V
75
275
314
85
MAX5941B, VOPTO = 4V
44
50
VSS(SHDN) = 0V
2.0
kHz
%
SOFT-START
SS Source Current
ISSO
SS Sink Current
Peak Soft-Start Voltage Clamp
Shutdown Threshold
4
4.6
6.5
1
µA
mA
No external load
2.331
2.420
2.500
VSS_SHDN falling (Note 11)
0.25
0.37
0.41
VSS_SHDN rising (Note 11)
0.53
0.59
0.65
_______________________________________________________________________________________
V
V
IEEE 802.3af-Compliant Power-Over-Ethernet
Interface/PWM Controller for Power Devices
IIN
dRi ≅
1V
(VINi + 1 - VINi)
=
(IINi + 1 - IINi) (IINi + 1 - IINi)
IOFFSET ≅ IINi -
VINi
dRi
IINi +1
dRi
IINi
IOFFSET
VINi
1V
VINi +1
Figure 1. Effective Differential Input Resistance/Offset Current
_______________________________________________________________________________________
5
MAX5941A/MAX5941B
All min/max limits for the PD interface are production tested at +85°C (extended grade)/+70°C (commercial grade). Limits
at +25°C and -40°C are guaranteed by design. All PWM controller min/max limits are 100% production tested at +25°C
and +85°C (extended grade)/+70°C (commercial grade). Limits at -40°C are guaranteed by design, unless otherwise
noted.
Note 2: The input offset current is illustrated in Figure 1.
Note 3: Effective differential input resistance is defined as the differential resistance between GND and VEE without any external
resistance.
Note 4: Classification current is turned off whenever the IC is in power mode.
Note 5: See Table 2 in the PD Classification Mode section. RDISC and RCL must be 100ppm or better.
Note 6: See Thermal Dissipation section for details.
Note 7: When UVLO is connected to the midpoint of an external resistor-divider with a series resistance of 25.5kΩ (±1%), the turnon threshold set point for the power mode is defined by the external resistor-divider. Make sure the voltage on the UVLO
pin does not exceed its maximum rating of 8V when VIN is at the maximum voltage.
Note 8: When the VUVLO is below VTH, G, UVLO, the MAX5941 sets the turn-on voltage threshold internally (VUVLO,ON).
Note 9: An input voltage or VUVLO glitch below their respective thresholds shorter than or equal to tOFF_DLY does not cause the
MAX5941A/MAX5941B to exit power-on mode (as long as the input voltage remains above an operable voltage level of 12V).
Note 10: PGOOD references to OUT while PGOOD references to VEE.
Note 11: Guaranteed by design.
Note 1:
Typical Operating Characteristics
(VIN = (GND - VEE) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = VEE, VDD = 13V, NDRV floating, TA = TMIN to TMAX.
Typical values are at TA = +25°C. All voltages are referenced to VEE (for graphs 1–11 in the Typical Operating Characteristics), all
voltages are referenced to V- (for graphs 12–30 in the Typical Operating Characteristics), unless otherwise noted.)
0.30
0.25
0.20
0.15
0.10
CLASS 3
25
20
CLASS 2
15
10
CLASS 1
CLASS 0
0
0
2
4
6
10
10
8
15
20
25
1.5
1.0
0.5
0
0
5
10
OFFSET CURRENT
vs. INPUT VOLTAGE
NORMALIZED UVLO
vs. TEMPERATURE
PGOOD OUTPUT LOW VOLTAGE
vs. CURRENT
1.010
MAX5941A/B toc04
1.008
-2.5
-3.0
4
5
6
7
8
9
180
160
1.004
140
1.002
1.000
0.998
120
100
80
0.996
60
0.994
40
0.992
20
0.990
-3.5
200
VPGOOD (mV)
-2.0
UVLO = VEE
1.006
NORMALIZED UVLO
-1.5
0
-40
10 11
-15
10
35
60
85
0
4
8
12
TEMPERATURE (°C)
ISINK (mA)
PGOOD OUTPUT LOW VOLTAGE
vs. CURRENT
OUT LEAKAGE CURRENT
vs. TEMPERATURE
INRUSH CURRENT CONTROL
(VIN = 12V)
300
250
200
150
100
VOUT = 67V
16
VGATE
5V/div
IINRUSH
100mA/div
12
8
VOUT
10V/div
4
50
0
PGOOD
10V/div
0
4
8
12
ISINK (mA)
16
20
20
MAX5941toc09
20
OUT LEAKAGE CURRENT (nA)
MAX5941A/B toc07
350
6
16
INPUT VOLTAGE (V)
400
0
15
INPUT VOLTAGE (V)
-1.0
3
2.0
INPUT VOLTAGE (V)
-0.5
2
2.5
INPUT VOLTAGE (V)
0
1
3.0
30
MAX5941A/B toc05
0
MAX5941A/B toc03
30
5
0.05
VPGOOD (mV)
35
3.5
MAX5941A/B toc08
DETECTION CURRENT (mA)
GND = V+ = V- = OUT
0.35
CLASS 4
EFFECTIVE DIFFERENTIAL INPUT
RESISTANCE vs. INPUT VOLTAGE
MAX5941A/B toc06
0.40
40
MAX5941A/B toc02
RDISC = 25.5kΩ
CLASSIFICATION CURRENT (mA)
MAX5941A/B toc01
0.45
EFFECTIVE DIFFERENTIAL INPUT RESISTANCE (MΩ)
CLASSIFICATION CURRENT
vs. INPUT VOLTAGE
DETECTION CURRENT vs. INPUT VOLTAGE
OFFSET CURRENT (µA)
MAX5941A/MAX5941B
IEEE 802.3af-Compliant Power-Over-Ethernet
Interface/PWM Controller for Power Devices
-40
-15
10
35
60
85
1ms/div
INPUT VOLTAGE (V)
_______________________________________________________________________________________
IEEE 802.3af-Compliant Power-Over-Ethernet
Interface/PWM Controller for Power Devices
VSS_SHDN vs. TEMPERATURE
(AT THE END OF SOFT-START)
INRUSH CURRENT CONTROL
(VIN = 67V)
1.003
VGATE
5V/div
VSS_SHDN (V) (NORMALIZED TO VREF = 2.4V)
MAX5941toc11
MAX5941toc10
VGATE
5V/div
IINRUSH
100mA/div
IINRUSH
100mA/div
VOUT
50V/div
VOUT
50V/div
PGOOD
50V/div
PGOOD
50V/div
OPTO = CS = V1.002
1.001
1.000
0.999
-40
2ms/div
2ms/div
MAX5941A/B toc12
INRUSH CURRENT CONTROL
(VIN = 48V)
-20
0
20
40
60
80
TEMPERATURE (°C)
NDRV FREQUENCY
vs. TEMPERATURE
MAXIMUM DUTY CYCLE
vs. TEMPERATURE
VOPTO = 4V, CS = V276
275
274
80.8
80.7
80.6
80.5
273
80.4
-20
0
20
40
60
80
-40
-20
0
20
40
60
TEMPERATURE (°C)
TEMPERATURE (°C)
MAXIMUM DUTY CYCLE
vs. TEMPERATURE
V+ SUPPLY CURRENT
vs. TEMPERATURE
MAX5941A/B toc15
48.0
47.8
VOPTO = 4V, CS = V47.6
47.4
47.2
80
1.46
1.45
V+ INPUT CURRENT (mA)
-40
MAX DUTY CYCLE (%)
MAX5941A/B toc14
VOPTO = 4V, CS = V80.9
MAX5941A/B toc16
NDRV FREQUENCY (kHz)
277
81.0
MAXIMUM DUTY CYCLE (%)
MAX5941A/B toc13
278
1.44
VOPTO = 4V, VDD = CS = V1.43
1.42
1.41
1.40
47.0
1.39
46.8
1.38
-40
-20
0
20
40
TEMPERATURE (°C)
60
80
-40
-20
0
20
40
TEMPERATURE (°C)
60
80
_______________________________________________________________________________________
7
MAX5941A/MAX5941B
Typical Operating Characteristics (continued)
(VIN = (GND - VEE) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = VEE, VDD = 13V, NDRV floating, TA = TMIN to TMAX.
Typical values are at TA = +25°C. All voltages are referenced to VEE (for graphs 1–11 in the Typical Operating Characteristics), all
voltages are referenced to V- (for graphs 12–30 in the Typical Operating Characteristics), unless otherwise noted.)
Typical Operating Characteristics (continued)
(VIN = (GND - VEE) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = VEE, VDD = 13V, NDRV floating, TA = TMIN to TMAX.
Typical values are at TA = +25°C. All voltages are referenced to VEE (for graphs 1–11 in the Typical Operating Characteristics), all
voltages are referenced to V- (for graphs 12–30 in the Typical Operating Characteristics), unless otherwise noted.)
4.85
4.80
4.75
V+ = 67V, OPTO = VCC
CS = SS_SHDN = V-
4.65
11.20
4.60
195
194
V+ SHUTDOWN CURRENT (µA)
4.90
11.25
MAX5941A/B toc18
4.95
V+ INPUT CURRENT (µA)
MAX5941A/B toc17
11.15
V+ = 67V, VOPTO = 4V,
CS = V-, VDD = 13V
11.10
11.05
4.55
V+ = 67V, OPTO = SS_SHDN =
CS = V-, VDD = 13V
193
192
191
190
189
188
187
186
4.50
-20
0
20
40
60
185
11.00
80
-40
-20
0
20
40
60
-40
80
0
20
40
TEMPERATURE (°C)
CS THRESHOLD VOLTAGE
vs. TEMPERATURE
NDRV RESISTANCE
vs. TEMPERATURE
CURRENT-LIMIT DELAY
vs. TEMPERATURE
0.487
NDRV RESISTANCE (Ω)
VOPTO = 4V, V+ = 67V
4.5
0.486
0.485
4.0
188
HIGH-SIDE DRIVER
3.5
3.0
2.5
2.0
LOW-SIDE DRIVER
0.484
-20
0
20
40
60
182
180
178
176
VOPTO = 4V, 100mV OVERDRIVE ON CS
170
-20
TEMPERATURE (°C)
0
20
60
40
TEMPERATURE (°C)
-40
80
-20
0
20
40
TEMPERATURE (°C)
VSS_SHDN vs. VDD
NDRV FREQUENCY vs. VDD
2.406
2.404
2.402
MAX5941A/B toc24
2.408
271.0
270.5
NDRV FREQUENCY (kHz)
MAX5941A/B toc23
2.410
VSS_SHDN (V)
184
172
-40
80
186
174
1.0
0.483
270.0
269.5
269.0
268.5
VOPTO = 4V, CS = V-
268.0
267.5
2.400
267.0
0
5
10
15
20
VDD (V)
25
30
80
190
CURRENT-LIMIT DELAY (ns)
MAX5941A/B toc20
5.0
1.5
8
60
TEMPERATURE (°C)
0.488
-40
-20
TEMPERATURE (°C)
MAX5941A/B toc21
-40
MAX5941A/B toc22
SOFT-START SOURCE CURRENT (µA)
5.00
4.70
V+ SHUTDOWN CURRENT
vs. TEMPERATURE
V+ INPUT CURRENT
vs. TEMPERATURE (AFTER STARTUP)
MAX5941A/B toc19
SOFT-START SOURCE CURRENT
vs. TEMPERATURE
CS THRESHOLD VOLTAGE (V)
MAX5941A/MAX5941B
IEEE 802.3af-Compliant Power-Over-Ethernet
Interface/PWM Controller for Power Devices
35
40
0
5
10
15
20
25
30
VDD (V)
_______________________________________________________________________________________
35
40
60
80
IEEE 802.3af-Compliant Power-Over-Ethernet
Interface/PWM Controller for Power Devices
MAX5941A/B toc25
VOPTO = 4V, CS = V-
10.1
47.6
47.5
DRIVER POWERED
FROM VDD
47.4
47.3
9.9
9.8
9.7
47.2
DRIVER POWERED
FROM V+
47.1
9.6
DEVICE POWERED
FROM V+
9.5
5
10
15
20
25
30
35
0
40
5
10
15
20
25
30
35
VDD (V)
VDD (V)
V+ SUPPLY CURRENT
vs. V+ VOLTAGE
V+ INPUT CURRENT vs. VOLTAGE
(AFTER STARTUP)
MAX5941A/B toc27
1.40
1.39
1.38
1.37
1.36
1.35
VOPTO = 4V, CS = VDD = V-
1.34
12
10
V+ INPUT CURRENT (µA)
0
1.33
VOPTO = 4V, CS = V-, VDD = 13V
40
MAX5941A/B toc28
47.0
V+ SUPPLY CURRENT (mA)
DEVICE POWERED FROM VDD
10.0
47.7
VCC (V)
MAXIMUM DUTY CYCLE (%)
47.9
47.8
10.2
MAX5941A/B toc26
VCC vs. VDD
MAXIMUM DUTY CYCLE vs. VDD
48.0
8
6
4
2
1.32
0
1.31
20
40
60
80
0 10 20 30 40 50 60 70 80 90 100 110
100
V+ VOLTAGE (V)
V+ VOLTAGE (V)
VCC VOLTAGE vs. VCC CURRENT
V+ = 67V, OPTO = CS = V10.2
10.0
9.8
VDD = 13V
9.6
VDD = OPTO = CS = V-
9.9
9.8
VCC VOLTAGE (V)
VCC VOLTAGE (V)
VDD = 36V
VCC VOLTAGE vs. VCC CURRENT
10.0
MAX5941A/B toc29
10.4
MAX5941A/B toc30
0
9.7
V+ = 67V
9.6
V+ = 48V
9.5
V+ = 36V
9.4
V+ = 24V
9.3
9.4
9.2
9.2
9.1
9.0
9.0
0
5
10
15
VCC CURRENT (mA)
20
0
5
10
15
20
VCC CURRENT (mA)
_______________________________________________________________________________________
9
MAX5941A/MAX5941B
Typical Operating Characteristics (continued)
(VIN = (GND - VEE) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = VEE, VDD = 13V, NDRV floating, TA = TMIN to TMAX.
Typical values are at TA = +25°C. All voltages are referenced to VEE (for graphs 1–11 in the Typical Operating Characteristics), all
voltages are referenced to V- (for graphs 12–30 in the Typical Operating Characteristics), unless otherwise noted.)
IEEE 802.3af-Compliant Power-Over-Ethernet
Interface/PWM Controller for Power Devices
MAX5941A/MAX5941B
Pin Description
PIN
NAME
1
V+
High-Voltage Startup Input. Referenced to V-. Connect directly to an input voltage range between 18V to 67V.
Connects internally to a high-voltage linear regulator that generates VCC during startup. Tie V+ to GND.
2
VDD
Line Regulator Input. Referenced to V-. VDD is the input to the linear regulator that generates VCC. For
supply voltages less than 36V, connect VDD and V+ to the supply. For supply voltages greater than 36V,
VDD receives its power from the tertiary winding of the transformer and accepts voltages from 13V to 36V.
Bypass VDD to V- with a 4.7µF capacitor.
3
OPTO
4
10
FUNCTION
Optocoupler Input. Referenced to V-. The control voltage range on this input is 2V to 3V.
Soft-Start Timing Capacitor Connection. Referenced to V-. Ramp time to full current limit is approximately
0.45ms/nF. Bypass with a minimum 10nF capacitor to V-. A 2.4V reference voltage appears across the
SS_SHDN
capacitor. Disable the PWM controller by pulling SS_SHDN below 0.25V. Tie to PGOOD to enable PWM
controller automatically from the PD interface.
5
UVLO
6
RCL
Undervoltage Lockout Programming Input for Power Mode. Referenced to VEE. When UVLO is above its
threshold, the device enters the power mode. Connect UVLO to VEE to use the default undervoltage lockout
threshold. Connect UVLO to an external resistor-divider to define a threshold externally. The series
resistance value of the external resistors must add to 25.5kΩ (±1%) and replaces the detection resistor. To
keep the device in undervoltage lockout, pull UVLO between VTH,G,UVLO and VREF,UVLO.
Classification Setting. Referenced to VEE. Add a resistor from RCL to VEE to set a PD class (see Tables 1 and 2).
7
GATE
Gate of Internal N-Channel Power MOSFET. Referenced to VEE . GATE sources 10µA when the device
enters the power mode. Connect an external 100V ceramic capacitor from GATE to VOUT to program the
inrush current. Pull GATE to VEE to turn off the internal MOSFET. The detection and classification functions
operate normally when GATE is pulled to VEE.
8
VEE
Negative Input Power. Source of the integrated isolation N-channel power MOSFET. Connect VEE to -48V.
9
OUT
Output Voltage. Referenced to VEE. Drain of the integrated isolation N-channel power MOSFET. Connect
OUT to V-.
10
PGOOD
Power-Good Indicator Output, Active High, Open Drain. PGOOD is referenced to OUT. PGOOD goes high
impedance when VOUT is within 1.2V of VEE and when GATE is 5V above VEE. Otherwise, PGOOD is pulled
to OUT (given that VOUT is at least 5V below GND). Connect PGOOD directly (no external pullup required)
to SS_SHDN to enable/disable the PWM controller.
11
PGOOD
Power-Good Indicator Output, Active Low, Open Drain. PGOOD is referenced to VEE. PGOOD is pulled to
VEE when VOUT is within 1.2V of VEE and when GATE is 5V above VEE. Otherwise, PGOOD goes high
impedance.
12
GND
13
CS
14
V-
15
NDRV
16
VCC
Ground. Referenced to VEE. GND is the positive input power. Connect to V+.
Current-Sense Input. Referenced to V-. Turns power switch off if VCS rises above 465mV for cycle-by-cycle
current limiting. CS is also the feedback for the current-mode controller. CS connects to the PWM controller
through a leading-edge blanking circuit.
V- is the ground terminal of the PWM Controller. Connect to GND.
Gate Drive. Referenced to V-. Drives a high-voltage external N-channel power MOSFET.
Regulated IC Supply. Referenced to V-. Provides power for MAX5941_. VCC is regulated from VDD during
normal operation and from V+ during startup. Bypass VCC with a 10µF tantalum capacitor in parallel with a
0.1µF ceramic capacitor to V-.
______________________________________________________________________________________
IEEE 802.3af-Compliant Power-Over-Ethernet
Interface/PWM Controller for Power Devices
CLASS
USAGE
RCL (Ω)
MAXIMUM POWER USED BY PD (W)
0
Default
10k
0.44 to 12.95
1
Optional
732
0.44 to 3.84
2
Optional
392
3.84 to 6.49
3
Optional
255
6.49 to 12.95
4
Not allowed
178
Reserved*
*Class 4 reserved for future use.
Detailed Description
The MAX5941A/MAX5941B integrate a complete power
IC for powered devices (PDs) in a power-over-ethernet
(PoE) system. The MAX5941A/MAX5941B provide PD
interface and a compact DC-DC PWM controller suitable
for flyback and forward converters in either isolated or
nonisolated designs.
The MAX5941A/MAX5941B powered device (PD) interface complies with the IEEE 802.3af standard, providing
the PD with a detection signature, a classification signature, and an integrated isolation switch with programmable inrush current control. These devices also feature
power-mode undervoltage lockout (UVLO) with wide hysteresis, and power-good status outputs.
An integrated MOSFET provides PD isolation during
detection and classification. The MAX5941A/MAX5941B
guarantee a leakage current offset of less than 10µA during the detection phase. A programmable current limit
prevents high inrush current during power-on. The
devices feature power-mode UVLO with wide hysteresis
and long deglitch time to compensate for twisted-pair
cable resistive drop and to ensure glitch-free transition
between detection, classification, and power-on/off phases. The MAX5941A/MAX5941B provide both active-high
(PGOOD) and active-low (PGOOD) outputs. Both
devices offer an adjustable UVLO threshold with a
default value compliant to the IEEE 802.3af standard.
The MAX5941A/MAX5941B are designed to work with or
without an external diode bridge in front of the PD.
Use the MAX5941A/MAX5941B PWM current-mode controllers to design flyback- or forward-mode power supplies. Current-mode operation simplifies control-loop
design while enhancing loop stability. An internal highvoltage startup regulator allows the device to connect
directly to the input supply without an external startup
resistor. Current from the internal regulator starts the controller. Once the tertiary winding voltage is established,
the internal regulator is switched off and bias current for
running the PWM controller is derived from the tertiary
winding. The internal oscillator is set to 275kHz and
trimmed to ±10%. This permits the use of small magnetic
components to minimize board space. Both the
MAX5941A and MAX5941B can be used in power supplies providing multiple output voltages. A functional diagram of the PWM controller is shown in Figure 4. Typical
applications circuits for forward and flyback topologies
are shown in Figure 5 and Figure 6, respectively.
Powered Device Interface
Operating Modes
The powered device (PD) front-end section of the
MAX5941A/MAX5941B operates in three different modes:
PD detection signature, PD classification, and PD power,
depending on its input voltage (VIN = GND - VEE). All
voltage thresholds are designed to operate with or without the optional diode bridge while still complying with
the IEEE 802.3af standard (see Application Circuit 1).
Detection Mode (1.4V ≤ VIN ≤ 10.1V)
In detection mode, the power source equipment (PSE)
applies two voltages on VIN in the range of 1.4V to
10.1V (1V step minimum), and then records the current
measurements at the two points. The PSE then computes ∆V/∆I to ensure the presence of the 25.5kΩ signature resistor. In this mode, most of the MAX5941A/
MAX5941B internal circuitry is off and the offset current
is less than 10µA.
If the voltage applied to the PD is reversed, install protection diodes on the input terminal to prevent internal
damage to the MAX5941A/MAX5941B (see Figure 7).
Since the PSE uses a slope technique (∆V/∆I) to calculate the signature resistance, the DC offset due to the
protection diodes is subtracted and does not affect the
detection process.
Classification Mode (12.6V ≤ VIN ≤ 20V)
In the classification mode, the PSE classifies the PD
based on the power consumption required by the PD.
This allows the PSE to efficiently manage power distribution. The IEEE 802.3af standard defines five different
classes as shown in Table 1. An external resistor (RCL)
connected from RCL to VEE sets the classification current.
______________________________________________________________________________________
11
MAX5941A/MAX5941B
Table 1. PD Power Classification/RCL Selection
MAX5941A/MAX5941B
IEEE 802.3af-Compliant Power-Over-Ethernet
Interface/PWM Controller for Power Devices
Table 2. Setting Classification Current
IEEE 802.3af PD CLASSIFICATION
CURRENT SPECIFICATION (mA)
CLASS CURRENT SEEN AT VIN (mA)
CLASS
RCL (Ω)
VIN* (V)
0
10k
12.6 to 20
1
732
2
392
3
4
MIN
MAX
MIN
MAX
0
4
0
4
12.6 to 20
9
12
9
12
12.6 to 20
17
20
17
20
255
12.6 to 20
26
30
26
30
178
12.6 to 20
36
42
36
44
*VIN is measured across the MAX5941 input pins (VEE and GND), which does not include the diode bridge voltage drop.
GND
UVLO
REF
2.4V,
REF
EN
GND
CLASSIFICATION
6.8V
RCL
R1
21.8V
PGOOD
2.4V, 0.8
HYST
MAX5941B
Q4
R2
39V
R3
VGATE, 6V
1.2V, REF
EN
UVLO
PGOOD
5V, REF
Q3
OUT
Q2
200mV
GATE
Q1
VEE
Figure 2. Powered Device Interface Block Diagram
12
______________________________________________________________________________________
IEEE 802.3af-Compliant Power-Over-Ethernet
Interface/PWM Controller for Power Devices
Power Mode
During power mode, when V IN rises above the
undervoltage lockout threshold (V UVLO,ON ), the
MAX5941A/ MAX5941B gradually turn on the internal Nchannel MOSFET Q1 (see Figure 2). The MAX5941A/
MAX5941B charge the gate of Q1 with a constant current
source (10µA, typ). The drain-to-gate capacitance of Q1
limits the voltage rise rate at the drain of MOSFET, thereby limiting the inrush current. To reduce the inrush current, add external drain-to-gate capacitance (see the
Inrush Current section). When the drain of Q1 is within
1.2V of its source voltage and its gate-to-source voltage is
above 5V, the MAX5941A/MAX5941B assert the PGOOD/
PGOOD outputs. The MAX5941A/MAX5941B have a wide
UVLO hysteresis and turn-off deglitch time to compensate
for the high impedance of the twisted-pair cable.
Undervoltage Lockout
The MAX5941A/MAX5941B operate up to a 67V supply
voltage with a default UVLO turn-on set at 39V and a
UVLO turn-off set at 30V. Adjust the UVLO threshold
using a resistor-divider connected to UVLO (see Figure
3). When the input voltage is above the UVLO threshold
(VUVLO,ON), the IC is in power mode and the MOSFET is
on. When the input voltage goes below the UVLO threshold (VUVLO,OFF) for more than tOFF_DLY, the MOSFET
turns off.
To adjust the UVLO threshold, connect an external
resistor-divider from GND to UVLO and from UVLO to
VEE. Use the following equations to calculate R1 and
R2 for a desired UVLO threshold:
V
R2 = 25.5kΩ x REF, UVLO
VIN, EX
R1 = 25.5kΩ - R2
where VIN, EX is the desired UVLO threshold. Since the
resistor-divider replaces the 25.5kΩ PD detection resistor, ensure that the sum of R1 and R2 equals 25.5kΩ
±1%. When using the external resistor-divider, the
VIN = 24V TO 60V
GND
R1
UVLO
MAX5941A
MAX5941B
R2
VEE
Figure 3. Setting Undervoltage Lockout with an External
Resistor-Divider
MAX5941 has an external reference voltage hysteresis of
20% (typ). In other words, when UVLO is programmed
externally, the turn-off threshold is 80% (typ) of the new
UVLO turn-on threshold.
Inrush Current Limit
The MAX5941A/MAX5941B charge the gate of the internal MOSFET with a constant current source (10µA, typ).
The drain-to-gate capacitance of the MOSFET limits the
voltage rise rate at the drain, thereby limiting the inrush
current. Add an external capacitor from GATE to OUT
to further reduce the inrush current. Use the following
equation to calculate the inrush current:
IINRUSH = IG x
COUT
CGATE
The recommended inrush current for a PoE application
is 100mA.
PGOOD/PGOOD Outputs
PGOOD is an open-drain, active-high logic output.
PGOOD goes high impedance when VOUT is within 1.2V
of VEE and when GATE is 5V above VEE. Otherwise,
PGOOD is pulled to VOUT (given that VOUT is at least 5V
below GND). Connect PGOOD to SS_SHDN to enable the
PWM controller. No external pullup resistor is required.
PGOOD is an open-drain, active-low logic output.
PGOOD is pulled to VEE when VOUT is within 1.2V of VEE
and when GATE is 5V above VEE. Otherwise, PGOOD
goes high impedance.
______________________________________________________________________________________
13
MAX5941A/MAX5941B
The PSE determines the class of a PD by applying a voltage at the PD input and measures the current sourced
out of the PSE. When the PSE applies a voltage between
12.6V and 20V, the MAX5941A/MAX5941B exhibit a current characteristic with values indicated in Table 2. The
PSE uses the classification current information to classify
the power requirement of the PD. The classification current includes the current drawn by the 25.5kΩ detection
signature resistor and the supply current of the
MAX5941A/MAX5941B so that the total current drawn by
the PD is within the IEEE 802.3af standard figures. The
classification current is turned off whenever the device is
in power mode.
MAX5941A/MAX5941B
IEEE 802.3af-Compliant Power-Over-Ethernet
Interface/PWM Controller for Power Devices
Thermal Dissipation
Optocoupled Feedback
During classification mode, if the PSE applies the maximum DC voltage, the maximum voltage drop from GND
to VRCL will be 13V. If the maximum classification current
of 42mA flows through the MAX5941A/MAX5941B, then
the maximum DC power dissipation will be close to
546mW, which is slightly higher than the maximum DC
power dissipation of the IC at maximum operating temperature. However, according to the IEEE 802.3af standard, the duration of the classification mode is limited to
75ms (max). The MAX5941A/MAX5941B handles the
maximum classification power dissipation for the maximum duration time without sustaining any internal damage. If the PSE violates the IEEE 802.3af standard by
exceeding the 75ms maximum classification duration, it
may cause internal damage to the IC.
Isolated voltage feedback is achieved by using an optocoupler and a shunt regulator as shown in Figure 5. The
output voltage set-point accuracy is a function of the
accuracy of the shunt regulator and feedback resistordivider tolerance.
PWM Controller
Current-Mode Control
The MAX5941A/MAX5941B offer current-mode control
operation with added features such as leading-edge
blanking with dual internal path that only blanks the
sensed current signal applied to the input of the PWM
comparator. The current-limit comparator monitors the
CS pin at all times and provides cycle-by-cycle current
limit without being blanked. The leading-edge blanking
of the CS signal prevents the PWM comparator from
prematurely terminating the on cycle. The CS signal
contains a leading-edge spike that is the result of the
MOSFET gate charge current, capacitive and diode
reverse recovery current of the power circuit. Since this
leading-edge spike is normally lower than the current
limit comparator threshold, current limiting is not
blanked and cycle-by-cycle current limiting is provided
under all conditions.
Use the MAX5941A in discontinuous flyback applications where wide line voltage and load current variation
is expected. Use the MAX5941B for single transistor
forward converters where the maximum duty cycle must
be limited to less than 50%.
Under certain conditions, it may be advantageous to
use a forward converter with greater than 50% duty
cycle. For those cases, use the MAX5941A. The large
duty cycle results in much lower operating primary RMS
currents through the MOSFET switch and in most cases
a smaller output filter inductor. The major disadvantage
to this is that the MOSFET voltage rating must be higher
and that slope compensation must be provided to stabilize the inner current loop. The MAX5941A provides
internal slope compensation.
14
Internal Regulators
The internal regulators of the MAX5941A/MAX5941B
enable initial startup without a lossy startup resistor and
regulate the voltage at the output of a tertiary (bias) winding to provide power for the IC. At startup, V+ is regulated down to VCC to provide bias for the device. The VDD
regulator then regulates from the output of the tertiary
winding to VCC. This architecture allows the tertiary winding to have only a small filter capacitor at its output thus
eliminating the additional cost of a filter inductor.
When designing the tertiary winding, calculate the number of turns so the minimum reflected voltage is always
higher than 12.7V. The maximum reflected voltage must
be less than 36V.
To reduce power dissipation, the high-voltage regulator
is disabled when the VDD voltage reaches 12.7V. This
greatly reduces power dissipation and improves efficiency. If V CC falls below the undervoltage lockout
threshold (VCC = 6.6V), the low-voltage regulator is disabled, and soft-start is reinitiated. In undervoltage lockout the MOSFET driver output (NDRV) is held low.
If the input voltage range is between 13V and 36V, V+
and VDD may be connected to the line voltage provided
that the maximum power dissipation is not exceeded.
This eliminates the need for a tertiary winding.
PWM Controller Undervoltage Lockout,
Soft-Start, and Shutdown
The soft-start feature of the MAX5941A/MAX5941B
allows the load voltage to ramp up in a controlled manner, thus eliminating output voltage overshoot.
While the controller is in undervoltage lockout, the
capacitor connected to the SS_SHDN pin is discharged. Upon coming out of undervoltage lockout, an
internal current source starts charging the capacitor to
initiate the soft-start cycle. Use the following equation to
calculate total soft-start time:
tstartup = 0.45
ms
× Css
nF
where CSS is the soft-start capacitor as shown in Figure 5.
Operation begins when VSS_SHDN ramps above 0.6V.
When soft-start has completed, VSS_SHDN is regulated
______________________________________________________________________________________
IEEE 802.3af-Compliant Power-Over-Ethernet
Interface/PWM Controller for Power Devices
MAX5941A/MAX5941B
VDD
VDD-OK
V+
IN
IN
HIGHVOLTAGE
REGULATOR
VEN
BIAS
WINDING
REGULATOR
OUT
EN
OUT
0.7V
VCC
UVLO
MAX5941A ONLY
6.6V
275kHz
OSCILLATOR
SLOPE
COMPENSATION
26mV/µs
R
NDRV
Q
80%/50%
DUTY CYCLE
CLAMP
26mV/µs
S
∑
ILIM
PWM
125mV
CS
OPTO
5kΩ
Vb
SS_SHDN
70ns
BLANKING
4µA
3R
2.4V
BUF
R
0.4V
Figure 4. MAX5941A/MAX5941B PWM Controller Functional Diagram
______________________________________________________________________________________
15
MAX5941A/MAX5941B
IEEE 802.3af-Compliant Power-Over-Ethernet
Interface/PWM Controller for Power Devices
4.7nF
250VAC
1N4148
CDD
47µF
GND
VDD
SBL204OCT
14 NR
CMHD2003
6 NT
VIN
(30V TO 72V)
VOUT
CIN
3 × 0.47µF
V+
NP
14
UVLO
20Ω
NS
5
M1
IRF640N
MAX5941B
L1
4.7µH
COUT
3 × 560µF
5V/10A
0.1µF
1nF
NDRV
100Ω
RCL
CS
RDISC
25.5kΩ
GATE
RSENSE
100mΩ
PGOOD
RCL
SS_SHDN
CSS
0.1µF
VOUT
VCC
220Ω
CCC
10µF
PGOOD
VEE
4.75kΩ
OPTO
OPTOCOUPLER
R1
25.5kΩ
3kΩ
0.1µF
240kΩ
TLV431
R2
8.25kΩ
Figure 5. Forward Converter
to 2.4V, the internal voltage reference. Pull VSS_SHDN
below 0.25V to disable the controller.
Undervoltage lockout shuts down the controller when
VCC is less than 6.6V. The regulators for V+ and the reference remain on during shutdown.
MOSFET source through a 100Ω resistor or an RC lowpass filter (Figures 5, 6). Select the current-sense resistor, RSENSE, according to the following equation:
RSENSE = 0.465V / ILimPrimary
Current-Sense Comparator
The current-sense (CS) comparator and its associated
logic limit the peak current through the MOSFET.
Current is sensed at CS as a voltage across a sense
resistor between the source of the MOSFET and GND.
To reduce switching noise, connect CS to the external
16
where ILimPrimary is the maximum peak primary-side
current.
When VCS > 465mV, the power MOSFET switches off.
The propagation delay from the time the switch current
reaches the trip level to the driver turn-off time is 170ns.
______________________________________________________________________________________
IEEE 802.3af-Compliant Power-Over-Ethernet
Interface/PWM Controller for Power Devices
MAX5941A/MAX5941B
4.7nF
250VAC
NT
VIN
VOUT
CDD
GND
VDD
CIN
V+
COUT
NP
MAX5941A
UVLO
NS
M1
NDRV
RCL
GATE
RDISC
25.5kΩ
100Ω
CS
PGOOD
RSENSE
SS_SHDN
V-
CSS
OUT
VCC
RCL
CCC
220Ω
PGOOD
VEE
OPTO
OPTOCOUPLER
R1
TLV431
R2
Figure 6. Flyback Converter
PWM Comparator and Slope Compensation
An internal 275kHz oscillator determines the switching
frequency of the controller. At the beginning of each
cycle, NDRV switches the N-channel MOSFET on.
NDRV switches the external MOSFET off after the maximum duty cycle has been reached, regardless of the
feedback.
The MAX5941B uses an internal ramp generator for
slope compensation. The internal ramp signal is reset
at the beginning of each cycle and slews at 26mV/µs.
The PWM comparator uses the instantaneous current,
the error voltage, the internal reference, and the slope
compensation (MAX5941A only) to determine when to
switch the N-channel MOSFET off. In normal operation,
the N-channel MOSFET turns off when:
IPRIMARY × RSENSE > VOPTO - VREF - VSCOMP
where IPRIMARY is the current through the N-channel
MOSFET, V REF is the 2.4V internal reference, and
VSCOMP is a ramp function starting at zero and slewing
at 26mV/µs (MAX5941A only). When using the
MAX5941A in a forward-converter configuration, the following condition must be met to avoid control-loop subharmonic oscillations:
______________________________________________________________________________________
17
MAX5941A/MAX5941B
IEEE 802.3af-Compliant Power-Over-Ethernet
Interface/PWM Controller for Power Devices
NS k × RSENSE × VOUT
×
= 26mV / µs
L
NP
where k = 0.75 to 1, and NS and NP are the number of
turns on the secondary and primary side of the transformer, respectively. L is the output filter inductor. This
makes the output inductor current downslope as referenced across RSENSE equal to the slope compensation. The controller responds to transients within one
cycle when this condition is met.
3) The turns ratio of the transformer is calculated based
on the minimum input voltage and the lower limit of
the maximum duty cycle for the MAX5941B (44%).
To enable the use of MOSFETs with drain-source
breakdown voltages of less than 200V, use the
MAX5941B with the 50% maximum duty cycle.
Calculate the turns ratio according to the following
equation:
NS VOUT + (VD1 × DMAX )
≥
NP
DMAX × VIN_MIN
N-Channel MOSFET Gate Driver
where:
NS/NP = Turns ratio (NS is the number of secondary
turns and NP is the number of primary turns).
NDRV drives an N-channel MOSFET. NDRV sources
and sinks large transient currents to charge and discharge the MOSFET gate. To support such switching
transients, bypass VCC with a ceramic capacitor. The
average current as a result of switching the MOSFET is
the product of the total gate charge and the operating
frequency. It is this current plus the DC quiescent current that determines the total operating current.
VOUT = Output voltage (5V).
VD1 = Voltage drop across D1 (typically 0.5V for
power Schottky diodes).
DMAX = Minimum value of maximum operating duty
cycle (44%).
Applications Information
VIN_MIN = Minimum Input voltage (30V).
Design Example
The following is a general procedure for designing a
forward converter (Figure 5) using the MAX5941B:
In this example:
NS 5V + (0.5V × 0.44)
≥
= 0.395
0.44 × 30V
NP
1) Determine the requirements.
2) Set the output voltage.
3) Calculate the transformer primary to secondary
winding turns ratio.
4) Calculate the reset to primary winding turns ratio.
Choose N P based on core losses and DC resistance. Use the turns ratio to calculate NS, rounding
up to the nearest integer. In this example, NP = 14
and NS = 6.
For a forward converter, choose a transformer with a
magnetizing inductance in the neighborhood of
200µH. Energy stored in the magnetizing inductance
of a forward converter is not delivered to the load
and must be returned back to the input; this is
accomplished with the reset winding.
The transformer primary to secondary leakage
inductance should be less than 1µH. Note that all
leakage energy will be dissipated across the MOSFET. Snubber circuits may be used to direct some or
all of the leakage energy to be dissipated across a
resistor.
To calculate the minimum duty cycle (DMIN), use the
following equation:
5) Calculate the tertiary to primary winding turns
ratio.
6) Calculate the current-sense resistor value.
7) Calculate the output inductor value.
8) Select the output capacitor.
The circuit in Figure 5 was designed as follows:
1) 30V ≤ VIN ≤ 67V, VOUT = 5V, IOUT = 10A, VRIPPLE ≤
50mV. Turn-on threshold is set at 38.6V.
2) To set the output voltage, calculate the values of
resistors R1 and R2 according to the following
equation:
VREF
R2
=
VOUT R1 + R2
where VREF is the reference voltage of the shunt
regulator, and R1 and R2 are the resistors shown in
Figures 5 and 6.
=
DMIN =
VOUT
= 17.7
N
VIN_MAX × S - VD1
NP
where VIN_MAX is the maximum input voltage (67V).
18
______________________________________________________________________________________
IEEE 802.3af-Compliant Power-Over-Ethernet
Interface/PWM Controller for Power Devices
NR ≤ NP ×
1-DMAX ′
DMAX ′
where:
NR/NP = Reset winding turns ratio.
DMAX’ = Maximum value of maximum duty cycle:
NR ≤ 14 ×
1- 0.5
= 14
0.5
Round NR to the nearest smallest integer.
The turns ratio of the reset winding (NR/NP) determines the peak voltage across the N-channel MOSFET.
Use the following equation to determine the maximum drain-source voltage across the N-channel
MOSFET:

N 
VDSMAX ≥ VIN_MAX × 1 + P 
NR 

VDSMAX = Maximum MOSFET drain-source voltage.
VIN_MAX = Maximum input voltage:
14 

VDSMAX ≥ 67V × 1 +
 = 134V

14 
Choose MOSFETs with appropriate avalanche
power ratings to absorb any leakage energy.
5) Choose the tertiary winding turns ratio (NT/NP) so that
the minimum input voltage provides the minimum
operating voltage at VDD (13V). Use the following
equation to calculate the tertiary winding turns ratio:
VDDMIN + 0.7
× NP ≤ NT ≤
VIN_MIN
VDDMAX + 0.7
× NP
VIN_MAX
where:
VDDMIN is the minimum VDD supply voltage (13V).
VDDMAX is the maximum VDD supply voltage (30V).
VIN_MIN is the minimum input voltage (30V).
VIN_MAX is the maximum input voltage (67V in this
design example).
NP is the number of turns of the primary winding.
NT is the number of turns of the tertiary winding:
13.7
36.7
× 14 ≤ NT ≤
× 14
30
67
6.39 ≤ NT ≤ 7.67
Choose NT = 7.
6) Choose RSENSE according to the following equation:
RSENSE ≤
VILIM
NS
× 1.2 × IOUTMAX
NP
where:
VILIM is the current-sense comparator trip threshold
voltage (0.465V).
NS/NP is the secondary side turns ratio (5/14 in this
example).
IOUTMAX is the maximum DC output current (10A in
this example):
RSENSE ≤
0.465V
6
× 1.2 × 10
14
= 90.4mΩ
7) Choose the inductor value so that the peak ripple
current (LIR) in the inductor is between 10% and
20% of the maximum output current:
L≥
(VOUT + VD ) × (1- DMIN )
2 × LIR × 275kHz × IOUTMAX
where VD is the output Schottky diode forward voltage drop (0.5V) and LIR is the ratio of inductor ripple current to DC output current:
L≥
(5.5) × (1- 0.198)
0.4 × 275kHz × 10A
= 4.01µH
8) The size and ESR of the output filter capacitor determine the output ripple. Choose a capacitor with a
low ESR to yield the required ripple voltage.
Use the following equations to calculate the peak-topeak output ripple:
2
2
VRIPPLE = VRIPPLE
+ VRIPPLE
,ESR
,C
______________________________________________________________________________________
19
MAX5941A/MAX5941B
4) The reset winding turns ratio (NR/NP) needs to be
low enough to guarantee that the entire energy in
the transformer is returned to V+ within the off cycle
at the maximum duty cycle. Use the following equation to determine the reset winding turns ratio:
MAX5941A/MAX5941B
IEEE 802.3af-Compliant Power-Over-Ethernet
Interface/PWM Controller for Power Devices
Table 3. Component Suppliers
COMPONENT
SUPPLIERS
International Rectifier
Power FETS
Current-Sense Resistors
Diodes
Capacitors
Magnetics
www.irf.com
Fairchild
www.fairchildsemi.com
Vishay-Siliconix
www.vishay.com/brands/siliconix/main.html
Dale-Vishay
www.vishay.com/brands/dale/main.html
IRC
www.irctt.com/pages/index.cfm
ON Semi
www.onsemi.com
General Semiconductor
www.gensemi.com
Central Semiconductor
www.centralsemi.com
Sanyo
www.sanyo.com
Taiyo Yuden
www.t-yuden.com
AVX
www.avxcorp.com
Coiltronics
www.cooperet.com
Coilcraft
www.coilcraft.com
Pulse Engineering
www.pulseeng.com
where:
VRIPPLE is the combined RMS output ripple due to
V RIPPLE,ESR , the ESR ripple, and V RIPPLE,C , the
capacitive ripple. Calculate the ESR ripple and
capacitive ripple as follows:
VRIPPLE,ESR = IRIPPLE x ESR
VRIPPLE,C = IRIPPLE/(2 x π x 275kHz x COUT)
20
WEBSITE
Layout Recommendations
All connections carrying pulsed currents must be very
short, be as wide as possible, and have a ground plane
as a return path. The inductance of these connections
must be kept to a minimum due to the high di/dt of the
currents in high-frequency switching power converters.
Current loops must be analyzed in any layout proposed, and the internal area kept to a minimum to
reduce radiated EMI. Ground planes must be kept as
intact as possible.
______________________________________________________________________________________
IEEE 802.3af-Compliant Power-Over-Ethernet
Interface/PWM Controller for Power Devices
MAX5941A/MAX5941B
POWER-OVER
SIGNAL PAIRS
VREG
RX
3
6
1
2
PHY
GND
DF025A
+
+
-
-
RJ-45
4
DF025A
TX
5
7
-48V
8
POWER OVER
SPARE PAIRS
VREG
V+
GND
NDRV
VDD
CS
MAX5941_
VCC
*D1
V-
GND
SS_SHDN
**R1
60V
RDISC =
25.5kΩ
UVLO
68nF
RCL
**R2
SMBJ58CA
VCC
PGOOD
PGOOD
OPTOCOUPLER
OPTO
RCL
GATE
*D2
-48V
OUT
VEE
TL431
*CGATE
* OPTIONAL.
* R1 AND R2 ARE OPTIONAL AND WHEN USED, THEY MUST TOTAL TO 25.5kΩ AND REPLACE THE 25.5kΩ RESISTOR.
Figure 7. PD with Power-Over-Ethernet (Power Is Provided by Either the Signal Pairs or the Spare Pairs)
______________________________________________________________________________________
21
MAX5941A/MAX5941B
IEEE 802.3af-Compliant Power-Over-Ethernet
Interface/PWM Controller for Power Devices
POWER-SUPPLY CIRCUIT 1
VREG1
V+
GND
NDRV
VDD
CS
MAX5941_
*D1
GND
V-
RDISC =
25.5kΩ
SS_SHDN
**R1
68nF
PGOOD
UVLO
60V
RCL
**R2
VCC
OPTOCOUPLER
PGOOD
RCL
OPTO
GATE
*D2
OUT
VEE
-48V
TL431
*CGATE
POWER-SUPPLY CIRCUIT 2
V+
VREG2
V+
NDRV
VDD
CS
MAX5014
GND
SS_SHDN
VCC
OPTOCOUPLER
OPTO
* OPTIONAL.
* R1 AND R2 ARE OPTIONAL AND WHEN USED,
THEY MUST TOTAL TO 25.5kΩ AND REPLACE
THE 25.5kΩ RESISTOR.
TL431
Figure 8. Power-Supply Circuit 1 Enabling PWM Controller of a Second Power Circuit
22
______________________________________________________________________________________
IEEE 802.3af-Compliant Power-Over-Ethernet
Interface/PWM Controller for Power Devices
VREG
V+
GND
NDRV
VDD
VCC
CS
MAX5941A
MAX5941B
GND
V-
SS_SHDN
PGOOD
RDISC =
25.5kΩ
60V
VCC
PGOOD
UVLO
RCL
OPTOCOUPLER
GATE
-48V
OPTO
OUT
VEE
CGATE
TL431
Chip Information
TRANSISTOR COUNT: 4232
PROCESS: BiCMOS
______________________________________________________________________________________
23
MAX5941A/MAX5941B
Typical Operating Circuit
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
28L 16L SOIC.EPS
MAX5941A/MAX5941B
IEEE 802.3af-Compliant Power-Over-Ethernet
Interface/PWM Controller for Power Devices
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.