PHILIPS NE572N Programmable analog compandor Datasheet

Philips Semiconductors RF Communications Products
Product specification
Programmable analog compandor
DESCRIPTION
NE/SA572
FEATURES
The NE572 is a dual-channel,
high-performance gain control circuit in which
either channel may be used for dynamic
range compression or expansion. Each
channel has a full-wave rectifier to detect the
average value of input signal, a linearized,
temperature-compensated variable gain cell
(∆G) and a dynamic time constant buffer. The
buffer permits independent control of
dynamic attack and recovery time with
minimum external components and improved
low frequency gain control ripple distortion
over previous compandors.
The NE572 is intended for noise reduction in
high-performance audio systems. It can also
be used in a wide range of communication
systems and video recording applications.
• Independent control of attack and recovery
PIN CONFIGURATION
D1, N, F Packages
time
• Improved low frequency gain control ripple
• Complementary gain compression and
expansion with external op amp
• Wide dynamic range—greater than 110dB
• Temperature-compensated gain control
• Low distortion gain cell
• Low noise—6µV typical
• Wide supply voltage range—6V-22V
• System level adjustable with external
TRACK TRIM A 1
16
RECOV. CAP A 2
15 TRACK TRIM B
RECT. IN A 3
14 RECOV. CAP B
ATTACK CAP A 4
VCC
13 RECT. IN B
∆G OUT A 5
12 ATTACK CAP B
11 ∆G OUT B
THD TRIM A 6
∆G IN A 7
10 THD TRIM B
GND 8
9
∆G IN B
NOTE:
1. D package released in large SO (SOL) package
only.
components
APPLICATIONS
• Dynamic noise reduction system
• Voltage control amplifier
• Stereo expandor
• Automatic level control
• High-level limiter
• Low-level noise gate
• State variable filter
ORDERING INFORMATION
DESCRIPTION
16-Pin Plastic Small Outline (SO)
16-Pin Plastic Dual In-Line Package (DIP)
TEMPERATURE RANGE
ORDER CODE
DWG #
0 to +70°C
NE572D
0005
0 to +70°C
NE572N
0406
16-Pin Plastic Small Outline (SO)
–40 to +85°C
SA572D
0005
16-Pin Ceramic Dual In-Line Package (Cerdip)
–40 to +85°C
SA572F
0582
16-Pin Plastic Dual In-Line Package (DIP)
–40 to +85°C
SA572N
0406
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
22
VDC
NE572
0 to +70
°C
SA572
–40 to +85
VCC
Supply voltage
TA
Operating temperature range
PD
October 7, 1987
Power dissipation
500
2
mW
853-0813 90829
Philips Semiconductors RF Communications Products
Product specification
Programmable analog compandor
NE/SA572
BLOCK DIAGRAM
R1
(5,11)
(7,9)
6.8k
∆G
(6,10)
500
Ω
GAIN CELL
(1,15)
–
–
(3,13)
+
+
10k
270
(16)
BUFFER
RECTIFIER
Ω
10k
P.S.
(8)
(4,12)
(2,14)
DC ELECTRICAL CHARACTERISTICS
Standard test conditions (unless otherwise noted) VCC=15V, TA=25°C; Expandor mode (see Test Circuit). Input signals at unity gain level (0dB)
= 100mVRMS at 1kHz; V1 = V2; R2 = 3.3kΩ; R3 = 17.3kΩ.
SYMBOL
PARAMETER
TEST CONDITIONS
NE572
Min
VCC
Supply voltage
ICC
Supply current
VR
Internal voltage reference
THD
Total harmonic distortion
(untrimmed)
THD
THD
Typ
6
No signal
SA572
Max
Min
22
6
Typ
22
6
mA
2.5
2.7
VDC
0.2
1.0
%
2.7
1kHz CA=1.0µF
0.2
1.0
Total harmonic distortion
(trimmed)
1kHz CR=10µF
0.05
0.05
%
Total harmonic distortion
(trimmed)
100Hz
0.25
0.25
%
Input to V1 and V2 grounded
(20–20kHz)
6
25
6
25
µV
Input change from no signal to
100mVRMS
±20
±50
±20
±50
mV
0
+1.5
dB
0.7
3
%
–2.5
dB
DC level shift (untrimmed)
Unity gain level
Large–signal distortion
–1
V1=V2=400mV
0
+1
0.7
3.0
2.3
VDC
6.3
2.5
No signal output noise
2.3
UNIT
Max
–1.5
Tracking error (measured
relative to value at unity
Rectifier input
gain)=
V2=+6dB V1=0dB
±0.2
[VO–VO (unity gain)]dB
V2=–30dB V1=0dB
±0.5
–V2dB
Channel crosstalk
PSRR
Power supply rejection ratio
October 7, 1987
±0.2
±0.5
–1.5
+0.8
200mVRMS into channel A, measured
output on channel B
120Hz
60
60
70
3
+1.6
dB
70
dB
Philips Semiconductors RF Communications Products
Product specification
Programmable analog compandor
NE/SA572
TEST CIRCUIT
100Ω
1µF
–15V
22µF
2.2µF
(7,9)
6.8k
V1
1%
R3
(5,11)
∆G
+
17.3k
82k
–
5Ω
270pF
(2,14)
NE5234
V0
2.2k
= 10µF
(6,10)
+
BUFFER
1k
+
2.2µF
(4,12)
(8)
(1,15)
2.2µF
V2
3.3k
(3,13)
+15V
RECTIFIER
(16)
+
R2
1%
AUDIO SIGNAL PROCESSING IC
COMBINES VCA AND FAST ATTACK/SLOW RECOVERY LEVEL
SENSOR
In high-performance audio gain control
applications, it is desirable to independently
control the attack and recovery time of the
gain control signal. This is true, for example,
in compandor applications for noise
reduction. In high end systems the input
signal is usually split into two or more
frequency bands to optimize the dynamic
behavior for each band. This reduces low
frequency distortion due to control signal
ripple, phase distortion, high frequency
channel overload and noise modulation.
Because of the expense in hardware, multiple
band signal processing up to now was limited
to professional audio applications.
With the introduction of the Signetics NE572
this high-performance noise reduction
concept becomes feasible for consumer hi fi
applications. The NE572 is a dual channel
gain control IC. Each channel has a
linearized, temperature-compensated gain
cell and an improved level sensor. In
conjunction with an external low noise op
amp for current-to-voltage conversion, the
VCA features low distortion, low noise and
wide dynamic range.
The novel level sensor which provides gain
control current for the VCA gives lower gain
control ripple and independent control of fast
attack, slow recovery dynamic response. An
October 7, 1987
.1µF
attack capacitor CA with an internal 10k
resistor RA defines the attack time tA. The
recovery time tR of a tone burst is defined by
a recovery capacitor CR and an internal 10k
resistor RR. Typical attack time of 4ms for
the high-frequency spectrum and 40ms for
the low frequency band can be obtained with
0.1µF and 1.0µF attack capacitors,
respectively. Recovery time of 200ms can be
obtained with a 4.7µF recovery capacitor for
a 100Hz signal, the third harmonic distortion
is improved by more than 10dB over the
simple RC ripple filter with a single 1.0µF
attack and recovery capacitor, while the
attack time remains the same.
The NE572 is assembled in a standard
16-pin dual in-line plastic package and in
oversized SOL package. It operates over a
wide supply range from 6V to 22V. Supply
current is less than 6mA. The NE572 is
designed for consumer application over a
temperature range 0-70 The SA572 is
intended for applications from –40°C to
+85°C.
NE572 BASIC APPLICATIONS
Description
The NE572 consists of two linearized,
temperature-compensated gain cells (∆G),
each with a full-wave rectifier and a buffer
amplifier as shown in the block diagram. The
two channels share a 2.5V common bias
reference derived from the power supply but
otherwise operate independently. Because of
4
22µF
inherent low distortion, low noise and the
capability to linearize large signals, a wide
dynamic range can be obtained. The buffer
amplifiers are provided to permit control of
attack time and recovery time independent of
each other. Partitioned as shown in the block
diagram, the IC allows flexibility in the design
of system levels that optimize DC shift, ripple
distortion, tracking accuracy and noise floor
for a wide range of application requirements.
Gain Cell
Figure 1 shows the circuit configuration of the
gain cell. Bases of the differential pairs Q1-Q2
and Q3-Q4 are both tied to the output and
inputs of OPA A1. The negative feedback
through Q1 holds the VBE of Q1-Q2 and the
VBE of Q3-Q4 equal. The following
relationship can be derived from the
transistor model equation in the forward
active region.
V BE
Q3Q4
BE
Q1Q2
(VBE = VT IIN IC/IS)
Philips Semiconductors RF Communications Products
Product specification
Programmable analog compandor
ǒ
V TI n
Ǔ
1
I )
2 G
1
I
2 O
IS
where I IN +
*
V TI n
ǒ
1
I *
2 G
NE/SA572
Ǔ
1
I
2 O
IS
V+
V IN
R1
R1 = 6.8kΩ
I1 = 140µA
I2 = 280µA
V TI n
ǒ
I1 )
I IN
IS
where I IN +
Ǔ
*
V TI n
ǒ
I2 *
I1 *
IS
I IN
Ǔ
1
I )
2 G
1
I
2 O
I1
140µA
(2)
A1
IO
V IN
R1
–
+
R1 = 6.8kΩ
I1 = 140µA
I2 = 280µA
Q4
Q3
Q1
Q2
R1
6.8k
IO is the differential output current of the gain
cell and IG is the gain control current of the
gain cell.
I2
280µA
IG
VREF
THD
TRIM
If all transistors Q1 through Q4 are of the
same size, equation (2) can be simplified to:
VIN
IO
2
+
@
I2
I IN @
IG *
1ǒ
I *
I2 2
2I 1Ǔ @
IG
The first term of Equation 3 shows the
multiplier relationship of a linearized two
quadrant transconductance amplifier. The
second term is the gain control feedthrough
due to the mismatch of devices. In the
design, this has been minimized by large
matched devices and careful layout. Offset
voltage is caused by the device mismatch
and it leads to even harmonic distortion. The
offset voltage can be trimmed out by feeding
a current source within ±25µA into the THD
trim pin.
The residual distortion is third harmonic
distortion and is caused by gain control
ripple. In a compandor system, available
control of fast attack and slow recovery
improve ripple distortion significantly. At the
unity gain level of 100mV, the gain cell gives
THD (total harmonic distortion) of 0.17% typ.
Output noise with no input signals is only 6µV
in the audio spectrum (10Hz-20kHz). The
output current IO must feed the virtual ground
input of an operational amplifier with a
resistor from output to inverting input. The
non-inverting input of the operational
amplifier has to be biased at VREF if the
output current IO is DC coupled.
October 7, 1987
Figure 1. Basic Gain Cell Schematic
(3)
Rectifier
The rectifier is a full-wave design as shown in
Figure 2. The input voltage is converted to
current through the input resistor R2 and
turns on either Q5 or Q6 depending on the
signal polarity. Deadband of the voltage to
current converter is reduced by the loop gain
of the gain block A2. If AC coupling is used,
the rectifier error comes only from input bias
current of gain block A2. The input bias
current is typically about 70nA. Frequency
response of the gain block A2 also causes
second-order error at high frequency. The
collector current of Q6 is mirrored and
summed at the collector of Q5 to form the full
wave rectified output current IR. The rectifier
transfer function is
IR +
V IN *
V REF
(4)
R2
If VIN is AC-coupled, then the equation will be
reduced to:
I RAC +
V IN(AVG)
R2
5
The internal bias scheme limits the maximum
output current IR to be around 300µA. Within a
±1dB error band the input range of the rectifier
is about 52dB.
Philips Semiconductors RF Communications Products
Product specification
Programmable analog compandor
NE/SA572
V+
IR +
V IN *
V REF
R2
+
VREF
A2
–
Q5
D7
Q6
R2
VIN
Figure 2. Simplified Rectifier Schematic
Buffer Amplifier
In audio systems, it is desirable to have fast
attack time and slow recovery time for a tone
burst input. The fast attack time reduces
transient channel overload but also causes
low-frequency ripple distortion. The
low-frequency ripple distortion can be
improved with the slow recovery time. If
different attack times are implemented in
corresponding frequency spectrums in a split
band audio system, high quality performance
can be achieved. The buffer amplifier is
designed to make this feature available with
minimum external components. Referring to
Figure 3, the rectifier output current is
mirrored into the input and output of the
unipolar buffer amplifier A3 through Q8, Q9
and Q10. Diodes D11 and D12 improve
tracking accuracy and provide
common-mode bias for A3. For a
positive-going input signal, the buffer
amplifier acts like a voltage-follower.
Therefore, the output impedance of A3 makes
the contribution of capacitor CR to attack time
insignificant. Neglecting diode impedance,
the gain Ga(t) for ∆G can be expressed as
follows:
Ga(t) + (Ga INT *
Q9
= 2IR2
IR2
X2
Q16
10k
V IN
R
–
D15
+
*
G RFNL e t
t
R
)
G RFNL
GR(t)=(GR INT–GR FNL) e +GR FNL
IR1
Q14
D11
D12
CR
TRACKING
TRIM
X2
Q18
τR=RR • CR=10k • CR
where τR is the recovery time constant and
RR is a 10k internal resistor. The gain control
current is mirrored to the gain cell through
Q14. The low level gain errors due to input
bias current of A2 and A3 can be trimmed
through the tracking trim pin into A3 with a
current source of ±3µA.
Basic Expandor
Figure 4 shows an application of the circuit as
a simple expandor. The gain expression of
the system is given by
Figure 3. Buffer Amplifier Schematic
October 7, 1987
where τA is the attack time constant and RA
is a 10k internal resistor. Diode D15 opens
the feedback loop of A3 for a negative-going
signal if the value of capacitor CR is larger
than capacitor CA. The recovery time
depends only on CR • RR. If the diode
impedance is assumed negligible, the
dynamic gain GR (t) for ∆G is expressed as
follows.
G R(t) + (G RINT *
D13
A3
CA
Ga FNL
τA=RA • CA=10k • CA
Q17
10k
)
GaFNL=Final Gain
Q10
IQ
IR +
t
A
GaINT=Initial Gain
V+
Q8
*
Ga FNL e t
6
Philips Semiconductors RF Communications Products
Product specification
Programmable analog compandor
R 3 @ V IN(AVG)
V OUT
2
+
@
V IN
I1
(5)
R2 @ R1
(I1=140µA)
Both the resistors R1 and R2 are tied to
internal summing nodes. R1 is a 6.8k internal
resistor. The maximum input current into the
gain cell can be as large as 140µA. This
corresponds to a voltage level of 140µA •
6.8k=952mV peak. The input peak current
into the rectifier is limited to 300µA by the
internal bias system. Note that the value of
R1 can be increased to accommodate higher
input level. R2 and R3 are external resistors.
It is easy to adjust the ratio of R3/R2 for
NE/SA572
desirable system voltage and current levels.
A small R2 results in higher gain control
current and smaller static and dynamic
tracking error. However, an impedance buffer
A1 may be necessary if the input is voltage
drive with large source impedance.
reference Pin 6 or 10. Resistor R4 is used to
bias up the output DC level of A2 for
maximum swing. The output DC level of A2 is
given by
The gain cell output current feeds the
summing node of the external OPA A2. R3
and A2 convert the gain cell output current to
the output voltage. In high-performance
applications, A2 has to be low-noise,
high-speed and wide band so that the
high-performance output of the gain cell will
not be degraded. The non-inverting input of
A2 can be biased at the low noise internal
V ODC + V REF 1 )
ǒ
R3
R4
Ǔ
*
VB
R3
R4
VB can be tied to a regulated power supply
for a dual supply system and be grounded for
a single supply system. CA sets the attack
time constant and CR sets the recovery time
constant. *5COL
R4
R3
+VB
17.3k
–
CIN2
A1
CIN1
VIN
R1
(7,9)
+
6.8k
(5,11)
∆G
A2
(6,10) R6
2.2µF
VREF
1k
(2,14)
R5
100k
(4,12)
BUFFER
CIN3
2.2µF
R2
3.3k
CA CR
1µF 10µF
(3,13)
(8)
(16)
+VCC
Figure 4. Basic Expandor Schematic
October 7, 1987
7
(6)
C1
2.2µF
VOUT
Philips Semiconductors RF Communications Products
Product specification
Programmable analog compandor
Basic Compressor
NE/SA572
R4
RDC1
Figure 5 shows the hook-up of the circuit as a
compressor. The IC is put in the feedback
loop of the OPA A1. The system gain
expression is as follows:
V OUT
+
V IN
ǒ
Ǔ
I1
R2 @ R1
@
2
R 3 @ V IN(AVG)
ǒ
V ODC + V REF 1 )
*
VB @
ǒ
C2
(7)
R DC1 ) R DC2
R4
.1µF
D1
CIN1
VIN
R DC1 ) R DC2
R4
Ǔ
9.1k
CDC
10µF
1
2
RDC1, RDC2, and CDC form a DC feedback
for A1. The output DC level of A1 is given by
RDC2
9.1k
D2
–
2.2µF
R3
17.3k
A1
VOUT
+
C1
(8)
1k R5
(6,10) VREF
Ǔ
R1
∆G
(7,9)
6.8k
The zener diodes D1 and D2 are used for
channel overload protection.
CIN2
2.2µF
(5,11)
(2,14)
Basic Compandor System
The above basic compressor and expandor
can be applied to systems such as tape/disc
noise reduction, digital audio, bucket brigade
delay lines. Additional system design
techniques such as bandlimiting, band
splitting, pre-emphasis, de-emphasis and
equalization are easy to incorporate. The IC
is a versatile functional block to achieve a
high performance audio system. Figure 6
shows the system level diagram for
reference.
October 7, 1987
(4,12)
CIN3
2.2µF
BUFFER
3.3k
R2
CR
10µF
CA
1µF
(3,13)
(8)
VCC
(16)
Figure 5. Basic Compressor Schematic
8
Philips Semiconductors RF Communications Products
Product specification
Programmable analog compandor
NE/SA572
1
2
VRMS
3.0V
2
REL LEVEL
COMPRESSION
IN
EXPANDOR
OUT
INPUT TO ∆G
AND RECT
ABS LEVEL
dBM
+29.54
+11.76
+14.77
+12.0
–3.00
–5.78
100MV
0.0
–17.78
10MV
–20
–37.78
1MV
–40
–57.78
100µV
–60
–77.78
10µV
–80
–97.78
547.6MV
400MV
Figure 6. NE572 System Level
October 7, 1987
dB
9
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