SILABS C8051F023 25 mips, 64 kb flash, 10-bit adc, 64-pin mixed-signal mcu Datasheet

C8051F023
25 MIPS, 64 kB Flash, 10-Bit ADC, 64-Pin Mixed-Signal MCU
Analog Peripherals
High-Speed 8051 µC Core
-
10-Bit ADC
-
±1 LSB INL; no missing codes
Programmable throughput up to 100 ksps
8 external inputs; programmable as single-ended or differential
Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
Data-dependent windowed interrupt generator
Built-in temperature sensor (±3 °C)
-
Memory
-
8-Bit ADC
-
-
±1 LSB INL; no missing codes
Programmable throughput up to 500 ksps
8 external inputs
Programmable amplifier gain: 4, 2, 1, 0.5
-
Can synchronize outputs to timers for jitter-free waveform generation
Two Comparators
Internal Voltage Reference
VDD Monitor/Brown-out Detector
-
-
On-Chip JTAG Debug & Boundary Scan
-
4352 bytes data RAM
64 kB Flash; in-system programmable in 512-byte sectors (512 bytes
are reserved)
External parallel data memory interface
Digital Peripherals
Two 12-Bit DACs
-
Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
Up to 25 MIPS throughput with 25 MHz system clock
22 vectored interrupt sources
On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
Provides breakpoints, single stepping, watchpoints, stack monitor
Inspect/modify memory and registers
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
IEEE1149.1 compliant boundary scan
32 port I/O; all are 5 V tolerant
Hardware SMBus™ (I2C™ compatible), SPI™, and two UART serial
ports available concurrently
Programmable 16-bit counter/timer array with 5 capture/compare modules
5 general-purpose 16-bit counter/timers
Dedicated watchdog timer; bidirectional reset
Real-time clock mode using Timer 3 or PCA
Clock Sources
-
Internal programmable oscillator: 2–16 MHz
External oscillator: Crystal, RC, C, or Clock
Can switch between clock sources on-the-fly
Supply Voltage: 2.7 to 3.6 V
-
Typical operating current: 10 mA at 25 MHz
Multiple power saving sleep and shutdown modes
64-Pin TQFP
Temperature Range: –40 to +85 °C
VDD
VDD
VDD
DGND
DGND
DGND
AV+
Port I/O
Config.
Digital Power
8
0
5
1
Analog Power
AGND
TCK
TMS
TDI
TDO
Boundary Scan
JTAG
Logic
Debug HW
Reset
RST
MONEN
VDD
Monitor
XTAL1
XTAL2
External
Oscillator
Circuit
C
o
r
e
WDT
System
Clock
Internal
Oscillator
VREF
VREF
DAC1
DAC1
(12-Bit)
DAC0
DAC0
(12-Bit)
CP0+
CP0CP1+
CP1-
UART1
C
R
O
S
S
B
A
R
SMBus
SPI Bus
PCA
SFR Bus
64 kB
FLASH
256 Byte
RAM
4 kB
RAM
Timers 0,
1, 2, 4
Timer 3/
RTC
P0, P1,
P2, P3
Latches
A
M
U
X
Prog
Gain
TEMP
SENSOR
P0
Drv
P0.0
P1
Drv
P1.0/AIN1.0
P2
Drv
P2.0
P3
Drv
P3.0
P0.7
P1.7/AIN1.7
P2.7
P3.7
Crossbar
Config.
REFADC
VDD
ADC
500 ksps
(8-Bit)
Prog
Gain
A
M
U
X
8:1
External Data Memory Bus
Bus Control
C
T
L
(REFADC)
VREFA
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
UART0
ADC
100 ksps
(10-Bit)
Address Bus
Data Bus
CP0
A
d
d
r
D
a
t
a
P4 Latch
P4
DRV
P5 Latch
P5
DRV
P6 Latch
P6
DRV
P7 Latch
P7
DRV
CP1
Precision Mixed Signal
Copyright © 2004 by Silicon Laboratories
6.15.2004
C8051F023
25 MIPS, 64 kB Flash, 10-Bit ADC, 64-Pin Mixed-Signal MCU
Selected Electrical Specifications
(TA = –40 to +85 C°, VDD = 2.7 V unless otherwise specified)
PARAMETER
CONDITIONS
GLOBAL CHARACTERISTICS
Digital Supply Voltage
Clock = 25 MHz
Digital Supply Current
Clock = 1 MHz
with CPU active
Clock = 32 kHz; VDD Monitor Disabled
(VDD = 2.7 V)
Digital Supply Current
Oscillator not running; VDD Monitor
(shutdown)
Enabled
Oscillator not running; VDD Monitor
Disabled
Digital Supply RAM Data
Retention Voltage
CPU & DIGITAL I/O PORTS
Clock Frequency Range
Port Output High Voltage
IOH = -3 mA, Port I/O push-pull
Port Output Low Voltage
IOL = 8.5 mA
Input High Voltage
Input Low Voltage
A/D CONVERTER
Resolution
Integral Nonlinearity
Differential Nonlinearity
Guaranteed Monotonic
Signal-to-Noise Plus
Distortion
Throughput Rate
Input Voltage Range
COMPARATORS
Response Time
| (CP+) – (CP-) | = 100 mV
Input Voltage Range
Input Bias Current
Input Offset Voltage
MIN
TYP
MAX
UNITS
3.6
10
0.8
20
10
V
mA
mA
µA
µA
0.1
µA
1.5
V
2.7
DC
VDD – 0.7
25
0.6
0.7 x VDD
0.3 x VDD
10
±1
±1
bits
LSB
LSB
dB
100
VREF
ksps
V
VDD + 0.25
+5
+10
µs
V
nA
mV
59
0
4
–0.25
–5
–10
0.001
MHz
V
V
V
V
C8051F020DK Development Kit
Package Information
D
D1
MIN NOM MAX
(mm) (mm) (mm)
A
E1
E
-
1.20
A1 0.05
-
0.15
A2 0.95
-
1.05
b
64
PIN 1
DESIGNATOR
1
A2
e
A
b
Precision Mixed Signal
-
0.17 0.22 0.27
D
-
12.00
-
D1
-
10.00
-
e
-
0.50
-
E
-
12.00
-
E1
-
10.00
-
A1
Copyright © 2004 by Silicon Laboratories
6.15.2004
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