LAN9313/LAN9313i Three Port 10/100 Managed Ethernet Switch with MII PRODUCT FEATURES Data Brief Highlights High performance and full featured 3 port switch with VLAN, QoS packet prioritization, Rate Limiting, IGMP monitoring and management functions Serial management via SPI/I2C or SMI Unique Virtual PHY feature simplifies software development by mimicking the multiple switch ports as a single port PHY Integrated IEEE 1588 Hardware Time Stamp Unit — Port mirroring/monitoring/sniffing: ingress and/or egress traffic on any ports or port pairs — Fully compliant statistics (MIB) gathering counters — Control registers configurable on-the-fly Cable, satellite, and IP set-top boxes Digital televisions Digital video recorders VoIP/Video phone systems Home gateways Test/Measurement equipment Industrial automation systems Ethernet Switch Fabric — 32K buffer RAM — 1K entry forwarding table — Port based IEEE 802.1Q VLAN support (16 groups) – Programmable IEEE 802.1Q tag insertion/removal — IEEE 802.1d spanning tree protocol support — QoS/CoS Packet prioritization – 4 dynamic QoS queues per port – Input priority determined by VLAN tag, DA lookup, TOS, DIFFSERV or port default value – Programmable class of service map based on input priority – Remapping of 802.1Q priority field on per port basis – Programmable rate limiting at the ingress/egress ports with random early discard, per port / priority — IGMP v1/v2/v3 monitoring for Multicast packet filtering — Programmable filter by MAC address SMSC LAN9313/LAN9313i 2 internal 10/100 PHYs with HP Auto-MDIX support 1 MII - PHY mode or MAC mode Fully compliant with IEEE 802.3 standards 10BASE-T and 100BASE-TX support Full and half duplex support Full duplex flow control Backpressure (forced collision) half duplex flow control Automatic flow control based on programmable levels Automatic 32-bit CRC generation and checking 2K Jumbo packet support Programmable interframe gap, flow control pause value Full transmit/receive statistics Auto-negotiation Automatic MDI/MDI-X Loop-back mode Serial Management — SPI/I2C (slave) access to all internal registers — MIIM (MDIO) access to PHY related registers — SMI (extended MIIM) access to all internal registers Key Benefits Ports — — — — — — — — — — — — — — — Target Applications Switch Management IEEE 1588 Hardware Time Stamp Unit — Global 64-bit tunable clock — Master or slave mode per port — Time stamp on TX or RX of Sync and Delay_req packets per port, Timestamp on GPIO — 64-bit timer comparator event generation (GPIO or IRQ) Other Features — General Purpose Timer — Serial EEPROM interface (I2C master or MicrowireTM master) for non-managed configuration — Programmable GPIOs/LEDs Single 3.3V power supply Available in Commercial & Industrial Temp. Ranges PRODUCT PREVIEW Revision 1.9 (03-13-12) Three Port 10/100 Managed Ethernet Switch with MII Order Number(s): LAN9313-NU For 128-Pin, VTQFP Lead-Free RoHS Compliant Package (0 TO 70°C Temp Range) LAN9313-NZW For 128-Pin, XVTQFP Lead-Free RoHS Compliant Package (0 TO 70°C Temp Range) LAN9313i-NZW For 128-Pin, XVTQFP Lead-Free RoHS Compliant Package (-40 TO 85°C Temp Range) LAN9313-NU-TR For 128-Pin, VTQFP Lead-Free RoHS Compliant Package (0 TO 70°C Temp Range) LAN9313-NZW-TR For 128-Pin, XVTQFP Lead-Free RoHS Compliant Package (0 TO 70°C Temp Range) LAN9313i-NZW-TR For 128-Pin, XVTQFP Lead-Free RoHS Compliant Package (-40 TO 85°C Temp Range) TR indicates tape & reel option. This product meets the halogen maximum concentration values per IEC61249-2-21 For RoHS compliance and environmental information, please visit www.smsc.com/rohs Copyright © 2012 SMSC or its subsidiaries. All rights reserved. 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Revision 1.9 (03-13-12) 2 PRODUCT PREVIEW SMSC LAN9313/LAN9313i Three Port 10/100 Managed Ethernet Switch with MII General Description The LAN9313/LAN9313i is a full featured, 3 port 10/100 managed Ethernet switch designed for embedded applications where performance, flexibility, ease of integration and system cost control are required. The LAN9313/LAN9313i combines all the functions of a 10/100 switch system, including the switch fabric, packet buffers, buffer manager, media access controllers (MACs), PHY transceivers, and serial management. The LAN9313/LAN9313i complies with the IEEE 802.3 (full/half-duplex 10BASET and 100BASE-TX) Ethernet protocol specification and 802.1D/802.1Q network management protocol specifications, enabling compatibility with industry standard Ethernet and Fast Ethernet applications. At the core of the LAN9313/LAN9313i is the high performance, high efficiency 3 port Ethernet switch fabric. The switch fabric contains a 3 port VLAN layer 2 switch engine that supports untagged, VLAN tagged, and priority tagged frames. The switch fabric provides an extensive feature set which includes spanning tree protocol support, multicast packet filtering and Quality of Service (QoS) packet prioritization by VLAN tag, destination address, port default value or DIFFSERV/TOS, allowing for a range of prioritization implementations. 32K of buffer RAM allows for the storage of multiple packets while forwarding operations are completed, and a 1K entry forwarding table provides ample room for MAC address forwarding tables. Each port is allocated a cluster of 4 dynamic QoS queues which allow each queue size to grow and shrink with traffic, effectively utilizing all available memory. This memory is managed dynamically via the buffer manager block within the switch fabric. All aspects of the switch fabric are managed via the switch fabric configuration and status registers, which are indirectly accessible via the system control and status registers. The LAN9313/LAN9313i provides 3 switched ports. Each port is fully compliant with the IEEE 802.3 standard and all internal MACs and PHYs support full/half duplex 10BASE-T and 100BASE-TX operation. The LAN9313/LAN9313i provides 2 on-chip PHYs, 1 Virtual PHY and 3 MACs. The Virtual PHY and the third MAC are used to connect the LAN9313/LAN9313i switch fabric to an external MAC or PHY. All ports support automatic or manual full duplex flow control or half duplex backpressure (forced collision) flow control. 2K jumbo packet (2048 byte) support allows for oversized packet transfers, effectively increasing throughput while deceasing CPU load. All MAC and PHY related settings are fully configurable via their respective registers within the LAN9313/LAN9313i. The integrated SPI, I 2 C and SMI slave controllers allow for full serial management of the LAN9313/LAN9313i via the integrated SPI/I 2C serial interface or MII interface respectively. The inclusion of these interfaces allows for greater flexibility in the incorporation of the LAN9313/LAN9313i into various designs. It is this flexibility which allows the LAN9313/LAN9313i to operate in 2 different modes and under various management conditions. In MAC mode, the LAN9313/LAN9313i can be connected to an external PHY via the MII interface. In PHY mode, the LAN9313/LAN9313i can be connected to an external MAC via the MII interface. In both MAC and PHY modes, the LAN9313/LAN9313i can be unmanaged, SMI managed, I2C managed or SPI managed. This flexibility in management makes the LAN9313/LAN9313i a candidate for virtually all switch applications. The LAN9313/LAN9313i contains an I2C/Microwire master EEPROM controller for connection to an optional EEPROM. This allows for the storage and retrieval of static data. The internal EEPROM Loader can be optionally configured to automatically load stored configuration settings from the EEPROM into the LAN9313/LAN9313i at reset, allowing the LAN9313/LAN9313i to operate unmanaged. In addition to the primary functionality described above, the LAN9313/LAN9313i provides additional features designed for extended functionality. These include a configurable 16-bit General Purpose Timer (GPT), a 32-bit 25MHz free running counter, a 12-bit configurable GPIO/LED interface, and IEEE 1588 time stamping on all ports and select GPIOs. The IEEE time stamp unit provides a 64-bit tunable clock for accurate PTP timing and a timer comparator to allow time based interrupt generation. The LAN9313/LAN9313i’s performance, features and small size make it an ideal solution for many applications in the consumer electronics and industrial automation markets. Targeted applications include: set top boxes (cable, satellite and IP), digital televisions, digital video recorders, voice over IP and video phone systems, home gateways, and test and measurement equipment. System-level and block-level diagrams of the LAN9313/LAN9313i can be seen in on the following pages. SMSC LAN9313/LAN9313i 3 PRODUCT PREVIEW Revision 1.9 (03-13-12) Three Port 10/100 Managed Ethernet Switch with MII System Level Block Diagrams I2C/Microwire To Ethernet Magnetics LAN9313/LAN9313i EEPROM (optional) External 25MHz Crystal To Ethernet Magnetics GPIOs/LEDs (optional) MII To Ethernet Magnetics 10/100 PHY Figure 1 System Level Block Diagram Utilizing the LAN9313/LAN9313i in MAC Mode I2C/Microwire To Ethernet Magnetics LAN9313/LAN9313i EEPROM (optional) External 25MHz Crystal To Ethernet Magnetics GPIOs/LEDs (optional) MII MIIM 10/100 MAC Figure 2 System Level Block Diagram Utilizing the LAN9313/LAN9313i in PHY Mode Revision 1.9 (03-13-12) 4 PRODUCT PREVIEW SMSC LAN9313/LAN9313i Three Port 10/100 Managed Ethernet Switch with MII Internal Block Diagram IEEE 1588 Time Stamp To Ethernet 10/100 PHY IEEE 1588 Time Stamp To Ethernet 10/100 PHY IEEE 1588 Clock & Events IEEE 1588 Time Stamp 10/100 MAC SMI (slave) Controller 10/100 MAC SPI (slave) I2C (slave) Controller Switch Fabric 10/100 MAC MII/MDIO To optional PHY, MAC, or SMI Master SPI / I2C To optional CPU serial management (via I2C/SPI slave) EEPROM Controller I2C / Microwire 2 I C (master) Microwire (master) Secondary Functions (Timers,GPIOs,LEDs,IRQ) To optional EEPROM (via I2C/Microwire master) LAN9313/LAN9313i Figure 3 LAN9313/LAN9313i Internal Block Diagram SMSC LAN9313/LAN9313i 5 PRODUCT PREVIEW Revision 1.9 (03-13-12) Three Port 10/100 Managed Ethernet Switch with MII 128-VTQFP Package Outline Figure 4 LAN9313 128-VTQFP Package Definition Table 1 LAN9313 128-VTQFP Dimensions MIN NOMINAL MAX REMARKS A - - 1.20 Overall Package Height A1 0.05 - 0.15 Standoff A2 0.95 1.00 1.05 Body Thickness D/E 15.80 16.00 16.20 X/Y Span D1/E1 13.80 14.00 14.20 X/Y Plastic Body Size L 0.45 0.60 0.75 Lead Foot Length b 0.13 0.18 0.23 Lead Width c 0.09 - 0.20 Lead Foot Thickness e 0.40 BSC Lead Pitch ddd 0.00 - 0.07 True Position Spread ccc - - 0.08 Coplanarity Revision 1.9 (03-13-12) 6 PRODUCT PREVIEW SMSC LAN9313/LAN9313i Three Port 10/100 Managed Ethernet Switch with MII Notes: 1. All dimensions are in millimeters unless otherwise noted. 2. 3. 4. Dimensions b & c apply to the flat section of the lead foot between 0.10 and 0.25mm from the lead tip. The base metal is exposed at the lead tip. Dimensions D1 and E1 do not include mold protrusions. Maximum allowed protrusion is 0.25mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. The pin 1 identifier may vary, but is always located within the zone indicated. Figure 5 LAN9313 128-VTQFP Recommended PCB Land Pattern SMSC LAN9313/LAN9313i 7 PRODUCT PREVIEW Revision 1.9 (03-13-12) Three Port 10/100 Managed Ethernet Switch with MII 128-XVTQFP Package Outline Figure 6 LAN9313/LAN9313i 128-XVTQFP Package Definition Revision 1.9 (03-13-12) 8 PRODUCT PREVIEW SMSC LAN9313/LAN9313i Three Port 10/100 Managed Ethernet Switch with MII Table 2 LAN9313/LAN9313i 128-XVTQFP Dimensions MIN NOMINAL MAX REMARKS A - - 1.20 Overall Package Height A1 0.05 - 0.15 Standoff A2 0.95 1.00 1.05 Body Thickness D/E 15.80 16.00 16.20 X/Y Span D1/E1 13.80 14.00 14.20 X/Y Plastic Body Size D2/E2 6.35 6.50 6.65 X/Y Exposed Pad Size L 0.45 0.60 0.75 Lead Foot Length b 0.13 0.18 0.23 Lead Width c 0.09 - 0.20 Lead Foot Thickness e 0.40 BSC Lead Pitch ddd 0.00 - 0.07 True Position Spread ccc - - 0.08 Coplanarity Notes: 1. All dimensions are in millimeters unless otherwise noted. 2. 3. 4. 5. Dimensions b & c apply to the flat section of the lead foot between 0.10 and 0.25mm from the lead tip. The base metal is exposed at the lead tip. Dimensions D1 and E1 do not include mold protrusions. Maximum allowed protrusion is 0.25mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. Dimensions D2 and E2 represent the size of the exposed pad. The exposed pad shall be coplanar with the bottom of the package within 0.05mm. The pin 1 identifier may vary, but is always located within the zone indicated. Figure 7 LAN9313/LAN9313i 128-XVTQFP Recommended PCB Land Pattern SMSC LAN9313/LAN9313i 9 PRODUCT PREVIEW Revision 1.9 (03-13-12)