ICST M2004-02-690.5692 Frequency synthesizer Datasheet

Micro Networks
M2004-02
An Integrated Circuit Systems Company
Preliminary Specifications
M2004-02
Frequency Synthesizer
DESCRIPTION
The M2004-02 integrates a high performance Phase
Locked Loop (PLL) with a Voltage Controlled SAW
Oscillator (VCSO) to provide a low jitter Frequency
Synthesizer in a 9mm x 9mm surface mount
package.
The internal high “Q” SAW filter provides low jitter
signal performance and determines the maximum
output frequency of the VCSO.
A programmable output divider can divide the VCSO
frequency to achieve an output as low as 38.88MHz.
FEATURES
The input to the Frequency Synthesizer is provided
by selecting between a differential input clock or a
single ended input clock.
Output Clock Frequency up to 700MHz
Internal Low-jitter SAW-based Oscillator
The output frequency is an integer multiple of the
input reference frequency. The multiplying factor is
programmed via a 6 bit parallel address.
Intrinsic Jitter <1ps rms (12kHz - 20MHz)
Differential Input Compatible with LVPECL,
LVDS, HSTL, SSTL, etc.
An external loop filter sets the PLL bandwidth which
can be optimized to provide jitter attenuation of the
input reference clock.
Dual Input MUX
Parallel Programming
The bandwidth control, low phase noise, and HOLD
features make the M2004-02 ideal for use as a clock
jitter attenuator, frequency translator, and clock
frequency generator in OC-3 through OC-192
applications.
Tunable Loop Filter Response
Differential LVPECL Outputs
3.3V Operation
Small 9mm x 9mm SMT Package
APPLICATIONS
SONET / SDH / 10GbE System
Synchronization
Add / Drop Muxes, Access and Edge
Switches
Line Card System Clock Cleaner /
Translator
Optical Module Clock Cleaner / Translator
ISO 9001
Registered
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
1
fax: 508-852-8456
www.micronetworks.com
Micro Networks
M2004-02
Preliminary Specifications
An Integrated Circuit Systems Company
FUNCTIONAL BLOCK DIAGRAM
Functional Description:
The multiplying factor is programmed via a 6-bit
parallel bus.
The internal PLL will adjust the VCSO output
frequency to be M (feedback divider) times the
selected input reference clock frequency. Note that
the product of M x the input reference frequency
The relationship between the VCSO frequency, the
M divider, and the Differential Input reference clock
is defined as follows:
F VCSO = F REF_CLK x M
OP_IN
nOP_IN
OP_OUT
nOP_OUT
Vc
When the N output divider is included, the
complete relationship for the output frequency is
defined as:
nVc
DIF_REF 0
nDIF_REF 0
Mux
REF_CLK
REF_SEL
M5:M0
Phase
Detector &
Active Loop
Filter
Output
Divider
VCSO
FOUT = F VCSO = F REF_CLK x M
N
N
F OUT
nF OUT
The N1 input can be hard wired to set the N divider
to a specific state that will automatically occur
during power-up.
N1
+M
Parallel Programming Interface
MR
must be such that it falls within the “lock” range of
the VCSO. The N output divider can be
programmed to divide the VCSO output frequency
by 1, 2, 4, or 8 and provide a 50% output duty
cycle.
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
2
fax: 508-852-8456
www.micronetworks.com
Micro Networks
M2004-02
An Integrated Circuit Systems Company
Preliminary Specifications
FUNCTIONAL DESCRIPTION
LOOP FILTER
FIGURE 2
The M2004-02 requires the use of an external loop
filter via the provided filter pins. Due to the
differential design, the implementation requires two
identical RC filters as shown in Figure 2.
Rloop
Cloop
Rpost
nVc
OP_IN
Cpost
nOP_OUT
OP_OUT
Cpost
Vc
nOP_IN
Rloop
Cloop
Rpost
TABLE 1. RECOMMENDED LOOP FILTER VALUES
REF_CLK
Frequency
VCSO
Frequency
M
N
FOUT
Rloop
Cloop
Rpost
Cpost
19.44MHz
622.0800MHz
32
1
622.0800MHz
5kΩ
1MF
20kΩ
250pf
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
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fax: 508-852-8456
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Micro Networks
M2004-02
Preliminary Specifications
An Integrated Circuit Systems Company
PIN DESCRIPTIONS
TABLE 2
Pin Number
1, 2, 3
GND
Name
I/O
GND
Configuration
4, 9
OP_IN, nOP_IN
Analog I/O
Used for external loop filter. See Figure 2.
5, 8
nOP_OUT, OP_OUT
Analog I/O
Used for external loop filter. See Figure 2
6, 7
nVC, VC
Input
VCSO Differential Control Voltage Input Pair
10, 14, 26
GND
GND
Power Supply Ground
11, 19, 33
VCC
Power
Positive Supply Pins
12, 13
N0, N1
Input
Pull - down
Description
Power Supply Ground
Determines the output divider value as
defined in Table 3C. LVCMOS / LVTTL
interface levels.
15, 16
FOUT, nFOUT
Output
Unterminated
Differential output, 3.3V LVPECL levels.
17
MR
Input
Pull - down
Logic HIGH resets the reference frequency and N
output dividers. Logic LOW enables the outputs.
LVCMOS / LVTTL interface levels.
18, 20, 21
NC
22
REF_SEL
No Connection
Input
Pull - down
Selects between the different reference clock
inputs as the PLL reference source. See table 3D.
LVCMOS / LVTTL interface levels.
23
NDIF_REF
Input
Pull - down
Inverting differential clock input. Compatible
logic levels include LVCMOS, LVDS, HSTL, etc.
24
DIF_REF
Input
Pull - down
Non-inverting differential clock input. Compatible
logic levels include LVCMOS, LVDS, HSTL, etc.
25
REF_ CLK
Input
Pull - down
Input reference clock. LVCMOS / LVTTL interface
levels.
27, 28, 29, 30, 31
M0, M1, M2, M3, M4 Input
Pull - down
M divider inputs. Data is always transparent. No
latch signal is required.
32
M5
34, 35, 36
DNC
Micro Networks
324 Clark Street
Input
Pull - down
Do not connect. Internal test pins.
Worcester, MA 01606
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Micro Networks
M2004-02
An Integrated Circuit Systems Company
Preliminary Specifications
PIN CHARACTERISTICS
TABLE 4
Symbol
CIN
Parameter
Input Capacitance
Test Conditions
Min
Typical
Max
Units
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
PARALLEL & SERIAL MODES FUNCTION
TABLE 5A
MR
Inputs
M
N
Conditions
H
X
X
Reset, Forces outputs LOW.
L
Data
Data
Data on M and N inputs passed directly to the M divider and N output divider.
Note: L = Low; H = High; X = Don’t care; ↑ = Rising Edge Transition; ↓ = Falling Edge Transition
PROGRAMMABLE VCSO FREQUENCY FUNCTION
TABLE 5B
13
32
M5
0
16
M4
0
8
M3
1
4
M2
1
2
M1
0
1
M0
1
350
14
0
0
1
1
1
0
375
15
0
0
1
1
1
1
400
16
0
1
0
0
0
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
600
24
0
1
1
0
0
0
625
25
0
1
1
0
0
1
650
26
0
1
1
0
1
0
VCSO Frequency
(MHz)
M Divide
325
NOTE 1: These M divide values and the resulting frequencies correspond to a reference frequency of 25MHz.
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
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fax: 508-852-8456
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Micro Networks
M2004-02
Preliminary Specifications
An Integrated Circuit Systems Company
PARALLEL MODE FUNCTION
SERIAL MODE FUNCTION
TABLE 5D
TABLE 5C
Inputs N Divider Output Frequency (MHz)
N1 N0
Value
Min
Max
Inputs
REF SEL
Reference
0
0
1
311
700
0
DIFF_REF
0
1
2
155.5
350
1
REF_CLK
1
0
4
77.75
175
1
1
8
38.875
87.5
POWER SUPPLY DC CHARACTERISTICS
Symbol
Parameter
Test Conditions
VDD
Power Supply Voltage
IDD
Power Supply Current
Min
Typ
Max
Units
3.135
3.3
3.465
V
162
mA
VCC= 3.3V ± 5%, TA= 0°C to 70°C
DIFFERENTIAL INPUT DC CHARACTERISTICS
Symbol
IIH
IIL
Parameter
Test Conditions
Min
Max
Units
Input High
nDIF_REF
5
µA
Current
DIF_REF
150
µA
Input Low
nDIF_REF
-150
µA
Current
DIF_REF
-5
µA
0.15
V
VP-P
Peak to Peak Input Voltage
VCMR
REF_SEL, REF_CLK
VCC +0.3 VCC -0.85
V
VCC = 3.3V ± 5%, TA = 0°C to 70°C
LVCMOS/LVTTL DC CHARACTERISTICS
Symbol
VIH
VIL
IIH
Parameter
Test Conditions
Min
Max
Units
2
VCC + 0.3
V
-0.3
1.3
V
Input High
REF_SEL, REF_CLK,
Voltage
N0:N1, M0:M5, MR
Input Low
REF_SEL, N0:N1, M0:M5, MR
Voltage
REF_CLK
Input High
M5
VDD = VIN = 3.465V
5
µA
Current
N0, N1, MR, M0:M4, S_CLOCK,
VDD = VIN = 3.465V
150
µA
REF_SEL, REF_CLK
IIL
Input Low
M5
VDD = 3.465, VIN = 0V
-150
µA
Current
N0, N1, MR, M0:M4,
VDD = 3.465, VIN = 0V
-5
µA
REF_SEL, REF_CLK
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Micro Networks
M2004-02
An Integrated Circuit Systems Company
Preliminary Specifications
LVPECL DC CHARACTERISTICS
Symbol
Parameter
Signal
Min
Max
Units
VOH
Output High Voltage: Note 1
FOUT, nFOUT
VDD – 1.4
Vcc – 1.0
V
VOL
Output Low Voltage: Note 1
FOUT, nFOUT
VDD – 2.0
Vcc – 1.7
V
Peak-to-Peak Output Voltage Swing
FOUT, nFOUT
0.6
0.85
V
VSWING
Note 1: Output terminated with 50Ω to VDD–2.V
INPUT FREQUENCY CHARACTERISTICS
Symbol
Parameter
FIN
Input Frequency
Test Conditions
Min
Max
Units
DIF_REF
10
175
MHz
nDIF_REF
10
175
MHz
VCC = 3.3V± 5%, TA = 0°C to 70°C
AC CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min
Typ
Output Frequency
ØNOISE
Single Side Band
1kHz offset
-72
dBc/Hz
Phase Noise
10kHz offset
-94
dBc/Hz
100kHz offset
-123
dBc/Hz
12kHz to 20 MHz
0.69
ps
50
%
Jitter (RMS)
odc
Output Duty Cycle
tR
(Note 1)
667
Units
FOUT
J (t)
38.88
Max
MHz
Output Rise Time
FOUT = 155MHz
20% to 80%, each
350
450
550
ps
for output pairs
FOUT = 311MHz
output of pair measured
325
425
500
ps
FOUT0, nFOUT0 &
FOUT= 622MHz
is terminated into 50Ω
200
275
350
ps
FOUT1, nFOUT1
load biased at Vcc-2V
tF
Output Fall Time
FOUT = 155MHz
20% to 80%, each
350
450
550
ps
(Note 1)
for output pairs
FOUT = 311MHz
output of pair measured
325
425
500
ps
FOUT0, nFOUT0 &
FOUT = 622MHz
is terminated into 50Ω
200
275
350
ps
1
ms
FOUT1, nFOUT1
tLOCK
load biased at Vcc-2V
PLL Lock Time
Note: The output frequencies of 155MHz, 311MHz and 622MHz were chosen for device characterization as these are common optical network clock frequencies.
Micro Networks
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tel: 508-852-5400
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fax: 508-852-8456
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Micro Networks
M2004-02
Preliminary Specifications
An Integrated Circuit Systems Company
PARAMETER MEASUREMENT INFORMATION
INPUT AND OUTPUT RISE AND FALL TIME
80%
80%
V
SWING
20%
20%
Clock Inputs
and Outputs
t
t
R
F
ODC & tPERIOD
Pulse Width
t
t
odc =
t
Micro Networks
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PERIOD
PW
PERIOD
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Micro Networks
M2004-02
An Integrated Circuit Systems Company
Preliminary Specifications
TEST EVALUATION BOARD
J3 9-PIN D
CONNECTOR
Pin
Signal
1
MR
3
SW1
Position
1
REF Select
2
M5
3
M4
4
M3
5
M2
6
M1
7
M0
8
N/C
S_CLOCK
Off
REF_CLK0
“1”
“0”
“0”
“0”
“0”
“0”
N/C
5
S_DATA
On
REF_CLK1
“0”
“1”
“1”
“1”
“1”
“1”
N/C
7
S_LOAD
9
nP_LOAD
Micro Networks
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JP1: N0
JP2: N1
Logic “1” when installed
Logic “0” when installed
Worcester, MA 01606
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Micro Networks
M2004-02
Preliminary Specifications
An Integrated Circuit Systems Company
MECHANICAL DIMENSIONS & PIN CONFIGURATION
.354 [9.0]
.110 [2.8]
#19
#27
#28
#18
.354 [9.0]
[ ]
#10
#36
ORIENTATION TAB
Pin #1
.200 [5.1]
.025 [0.6]
C
CL
.041 [1.0]
R.006 [R0.2]
.007 [0.2]
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Designation
GND
GND
GND
OP_IN
nOP_OUT
nVC
VC
OP_OUT
nOP_IN
GND
VCC
NO
N1
GND
FOUT
nFOUT
MR
Pin#
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34, 35, 36
Designation
N/C
VCC
N/C
N/C
REF_SEL
nDIF_REF
DIF_REF
REF_CLK
GND
M0
M1
M2
M3
M4
M5
VCC
DNC
Dimensions are in inches, (dimensions) are in mm.
ORDERING INFORMATION
PART NUMBER
M2004-02-622.0800
Series
Model
VCSO Center Frequency
(i.e. 622.0800MHz)
Available VCSO Frequencies
500.0000
622.0800
669.1281
625.0000
669.3266
627.3296
672.1600
644.5313
690.5692
666.5143
693.4830
Micro Networks makes no assertion or warranty that the circuitry and the uses thereof
disclosed herein are non-infringing on any valid US or foreign patents. Micro Networks
assumes no liability as a result of the use of said specifications and reserves the right to
make changes to specifications without notice. Contact your nearest Micro Networks
sales representative office for the latest specifications.
Micro Networks
An Integrated Circuit Systems Company
324 Clark Street Worcester, MA 01606 tel: 508-852-5400 fax: 508-852-8456
European Sales Headquarters Hertogsingel 20 6214 AD Maastricht The Netherlands tel: +31-43-32-70912 fax: +31-43-32-70715
Micro Networks 324 Clark Street Worcester, MA
01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.c2
Rev. 7.3
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