White Electronic Designs EDI88512CA-RP 512Kx8 Plastic Monolithic SRAM CMOS WEDC's ruggedized plastic 512Kx8 SRAM that allows the user to capitalize on the cost advantage of using a plastic component while not sacrificing all of the reliability available in a full military device. FEATURES 512Kx8 bit CMOS Static Random Access Memory Extended temperature testing is performed with the test patterns developed for use on WEDC’s fully compliant 512Kx8 SRAMs. WEDC fully characterizes devices to determine the proper test patterns for testing at temperature extremes. This is critical because the operating characteristics of device change when it is operated beyond the commercial guarantee a device that operates reliably in the field at temperature extremes. Users of WEDC’s ruggedized plastic benefit from WEDC’s extensive experience in characterizing SRAMs for use in military systems. • Access Times of 17, 20, 25ns • Data Retention Function (LPA version) • Extended Temperature Testing • Data Retention Functionality Testing 36 lead JEDEC Approved Revolutionary Pinout • Plastic SOJ (Package 319) Single +5V (±10%) Supply Operation WEDC ensures Low Power devices will retain data in Data Retention mode by characterizing the devices to determine the appropriate test conditions. This is crucial for systems operating at -40°C or below and using dense memories such as 512Kx8s. WEDC’s ruggedized plastic SOJ is footprint compatible with WEDC’s full military ceramic 36 pin SOJ. FIG. 1 – PIN CONFIGURATION PIN Description TOP VIEW A0 A1 A2 A3 A4 CS# I/O0 I/O1 VCC VSS I/O2 I/O3 WE# A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36pin Revolutionary 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A18 A17 A16 A15 OE# I/O7 I/O6 VSS VCC I/O5 I/O4 A14 A13 A12 A11 A10 NC BLOCK DIAGRAM I/O0-7 Data Inputs/Outputs A0-18 Address Inputs WE# Write Enables CS# Chip Selects OE# Output Enable VCC Power (+5V ±10%) VSS Ground NC Not Connected Memory Array AØ-18 Address Buffer Address Decoder I/O Circuits I/OØ-7 WE# CS# OE# May 2004 Rev. 6 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs EDI88512CA-RP ABSOLUTE MAXIMUM RATINGS TRUTH TABLE Unit OE# CS# WE# Mode Output Power -0.5 to 7.0 V X H X Standby High Z Icc2, Icc3 H L H Output Deselect High Z Icc1 0 to +70 °C L H Data Out Icc1 °C L Read -40 to +85 X L L Write Data In Icc1 Parameter Voltage on any pin relative to Vss Operating Temperature TA (Ambient) Commercial Industrial Military -55 to +125 °C Storage Temperature, Plastic -65 to +150 °C Power Dissipation 1.5 W Output Current 20 mA Junction Temperature, TJ 175 °C RECOMMENDED OPERATING CONDITIONS Parameter NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Symbol Min Typ Max Unit V Supply Voltage VCC 4.5 5.0 5.5 Supply Voltage VSS 0 0 0 V Input High Voltage VIH 2.2 — VCC + 0.5 V Input Low Voltage VIL -0.3 — +0.8 V CAPACITANCE TA = +25°C Parameter Symbol Condition Max Unit Address Lines CI VIN = Vcc or Vss, f = 1.0MHz 6 pF Data Lines CO VIN = Vcc or Vss, f = 1.0MHz 8 pF These parameters are sampled, not 100% tested. DC CHARACTERISTICS VCC = 5V, VSS = 0V, -55°C ≤ TA ≤ +125°C Parameter Symbol Input Leakage Current Conditions Min Max Units 10 µA ILI VCC = 5.5, VIN = VSS to VCC Output Leakage Current ILO CS# = VIL, OE# = VIH, VOUT = VSS to VCC 10 µA Operating Supply Current ICC CS# = VIL, OE# = VIH, f = 5MHz, VCC = 5.5 180 mA 15 mA Standby Current ISB CS# = VIH, OE# = VIH, f = 5MHz, VCC = 5.5 Output High Volltage VOH IOH = -4.0mA, VCC = 4.5 Output Low Voltage VOL IOL = 8.0mA, VCC = 4.5 2.4 V 0.4 V NOTE: DC test conditions: VIL = 0.3V, VIH = VCC -0.3V AC TEST CONDITIONS Figure 1 Figure 2 Vcc 480Ω Q Vcc Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load 480Ω Q VSS to 3.0V 5ns 1.5V Figure 1 NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF (Figure 2) 255Ω May 2004 Rev. 6 30pF 255Ω 5pF 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs EDI88512CA-RP AC CHARACTERISTICS – READ CYCLE VCC = 5.0V, VSS = 0V, 0°C ≤ TA ≤ +70°C Parameter Symbol JEDEC Alt. Min 17ns tRC 17 20ns Max Min 25ns Max 20 Min Max 25 Units ns Read Cycle Time tAVAV Address Access Time tAVQV tAA 17 20 25 ns Chip Enable Access Time tELQV tACS 17 20 25 ns 10 ns 12 ns Chip Enable to Output in Low Z (1) tELQX tCLZ 3 Chip Disable to Output in High Z (1) tEHQZ tCHZ 0 Output Hold from Address Change tAVQX tOH 0 Output Enable to Output Valid tGLQV tOE Output Enable to Output in Low Z (1) tGLQX tOLZ 0 Output Disable to Output in High Z(1) tGHQZ tOHZ 0 3 7 3 0 8 0 ns 0 0 8 ns 10 0 7 0 0 8 0 Max Min ns 10 ns Max Units 1. This parameter is guaranteed by design but not tested. AC CHARACTERISTICS – WRITE CYCLE VCC = 5.0V, VSS = 0V, 0°C ≤ TA ≤ +70°C Parameter Symbol JEDEC Alt. Min 17ns 20ns Max Min 25ns Write Cycle Time tAVAV tWC 17 20 25 ns Chip Enable to End of Write tELWH tELEH tCW tCW 14 14 15 15 17 17 ns ns Address Setup Time tAVWL tAVEL tAS tAS 0 0 0 0 0 0 ns ns Address Valid to End of Write tAVWH tAVEH tAW tAW 14 14 15 15 17 17 ns ns Write Pulse Width tWLWH tWLEH tWP tWP 14 14 15 15 17 17 ns ns Write Recovery Time tWHAX tEHAX tWR tWR 0 0 0 0 0 0 ns ns Data Hold Time tWHDX tEHDX tDH tDH 0 0 0 0 0 0 ns ns Write to Output in High Z (1) tWLQZ tWHZ 0 Data to Write Time tDVWH tDVEH tDW tDW 8 8 10 10 12 12 ns ns Output Active from End of Write (1) tWHQX tWLZ 0 0 0 ns 8 0 8 0 10 ns 1. This parameter is guaranteed by design but not tested. May 2004 Rev. 6 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs EDI88512CA-RP FIG. 2 – TIMING WAVEFORM — READ CYCLE tAVAV ADDRESS tAVQV CS# tAVAV ADDRESS ADDRESS 1 ADDRESS 2 tAVQV tAVQX tELQV tELQX tEHQZ tGLQV tGLQX tGHQZ OE# DATA I/O DATA 1 DATA OUT DATA 2 READ CYCLE 2 (WE# HIGH) READ CYCLE 1 (WE# HIGH; OE#, CS# LOW) FIG. 3 – WRITE CYCLE — WE# CONTROLLED tAVAV ADDRESS tAVWH tELWH tWHAX CS# tAVWL tWLWH WE# tDVWH DATA IN tWHDX DATA VALID tWLQZ tWHQX HIGH Z DATA OUT WRITE CYCLE 1, WE# CONTROLLED FIG. 4 – WRITE CYCLE — CS# CONTROLLED tAVAV ADDRESS tAVEH tELEH WS32K32-XHX tEHAX CS# tAVEL tWLEH WE# tDVEH DATA IN tEHDX DATA VALID HIGH Z DATA OUT WRITE CYCLE 2, CS# CONTROLLED May 2004 Rev. 6 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs EDI88512CA-RP DATA RETENTION CHARACTERISTICS (EDI88512LPA ONLY) -55°C ≤ TA ≤ +125°C Characteristic Low Power Version only Sym Conditions Min Typ Max Units Data Retention Voltage Data Retention Quiescent Current VDD ICCDR VDD = 2.0V CS# ≥ VDD -0.2V 2 – – – – 2 V mA Chip Disable to Data Retention Time Operation Recovery Time TCDR TR VIN ≥ VDD -0.2V or VIN ≤ 0.2V 0 TAVAV – – – ns ns FIG. 5 – DATA RETENTION - CS# CONTROLLED Data Retention Mode 4.5V Vcc VDD 4.5V tCDR CS# tR CS# = VDD -0.2V DATA RETENTION, CS# CONTROLLED May 2004 Rev. 6 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs EDI88512CA-RP FIG. 6 – NORMALIZED OPERATING GRAPHS Write Pulse Width vs. Temp. ICC1 (20ns) vs Temp 14 13 Write Pulse Width (ns) 220 ICC1 (ma) 210 200 190 180 11 10 9 8 7 170 160 12 6 -55 25 -55 125 25 TAVQV vs. Temp ICC3 vs. Temp 10 22 TAVQV (ns) ICC3 (ma) 125 Temp. (C) Temp. (C) 1 20 18 190 16 0.1 14 12 0.01 -55 25 -55 125 25 125 Temp. (C) Temp. (C) ICCDR vs. Temp 10 Normalized curves are offered as a service to our customers. They are not to be construed as a guarantee of operating characterics. ICCDR (ma) 1 0.1 Characteristics of actual devices will vary. 0.01 0.001 -55 25 125 Temp. (C) IDR, 2V May 2004 Rev. 6 6 IDR, 3V White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs EDI88512CA-RP PACKAGE 319: 36 LEAD, PLASTIC SMALL OUTLINE J-LEAD (SOJ) 0.920 0.930 0.395 0.405 0.360 0.435 0.380 0.445 0.026 0.032 Pin 1 Indicator 0.148 max. 0.375 TYP. 0.050 TYP. 0.027 min. 0.015 0.021 ALL DIMENSIONS ARE IN INCHES ORDERING INFORMATION EDI 8 8 512 CA X X X WHITE ELECTRONIC DESIGNS SRAM ORGANIZATION, 512Kx8 TECHNOLOGY: CA = CMOS Standard Power LPA = Low Power ACCESS TIME (ns) PACKAGE TYPE: M = 36 lead Plastic SOJ DEVICE GRADE: B = MIL-STD-883 Compliant M = Military Screened I = Industrial C = Commercial May 2004 Rev. 6 -55°C to +125°C -40°C to +85°C 0°C to +70°C 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com