LT4275 LTPoE++/PoE+/PoE PD Controller Description Features n n n n n n n n n n n n n IEEE 802.3af/at and LTPoE++™ Powered Device (PD) Controller LTPoE++ Supports Power Levels Up to 90W LT4275A Supports All of the Following Standards: n LTPoE++ 38.7W, 52.7W, 70W and 90W n IEEE 802.3at 25.5W Compliant n IEEE 802.3af Up to 13W Compliant LT4275B is IEEE 802.3at/af Compliant LT4275C is IEEE 802.3af Compliant 100V Absolute Maximum Input Voltage Wide Junction Temperature Range (–40°C to 125°C) Overtemperature Protection Integrated Signature Resistor External Hot Swap™ N-Channel MOSFET for Lowest Power Dissipation and Highest System Efficiency Programmable Aux Power Support as Low as 9V Optional Support of Non-Standard Low Voltage PoE Available in 10-Lead MSOP and 3mm × 3mm DFN Packages The LT®4275 is a pin-for-pin compatible family of IEEE 802.3 and LTPoE++ powered device (PD) controllers. The LT4275A employs a proprietary LTPoE++ classification scheme, delivering 38.7W, 52.7W, 70W or 90W of power at the PD RJ45 connector. The LT4275A is fully compatible with IEEE 802.3. The LT4275B is an IEEE 802.3at compliant, Type 2 (PoE+) PD delivering up to 25.5W. The LT4275C is an IEEE 802.3af compliant, Type 1 (PoE) PD delivering up to 13W. The LT4275 internal charge pump provides an N-channel MOSFET solution, eliminating a larger and more costly P-channel MOSFET. A low RDS(ON) MOSFET also maximizes power delivery and efficiency, reduces power and heat dissipation, and eases thermal design. Startup inrush current is adjustable with an external capacitor. The LT4275 also includes a power good output, on-board signature resistor, undervoltage lockout, and thermal protection. The LT4275A/LT4275B drives a single opto-coupler to indicate the power level of the attached PSE. Pin-selectable support for non-standard low voltage operation is provided. Auxiliary power override is supported with the AUX pin. Applications n n n n High Power Wireless Data Systems Outdoor Security Camera Equipment Commercial and Public Information Displays High Temperature Industrial Applications The LT4275A can be configured to support all possible LTPoE++, 802.3at and 802.3af power levels with external component changes. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and LTPoE++ and Hot Swap are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical Application LTPoE++ 90W Powered Device Interface VAUX (9V TO 60V) DATA PAIR SPARE PAIR ~ + ~ – ~ + ~ + LT4275 Family CPORT MAX DELIVERED POWER LTPoE++ 90W FDMC86102 VPORT CPD 0.1µF 3.3k VIN 47nF VPORT HSGATE – PWRGD AUX RCLASS RCLASS++ RCLS RCLS++ HSSRC ISOLATED POWER SUPPLY RUN + VOUT – LT4275A GND IEEEUVLO T2P OPTO PSE TYPE (TO µP) LTPoE++ 70W LTPoE++ 52.7W LT4275 GRADE A B C l l l LTPoE++ 38.7W l 25.5W l l 13W l l l 4275 TA01a 4275f 1 LT4275 Absolute Maximum Ratings (Notes 1, 3) VPORT, HSSRC Voltages.......................... –0.3V to 100V HSGATE Current.................................................. ±20mA IEEEUVLO, RCLASS, RCLASS++ Voltages........ –0.3V to 8V (and ≤ VPORT) AUX Current......................................................... ±1.4mA T2P, PWRGD Voltage................................ –0.3V to 100V T2P, PWRGD Current................................................5mA Operating Junction Temperature Range (Note 4) LT4275AI/LT4275BI/LT4275CI...............–40°C to 85°C LT4275AH/LT4275BH/LT4275CH........ –40°C to 125°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10 sec.)................... 300°C Pin Configuration TOP VIEW IEEEUVLO 1 10 VPORT AUX 2 9 HSGATE RCLASS 3 RCLASS++/NC* 4 GND 5 11 GND TOP VIEW IEEEUVLO AUX RCLASS RCLASS++/NC* GND 8 HSSRC 7 PWRGD 6 T2P/NC* 1 2 3 4 5 10 9 8 7 6 VPORT HSGATE HSSRC PWRGD T2P/NC* MS PACKAGE 10-LEAD PLASTIC MSOP DD PACKAGE 10-LEAD (3mm × 3mm) PLASTIC DFN TJMAX = 150°C, θJC = 45°C/W TJMAX = 150°C, θJC = 5°C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB GND * RCLASS++ is not connected in the LT4275B/C versions. T2P is not connected in the LT4275C version. Order Information MAX PD POWER LEAD FREE FINISH TAPE AND REEL PART MARKING* LT4275AIDD#PBF LT4275AIDD#TRPBF LGBS 90W PACKAGE DESCRIPTION TEMPERATURE RANGE 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LT4275AHDD#PBF LT4275AHDD#TRPBF LGBS 90W 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LT4275AIMS#PBF LT4275AIMS#TRPBF LTGBT 90W 10-Lead Plastic MSOP –40°C to 85°C LT4275AHMS#PBF LT4275AHMS#TRPBF LTGBT 90W 10-Lead Plastic MSOP –40°C to 125°C LT4275BIDD#PBF LT4275BIDD#TRPBF LGBV 25.5W 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LT4275BHDD#PBF LT4275BHDD#TRPBF LGBV 25.5W 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LT4275BIMS#PBF LT4275BIMS#TRPBF LTGBW 25.5W 10-Lead Plastic MSOP –40°C to 85°C LT4275BHMS#PBF LT4275BHMS#TRPBF LTGBW 25.5W 10-Lead Plastic MSOP –40°C to 125°C LT4275CIDD#PBF LT4275CIDD#TRPBF LGBX 13W 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LT4275CHDD#PBF LT4275CHDD#TRPBF LGBX 13W 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LT4275CIMS#PBF LT4275CIMS#TRPBF LTGBY 13W 10-Lead Plastic MSOP –40°C to 85°C LT4275CHMS#PBF LT4275CHMS#TRPBF LTGBY 13W 10-Lead Plastic MSOP –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on nonstandard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 4275f 2 LT4275 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VPORT Operating Input Voltage At VPORT Pin l 23 60 V VSIG VPORT Signature Range At VPORT Pin l 1.5 10 V VCLASS VPORT Classification Range At VPORT Pin l 12.5 21 V VMARK VPORT Mark Range At VPORT Pin, Preceded by VCLASS l 5.6 10 V VPORT Aux Mode Range At VPORT Pin, AUX > VAUXT l 8 60 V 5.6 V 37 29 V V Signature/Class Hysteresis Window l 1.0 VRESET Reset Threshold l 2.6 VHSON Hot Swap Turn-On Voltage IEEEUVLO = 0V IEEEUVLO Open l l VHSOFF Hot Swap Turn-Off Voltage IEEEUVLO = 0V IEEEUVLO Open l l 30 21.5 l 3 Hot Swap On/Off Hysteresis Window V 35 27 31 22.5 V V V Supply Current Supply Current VPORT = HSSRC = 57V l Supply Current During Classification VPORT = 17.5V, RCLASS and RCLASS++ Open l 0.4 Supply Current During Mark Event VMARK l 0.5 VSIG (Note 2) l 23.7 l 5.8 l 1.32 2 mA 1.1 mA 2.2 mA 24.4 25.2 kΩ 8.3 11 kΩ 1.40 1.43 0.7 Signature and Classification Signature Resistance VRCLS Signature Resistance During Mark Event VMARK (Note 2) RCLASS/RCLASS++ Operating Voltage –10mA ≥ IRCLASS ≥ –36mA, VCLASS Classification Stability Time VPORT Step to 17.5V, RCLASS = 34.8Ω 2 l V ms Analog/Digital Interface VAUXT AUX Threshold l 6.1 6.3 AUX = 6.1V l IAUXH AUX Pin Hysteresis Current T2P Output Low 6.5 V 4 5.8 1mA Load (LT4275A/LT4275B Only) l 8 µA 0.8 V PWRGD Output Low 1mA Load l 0.8 V PWRGD Leakage Current PWRGD = 60V l 5 µA T2P Leakage Current T2P = 60V l 5 µA 27 µA 18 V Hot Swap Control IGPU HSGATE Pull-Up Current VHSGATE – VHSSRC = 5V, VPORT > 42V, Out of Pin l 18 VGOC HSGATE Open Circuit Voltage VHSGATE – VHSSRC, 0µA to 10µA Load with Respect to HSSRC l 10 HSGATE Pull-Down Current VHSGATE – VHSSRC = 5V l 200 T2P Frequency After PWRGD Valid, if LTPoE++ PSE Is Mutually Identified l 690 22 µA Timing fT2P Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Signature resistance specifications do not include resistance added by the external diode bridge which can add as much as 1.1k to the port resistance. 840 990 Hz Note 3: All voltages with respect to GND unless otherwise noted. Positive currents are into pins; negative currents are out of pins unless otherwise noted. Note 4: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 150°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. 4275f 3 LT4275 Typical Performance Characteristics VPORT Current vs VPORT Voltage 25k Detection Range 37 T = –40°C T = 25°C T = 75°C T = 125°C 0.3 0.2 35 34 33 32 2 4 6 VPORT VOLTAGE (V) 8 30 –50 10 –25 0 25 50 75 TEMPERATURE (°C) 4275 G01 24.25 5 7 VPORT VOLTAGE (V) Hot Swap OFF –25 0 25 50 75 TEMPERATURE (°C) 2 3 CURRENT (mA) 4 5 4275 G07 –25 0 25 50 75 TEMPERATURE (°C) 125 T2P Frequency 990 DETECT OR MARK TO CLASS CLASS TO MARK 940 11.5 11.0 10.0 –50 100 4275 G06 T2P FREQUENCY (Hz) VOLTAGE (V) VPORT VOLTAGE (V) 1 2.6 –50 125 10.5 0 3.6 3.1 12.0 1 0 100 4.1 VPORT Classification Thresholds T = –40°C T = 25°C T = 75°C T = 125°C 60 4.6 4275 G05 12.5 55 5.1 24.5 21.5 –50 9 2 45 50 VPORT VOLTAGE (V) Reset Threshold 26.0 PWRGD, T2P Output Low Voltage vs Current 3 40 5.6 4275 G04 4 35 4275 G03 Hot Swap ON 23.0 3 0 125 VPORT VOLTAGE (V) VPORT VOLTAGE (V) SIGNATURE RESISTANCE (kΩ) 24.75 1 100 IEEEUVLO = FLOAT 27.5 25.25 23.75 0.5 VPORT Hot Swap Thresholds 29.0 T = –40°C T = 25°C T = 75°C T = 125°C 25.75 1.0 4275 G02 Signature Resistance vs Input Voltage 26.25 1.5 Hot Swap OFF 31 0 T = –40°C T = 25°C T = 75°C T = 125°C Hot Swap ON 0.1 0 Supply Current During Power-On 2.0 IEEEUVLO = 0V 36 VPORT VOLTAGE (V) 0.4 VPORT CURRENT (mA) VPORT Hot Swap Thresholds SUPPLY CURRENT (mA) 0.5 890 840 790 740 –25 0 25 50 75 TEMPERATURE (°C) 100 125 4275 G08 690 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 4275 G09 4275f 4 LT4275 Pin Functions IEEEUVLO (Pin 1): Hot Swap Turn-on Threshold Level Control. Connect to ground for IEEE compliant turn-on and turn-off (UVLO) voltage thresholds. Leave open for lower turn-on and turn-off voltage thresholds. AUX (Pin 2): Auxiliary Sense. Assert AUX via a resistive divider from the auxiliary power input to set the voltage at which the auxiliary supply takes over. Asserting AUX pulls down HSGATE, disconnects the signature resistor, disables classification and floats the PWRGD pin. The AUX pin sinks IAUXH when below its threshold voltage of VAUXT to provide hysteresis. Tie to GND when not used. RCLASS (Pin 3): Programmable PoE Classification Resistor. See Table 1. RCLASS++ (Pin 4, LT4275A Only): Programmable LTPoE++ Classification Resistor. This pin is not connected on the LT4275B/LT4275C. See Table 1. GND (Pin 5): Ground Pin. Must be soldered to PCB GND. T2P (Pin 6, LT4275A/LT4275B Only): PSE Type Indicator, Open-Drain Output. T2P floats for a 13W PSE. T2P pulls down for a 25.5W PSE. T2P pulls down at fT2P with a 50% (typical) duty cycle to indicate the presence of an LTPoE++ PSE. T2P is valid after PWRGD is active. This pin is not connected on the LT4275C. See the Applications Information section for behavior when using the AUX pin. PWRGD (Pin 7): Power Good Indicator, Open-Drain Output. Pulls down during VCLASS and inrush. HSSRC (Pin 8): External Hot Swap MOSFET Source. Connect to source of the external MOSFET. HSGATE (Pin 9): External Hot Swap MOSFET Gate Control, Output. Connect to gate of the external MOSFET. VPORT (Pin 10): PD interface upper power rail and external Hot Swap MOSFET drain connection. Exposed Pad (Pin 11, DFN Package Only): GND. Must be soldered to PCB GND. Block Diagram VPORT VPORT VOLTAGE AND CURRENT REFERENCES PWRGD IEEEUVLO CONTROL LOGIC HSGATE CHARGE PUMP ON VGOC AUX 6.3V + – OVERTEMP VPORT 1.4V + EN – CLASSIFICATION LOGIC RCLASS HSSRC T2P VPORT EN + – 1.4V RCLASS++ GND 4275 BD 4275f 5 LT4275 Applications Information Overview VHSON VHSOFF CLASS VPORT Power over Ethernet (PoE) continues to gain popularity as products take advantage of DC power and high speed data available from a single RJ45 connector. Powered device (PD) equipment vendors are running into the 25.5W power limit established by the IEEE 802.3 standard. The LT4275A allows higher power while maintaining backwards compatibility with existing PSE systems. The LT4275 utilizes a low RDS(ON) N-channel MOSFET to maximize efficiency and delivered power. Heat is also reduced, easing thermal design. POWER ON VSIGMAX Detection During detection, the PSE looks for a 25kΩ signature resistor which identifies the device as a PD. The PSE will apply two voltages in the range of 2.8V to 10V and measure the corresponding currents. Figure 1 shows the detection voltages. The PSE calculates the signature resistance using a ∆V/∆I measurement technique. The LT4275 presents its precision, temperature-compensated 24.4k resistor between the VPORT and GND pins, allowing the PSE to recognize a PD is present and requesting power to be applied. The LT4275 signature resistor is smaller than 25k to compensate for the additional series resistance introduced by the IEEE required bridge. DETECT VRESET VSIGMIN Modes of Operation The LT4275 has several modes of operation depending on the input voltage sequence applied to the VPORT pin. These modes include 25kΩ signature detection, classification, mark, inrush and powered on. VCLASSMIN 4275 F01 Figure 1. Type 1 Detect/Class Signaling Waveform A Type 2 PSE may declare the availability of high power by performing 2-event (Physical Layer) classification or by communicating over the (Data Link Layer) high speed data line. A Type 2 PD must recognize both types of communication. Since Layer 2 communications takes place directly between the PSE and the PD application, the LT4275A/LT4275B responsibility ends with supporting 2-event classification. In 2-event classification, a Type 2 PSE probes for power classification twice as shown in Figure 2. The LT4275A or LT4275B recognizes this and pulls the T2P pin down to signal the load that Type 2 power is available. If an LT4275A senses an LTPoE++ PSE it alternates between pulling T2P down and floating T2P at a rate of fT2P. POWER ON VHSON VHSOFF 1ST CLASS 2ND CLASS The detection/classification process varies depending on whether the PSE is Type 1, Type 2, or LTPoE++. A Type 2 PSE may use Type 1 classification signaling and later renegotiate a higher power classification with the PD over the data layer. A Type 1 PSE, after a successful detection, may apply a classification probe voltage of 15.5V to 20.5V and measure current. VPORT Classification VCLASSMIN VSIGMAX VRESET VSIGMIN DETECT 1ST MARK 2ND MARK 4275 F01 Figure 2. Type 2 Detect/Class Signaling Waveform 4275f 6 LT4275 Applications Information Table 1. Classification Codes, Power Levels and Resistor Selection PD POWER NOMINAL CLASS CLASS AVAILABLE PD TYPE CURRENT 0 13W Type 1 <0.4mA 1 3.84W Type 1 10.5mA 2 6.49W Type 1 18.5mA 3 13W Type 1 28mA 4 25.5W Type 2 40mA 4* 38.7W LTPoE++ 40mA 4* 52.7W LTPoE++ 40mA 4* 70W LTPoE++ 40mA ++ 4* 90W LTPoE 40mA *An LTPoE++ PD will be classified as class 4 by an IEEE 802.3 compliant PSE. LTPoE++ Classification The LT4275A allows higher power allocation while maintaining backwards compatibility with existing PSE systems by extending the classification signaling of IEEE 802.3. Linear Technology PSE controllers that are capable of LTPoE++ are listed in the Related Parts section. IEEE PSEs will classify an LTPoE++ PD as a Type 2 PD. Signature Corrupt During Mark During the mark state, the LT4275 presents <11kΩ to the port as required by the IEEE specification. A LT4275 GRADE CAPABILITY B RESISTOR RCLS RCLS++ Open Open 140Ω Open 76.8Ω Open 49.9Ω Open 34.8Ω Open Open 34.8Ω 140Ω 46.4Ω 76.8Ω 64.9Ω 49.9Ω 118Ω C power delivery and efficiency, reduces power and heat dissipation, and eases thermal design. The PWRGD pin is held low by its open drain output until HSGATE charges up to approximately 7V above HSSRC. The PWRGD pin is used to hold off the isolated power supply until inrush is complete and the external MOSFET is fully enhanced. The HSGATE pin will remain high and the PWRGD pin pulled down until the port voltage falls below VHSOFF or the AUX pin is above VAUXT. IINRUSH 3.3k To meet IEEE requirements, design IINRUSH to be approximately 100mA. See equation below: IINRUSH = IGPU • CPORT CGATE The LT4275 internal charge pump provides an N-channel MOSFET solution, eliminating a larger and more costly P-channel FET. The low RDS(ON) MOSFET also maximizes CPORT CGATE Inrush and Powered On Once the PSE detects and optionally classifies the PD, the PSE then powers on the PD. When the port voltage rises above the VHSON threshold, it begins to source IGPU out of the HSGATE pin. This current flows into an external capacitor (CGATE in Figure 3) that causes a voltage to ramp up the gate of the external MOSFET. The external MOSFET acts as a source follower and ramps the voltage up on the output bulk capacitor (CPORT in Figure 3) thereby determining the inrush current (IINRUSH in Figure 3). + VPORT HSGATE VPORT HSSRC LT4275A GND 4275 F03 Figure 3. Programming IINRUSH Auxiliary Supply Override If the AUX pin is held above VAUXT, the LT4275 enters auxiliary power supply override mode. In this mode the signature resistor is disconnected, classification is disabled, HSGATE is pulled down, and the PWRGD pin is allowed to float. The T2P pin pulls down on the LT4275A/ LT4275B when no RCLS++ resistor is present. The T2P pin alternates between pulling down and floating at fT2P on the LT4275A when the RCLS++ resistor is present. 4275f 7 LT4275 Applications Information The AUX pin allows for setting the auxiliary supply turn on (VAUXON) and turn off (VAUXOFF) voltage thresholds. The auxiliary supply hysteresis voltage (VAUXHYS) is set by sinking current (IAUXH) only when the AUX pin voltage is less than VAUXT. Use the following equations to set VAUXON and VAUXOFF via R1 and R2 in Figure 4. R1= R2 = R1≥ VAUXON − VAUXOFF VAUXHYS = IAUXH IAUXH + R1 VAUXOFF − 1 V AUXT VAUX(MAX) − VAUXT 1.4mA VAUX AUX Classification Resistor (RCLS and RCLS++) R2 – The LT4275 specifies an absolute maximum voltage of 100V and is designed to tolerate brief overvoltage events. However, the pins that interface to the outside world can routinely see excessive peak voltages. To protect the LT4275, install a unidirectional transient voltage suppressor (TVS) such as an SMAJ58A between the port voltage and GND. This TVS must be mounted near the LT4275. For extremely high cable discharge and surge protection contact Linear Technology Applications. LT4275A R1 Transient Voltage Suppressor GND 4275 F04 Figure 4. AUX Threshold and Hysteresis Calculation Thermal Protection The IEEE 802.3 specification requires a PD to withstand any applied voltage from 0V to 57V indefinitely. During classification, however, the power dissipation in the LT4275 may be as high as 1.5W. The LT4275 can easily tolerate this power for the maximum IEEE timing but will overheat if this condition persists abnormally. The LT4275 includes a thermal protection feature which protects itself from excessive heating. If the junction temperature exceeds the overtemperature threshold, the LT4275 pulls down the HSGATE and PWRGD pins and disables classification. External Interface and Component Selection Input Diode Bridge The input diode bridge introduces a voltage drop that affects the voltage range for each mode of operation. The LT4275 is designed to tolerate these voltage drops. The voltages shown in the Electrical Specifications are measured at the LT4275 package pins. Input Capacitor A 0.1µF capacitor is needed from VPORT to GND to meet an input impedance requirement in IEEE 802.3. The RCLS resistors set the classification load current corresponding to the PD power classification. Select the value of RCLS from Table 1 and connect the resistor between the RCLASS pin and GND, or float the RCLASS pin if class 0 is required. The resistor tolerance must be 1% or better to avoid degrading the overall accuracy of the classification circuit. For LTPoE++ use the LT4275A and select the value of RCLS++ from Table 1 in addition to RCLS. Power Good Interface The LT4275 provides a power good signal (PWRGD) to simplify the isolated power supply design. The power good signal is used to delay isolated power supply startup until the CPORT capacitor is fully charged. Exposed Pad The LT4275A/LT4275B/LT4275C DFN package has an exposed pad that is internally electrically connected to GND. The exposed pad may only be connected to GND on the printed circuit board. Layout Considerations Avoid excessive parasitic capacitance on the RCLASS pin and place resistor RCLS close to the LT4275. For the LT4275A, place RCLS++ nearby as well. It is strictly required for maximum protection to place the input capacitor (CPD) and transient voltage suppressor as close to the LT4275 as possible. 4275f 8 LT4275 Typical Applications IEEE 802.3af (Type 1) 13W Powered Device ~ ETHERNET MAGNETICS ~ – ~ + ~ FDN8601 + VPORT CPD 0.1µF SMAJ58A + 3.3k CPORT VIN 47nF VPORT HSGATE – HSSRC ISOLATED POWER SUPPLY PWRGD RUN + VOUT – LT4275A/LT4275B/LT4275C RCLASS RCLASS++ GND IEEEUVLO RCLS T2P AUX 4275 TA02 IEEE 802.3at (Type 2) 25.5W Powered Device ETHERNET MAGNETICS ~ + ~ – ~ + ~ FDN8601 VPORT CPD 0.1µF SMAJ58A + 3.3k CPORT VIN 47nF VPORT HSGATE – HSSRC ISOLATED POWER SUPPLY PWRGD RUN LT4275A/LT4275B RCLASS RCLASS++ GND IEEEUVLO RCLS – PSE TYPE (TO µP) OPTO T2P AUX + VOUT 4275 TA03 LTPoE++ 38.7W to 90W Powered Device ~ WÜRTH 749022016 ~ – ~ + ~ FDMC86102 + VPORT CPD 0.1µF SMAJ58A + 3.3k VIN 47nF VPORT HSGATE – RCLASS RCLASS++ RCLS RCLS++ CPORT HSSRC ISOLATED POWER SUPPLY PWRGD RUN + VOUT – LT4275A GND IEEEUVLO AUX T2P OPTO PSE TYPE (TO µP) 4275 TA04 4275f 9 LT4275 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. DD Package Package 10-Lead Plastic DFNDD (3mm × 3mm) 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699 Rev C) (Reference LTC DWG # 05-08-1699 Rev C) 0.70 ±0.05 3.55 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 3.00 ±0.10 (4 SIDES) R = 0.125 TYP 6 0.40 ±0.10 10 1.65 ±0.10 (2 SIDES) PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER PIN 1 TOP MARK (SEE NOTE 6) 0.200 REF 0.75 ±0.05 0.00 – 0.05 5 1 (DD) DFN REV C 0310 0.25 ±0.05 0.50 BSC 2.38 ±0.10 (2 SIDES) BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 4275f 10 LT4275 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MS Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661 Rev E) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 0.50 0.305 ± 0.038 (.0197) (.0120 ± .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 10 9 8 7 6 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 4.90 ± 0.152 (.193 ± .006) DETAIL “A” 0.497 ± 0.076 (.0196 ± .003) REF 0° – 6° TYP GAUGE PLANE 1 2 3 4 5 0.53 ± 0.152 (.021 ± .006) DETAIL “A” 0.18 (.007) SEATING PLANE 0.86 (.034) REF 1.10 (.043) MAX 0.17 – 0.27 (.007 – .011) TYP 0.50 (.0197) BSC NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.1016 ± 0.0508 (.004 ± .002) MSOP (MS) 0307 REV E 4275f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 11 LT4275 Typical Application 25W PD Solution with 12VDC and 24VAC Auxiliary Input VAUX 9V TO 57VDC OR 24VAC B2100 (4plcs) ~ ~ + MMSD4148 (2plcs) 470µF TO ISOLATED POWER SUPPLY MMSD4148 158k 0.1µF FDN8601 13 8.2Ω WÜRTH 7499511001 15 SMAJ58A 16 0.1µF 931k HSGATE 1–12 HSSRC 3.3k 47nF LT4275A/LT4275B 34.8Ω IEEEUVLO GND 14 TO PHY VPORT AUX RCLASS B2100 (8plcs) PWRGD T2P TO ISOLATED POWER SUPPLY RUN OPTO PSE TYPE (TO µP) 4275 TA05 Related Parts PART NUMBER DESCRIPTION COMMENTS LTC4257-1 IEEE 802.3af PD Interface Controller Internal 100V, 400mA Switch, Dual Current Limit, Programmable Class LTC4263 Single IEEE 802.3af PSE Controller Internal FET Switch LTC4265 IEEE 802.3at PD Interface Controller Internal 100V, 1A Switch, 2-Event Classification Recognition LTC4266 With Programmable ICUT/ILIM, 2-Event Classification LTC4266A Quad IEEE 802.3at PoE PSE Controller Quad LTPoE++ PSE Controller LTC4266C Quad IEEE 802.3af PSE Controller With Programmable ICUT/ILIM, 1-Event Classification LTC4267-3 IEEE 802.3af PD Interface with Integrated Switching Regulator Internal 100V, 400mA Switch, Programmable Class, 300kHz Constant Frequency PWM LTC4269-1 IEEE 802.3af PD Interface with Integrated Flyback Switching Regulator 2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller, 50kHz to 250kHz, Aux Support LTC4269-2 IEEE 802.3af PD Interface with Integrated Forward Switching Regulator LTC4270/LTC4271 12-Port PoE/PoE+/LTPoE++ PSE Controller Provides Up to 90W. Backwards Compatible with IEEE 802.3af and IEEE 802.3at PDs. With Programmable ICUT/ILIM, 2-Event Classification 2-Event Classification, Programmable Class, Synchronous Forward Controller, 100kHz to 500kHz, Aux Support Transformer Isolation, Supports IEEE 802.3af, IEEE 802.3at and LTPoE++ PDs LTC4274 Single IEEE 802.3at PoE PSE Controller With Programmable ICUT/ILIM, 2-Event Classification LTC4274A Single LTPoE++ PSE Controller Provides Up to 90W. Backwards Compatible with IEEE 802.3 PDs. With Programmable ICUT/ILIM, 2-Event Classification LTC4274C Single IEEE 802.3af PSE Controller With Programmable ICUT/ILIM, 1-Event Classification LTC4278 IEEE 802.3af PD Interface with Integrated Flyback Switching Regulator LTC4290/LTC4271 8-Port PoE/PoE+/LTPoE++ PSE Controller 2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller, 50kHz to 250kHz, 12V Aux Support Transformer Isolation, Supports IEEE 802.3af, IEEE 802.3at and LTPoE++ PDs 4275f 12 Linear Technology Corporation LT 0712 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2012