NTD3817N Power MOSFET 16 V, 34.5 A, Single N-Channel, DPAK/IPAK Features •Low RDS(on) to Minimize Conduction Losses •Low Capacitance to Minimize Driver Losses •Optimized Gate Charge to Minimize Switching Losses •Three Package Variations for Design Flexibility •These are Pb-Free Devices http://onsemi.com V(BR)DSS RDS(ON) MAX ID MAX 13.9 mW @ 10 V 16 V 34.5 A Applications 29 mW @ 4.5 V •DC-DC Converters •High Side Switching D MAXIMUM RATINGS (TJ = 25°C unless otherwise stated) Value Unit VDSS 16 V VGS ±16 V ID 10.8 A Continuous Drain Current RqJA (Note 1) TA = 25°C Power Dissipation RqJA (Note 1) TA = 25°C PD 2.5 W Continuous Drain Current RqJA (Note 2) TA = 25°C ID 7.6 A Steady State 8.4 TA = 85°C 1 2 5.9 1.2 W Continuous Drain Current RqJC (Note 1) TC = 25°C ID 34.5 A Power Dissipation RqJC (Note 1) TC = 25°C PD 25.9 W TA = 25°C IDM 78 A TA = 25°C IDmaxPkg 22 A TJ, TSTG -55 to +175 °C tp=10ms Current Limited by Package Operating Junction and Storage Temperature Source Current (Body Diode) 26.8 IS 21.6 A Drain to Source dV/dt dV/dt 6 V/ns Single Pulse Drain-to-Source Avalanche Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V, IL = 10 Apk, L = 0.3 mH, RG = 25 W) EAS 15 mJ Lead Temperature for Soldering Purposes (1/8” from case for 10 s) TL 1 3 PD TC = 85°C 4 4 4 TA = 25°C Pulsed Drain Current S N-CHANNEL MOSFET °C 260 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. CASE 369AA DPAK (Bent Lead) STYLE 2 2 3 1 2 3 CASE 369AC CASE 369D 3 IPAK IPAK (Straight Lead) (Straight Lead DPAK) MARKING DIAGRAMS & PIN ASSIGNMENTS 4 Drain 4 Drain 4 Drain YWW 38 17NG Power Dissipation RqJA (Note 2) TA = 85°C G YWW 38 17NG Gate-to-Source Voltage Symbol YWW 38 17NG Parameter Drain-to-Source Voltage 2 1 2 3 1 Drain 3 Gate Source Gate Drain Source 1 2 3 Gate Drain Source Y WW 3817N G = Year = Work Week = Device Code = Pb-Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2007 December, 2007 - Rev. 0 1 Publication Order Number: NTD3817N/D NTD3817N THERMAL RESISTANCE MAXIMUM RATINGS Symbol Value Unit Junction-to-Case (Drain) Parameter RqJC 5.8 °C/W Junction-to-TAB (Drain) RqJC-TAB 4.5 Junction-to-Ambient – Steady State (Note 1) RqJA 59 Junction-to-Ambient – Steady State (Note 2) RqJA 121 1. Surface-mounted on FR4 board using 1 sq-in pad, 1 oz Cu. 2. Surface-mounted on FR4 board using the minimum recommended pad size. ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Symbol Test Condition Min Drain-to-Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 16 Drain-to-Source Breakdown Voltage Temperature Coefficient V(BR)DSS/ TJ Parameter Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current Gate-to-Source Leakage Current IDSS V 15.5 VGS = 0 V, VDS = 16 V mV/°C TJ = 25°C 1.0 TJ = 125°C 10 IGSS VDS = 0 V, VGS = ±16 V VGS(TH) VGS = VDS, ID = 250 mA mA ±100 nA 2.5 V ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coefficient VGS(TH)/TJ Drain-to-Source On Resistance RDS(on) Forward Transconductance gFS 1.5 5.1 mV/°C VGS = 10 V ID = 15 A 12.8 13.9 VGS = 4.5 V ID = 15 A 19.2 29 VDS = 1.5 V, ID = 15 A 28 mW S CHARGES AND CAPACITANCES Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS 168 Total Gate Charge QG(TOT) 7.0 Threshold Gate Charge QG(TH) Gate-to-Source Charge Gate-to-Drain Charge Total Gate Charge QGS 702 VGS = 0 V, f = 1.0 MHz, VDS = 12 V pF 10.5 0.6 VGS = 4.5 V, VDS = 12 V, ID = 15 A QGD QG(TOT) 257 2.5 nC 3.5 VGS = 10 V, VDS = 12 V, ID = 15 A 13.5 nC SWITCHING CHARACTERISTICS (Note 4) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time td(ON) tr td(OFF) 12 VGS = 4.5 V, VDS = 12 V, ID = 15 A, RG = 3.0 W 50 12 tf 4.6 td(ON) 8.0 tr td(OFF) VGS = 10 V, VDS = 12 V, ID = 15 A, RG = 3.0 W tf 47 20 10 3. Pulse Test: pulse width v 300 ms, duty cycle v 2%. 4. Switching characteristics are independent of operating junction temperatures. 5. Assume standoff of 110 mm http://onsemi.com 2 ns ns NTD3817N ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Typ Max TJ = 25°C 0.96 1.1 TJ = 125°C 0.86 Unit DRAIN-SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge VSD VGS = 0 V, IS = 15 A tRR ta tb V 11 VGS = 0 V, dIS/dt = 100 A/ms, IS = 15 A 5.4 ns 5.6 QRR 2.8 nC Source Inductance LS 2.49 nH Drain Inductance, DPAK LD 0.0164 Drain Inductance, IPAK (Note 5) LD PACKAGE PARASITIC VALUES TA = 25°C 1.88 Gate Inductance LG 3.46 Gate Resistance RG 1.0 3. Pulse Test: pulse width v 300 ms, duty cycle v 2%. 4. Switching characteristics are independent of operating junction temperatures. 5. Assume standoff of 110 mm http://onsemi.com 3 W NTD3817N TYPICAL PERFORMANCE CURVES 35 4.5 V 10 V ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) 4.0 V 3.8 V 20 3.6 V 15 10 3.4 V 5 3.2 V 3.0 V 0.5 1 1.5 2.5 2 TJ = 125°C 10 TJ = 25°C 5 TJ = -55°C 1 2 3 4 5 Figure 2. Transfer Characteristics 0.05 0.045 0.04 0.035 0.03 0.025 0.02 0.015 0.01 4 5 6 8 7 9 10 0.030 TJ = 25°C 0.025 VGS = 4.5 V 0.020 0.015 VGS = 10 V 0.010 0.005 0.000 5 10 15 20 25 30 35 40 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS) Figure 3. On-Resistance vs. Gate-to-Source Voltage Figure 4. On-Resistance vs. Drain Current and Gate Voltage 1.6 10000 VGS = 0 V ID = 15 A VGS = 10 V IDSS, LEAKAGE (nA) RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 15 Figure 1. On-Region Characteristics ID = 15 A TJ = 25°C 1.4 20 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 0.06 3 25 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 0.055 0.005 30 0 3 RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) 0 VDS ≥ 10 V 35 25 0 RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) TJ = 25°C 6V 30 1.2 1.0 TJ = 150°C 1000 100 TJ = 125°C 0.8 0.6 -50 10 -25 0 25 50 75 100 125 150 175 5 7 9 11 13 15 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current vs. Drain Voltage http://onsemi.com 4 NTD3817N TYPICAL PERFORMANCE CURVES VGS = 0 V 900 C, CAPACITANCE (pF) VGS , GATE-TO-SOURCE VOLTAGE (VOLTS) 1000 TJ = 25°C Ciss 800 700 600 500 Coss 400 300 200 Crss 100 0 0 2 4 6 8 10 12 14 16 DRAIN-TO-SOURCE VOLTAGE (VOLTS) 10 QT 8 6 2 ID = 15 A TJ = 25°C 0 0 IS, SOURCE CURRENT (AMPS) 100 tr td(off) tf td(on) 10 10 RG, GATE RESISTANCE (OHMS) 3 4 5 6 7 8 9 10 11 12 13 14 VGS = 0 V 12 8 6 4 2 100 ms 1 ms VGS = 20 V SINGLE PULSE TC = 25°C 10 ms dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 0.6 0.7 0.8 1.0 0.9 Figure 10. Diode Forward Voltage vs. Current 10 ms 10 0.5 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 100 TJ = 25°C 10 0 0.4 100 1000 I D, DRAIN CURRENT (AMPS) 2 QG, TOTAL GATE CHARGE (nC) Figure 9. Resistive Switching Time Variation vs. Gate Resistance 0.1 0.1 1 14 VDD = 12 V ID = 15 A VGS = 10 V 1 Q2 Figure 8. Gate-To-Source and Drain-To-Source Voltage vs. Total Charge 1000 t, TIME (ns) Q1 4 Figure 7. Capacitance Variation 1 1 VGS 15 ID = 10 A 12.5 10 7.5 5.0 2.5 0 25 Figure 11. Maximum Rated Forward Biased Safe Operating Area 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 5 175 NTD3817N ORDERING INFORMATION Package Shipping† NTD3817NT4G DPAK (Pb-Free) 2500 / Tape & Reel NTD3817N-1G IPAK (Pb-Free) 75 Units / Rail NTD3817N-35G IPAK Trimmed Lead (3.5 " 0.15 mm) (Pb-Free) 75 Units / Rail Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 6 NTD3817N PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369AA-01 ISSUE A -TC B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. SEATING PLANE E R 4 Z A S 1 2 DIM A B C D E F H J L R S U V Z H 3 U F J L D STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN 2 PL 0.13 (0.005) M INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.025 0.035 0.018 0.024 0.030 0.045 0.386 0.410 0.018 0.023 0.090 BSC 0.180 0.215 0.024 0.040 0.020 --0.035 0.050 0.155 --- T SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.101 5.80 0.228 3.0 0.118 1.6 0.063 6.172 0.243 SCALE 3:1 mm Ǔ ǒinches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.63 0.89 0.46 0.61 0.77 1.14 9.80 10.40 0.46 0.58 2.29 BSC 4.57 5.45 0.60 1.01 0.51 --0.89 1.27 3.93 --- NTD3817N PACKAGE DIMENSIONS 3 IPAK, STRAIGHT LEAD CASE 369AC-01 ISSUE O B V NOTES: 1.. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2.. CONTROLLING DIMENSION: INCH. 3. SEATING PLANE IS ON TOP OF DAMBAR POSITION. 4. DIMENSION A DOES NOT INCLUDE DAMBAR POSITION OR MOLD GATE. C E R DIM A B C D E F G H J K R V W A SEATING PLANE K W F J G H D 3 PL 0.13 (0.005) W INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.043 0.090 BSC 0.034 0.040 0.018 0.023 0.134 0.142 0.180 0.215 0.035 0.050 0.000 0.010 MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.09 2.29 BSC 0.87 1.01 0.46 0.58 3.40 3.60 4.57 5.46 0.89 1.27 0.000 0.25 IPAK (STRAIGHT LEAD DPAK) CASE 369D-01 ISSUE B C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. E R 4 Z A S 1 2 3 -TSEATING PLANE K J F H D G DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 --- MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 --- 3 PL 0.13 (0.005) M STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN T ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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