TI1 LDC1051NHRR 8-bit rp only inductance-to-digital converter with spi Datasheet

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LDC1051
SNOSCY0 – MARCH 2014
LDC1051: 8-bit Rp only Inductance-to-Digital Converter with SPI
1 Features
•
1
•
•
•
•
•
•
•
•
•
Axial Distance Sensing Application
Remote Sensor Placement (Decoupling The LDC
From Harsh Environments)
High Durability (By Virtue Of Contactless
Operation)
Higher Flexibility For System Design (Using Coils
Or Springs As Sensors)
Insensitive to Non-conductive Environmental
Interferers (such As Dirt, Dust, Oil etc.)
Magnet-free Operation
Supply Voltage: 5 V, typ
Supply Voltage, IO: 1.8V to 5.5V
Stand-by Current: 250uA, typ
Rp Resolution: 8-bit
LC Frequency Range: 5kHz to 5MHz
Application Schematic
5V
2 Applications
•
•
•
VIO
5V
LDO
Proximity Sensing
Level Sensing
Lateral Position Sensing
VIO
VDD
MOSI
SDI
INA
MISO
SDO
SCLK
SCLK
GPIO
CSB
INT/GPIO
INTB
VIO
MCU
3 Description
Sensor
CFA
CFB
Inductive sensing is a contactless, short-range
sensing technology enabling high-resolution and lowcost position sensing of conductive targets, even in
harsh environments. Using a coil or spring as a
sensor, the LDC1051 inductance-to-digital converter
provides system designers a way to achieve high
performance and reliability at a lower system cost
than other competing solutions.
The LDC1051 is available in a 5mm x 4mm WSON16 package. Device programming via SPI allows for
easy configuration using a microcontroller.
Device Information
PACKAGE
DGND
GND
DGND
CLDO
DAP
DGND
AGND
DGND
Rp vs Distance With 14mm PCB Coil
14
12
10
Rp (kŸ
The LDC1051 is pin compatible with the LDC1000
(16-bit Rp/24-bit L) and the LDC1041 (8-bit Rp/24-bit
L). This family of devices offers system designers
different resolution options based on their application
and system requirements.
ORDER NUMBER
INB
LDC1051
8
6
4
2
0
BODY SIZE
LDC1051NHRT
WSON (16)
5 mm × 4 mm
LDC1051NHRR
WSON (16)
5 mm × 4 mm
LDC1051NHRJ
WSON (16)
5 mm × 4 mm
0
1
2
3
4
5
Distance (mm)
6
7
8
C002
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LDC1051
SNOSCY0 – MARCH 2014
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Terminal Configuration and Functions................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
7.3
7.4
7.5
7.6
8
Feature Description................................................... 8
Device Functional Modes........................................ 11
Programming........................................................... 14
Register Map and Description................................. 15
Applications and Implementation ...................... 20
8.1 Application Information............................................ 20
8.2 Typical Applications ................................................ 21
9 Power Supply Recommendations...................... 25
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 26
11 Device and Documentation Support ................. 27
11.1 Trademarks ........................................................... 27
11.2 Electrostatic Discharge Caution ............................ 27
11.3 Glossary ................................................................ 27
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
12 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
2
DATE
REVISION
NOTES
March 2014
*
Initial release.
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5 Terminal Configuration and Functions
WSON-16
Top View
SCLK
1
16
INTB
CSB
2
15
N/C
SDI
3
14
N/C
VIO
4
13
CLDO
SDO
5
12
VDD
DGND
6
11
GND
CFB
7
10
INB
CFA
8
9
INA
DAP
(GND)
Terminal Functions
TERMINAL
NAME
TERMINAL
NO.
TERMINAL
TYPE
DESCRIPTION
SCLK
1
DO
SPI clock input. SCLK is used to clock-out/clock-in the data from/into the chip
CSB
2
DI
SPI CSB(Chip Select Bar). Multiple devices can be connected on the same SPI bus and CSB
can be used to select the device to be communicated with
SDI
3
DI
SPI Slave Data In (Master Out Slave In). This should be connected to the Master Out Slave In
of the master
VIO
4
P
Digital IO Supply
SDO
5
DO
DGND
6
P
SPI Slave Data Out (Master In Slave Out).It is high impedance when CSB is high
Digital ground
CFB
7
A
LDC filter capacitor
CFA
8
A
LDC filter capacitor
INA
9
A
External LC Tank. Connect to external LC tank
INB
10
A
External LC Tank. Connect to external LC tank
GND
11
P
Analog ground
VDD
12
P
Analog supply
CLDO
13
A
LDO bypass capacitor. A 56nF capacitor should be connected from this Terminal to GND
N/C
14
N/C
No Connection
N/C
15
N/C
No Connection
INTB
16
DO
Configurable interrupt. This Terminal can be configured to behave in 3 different ways by
programing the INT Terminal mode register. Either threshold detect, wakeup, or DRDYB
DAP
17
P
Connect to GND
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6 Specifications
6.1 Absolute Maximum Ratings
MAX
UNIT
Analog Supply Voltage (VDD – GND)
MIN
6
V
IO Supply Voltage (VIO – GND)
6
V
V
Voltage on any Analog Terminal
–0.3
VDD + 0.3
Voltage on any Digital Terminal
–0.3
VIO + 0.3
V
8
mA
150
°C
Input Current on INA and INB
Junction Temperature, TJ
6.2 Handling Ratings
MIN
MAX
UNIT
Tstg
Storage Temperature range
-65
150
°C
VESD
Human Body Model (HBM) ESD stress voltage
1k
1k
V
250
250
V
Charge Device Model (CDM) ESD stress voltage
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Analog Supply Voltage (VDD – GND)
IO Supply Voltage (VIO – GND)
MIN
MAX
UNIT
4.75
5.25
V
1.8
5.25
V
125
°C
VDD-VIO
0
Operating Temperature, TA
-40
V
6.4 Thermal Information
THERMAL METRIC (1)
θJA
(1)
4
Junction-to-ambient thermal resistance
NHR
(16-TERMINALS)
UNIT
28
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics (1)
Unless otherwise specified, all limits ensured for TA = TJ = 25°C, VDD = 5 V, VIO = 3.3 V
PARAMETER
TEST CONDITIONS
MIN (2)
TYP (3)
MAX (2)
4.75
5
5.25
1.8
3.3
5.25
V
1.7
2.3
mA
14
µA
UNIT
POWER
VDD
Analog supply voltage
VIO
IO supply voltage
IDD
Supply current, VDD
Does not include sensor current. (4)
IVIO
IO supply current
Static current
IDD_LP
Stand-by mode supply
current
tSTART
Start-Up Time
VIO≤VDD
From POR to ready-to-convert.
V
250
µA
2
ms
LDC
ƒsensor_MIN
Minimum sensor frequency
5
kHz
ƒsensor_MAX Maximum sensor frequency
5
MHz
Asensor_MIN
Minimum sensor amplitude
1
VPP
Asensor_MAX Maximum sensor amplitude
4
VPP
10
1/fsensor
tREC
Oscillation start-up time after Rp underrange condition
Recovery time
Rp Min
Minimum sensor Rp range
798
Ω
Rp Max
Maximum Sensor Rp range
3.93
MΩ
Rp Res
Rp measurement resolution
8
Bits
tS_MIN
Minimum response time
Minimum programmable settling time of
digital filter
tS_MAX
Maximum response time
Maximum programmable settling time
of digital filter
192 × 1 / ƒsensor
s
6144 × 1 /
ƒsensor
s
DIGITAL I/O CHARACTERISTICS
VIH
Logic 1 input voltage
VIL
Logic 0 input voltage
VOH
Logic 1 output voltage
ISOURCE = 400 µA
VOL
Logic 0 output voltage
ISINK = 400 µA
IIOHL
Digital IO leakage current
(1)
(2)
(3)
(4)
0.8 × VIO
V
0.2 ×
VIO
V
VIO – 0.3
–500
V
0.3
V
500
nA
Electrical Characteristics Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions
result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond
which the device may be permanently degraded, either mechanically or electrically.
Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through
correlations using statistical quality control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped
production material.
LC tank current depends on the Q-factor of the tank, distance and material of the target.
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6.6 Timing Requirements
Unless otherwise noted, all limits specified at TA = 25°C, VDD = 5, VIO = 3.3, 10 pF capacitive load in parallel with a 10 kΩ
load on the SDO terminal. Specified by design; not production tested.
PARAMETER
MIN
TYP
MAX
UNIT
4
MHz
ƒSCLK
Serial Clock Frequency
tPH
SCLK Pulse Width High
ƒSCLK = 4 MHz
0.4 / ƒSCLK
tPL
SCLK Pulse Width Low
ƒSCLK = 4 MHz
0.4 / ƒSCLK
s
tSU
SDI Setup Time
10
ns
tH
SDI Hold Time
10
ns
tODZ
SDO Driven-to-Tristate Time
Measured at 10% / 90% point
20
ns
tOZD
SDO Tristate-to-Driven Time
Measured at 10% / 90% point
20
ns
tOD
SDO Output Delay Time
20
ns
tCSS
CSB Setup Time
20
ns
tCSH
CSB Hold Time
20
ns
tIAG
Inter-Access Gap
100
ns
tDRDYB
Data ready pulse width
s
Data ready pulse at every 1 / ODR if no
data is read
1 / ƒsensor
s
Unless otherwise noted, all limits specified at TA = 25°C, VDD=5.0, VIO=3.3, 10pF capacitive load in parallel with
a 10kΩ load on SDO. Specified by design; not production tested.
ttPLt
ttPHt
16th Clock
SCLK
ttSUt
ttHt
Valid Data
SDI
Valid Data
Figure 1. Write Timing Diagram
1st Clock
8th Clock
16th Clock
SCLK
t
t CSHt
t
t CSSt
t
tCSHt
t
t CSSt
CSB
tOZD
SDI
tOD
D7
D1
ttHt
D0
Figure 2. Read Timing Diagram
6
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6.7 Typical Characteristics
14
60
12
50
Code (decimal)
Rp (kŸ
10
8
6
4
40
30
20
10
2
0
0
0
1
2
3
4
5
6
Distance (mm)
Sensor
Details:
Target
Material:
7
8
0
1
2
Table 16
Rp_MIN:
1.347 kΩ
Stainless
Steel
Rp_MAX:
38.785 kΩ
3
4
5
6
7
Distance (mm)
C002
Sensor
Details:
Target
Material:
Figure 3. Rp vs Distance
8
C003
Table 16
Rp_MIN:
1.347 kΩ
Stainless
Steel
Rp_MAX:
38.785 kΩ
Figure 4. Proximity Data vs Distance
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7 Detailed Description
7.1 Overview
The LDC1051 is an Inductance-to-Digital Converter that measures the parallel impedance of an LC resonator. It
accomplishes this task by regulating the oscillation amplitude in a closed loop configuration to a constant level,
while monitoring the energy dissipated by the resonator. By monitoring the amount of power injected into the
resonator, the LDC1051 can determine the value of Rp; it returns this as a digital value which is inversely
proportional to Rp.
The threshold detector block provides a comparator with hysteresis, with the threshold registers programed and
comparator enabled, proximity data register is compared with threshold registers and INTB terminal indicates the
output.
The device has a simple 4-wire SPI interface. The INTB terminal provides multiple functions which are
programmable with SPI.
The device has separate supplies for Analog and I/O, with analog operating at 5V and I/O at 1.8-5V. The
integrated LDO needs a 56nF capacitor connected from CLDO terminal to GND.
7.2 Functional Block Diagram
CFA
CFB
Threshold
Detector
L
INA
Proximity Data
Register
LDC
C
INB
SCLK
4-Wire
Serial
Interface
SDI
SDO
CS
INTB
Rs
Power
VDD
GND
VIO
DGND
CLDO
7.3 Feature Description
7.3.1 Inductive Sensing
An AC current flowing through a coil will generate an AC magnetic field. If a conductive material, such as a metal
target, is brought into the vicinity of the coil, this magnetic field will induce circulating currents (eddy currents) on
the surface of the target. These eddy currents are a function of the distance, size, and composition of the target.
The eddy currents then generate their own magnetic field, which opposes the original field generated by the coil.
This mechanism is best compared to a transformer, where the coil is the primary core and the eddy current is the
secondary core. The inductive coupling between both cores depends on distance and shape. Hence the
resistance and inductance of the secondary core (eddy current), shows up as a distant dependent resistive and
inductive component on the primary side (coil). The figures(Figure 5 to Figure 8) below show a simplified circuit
model.
8
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Feature Description (continued)
d
Metal
Target
Figure 5. Inductor With A Metal Target
Eddy currents generated on the surface of the target can be modeled as a transformer as shown in Figure 6. The
coupling between the primary and secondary coils is a function of the distance and the conductor’s
characteristics. In Figure 6, the inductance Ls is the coil’s inductance, and Rs is the coil’s parasitic series
resistance. The inductance L(d), which is a function of distance d, is the coupled inductance of the metal target.
Likewise, R(d) is the parasitic resistance of the eddy currents and is also a function of distance.
Eddy
Currents
Ls + L(d)
Conductance
of Metal
Target Metal
Surface
Distance d
Rs + R(d)
Figure 6. Metal Target Modeled As L And R With Circulating Eddy Currents
Generating an alternating magnetic field with just an inductor will consume a large amount of power. This power
consumption can be reduced by adding a parallel capacitor, turning it into a resonator as shown in Figure 7. In
this manner the power consumption is reduced to the eddy and inductor losses Rs+R(d) only.
L(d)
C
Oscillator
Rs(d)
Figure 7. LC Tank Connected To Oscillator
The LDC1051 doesn’t measure the series resistance directly; instead it measures the equivalent parallel
resonance impedance Rp (see Figure 8). This representation is equivalent to the one shown in Figure 8, where
the parallel resonance impedance Rp(d) is given by:
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Feature Description (continued)
Rp(d)
Ls L(d)
[Rs R(d)] u C
(1)
L(d)
C
Rp(d)
Oscillator
Figure 8. Equivalent Resistance Of Rs in Parallel With LC Tank
Figure 9 below shows the variation in Rp as a function of distance for a 14mm diameter PCB coil (Sensor
Details:Table 16). The target in this example is a section of a 2mm thick stainless steel disk.
14
12
Rp (kŸ
10
8
6
4
2
0
0
1
2
3
4
5
Distance (mm)
6
7
8
C002
Figure 9. Typical Rp vs Distance With 14mm PCB Coil
7.3.2 Measuring Rp with LDC1051
The LDC1051 supports a wide range of LC combinations, with oscillation frequencies ranging from 5kHz to
5MHz and Rp ranging from 798Ω to 3.93MΩ. This range of Rp can be viewed as the maximum input range of an
ADC. As illustrated in Figure 9, the range of Rp is typically much smaller than the maximum input range
supported by the LDC1051. To get better resolution in the desired sensing range, the LDC1051 offers a
programmable input range through the Rp_MIN and Rp_MAX registers. Refer to Calculation of Rp_MIN and
Rp_MAX below for how to set these registers.
When the sensor’s resonance impedance Rp drops below the programed Rp_MIN, the LDC’s Rp output will clip
at its full scale output. This situation could, for example, happen when a target comes too close to the coil.
10
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Feature Description (continued)
60
Code (decimal)
50
40
30
20
10
0
0
1
2
3
4
5
Distance (mm)
6
7
8
C003
Figure 10. Transfer Characteristics Of LDC1051 With Rp_MIN= 1.347 kΩ And Rp_MAX= 38.785 kΩ
The resonance impedance can be calculated from the digital output code as follows:
Rp _ MAX u Rp _ MIN
Rp
Rp _ MIN u (1 Y) Rp _ MAX u Y
Where:
•
•
•
Y=Proximity Data/27
Rp_MAX and Rp_MIN are the maximum and minimum Rp values selected in the respective registers
Proximity data is the LDC output, register address 0x22.
(2)
Example: If Proximity data (address 0x22) is 50, Rp_MIN is 2.394 kΩ, and Rp_MAX is 38.785 kΩ, the
resonance impedance is given by:
Y=50/27 = 0.3906
Rp=(38785*2394)/(2394×(1-0.3906) + 38785×0.3906) =(92851290)/(15149.421 + 1458.9036)
Rp = 5.59 kΩ
7.4 Device Functional Modes
7.4.1 Power Modes
The LDC1051 has two power modes:
•
•
Active Mode : In this mode the Proximity data conversion is enabled.
Stand-by Mode: This is the default mode on device power-up. In this mode conversion is disabled.
7.4.2 INTB terminal Modes
The INTB terminal is a configurable output terminal which can be used to drive an interrupt on an MCU. The
LDC1051 provides three different modes on INTB terminal:
1. Comparator Mode
2. Wake-Up Mode
3. DRDY Mode
LDC1051 has built-in High and Low trigger threshold registers which can be used as a comparator with
programmable hysteresis or in a special mode which can be used to wake-up an MCU. These modes are
explained in detail below.
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Device Functional Modes (continued)
7.4.2.1 Comparator Mode
In the Comparator mode, the INTB terminal is asserted or deasserted when the proximity register value
increases above Threshold High or decreases below Threshold Low registers respectively. In this mode, the
LDC1051 essentially behaves as a proximity switch with programmable hysteresis.
Threshold High
Rp Data
Threshold Low
INTB
t
Figure 11. Behavior Of INTB Terminal In Comparator Mode
7.4.2.2 Wake-Up Mode
In Wake-Up mode, the INTB terminal is asserted when proximity register value increases above Threshold High
and de-asserted when wake-up mode is disabled in INTB terminal mode register.
This mode can be used to wake-up an MCU from sleep, to conserve power.
Threshold High
Rp Data
Threshold Low
INTB
CSB
SPI
SPI: INTB Pin Mode Changed to DRDYB
t
Figure 12. Behavior Of INTB Terminal In Wake-Up Mode
7.4.2.3 DRDYB Mode
In DRDY(Data Ready) mode, the INTB terminal is asserted every time the conversion data is available and deasserted once the read command on register 0x22 is registered internally; if the read is in progress, the terminal
is pulsed instead. The valid condition for new data availability is CSB high and DRDYB falling edge.
12
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Device Functional Modes (continued)
t1/ODRt
INTB
New Data
available to Read
CSB
CMD:
Read 0x22
SPI
Data Read
CMD:
Read 0x22
t
Figure 13. Behavior of INTB Terminal in DRDYB Mode with SPI Extending Beyond Subsequent
Conversions
ODRt
t
INTB
CSB
SPI
CMD:
Read 0x22
Data
Read
t
Figure 14. Behavior Of INTB Terminal In DRDYB Mode with SPI Reading The Data Within Subsequent
Conversion
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7.5 Programming
The LDC1051 utilizes a 4-wire SPI to access control and data registers. The LDC1051 is an SPI slave device
and does not initiate any transactions.
7.5.1 SPI Description
A typical serial interface transaction begins with an 8-bit instruction, which is comprised of a read/write bit (MSB,
R=1) and a 7 bit address of the register, followed by a data field which is typically 8 bits. However, the data field
can be extended to a multiple of 8 bits by providing sufficient SPI clocks. Refer to the Extended SPI Transactions
section below.
1
2
3
4
5
C7
C6
C5
C4
C3
R/Wb
A6
A5
A4
A3
6
7
8
C2
C1
C0
A2
A1
A0
9
10
11
D7
D6
(MSB)
D5
12
13
14
15
16
D2
D1
D0
(LSB)
D2
D1
D0
(LSB)
17
SCLK
CSB
tCOMMAND FIELDt
SDI
R/Wb = Read/Write
0: Write Data
1: Read Data
SDO
Address (7-bits)
tDATA FIELDt
D4
D3
Write DATA
D7
D6
(MSB)
D5
High-Z
D4
D3
Read DATA
Data (8-bits)
tSingle Access Cyclet
Figure 15. Serial Interface Protocol
Each assertion of CSB starts a new register access. The R/Wb bit in the command field configures the direction
of the access; a value of 0 indicates a write operation and a value of 1 indicates a read operation. All output data
is driven on the falling edge of the serial clock (SCLK), and all input data is sampled on the rising edge of the
serial clock (SCLK). Data is written into the register on the rising edge of the 16th clock. It is required to deassert
CSB after the 16th clock; if CSB is deasserted before the 16th clock, no data write will occur.
7.5.1.1 Extended SPI Transactions
A transaction may be extended to multiple registers by keeping the CSB asserted beyond the initial 16 clocks. In
this mode, the register addresses increment automatically. CSB must be asserted during 8*(1+N) clock cycles of
SCLK, where N is the amount of bytes to write or read during the transaction.
During an extended read access, SDO outputs the register contents every 8 clock cycles after the initial 8 clocks
of the command field. During an extended write access, the data is written to the registers every 8 clock cycles
after the initial 8 clocks of the command field.
14
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7.6 Register Map and Description
Table 1. Register Map (1) (2) (3)
Register
Name
Address
Direction Default
Device ID
0x00
RO
0x84
Device ID
Rp_MAX
0x01
R/W
0x0E
Rp Maximum
Rp_MIN
0x02
R/W
0x14
Rp Minimum
Watchdog
Timer
Frequency
0x03
R/W
0x45
Min Sensor Frequency
LDC
Configuration
0x04
R/W
0x1B
Reserved
0x05
RO
0x01
Reserved
0x06
R/W
0xFF ??
Comparator
Threshold
High MSB
0x07
R/W
0xFF
Reserved
0x08
R/W
0x00 ??
Comparator
Threshold
Low MSB
0x09
R/W
0x00
INTB
Terminal
Configuration
0x0A
R/W
0x00
Power
Configuration
0x0B
R/W
0x00
Status
0x20
RO
Reserved
0x21
RO
Reserved(00000000)
Proximity
Data
0x22
RO
Proximity Data
Reserved
0x23
RO
Reserved
Reserved
0x24
RO
Reserved
Reserved
0x25
RO
Reserved
(1)
(2)
(3)
Bit 7
Bit 6
Bit 5
Bit 4
Reserved(000)
Bit 3
Amplitude
Bit 2
Bit 1
Bit 0
Response Time
Reserved(00000001)
Reserved
Threshold High MSB
Reserved
Threshold Low MSB
Reserved(00000)
INTB_MODE
Reserved(0000000)
OSC
Dead
DRDYB
Wake-up
Compara
tor
PWR_M
ODE
Do Not Care
Values of register fields which are unused should be set to default values only.
Registers 0x01 through 0x05 are Read Only when the part is awake (PWR_MODE bit is SET)
R/W: Read/Write. RO: Read Only. WO: Write Only.
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Table 2. Revision ID
Address = 0x00, Default=0x84, Direction=RO
Bit Field
Field Name
7:0
Revision ID
Description
Revision ID of Silicon.
Table 3. Rp_MAX
Address = 0x01, Default=0x0E, Direction=R/W
Bit Field
Field Name
7:0
Rp Maximum
Description
Maximum Rp that LDC1051 needs to
measure. Configures the input dynamic
range of LDC1051. See Table 4 for register
settings.
Table 4. Register Settings for Rp_MAX
16
Register setting
Rp (kΩ)
0x00
3926.991
0x01
3141.593
0x02
2243.995
0x03
1745.329
0x04
1308.997
0x05
981.748
0x06
747.998
0x07
581.776
0x08
436.332
0x09
349.066
0x0A
249.333
0x0B
193.926
0x0C
145.444
0x0D
109.083
0x0E
83.111
0x0F
64.642
0x10
48.481
0x11
38.785
0x12
27.704
0x13
21.547
0x14
16.160
0x15
12.120
0x16
9.235
0x17
7.182
0x18
5.387
0x19
4.309
0x1A
3.078
0x1B
2.394
0x1C
1.796
0x1D
1.347
0x1E
1.026
0x1F
0.798
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Table 5. Rp_MIN
Address = 0x02, Default=0x14, Direction=R/W
(1)
Bit Field
Field Name
7:0
Rp Minimum
Description
Minimum Rp that LDC1051 needs to measure. Configures the input
dynamic range of LDC1051. See Table 6 for register settings. (1)
This Register needs a mandatory write as it defaults to 0x14.
Table 6. Register Settings for Rp_MIN
Register setting
Rp (kΩ)
0x20
3926.991
0x21
3141.593
0x22
2243.995
0x23
1745.329
0x24
1308.997
0x25
981.748
0x26
747.998
0x27
581.776
0x28
436.332
0x29
349.066
0x2A
249.333
0x2B
193.926
0x2C
145.444
0x2D
109.083
0x2E
83.111
0x2F
64.642
0x30
48.481
0x31
38.785
0x32
27.704
0x33
21.547
0x34
16.160
0x35
12.120
0x36
9.235
0x37
7.182
0x38
5.387
0x39
4.309
0x3A
3.078
0x3B
2.394
0x3C
1.796
0x3D
1.347
0x3E
1.026
0x3F
0.798
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Table 7. Watchdog Timer Frequency
Address = 0x03, Default=0x45, Direction=R/W
Bit Field
Field Name
7:0
Min Sensor Frequency
Description
Sets the watchdog timer. The Watchdog timer is set based on the lowest
sensor frequency.
N
§ F ·
68.94 u log10 ¨
¸
© 2500 ¹
where
•
F is the sensor frequency
(3)
Example:
If Sensor frequency is 1Mhz
Min Sensor Frequency=68.94*log10(1M/2500)=Round to nearest
integer(179.38)=179
Table 8. LDC Configuration
Address = 0x04, Default=0x1B, Direction=R/W
Bit Field
Field Name
Description
7:5
Reserved
Reserved to 0
4:3
Amplitude
Sets the oscillation amplitude
00:1V
01:2V
10:4V
11:Reserved
2:0
Response Time
000: Reserved
001: Reserved
010: 192
011: 384
100: 768
101: 1536
110: 3072
111: 6144
Table 9. Comparator Threshold High MSB
Address = 0x07, Default=0xFF, Direction=R/W
Bit Field
Field Name
7:0
Threshold High
Description
Threshold High Register.
Table 10. Comparator Threshold Low MSB
Address = 0x09, Default=0x00, Direction=R/W
18
Bit Field
Field Name
7:0
Threshold Low
Description
Threshold Low Register.
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Table 11. INTB Terminal Configuration
Address = 0x0A, Default=0x00, Direction=R/W
Bit Field
Field Name
7:3
Reserved
2:0
Mode
Description
Reserved to 0
000: All modes disabled
001: Wake-up Enabled on INTB terminal
010: INTB terminal indicates the status of Comparator output
100: DRDYB Enabled on INTB terminal
All other combinations are Reserved
Table 12. Power Configuration
Address = 0x0B, Default=0x00, Direction=R/W
Bit Field
Field Name
7:1
Reserved
0
PWR_MODE
Description
Reserved to 0
0:Stand-By mode
1:Active Mode. Conversion is Enabled
Refer to Power Modes for more details.
Table 13. Status
Address = 0x20, Default=NA, Direction=RO
Bit Field
Field Name
7
OSC status
6
Data Ready
Description
1:Indicates oscillator overloaded and stopped
0:Oscillator working
1:No new data available
0:Data is ready to be read
5
Wake-up
4
Comparator
3:0
Do not Care
1:Wake-up disabled
0:Wake-up triggered. Proximity data is more than Threshold High value.
1:Proximity data is less than Threshold Low value
0:Proximity data is more than Threshold High value
Table 14. Proximity Data
Address = 0x22, Default=NA, Direction=RO
Bit Field
Field Name
7:0
Proximity data
Description
Proximity data
Conversion data is updated to the proximity register only when a read is initiated on 0x22 register. If the read is
delayed between subsequent conversions, these registers are not updated until another read is initiated on 0x22.
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8 Applications and Implementation
8.1 Application Information
8.1.1 Calculation of Rp_MIN and Rp_MAX
Different sensing applications may have a different range of the resonance impedance Rp to measure. The
LDC1051 measurement range of Rp is controlled by setting 2 registers – Rp_MIN and Rp_MAX. For a given
application, Rp must never be outside the range set by these register values, otherwise the measured value will
be clipped. For optimal sensor resolution, the range of Rp_MIN to Rp_MAX should not be unnecessarily large.
The following procedure is recommended to determine the Rp_MIN and Rp_MAX register values.
8.1.1.1 Setting Rp_MAX
Rp_MAX sets the upper limit of the LDC1051 resonant impedance input range.
•
•
•
Configure the sensor such that the eddy current losses are minimized. As an example, for a proximity sensing
application, set the distance between the sensor and the target to the maximum sensing distance.
Measure the resonant impedance Rp using an impedance analyzer.
Multiply Rp by 2 and use the next higher value from Table 4.
Note that setting Rp_MAX to a value not listed in Table 4 can result in indeterminate behavior.
8.1.1.2 Setting Rp_MIN
Rp_MIN sets the lower limit of the LDC1051 resonant impedance input range.
•
•
•
Configure the sensor such that the eddy current losses are maximized. As an example, for a proximity
sensing application, set the distance between the sensor and the metal target to the minimum sensing
distance.
Measure the resonant impedance Rp using an impedance analyzer.
Divide the Rp value by 2 and then select the next lower Rp value from Table 6.
Note that setting Rp_MIN to a value not listed on Table 6 can result in indeterminate behavior. In addition,
Rp_MIN powers on with a default value of 0x14 which must be set to a value from Table 6 prior to powering on
the LDC.
8.1.2 Output Data Rate
Output data rate of LDC1051 depends on the sensor frequency, fsensor and 'Response Time' field in LDC
Configuration register(Address:0x04).
fsensor
Output Data Rate
§ Response time ·
¨
¸
3
©
¹
(4)
8.1.3 Choosing Filter Capacitor (CFA and CFB Terminals)
The Filter capacitor is critical to the operation of the LDC1051. The capacitor should be low leakage, temperature
stable, and it must not generate any piezoelectric noise (the dielectrics of many capacitors exhibit piezoelectric
characteristics and any such noise is coupled directly through Rp into the converter). The optimal capacitance
values range from 20pF to 100nF. The value of the capacitor is based on the time constant and resonating
frequency of the LC tank.
If a ceramic capacitor is used, then a C0G (or NP0) grade dielectric is recommended; the voltage rating should
be ≥10V. The traces connecting CFA and CFB to the capacitor should be as short as possible to minimize any
parasitics.
For optimal performance, the chosen filter capacitor, connected between terminals CFA and CFB, needs to be as
small as possible, but large enough such that the active filter does not saturate. The size of this capacitor
depends on the time constant of the sense coil, which is given by L/Rs, (L=inductance, Rs=series resistance of
the inductor at oscillation frequency). The larger this time constant, the larger filter capacitor is required. Hence,
this time constant reaches its maximum when there is no target present in front of the sensing coil.
20
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Application Information (continued)
The following procedure can be used to find the optimal filter capacitance:
1. Start with a large filter capacitor. For a ferrite core coil, 10nF is usually large enough. For an air coil or PCB
coil, 100pF is usually large enough.
2. Power on the LDC and set the desired register values. Minimize the eddy currents losses. This is done by
minimizing the amount of conductive target covering the sensor. For an axial sensing application, the target
should be at farthest distance from coil. For a lateral or angular position sensing application, the target
coverage of the coil should be minimized.
3. Observe the signal on the CFB terminal using a scope. Since this node is very sensitive to capacitive
loading, it is recommended to use an active probe. As an alternative, a passive probe with a 1kΩ series
resistance between the tip and the CFB terminal can be used.
4. Vary the values of the filter capacitor until that the signal observed on the CFB terminal has an amplitude of
approximate 1V peak-to-peak. This signal scales linearly with the reciprocal of the filter capacitance. For
example, if a 100pF filter capacitor is applied and the signal observed on the CFB terminal has a peak-topeak value of 200mV, the desired 1V peak-to-peak value is obtained using a 200mV / 1V * 100pF = 20pF
filter capacitor.
8.2 Typical Applications
8.2.1 Axial Distance Sensing Using a PCB Sensor with LDC1051
LDC10xx NHR
18uH
Figure 16. Typical Application Schematic, LDC10xx
8.2.1.1 Design Requirements
For this design example, use the following as the input parameters.
Table 15. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Minimum sensing distance
1 mm
Maximum sensing distance
8 mm
Output data rate
78 KSPS (Max data rate with LDC10xx series)
Number of PCB layers for sensor
2 layers
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8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Sensor and Target
In this example, consider a sensor with the below characteristics.
Table 16. Sensor Characteristics
PARAMETER
VALUE
Layers
2
Thickness of copper
1 Oz
Coil shape
Circular
Number of turns
23
Trace thickness
4 mil
Trace spacing
4 mil
PCB core material
FR4
Rp @ 1 mm
5 kΩ
Rp @ 8 mm
12.5 kΩ
Nominal Inductance
18 µH
Target material used is stainless steel
8.2.1.2.2 Calculating Sensor Capacitor
Sensor frequency depends on various factors in the application. In this example since one of the design
parameter is to achieve output data rate of 78 KSPS, sensor frequency can be calculated as below.
fsensor
Output Data Rate
§ Response time ·
¨
¸
3
©
¹
(5)
With the lowest Response time of 192 and output data rate of 78 KSPS, sensor frequency calculated using the
above formula is 4.99 MHz.
Now, using the below formula sensor capacitor is calculated to be 55 pF with a sensor inductance of 18 µH
1
L
C u (2S u fsensor )2
(6)
8.2.1.2.3 Choosing Filter Capacitor
Using the steps given in Choosing Filter Capacitor (CFA and CFB Terminals) filter capacitor for the example
sensor is 20 pF. Below waveform shows the pattern on CFB terminal with 100 pF and 20 pF filter capacitor.
Figure 17. Waveform On CFB With 100pf
22
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Figure 18. Waveform On CFB With 20pf
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8.2.1.2.4 Setting Rp_MIN and Rp_MAX
Calculating value for Rp_MAX Register : Rp at 8mm is 12.5kΩ, 12500×2 = 25000. In Table 4, then 27.704 kΩ is
the nearest value larger than 25kΩ; this corresponds to Rp_MAX value of 0x12
Calculating value for Rp_MIN Register : Rp at 1mm is 5kΩ, 5000/2 = 2500. In Table 6, 2.394kΩ is the nearest
value lower than 2.5kΩ; this corresponds to Rp_MIN value of 0x3B
8.2.1.2.5 Calculating Minimum Sensor Frequency
Using,
N
§ F ·
68.94 u log10 ¨
¸
© 2500 ¹
(7)
N is 227.51, round off to 228 decimal. This value has to be written into Watchdog Timer Register, which is used
to wake up the internal circuit when the sensor is saturated.
8.2.1.3 Application Curves
14
12
Rp (kŸ
10
8
6
4
2
0
0
1
2
3
4
5
6
Distance (mm)
7
8
C002
Figure 19. Rp vs Distance
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8.2.2 Lateral Position Sensing Application Diagram
Figure 20. Linear Position Sensing
8.2.3 Angular Position Sensing Application Diagram
Figure 21. Angular Position Sensing
24
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9 Power Supply Recommendations
The LDC1051 is designed to operate from an analog supply range of 4.75 V to 5.25 V and digital I/O supply
range of 1.8V to 5.25V. The analog supply voltage should be greater than or equal to the digital supply voltage
for proper operation of the device. The supply voltage should be well regulated. If the supply is located more than
a few inches from the LDC1051 additional bulk capacitance may be required in addition to the ceramic bypass
capacitors. An electrolytic capacitor with a value of 10uF is a typical choice.
10 Layout
10.1 Layout Guidelines
•
•
•
•
•
The VDD and VIO terminal should be bypassed to ground with a low ESR ceramic bypass capacitor. The
typical recommended bypass capacitance is 0.1uF ceramic with a X5R or X7R dielectric.
The optimum placement is closest to the VDD/VIO and GND/DGND terminals of the device. Care should be
taken to minimize the loop area formed by the bypass capacitor connection, the VDD/VIO terminal, and the
GND/DGND terminal of the IC. See Figure 22 for a PCB layout example.
The CLDO terminal should be bypassed to digital ground (DGND) with a 56nF ceramic bypass capacitor.
The filter capacitor selected for the application using the procedure described in section Choosing Filter
Capacitor (CFA and CFB Terminals) is connected between CFA and CFB terminals. Place the filter capacitor
close to the CFA and CFB terminals. Do not use any ground/power plane below the capacitor and the trace
connecting the capacitor and the CFA /CFB terminals.
Use of two separate ground plane for GND and DGND is recommended with a start connection. See
Figure 22 for a PCB layout example.
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10.2 Layout Example
Figure 22. LDC10xx Board Layout
26
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11 Device and Documentation Support
11.1 Trademarks
All trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LDC1051NHRJ
ACTIVE
WSON
NHR
16
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LDC1051
LDC1051NHRR
ACTIVE
WSON
NHR
16
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LDC1051
LDC1051NHRT
ACTIVE
WSON
NHR
16
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LDC1051
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-May-2014
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
NHR0016B
SDA16B (Rev A)
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