TI BQ24721RHBT Advanced multi-chemistry and multi-cell synchronous switch-mode charger and system power selector Datasheet

bq24721
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SLUS683 – NOVEMBER 2005
ADVANCED MULTI-CHEMISTRY AND MULTI-CELL SYNCHRONOUS SWITCH-MODE
CHARGER AND SYSTEM POWER SELECTOR
FEATURES
APPLICATIONS
•
•
•
•
PH
REGN
LODRV
PGND
ALARM
28
27
26
25
HIDRV
30
29
1
24
BATDRV
ACDRV
2
23
SYS
ACN
3
22
SYNP
ACP
4
21
SYNN
ACDET
5
20
SRP
BYPASS
6
19
SRN
EAO
7
18
BAT
EAI
8
17
IOUT
14
15
16
TS
ISYNSET
13
SDA
SCL
11
bq24721
12
SBS-Like interface is not 100% SBS compliant. SBS-Like
interface is SMBus1.1 complaint but does not support Packet
Error Correction (PEC). The control and status registers were
changed to simplify and enhance notebook charger control.
An eight bit address (0x12) is used. See Table 1 for a
comparison between SBS-like vs SBS Specification.
CHGEN
VCC
(1)
5x5 QFN PACKAGE (TOP VIEW)
VREF5
•
•
•
PVCC
•
Integrated features such as charger soft start, charge
overcurrent protection, and IC temperature monitoring
provide a second level of protection, in addition to
pack and system protection functions.
BTST
•
The adapter isolation diode can be bypassed with an
external MOSFET using a control signal provided by
the bq24721, thus reducing overall power dissipation.
32
•
High accuracy current sense amplifiers enable
accurate measurement of either the charge current or
the ac adapter current, allowing termination of
nonsmart packs and monitoring of overall system
power.
31
•
•
•
•
•
The dynamic power management (DPM) function
modifies the charge current depending on system
load conditions, avoiding ac adapter overload.
9
•
The bq24721 is a simple to use, high efficiency
synchronous battery pack charger with high level of
integration for portable applications. This device
implements a high performance analog front-end that
easily interfaces to the system power management
micro-controller through a simplified SBS-like SMBus
interface.
10
•
•
•
DESCRIPTION
FBO
•
Portable Notebook Computers
Portable DVD Players
Webpads, PC Tablets
AGND
•
High Efficiency NMOS-NMOS Synchronous
Buck Converter With User-Selectable 300 kHz
or 500 kHz frequency
SBS-Like (1) SMBus Interface for Control and
Status Communications With Host
Programmable Battery Voltage, Charge
Current, and AC Adapter Current via SBS-Like
SMBus Interface
0.4% Charge Voltage Regulation Accuracy
3% Charge Current Regulation Accuracy
3% Adapter Current Regulation Accuracy
Dynamic Power Management (DPM)
2% Accuracy Integrated Charge and AC
Adapter 20x Current Amplifier Output
Battery Pack Voltage Range 0 V – 19.2 V
AC Adapter Operating Range 8 V – 28 V
99.5% Max Duty Cycle
Internal Soft Start
Integrated 5% 5-V LDO When AC Adapter
Applied
6-V Drive Supply Voltage for Increased
Efficiency
Reverse Battery to Adapter Discharge
Protection
Battery/Adapter to System Power Selector
Function
Charge and Adapter Overcurrent Protection
Battery Thermistor Sense, TS, Comparators
Available in 32-Pin 5x5mm QFN Package
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
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SLUS683 – NOVEMBER 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PART NO.
PACKAGE
THERMISTOR
SENSE
BATTERY SHORTED
(VERY LOW BATTERY
VOLTAGE) OPERATION
bq24721
32 PIN
5x5mm QFN
TS
Charge Current Changes to
C/8
ORDERING NUMBER
(TAPE AND REEL)
QUANTITY
bq24721RHBR
3000
bq24721RHBT
250
PACKAGE THERMAL DATA
(1)
(2)
PACKAGE (1)
θJA
TA ≤ 40°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
RHB (2)
36°C/W
2.36 W
0.028 W/°C
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
This data is based on using the JEDEC High-K board and the exposed die pad is connected to a copper pad on the board. This is
connected to the ground plane by a 2×3 via matrix.
DEVICE INFORMATION
TERMINAL FUNCTIONS
TERMINAL
NAME
DESCRIPTION
NO.
TERMINAL
NAME
DESCRIPTION
NO
CHGEN
1
Charge enable logic level low input
IOUT
17
Battery charger or adapter current amplifier
output
ACDRV
2
AC adapter to system switch driver output
BAT
18
Battery voltage remote sense
ACN
3
Adapter current sense resistor, negative input
SRN
19
Charge current sense resistor, negative input
ACP
4
Adapter current sense resistor, positive input
SRP
20
Charge current sense resistor, positive input
ACDET
5
AC adapter detected sense voltage input
SYNN
21
SROC and SRUC, Negative sense resistor in
BYPASS
6
Adapter Schottky diode bypass switch
SYNP
22
SROC and SRUC, Positive sense resistor in
EAO
7
Error amplifier output for compensation
SYS
23
System load, voltage sense
EAI
8
Error amplifier input for compensation
BATDRV
24
Battery to system switch driver output
FBO
9
Feedback output for compensation
ALARM
25
Alarm indicating charger status change,
open-drain output
AGND
10
Analog ground
PGND
26
Power ground
VREF5
11
5V regulated voltage output. Can be used to
indicate ac present status
LODRV
27
PWM low side driver output
VCC
12
IC analog positive supply
REGN
28
Low-side driver gate voltage regulator. Add
1uFfilter capacitor
SDA
13
SMBus Data input
PH
29
High-side driver negative supply, connect
neg-side of boot-strap capacitor
SCL
14
SMBus Clock input
HIDRV
30
PWM high side driver output
TS
15
Thermistor sense input
BTST
31
High-side driver positive supply, connect
pos-side of boot-strap capacitor.
ISYNSET
16
Program SRUC of charge regulator
PVCC
32
IC power positive supply
2
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SLUS683 – NOVEMBER 2005
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1) (2)
PARAMETER
PIN
VALUE / UNIT
ACN, ACP, PVCC, ACDRV, SYNN, SYNP, SRP, SRN ,
BATDRV, BAT, BYPASS, SYS, VCC
Supply voltage range
–0.3 V to 30 V
PH
–1 V to 30 V
LODRV, REGN, FBO, EAI, EAO, ISYNSET, CHGEN, TS ,
VREF5, ACDET, IOUT, ALARM, SCL, SDA
–0.3 V to 7 V
BTST, HIDRV (with respect to AGND and PGND)
Maximum differential voltage
AGND-PGND
Maximum difference voltage
ACP–ACN , SRP–SRN, and SYNP–SYNN
Maximum voltage with respect to VCC
SRN, SRP, SYNN, SYNP, BAT, PH
Maximum difference voltage
PVCC-BAT, SYS–BAT
–1 V to 36 V
–0.3 V to 0.3 V
0.6 V
–20 V to 30 V
–20 V to 30 V
Operating ambient temperature range (TA)
–40°C to 85°C
Maximum junction temperature (TJ_MAX)
150°C
Storage temperature range (Tstg)
(1)
(2)
–65°C to 150°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to AGND, unless otherwise noted. Currents are positive into, negative out of the specified terminal. Consult
Packaging Section of the Databook for thermal limitations and considerations of packages.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
PIN
ACN, ACP, PVCC, ACDRV, SRP, SRN,
BATDRV, BAT, BYPASS, SYS, VCC, SYNN,
SYNP
PH
Supply voltage range
MIN
0
NOM
MAX
UNIT
24
V
–0.5
30
V
LODRV, REGN, VREF5
0
6.5
V
FBO, EAI, EAO, ISYNSET, CHGEN, TS ,
ACDET, SCL, SDA, ALARM
0
5.5
V
IOUT, ACDET
0
5.5
V
BTST, HIDRV
0
30
V
0
V
Maximum differential voltage
AGND-PGND
Maximum difference voltage
ACP–ACN, SYNN–SYNP, SRP–SRN
0.5
V
Maximum voltage with respect to
VCC
SRN, SRP, SYNN, SYNP, BAT, PH
–19
24
V
Maximum difference voltage
SYS–BAT, PVCC-BAT
–19
24
V
0
125
°C
-55
150
°C
Junction temperature Range (TJ)
Storage temperature Range (Tstg)
3
bq24721
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SLUS683 – NOVEMBER 2005
ELECTRICAL CHARACTERISTICS
8 Vdc ≤ V(VCC) ≤ 24 Vdc, 0°C ≤ TJ ≤ 125°C, all voltages with respect to AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BATTERY VOLTAGE REGULATION
VBAT_ICR
V(VBATREG)
VBAT Input voltage range
V(BAT)
Battery Regulation Voltage Accuracy
Full valid voltage DAC range,
SMBus DAC register 0×15
0
PVCC
V
TJ = 0°C – 85°C
–0.4
0.4
%
TJ = 0°C – 125°C
–0.5
0.5
%
9
19.2
V
1.28
162.56
BAT voltage regulation range
PWM AC ADAPTER INPUT CURRENT REGULATION, DPM (Dynamic Power Management)
V(IREG_DPM)
ACP-ACN differential voltage range
for input current regulation
V(IREG_DPM) = V(ACP)- V(ACN)
SMBus DAC register 0×3F, bits b0–b13
I(REG_step_DPM)
Current regulation LSB programming
current step
V(ACP-ACN) / 10mΩ
Using a 10mΩ sense resistor, R(SNS)
Current regulation accuracy
VCC ≥ VCC (min),
VCC ≥ VI(BAT) + V(DO-MAX), (1)
Over differential threshold range, V(IREG),
Does not include error induced by the
tolerance of the sense resistor, R(SNS)
128
mV
mA
V(ACP) – V(ACN) > 40.96 mV
(4096 mA with 10 mΩ)
–3
3
%
V(ACP) – V(ACN) > 20.48 mV
(2048 mA with 10 mΩ)
–5
5
%
V(ACP) – V(ACN) > 5.12 mV
(512 mA with 10 mΩ)
–25
25
%
1.28
162.56
PWM BATTERY CHARGE CURRENT REGULATION
V(IREG_CHG)
SRP-SRN differential voltage range
for input current regulation
V(IREG_CHG) = V(SRP)- V(SRN)
SMBus DAC register 0×14, bits b0–b13
I(REG_step_CHG)
Current regulation LSB programming
current step
V(SRP-SRN) / 10 mΩ
Using a 10mΩ sense resistor, R(SNS)
Current regulation accuracy
VCC ≥ VCC (min),
VCC ≥ VI(BAT) + V(DO-MAX), (1)
Over differential threshold range, V(IREG),
Does not include error induced by the
tolerance of the sense resistor, R(SNS)
128
mV
mA
V(SRP-SRN) > 40.96 mV
(4096 mA with 10 mΩ)
–3
3
%
V(SRP-SRN) >20.48 mV
(2048 mA with 10 mΩ)
–5
5
%
V(SRP-SRN) > 5.12 mV
(512 mA with 10 mΩ)
–25
25
%
2.5
20
V
0
3.5
V
CHARGE CURRENT AMPLIFIER – IBAT AMPLIFIER and IADAPT AMPLIFIER → MUX TO IOUT
SRP, SRN common-mode input
voltage range
V(IOUT_IBAT)
A(IBAT)
IOUT output voltage range with IBAT
selected
V(IOUT) = V(SRP, SRN)× A(IBAT)
V(BAT) > 2.5 V or V(BAT) > V(IOUT) + V(DO-MAX) (1)
Voltage gain
A(IOUT) = V(IOUT)/ V(SRP, SRN)
Charge current amplifier accuracy
V(BAT) > 2.5 V or V(BAT) >
V(IOUT) + V(DO-MAX) (1)
20
SRN)
= 40 mV and higher
–2
2
%
V(SRP,
SRN)
= 20 mV and higher
–3
3
%
V(SRP,
SRN)
= 5 mV and higher
–25
25
%
0
24
V
ACP, ACN Common-mode input
voltage range
V(IOUT_IADAPT)
A(IADP)
I(OUT_LIM)
(1)
4
IOUT output voltage range with
IADAPT selected
V(IOUT) = V(ACP, ACN)× A(IADP)
V(SRP) > 2.5 V or V(SRP) > V(IOUT) + 1V
Voltage gain
A(IADP) = V(IOUT)/ V(ACP, ACN)
Adapter current amplifier accuracy
V(BAT) > 2.5 V or V(BAT) >
V(IOUT) + V(DO-MAX) (1)
IOUT output current limit
IOUT shorted to AGND
V/V
V(SRP,
0
3.5
20
V
V/V
V(ACP,
ACN)
= 40 mV and higher
–2
2
%
V(ACP,
ACN)
= 30 mV and higher
–3
3
%
V(ACP,
ACN)
= 5 mV and higher
–25
25
4.5
V(DO-max) is defined as the maximum drop-out voltage. V(DO-max)=1 V unless other wise specified. In an actual application, V(DO
(R(SNS) * IO) + V(DSON_HIGH_SIDE_FET) + V(DSON_BYPASS_FET).
%
mA
- MAX)
=
bq24721
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SLUS683 – NOVEMBER 2005
ELECTRICAL CHARACTERISTICS
8 Vdc ≤ V(VCC) ≤ 24 Vdc, 0°C ≤ TJ ≤ 125°C, all voltages with respect to AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING CONDITIONS
V(INOP)
V(VCC), V(PVCC), input voltage
operating range
Selector and charger operational.
8
24
V
254
µA
1
µA
QUIESCENT CURRENT – NO ADAPTER CONNECTED
I(VCC,PVCC)
VCC and PVCC quiescent
current
I(VCC,PVCC) = ( I(VCC) + I(PVCC) ) at V(VCC) = V(PVCC) = 16.8 V
I(ACP,ACN)
ACP and ACN quiescent
current
I(ACP,ACN) = ( I(ACP) + I(ACN) ) at V(ACP) = V(ACN) = V(VCC) = V(PVCC) =
16.8 V
I(BAT)
BAT quiescent current
I(BAT) at V(BAT) = V(VCC) = V(PVCC) = 16.8 V
17
µA
I(SRP,SRN)
SRP and SRN quiescent
current
I(SRP,SRN) = ( I(SRP) + I(SRN) ) at V(SRP) = V(SRN) = V(VCC) = V(PVCC) =
16.8 V
1
µA
I(SYNN,SYNP)
SYNN and SYNP quiescent
current
I(SYNN,SYNP) = ( I(SYNN) + I(SYNP) ) at V(SYNP) = V(SYNN) = V(VCC) =
V(PVCC) = 16.8 V
1
µA
I(SYS)
SYS quiescent current
I(SYS) at V(SYS) = V(VCC) = V(PVCC) = 16.8 V
25
µA
I(PH)
PH quiescent current
I(PH) at V(PH) = V(VCC) = V(PVCC) = 16.8 V
1
µA
I(BTST)
BTST quiescent current
I(BTST) at V(BTST) = V(VCC) = V(PVCC) = 16.8 V
1
µA
QUIESCENT CURRENT – ADAPTER CONNECTED AND READY TO CHARGE
I(VCC,PVCC)
VCC and PVCC quiescent
current
I(VCC,PVCC) = (I(VCC) + I(PVCC) at V(VCC) = V(PVCC) = 16.8 V
4.45
mA
I(ACP,ACN)
ACP and ACN quiescent
current
I(ACP,ACN) = (I(ACP) + I(ACN) ) at V(ACP) = V(ACN) = V(VCC) = V(PVCC) =
16.8 V
815
µA
I(BAT)
BAT quiescent current
I(BAT) at V(BAT) = V(VCC) = V(PVCC) = 16.8 V
500
µA
I(SRP,SRN)
SRP and SRN quiescent
current
I(SRP,SRN) = ( I(SRP) + I(SRN) ) at V(SRP) = V(SRN) = V(VCC) = V(PVCC) =
16.8 V
305
µA
I(SYNN,SYNP,SYS SYNN, SYNP, and SYS
quiescent current
)
I(SYNN,SYNP,SYS) = ( I(SYNN) + I(SYNP) + I(SYS) ) at V(SYNP) = V(SYNN) =
V(SYS) = V(VCC) = V(PVCC) = 16.8 V
321
µA
I(PH)
PH quiescent current
I(PH) at V(PH) = V(VCC) = V(PVCC) = 16.8 V
1
µA
I(BTST)
BTST quiescent current
I(BTST) at V(BTST) = V(VCC) = V(PVCC) = 16.8 V
1
µA
VCC Current while converter
is switching including gate
drive current
I(VCC_SW) = I(VCC)
FPWM = 300 kHz, charger on (CHGEN = LO) = ENABLED
Qg at HIDRV = Qg at LODRV = 30 nC, [No Load on VREF5]
Gate drive switching current = Qg × FPWM = (30nC + 30nC) ×
300kHz = 18mA
I(VCC_SW)
25
mA
5V REFERENCE LDO VOLTAGE AND AC DETECTION STATUS (VREF5, turns-on when AC detected)
VVREF5
5V Regulator output voltage
Adapter detected (VACDET>V(ACD)), VCC> 7 V
0 → 10 mA, source current
VVREF5_SAT
Saturation voltage when
VREF5 is off
Adapter not detected, (VACDET< V(ACD))
0 →– 10 mA, ac adapter inserted, CO = 1 µF, discharge Load
IVREF5_LIM
Short-circuit current
V(VREF5) = AGND
20
mA
Under voltage lockout
threshold
VREF5 rising, POR mode set at VREF5 < V(UVLO)
3.7
V
V(UVLO) hysteresis
VREF5 falling
100
mV
4.75
5
5.25
V
0.3
V
UNDERVOLTAGE LOCKOUT CIRCUIT
UVLO
SBS-Like SMBus LOGIC LEVELS
VIL
Input low threshold level
2.7 V < V(pull-up) < 5.5 V, SDA and SCL
VIH
Input high threshold level
2.7 V < V(pull-up) < 5.5 V, SDA and SCL
Ibias
Input bias current
2.7 V < V(pull-up) < 5.5 V, SDA and SCL
0.8
V
1
µA
0.5
V
1
µA
2.1
V
ALARM OPEN DRAIN OUTPUTS
V(ALARM_sat)
ALARM output low saturation
level
I(ALARM) = 5mA
Ilkg(ALARM)
ALARM leakage current
VALARM = 5V
THERMAL SHUTDOWN
T(SHUT)
Thermal shutdown Threshold
TJ rising, Charge disabled at TJ > T(SHUT)
T(SHUTH)
Hysteresis
TJ falling, Charge enabled at TJ < T(SHUT)– T(SHUTH)
Deglitch time, thermal
shutdown
TJ rising/falling
145
°C
15
°C
8
ms
5
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ELECTRICAL CHARACTERISTICS (continued)
8 Vdc ≤ V(VCC) ≤ 24 Vdc, 0°C ≤ TJ ≤ 125°C, all voltages with respect to AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
THERMISTOR COMPARATORS, TS
V(LTF)
Cold temperature threshold,
TS pin voltage
V(TS) rising
72.8
73.5
74.2
%VREF5
V(LTFH)
Hysteresis for LTF threshold
V(TS) falling
0.5
1
1.5
%VREF5
V(TCO)
Cutoff temperature threshold,
TS pin voltage
V(TS) rising
28.7
29.3
29.9
%VREF5
V(HTF)
Hot temperature threshold, TS
V(TS) rising/falling
pin voltage
33.7
34.4
35.1
%VREF5
V(TSDET)
Pack thermistor insertion
detected
VT(S) rising/falling
82.45
85
87.55
%VREF5
Deglitch time for temperature
out of range detection
V(TS) rising above V(LTF), or V(TS) falling below V(TCO) , or V(TS)
falling below V(HTF)
Deglitch time for temperature
in valid range detection
V(TS) falling below (V(LTF) - V(LTFH)), or V(TS) rising above V(TCO) , or
V(TS) rising above V(HTF)
Deglitch time for thermistor
removal detection
Deglitch time for thermistor
insertion detection
16
µs
8
ms
V(TS) rising above V(TSDET)
V(TS) > V(TSDET) (pack removed)
16
µs
V(TS) falling below V(TSDET)
V(TS) < V(TSDET) (pack inserted)
1
s
CHARGE OVERCURRENT COMPARATOR
V(OLP)
Overcurrent protection
threshold
V(SRP-SRN) rising
200
%I(REG_CHG)
V(OLPH)
Hysteresis
V(SRP-SRN) falling
20
%I(REG_CHG)
6
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SLUS683 – NOVEMBER 2005
ELECTRICAL CHARACTERISTICS
8 Vdc ≤ V(VCC) ≤ 24 Vdc, 0°C ≤ TJ ≤ 125°C, all voltages with respect to AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SYSTEM STATUS COMPARATORS INPUT SPECIFICATIONS
VICR
Commom mode input range at
pin: ACDET
0
5
V
Commom mode input range at
TS pin
0.5
VREF5
V
0
VCC
V
0.2
µA
2.2
2.9
V/cell
-2
2
Common mode input voltage
range at pins: BAT, SYS
Input bias currents at pins:
ACDET, TS, BATDEP, SYS
I(bias)
BATTERY DEPLETED COMPARATOR (BATDEP)
V(BATDEP)
BAT depleted voltage range
V(BATDEP) = 2.2 V + Vstep × batdep_dac_code, where
batdep_dac_code = 0 - 7, and Vstep = 0.1V, SMBus Charge Mode
register 0×12, bits b9, b10, b11
For programmed V(BATREG) = 9 V, then cell = 2
For programmed V(BATREG) = 12 V - 14.4 V, then cell = 3
For programmed V(BATREG) = 16 V - 19.2 V, then cel l= 4
BAT depleted accuracy
%
Battery depleted detection
deglitch time
V(BAT) falling
1
s
Battery not depleted detection
deglitch time
V(BAT) rising
1
s
AC ADAPTER DETECT COMPARATOR (ACDET)
V(ACD)
AC adapter detect threshold
V(ACDET) rising, When adapter detected, VREF5 is enabled, and
REGN regulates to 6 V
V(ACDH)
AC adapter detect hysteresis
V(ACDET) falling
15
mV
AC adapter detected deglitch
time
V(ACDET) rising
8
ms
AC adapter not detected
deglitch time
V(ACDET) falling
1
µs
1.176
1.2
1.224
V
AC ADAPTER (ACP) - BATTERY (BAT) COMPARATOR
V(ACP-BAT)
ACP voltage above BAT voltage
V(ACP) falling with respect to V(BAT)
threshold
V(ACP-
Hysteresis
V(ACP-BAT) rising with respect to V(BAT)
50
mV
V(ACP-BAT) falling below
threshold deglitch time
V(ACP) falling with respect to V(BAT)
16
µs
V(ACP-BAT) rising above
thresholddeglitch time
V(ACP-BAT) rising with respect to V(BAT)
8
ms
BAT)HYS
250
300
mV
SYSTEM (SYS) - BATTERY (BAT) COMPARATOR
V(SYS-BAT)
System voltage above pack
voltage at V(VS,BAT) > V(SYS)
V(SYS-BAT)HYS Hysteresis
V(SYS-BAT) falling below
threshold deglitch time
V(SYS-BAT) rising above
thresholddeglitch time
V(SYS) falling with respect to V(BAT)
250
V(SYS-BAT) rising with respect to V(BAT)
300
mV
50
mV
V(SYS) falling with respect to V(BAT)
1
µs
V(SYS-BAT) rising with respect to V(BAT)
8
ms
BATTERY SHORTED COMPARATOR
V(BATSHORT)
V(SHRT_HYS))
(1)
Battery shorted threshold (1)
V(BAT) falling,
Programmed V(BAT) = 9V
3.230
3.4
3.570
V
V(BAT) falling,
Programmed V(BAT) = 12-14.4V
4.845
5.1
5.355
V
V(BAT) falling,
Programmed V(BAT) = 16-19.2V
6.460
6.8
7.140
V
Hysteresis
V(BAT) rising
Battery shorted deglitch time
V(BAT) rising/falling
200
1
mV/cell
s
For the bq24721: When BAT falls below the V(BATSHORT) threshold, the charger continues regulating at the programmed current down to
zero volts on BAT; then after 1 second deglitch time, the charge current automatically changes to 1/8 the programmed charge current.
The charge current automatically changes from 1/8 the programmed charge current to the full programmed charge current when BAT
voltage rises above (V(BATSHORT) + 200 mV hysteresis), after 1 second deglitch time.
7
bq24721
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SLUS683 – NOVEMBER 2005
ELECTRICAL CHARACTERISTICS
8 Vdc ≤ V(VCC) ≤ 24 Vdc, 0°C ≤ TJ ≤ 125°C, all voltages with respect to AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BYPASS P-Channel MOSFET DRIVER (BYPASS)
R(DS_BYP)
R(DS_BYP)
Hi
Lo
V(REGBYPASS)
BYPASS off-state resistance
Driver output = HI, BYPASS = V(PVCC), V(PVCC) = 18 V
1
2
kΩ
BYPASS on-state resistance
Driver output = LO,
BYPASS = V(PVCC) - V(REGBYPASS), V(PVCC) = 18 V
1
2
kΩ
Drive regulator turn-on voltage
for BYPASS with respect to
V(PVCC)
V(VCC, BYPASS), V(VCC) > 13 V, I(BYPASS) = 5 mA
-6
-7.5
100
150
Ω
10
20
kΩ
-6.5
-7.5
100
150
Ω
10
20
kΩ
-6.5
-7.5
-5
V
AC ADAPTER P-Channel MOSFET DRIVER (ACDRV)
R(DS_AC)
Hi
ACDRV off-state resistance
Driver output = HI, ACDRV = PVCC, V(PVCC) = 18 V
R(DS_AC)
Lo
ACDRV on-state resistance
Driver output = LO, ACDRV =V(PVCC)-V(REGAC), V(PVCC) = 18 V
Drive regulator turn-on voltage
for ACDRV with respect to
V(PVCC)
V(VCC, ACDRV), V(VCC) > 13 V, I(ACDRV) = 5 mA
V(REGAC)
-5
V
BATTERY P-Channel MOSFET DRIVER (BATDRV )
R(DS_BAT)
Hi
BATDRV off-state resistance
Driver output = HI, V(PVCC) = 18 V
R(DS_BAT)
Lo
BATDRV on-state resistance
Driver output = LO, BATDRV=V(PVCC)-V(REGBAT), V(PVCC) = 18 V
Drive regulator negative turn-on
voltage for BATDRV with
respect to V(SYS)
V(VCC, BATDRV), V(VCC) > 13 V, I(BATDRV) = 5 mA
V(REGBAT)
-5
V
SYSTEM POWER SELECTOR TIMING
Dead time when switching
between ACDRV and BATDRV
No load at ACDRV and BATDRV
1
µs
1
µs
BYPASS SWITCH TIMING
Delay to turn-off BYPASS
8
bq24721
www.ti.com
SLUS683 – NOVEMBER 2005
ELECTRICAL CHARACTERISTICS
8 Vdc ≤ V(VCC) ≤ 24 Vdc, 0°C ≤ TJ ≤ 125°C, all voltages with respect to AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PWM HIGH-SIDE N-Channel MOSFET DRIVER (HIDRV)
R(DS_HIDRV)
High-side on-state resistance
HSD switch on, HIDRV = HI, V(BOOST,PH) = 5.5 V
2.2
3
Ω
High-side off-state resistance
HSD switch off, HIDRV = LO, V(BOOST,PH) = 5.5 V
1.5
2.5
Ω
Hi
R(DS_HIDRV)
Lo
PWM LOW-SIDE N-Channel MOSFET DRIVER (LODRV)
R(DS_LODRV)
Low-side on-state resistance
LSD switch on, LODRV = HI, V(PVCC) = 7 V
2.2
3
Ω
Low-side off-state resistance
LSD switch off, LODRV = LO, V(PVCC) = 7 V
1.5
2.5
Ω
6
6.5
V
Hi
R(DS_LODRV)
Lo
PWM LOW-SIDE DRIVER REGULATOR (REGN)
VO(HREGN)
IO(REGN_SW)
I(REGN_LIM)
REGN output voltage
REGN output current while
charger switching
REGN Current limit
Adapter detected
REGN Current limit
Adapter not detected
V(REGN) at I(REGN) = 10 mA, sourcing,
Adapter detected (VACDET > V(ACD)), V(PVCC) > 7 V
5.5
V(REGN) at I(REGN) = 10 mA, sourcing,
Adapter not detected, (VACDET < V(ACD)), V(PVCC) > 7 V
4.2
V
2 times 25 nC load, Fs = 300 kHz
15
mA
2 times 25 nC load, Fs = 500 kHz
25
mA
VREGN = 5 V
Adapter detected (VACDET > V(ACD)), V(PVCC)> 7 V
100
mA
VREGN = 0 V, shorted
Adapter detected (VACDET > V(ACD)), V(PVCC)> 7 V
13.3
mA
15
mA
30
ns
0.35
V
VREGN = 4.2 V
Adapter not detected, (VACDET < V(ACD)), V(PVCC)> 7 V
PWM DRIVERS TIMING
Dead time when switching
between LSD and HSD, no
load at LSD and HSD
PWM OSCILLATOR
V(RAMPLO)
PWM oscillator ramp voltage ,
low value
0% duty cycle occurs below this threshold
V(RAMPHI)
PWM oscillator ramp voltage ,
high value
near 100% duty cycle occurs above this threshold
VPP(RAMP)
PWM ramp peak-to-peak
amplitude
V(RAMPCL)
PWM oscillator ramp clamp
voltage
FS
3
V
0.1×VCC
V
3.5
V
PWM oscillator frequency (300
kHz)
265
300
345
kHz
PWM oscillator frequency (500
kHz)
425
500
575
kHz
INTERNAL SOFT START (8 steps to Ireg)
SRSET pin voltage number of
steps during soft start.
Eight steps of charge current regulation to get to programmed
value
(SRSET = 1 V).
Step Duration.
Eight steps of charge current regulation to get to programmed
value
(SRSET = 1 V).
8
0.8
1
step
1.2
ms/step
CHARGER SECTION POWER-UP SEQUENCING
Time delay between power up
of charger block references
(first) and start charge (second)
Time delay from adapter
detected until ACDRV enable
and charger block enable
1
ms
500
ms
9
bq24721
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SLUS683 – NOVEMBER 2005
TYPICAL CHARACTERISTICS
VREF5 LOAD REGULATION
vs
LOAD CURRENT
VREF5 LINE REGULATION
vs
INPUT VOLTAGE
5
4.988
VI = 20 V
4.99
114
VI = 20 V
VI = 20 V
IL - VREF5 Current Limit - mA
4.986
TJ = 0 C
VREF5 Line Regulation - V
VREF5 Load Regulation - V
o
4.98
o
TJ = 25 C
4.97
4.96
o
TJ = 85 C
4.95
4.94
o
TJ = 125 C
4.93
o
o
TJ = 0 C
4.984
TJ = 25 C
o
4.982
TJ = 85 C
4.98
4.978
o
TJ = 125 C
4.976
4.92
VREF5 CURRENT LIMIT
vs
JUNCTION TEMPERATURE
5
10 15
20 25 30 35 40 45 50
112
111
110
109
108
4.974
0
113
7
9
11
IL − Load Current − mA
13
15
17
19
21
REGN LOAD REGULATION
vs
LOAD CURRENT
REGN LINE REGULATION
vs
INPUT VOLTAGE
REGN CURRENT LIMIT
vs
JUNCTION TEMPERATURE
116
5.92
VI = 20 V
VI = 20 V
TJ = 0 C
o
TJ = 25 C
5.85
5.8
o
TJ = 85 C
5.75
5.91
o
TJ = 25 C
5.9
o
TJ = 85 C
5.89
5.88
o
TJ = 125 C
o
5.7
IL - REGN Current Limit - mA
o
TJ = 0 C
REGN Loin Regulation - V
10 15
20 25 30 35 40 45 50
7
9
IL − Load Current − mA
11
13
15
17
19
21
115.5
115
114.5
114
113.5
113
0
5.87
5
23 24
20
40
60
80
100
110 120 125
o
TJ − Junction Temperature − C
VI − Input Voltage − V
Figure 4.
Figure 5.
Figure 6.
REGN CURRENT LIMIT
vs
FORCED REGN VOLTAGE
QUIESCENT CURRENT, NO
ADAPTER
vs
JUNCTION TEMPERATURE
QUIESCENT CURRENT, WITH
ADAPTER
vs
JUNCTION TEMPERATURE
160
280
Quiescent Current, No Adapter - mA
VCC = 24 V
120
100
80
60
40
20
0
270
260
250
VI = 16.8 V
240
VI = 12.6 V
230
220
210
200
1
2
3
4
5
VI − Forced REGN Voltage − V
Figure 7.
6
0
20
40
60
80
100
110 120 125
o
TJ − Junction Temperature − C
Figure 8.
Quescent Current, Adapter Connected - mA
REGN Load Regulation - V
110 120 125
Figure 3.
TJ = 125 C
IL - REGN Current Limit - mA
100
o
o
10
80
Figure 2.
5.9
0
60
Figure 1.
VI = 20 V
140
40
TJ − Junction Temperature − C
VI − Input Voltage − V
5.95
0
20
0
23 24
5.8
5.6
5.4
VI = 16.8 V
5.2
5
VI = 12.6 V
4.8
4.6
4.4
4.2
4
-15
5
25
45
65
85
105 125
o
TJ − Junction Temperature − C
Figure 9.
bq24721
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SLUS683 – NOVEMBER 2005
TYPICAL CHARACTERISTICS (continued)
ACDET THRESHOLD
vs
JUNCTION TEMPERATURE
ACDET HYSTERESIS
vs
JUNCTION TEMPERATURE
1.2012
19.25
VI = 20 V
2.7
19.2
1.2008
1.2006
1.2004
1.2002
1.2
1.1998
VI = 20 V
VI = 20 V
19.15
2.5
rDS(on) - HIDRV Pull Up - W
Vhys - ACDET Hysteresis - mV
VI - ACDET Threshold - V
1.201
19.1
19.05
19
18.95
18.9
18.85
18.75
0
20
40
60
80
100
110 120 125
2.1
1.9
1.7
1.5
0
o
20
40
60
80
100
110 120 125
0
o
20
40
60
80
100
110 120 125
o
TJ − Junction Temperature − C
TJ − Junction Temperature − C
Figure 10.
Figure 11.
Figure 12.
HIDRV, rDS(on), PULL DOWN
vs
JUNCTION TEMPERATURE
LODRV, rDS(on), PULL UP
vs
JUNCTION TEMPERATURE
LODRV, rDS(on), PULL DOWN
vs
JUNCTION TEMPERATURE
1.9
TJ − Junction Temperature − C
2.7
1.9
VI = 20 V
VI = 20 V
1.7
1.6
1.5
1.4
1.3
1.2
VI = 20 V
1.8
2.5
rDS(on) - LODRV Pull Down - W
rDS(on) - LODRV Pull Up - W
1.8
2.3
2.1
1.9
1.7
1.1
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
1.5
20
0
40
60
80
100
110 120 125
1
0
o
20
40
60
80
100
110 120 125
0
o
TJ − Junction Temperature − C
20
40
60
80
100
110 120 125
o
TJ − Junction Temperature − C
TJ − Junction Temperature − C
Figure 13.
Figure 14.
Figure 15.
BATTERY VOLTAGE REGULATION
ACCURACY
vs
BATTERY VOLATGE
BATTERY VOLTAGE REGULATION
vs
JUNCTION TEMPERATURE
CHARGE CURRENT REGULATION
ACCURACY
vs
SRP-SRN VOLTAGE
VI = 24 V
0.08
0.06
o
TJ = 85 C
0.04
0.02
0
-0.02
o
TJ = 25 C
-0.04
o
TJ = 125 C
-0.06
-0.08
o
TJ = 0 C
0.1
15
Charge Current, Regulation Accuracy - %
0.1
Battery Voltage Regulation Accuracy - %
Battery Voltage Regulation Accuracy - %
2.3
18.8
1.1996
rDS(on) - HIDRV Pull Down - W
HIDRV, rDS(on), PULL UP
vs
JUNCTION TEMPERATURE
0.08
0.06
0.04
VI = 12.6 V
0.02
0
VI = 16.8 V
-0.02
-0.04
-0.06
-0.08
-0.1
-0.1
9
11
13
15
17
V(BAT) − Battery Voltage − V
Figure 16.
19
0
20
40
60
80
100
110 120 125
o
TJ − Junction Temperature − C
Figure 17.
VI = 20 V
13
11
o
TJ = 125 C
9
7
o
TJ = 85 C
5
o
TJ = 25 C
3
o
TJ = 0 C
1
-1
5
15
25
35
45
55
65
VI − SPR-SRN Voltage − mV
Figure 18.
11
bq24721
www.ti.com
SLUS683 – NOVEMBER 2005
TYPICAL CHARACTERISTICS (continued)
VI = 20 V
11
9
o
TJ = 125 C
7
o
TJ = 85 C
5
o
TJ = 25 C
3
o
TJ = 0 C
1
-1
9
13
17
21
25
29
33
37
41
VI = 20 V
4
5.12 mV
3
2
10.24 mV
1
40.96 mV
20.48 mV
0
-1
14
16
0.18
0.16
o
o
TJ = 125 C
TJ = 25 C
0.14
0.12
0.1
0
10
20 30 40 50 60
70 80 90 100
IO = DPM CURRENT SENSE
AMPLIFIER OFFSET
vs
JUNCTION TEMPERATURE
IO = ADAPTER OUTPUT CURRENT
LIMIT
vs
JUNCTION TEMPERATURE
IO = CHARGE SENSE AMPLIFIER
ACCURACY
vs
SRP-SRN VOLATGE
VI = 20 V
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
20
40
60
80
100
110 120 125
5.95
5.9
5.85
5.8
5.75
5.7
5.65
5.6
0
TJ − Junction Temperature − C
20
40
60
80
100
110 120 125
o
TJ − Junction Temperature − C
0.2
0
-0.2
o
TJ = 125 C
-0.4
o
TJ = 85 C
-0.6
-0.8
o
TJ = 25 C
-1
VI = 20 V
o
TJ = 0 C
-1.2
-1.4
0
10
20 30 40 50 60
70 80 90 100
VI − SRP-SRN Voltage − mV
Figure 22.
Figure 23.
Figure 24.
IO = CHARGE CURRENT LIMIT
vs
JUNCTION TEMPERATURE
300-kHz SWITCHING FREQUENCY
vs
INPUT VOLTAGE
300-kHz SWITCHING FREQUENCY
vs
JUNCTION TEMPERATURE
311
300-kHz Switching Frequency - kHz
5.7
5.65
5.6
5.55
5.5
5.45
5.4
311
o
TJ = 85 C
VI = 20 V
300-kHz Switching Frequency - kHz
5.75
310.5
o
TJ = 125 C
310
309.5
o
TJ = 25 C
309
308.5
o
TJ = 0 C
20
40
60
80
100
110 120 125
o
TJ − Junction Temperature − C
Figure 25.
VI = 20 V
310.5
310
309.5
309
308.5
308
0
o
TJ = 85 C
0.2
VI − ACP-ACN Voltage − mV
6
0.8
0.22
Figure 21.
1
0.9
0.24
Figure 20.
IO - Adapter Output Current Limit - mA
IO = DPM Current Sense Amplifier Offset - mV
24
VI = 20 V
o
TJ = 0 C
Figure 19.
o
IO - Charge Output Current Limit - mA
22
0.28
0.26
VI − Voltage − mV
VI − ACP-ACN Voltage − mV
12
20
18
IO = Charge Current Sense Amplifier Accuracy - %
5
5
IO = DPM CURRENT SENSE
AMPLIFIER ACCURACY
vs
ACP-ACN VOLATGE
IO = DPM Current Sense Amplifier Accuracy - %
13
INPUT CURRENT REGULATION
(DPM) ACCURACY
vs
INPUT VOLATGE
Input Current Regulation (DPM) Accuracy - %
Input Current Regulation (DPM) Accuracy - %
INPUT CURRENT REGULATION
(DPM) ACCURACY
vs
ACP-ACN VOLATGE
14
16
18
20
VI − Input Voltage − V
Figure 26.
22
24
0
20
40
60
80
100
110 120 125
o
TJ − Junction Temperature − C
Figure 27.
bq24721
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SLUS683 – NOVEMBER 2005
TYPICAL CHARACTERISTICS (continued)
500-kHz SWITCHING FREQUENCY
vs
INPUT VOLTAGE
o
TJ = 125 C
497.5
497
496.5
o
TJ = 25 C
496
o
TJ = 0 C
495
494.5
73.65
VI = 20 V
498
497.5
497
496.5
496
495.5
495
494.5
18
16
14
20
22
24
VI = 20 V
73.6
73.55
73.5
73.45
73.4
73.35
0
VI − Input Voltage − V
20
40
60
80
100
110 120 125
0
o
20
40
60
80
100
110 120 125
o
TJ − Junction Temperature − C
TJ − Junction Temperature − C
Figure 28.
Figure 29.
Figure 30.
THERMISTER LTF THRESHOLD
vs
JUNCTION TEMPERATURE
THERMISTER TCO THRESHOLD
vs
JUNCTION TEMPERATURE
THERMISTER TSDET THRESHOLD
vs
JUNCTION TEMPERATURE
VREF% - Thermister TCO Threshold - %
34.395
VI = 20 V
34.39
34.385
34.38
34.375
34.37
34.365
34.36
34.355
34.35
VREF% - Thermister TSDET Threshold - %
29.3
34.4
VREF% - Thermister HTF Threshold - %
VREF% - Thermister LTF Threshold - %
498
495.5
THERMISTER LTF THRESHOLD
vs
JUNCTION TEMPERATURE
498.5
o
TJ = 85 C
500-kHz Switching Frequency - kHz
500-kHz Switching Frequency - kHz
498.5
500-kHz SWITCHING FREQUENCY
vs
JUNCTION TEMPERATURE
VI = 20 V
29.28
29.26
29.24
29.22
29.2
0
20
40
60
80
100
110 120 125
o
0
20
40
60
80
100
110 120 125
o
84.8
VI = 20 V
84.79
84.78
84.77
84.76
84.75
84.74
84.73
84.72
84.71
84.7
0
20
40
60
80
100
110 120 125
o
TJ − Junction Temperature − C
TJ − Junction Temperature − C
TJ − Junction Temperature − C
Figure 31.
Figure 32.
Figure 33.
13
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SLUS683 – NOVEMBER 2005
TYPICAL CHARACTERISTICS (continued)
EFFICIENCY
vs
BATTERY CHARGE CURRENT
BATTERY REMOVAL (CONSTANT CURRENT MODE)
100
V(BAT) = 16.8 V
Efficiency - %
95
90
V(BAT) = 12.6 V
85
VI = 19.5 V
80
TA = 20oC
75
0
1
2
3
5
4
6
7
8
Battery Charge Current − A
Figure 34.
Figure 35.
REGULATION CURRENT
vs
SYSTEM CURRENT
TRANSIENT SYSTEM LOAD
4500
IDPM
4000
Regulation Current − mA
3500
V(BAT) = 12 V
VCC = 20 V
3000
R(sns) = 10 mW
2500
ICHG
2000
DPM Active
1500
1000
ILOOP Active
500
0
0
500
1 k 1.5 k 2 k 2.5 k 3 k 3.5 k
4k
4.5 k
System Current − mA
Figure 36.
14
Figure 37.
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SLUS683 – NOVEMBER 2005
TYPICAL CHARACTERISTICS (continued)
SYSTEM SELECTOR GATE DRIVES AFTER ACDET
SYSTEM SELECTOR ADAPTER INSERTION
Figure 38.
Figure 39.
SYSTEM SELECTOR ADAPTER REMOVAL
REGN VREF5 POWER UP
Figure 40.
Figure 41.
15
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SLUS683 – NOVEMBER 2005
TYPICAL CHARACTERISTICS (continued)
16
SOFTSTART CHARGE CURRENT
NON-SYNCHRONOUS TO SYNCHRONOUS TRANSITION
Figure 42.
Figure 43.
SYNCHRONOUS TO NON-SYNCHRONOUS TRANSITION
NEAR 100% DUTY CYCLE BTST RECHARGE PULSE
Figure 44.
Figure 45.
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SLUS683 – NOVEMBER 2005
TYPICAL CHARACTERISTICS (continued)
BATTERY SHORT RESPONSE
CHARGE OVERCURRENT
Figure 46.
Figure 47.
ACOC ACDRV TURN OFF (32-µs DEGLITCH)
ACOC ACDRV TURN ON (500-ms DEGLITCH)
Figure 48.
Figure 49.
17
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SLUS683 – NOVEMBER 2005
TYPICAL CHARACTERISTICS (continued)
18
SWITCHING CONTINUOUS CURRENT MODE (CCM)
SWITCHING DISCONTINUOUS CURRENT MODE
vs
(DCM)
Figure 50.
Figure 51.
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SLUS683 – NOVEMBER 2005
SIMPLIFIED BLOCK DIAGRAM
AGND
VCC
REFERENCE SYSTEM
−
−
−
−
−
5v ldo when ACPRES
Power−on reset
UVLO
Voltage references
Internal timebase
ACDRV
BYPASS
VREF5
BYPASS SW
DRIVER
20X
Select Adaptor current
or Charge current
Always on
AC SW AND BAT SW DRIVERS
− break−before−make LOGIC
Always on
IOUT
BATDRV
Always on
SRP
Always on
BYPON
SYNCHRONOUS SWITCHING
PWM CONVERTER
ACON
SRN
ACOC
LOGIC
ACP
CHGOC
− Power up/down sequencing
− Charge enable logic
− Charge enable sequencing
BDEP, ACCHG, THDET,
− System power selector logic
TCOLD, THOT ,VSHI, TERMDET, − System selector bbm logic
ADPSRC, VCCGTBAT, TCMP
− Deglitch times
CLK, POR
SYSTEM STATUS
COMPARATORS
ACGOOD
ACDET
SYS
TS
−
−
−
−
−
−
−
POWERON
CHARGERON
Always on
Battery depleted (1)
AC detection
(1)
*Thermistor inserted (1)
*Thermistor cold (2)
*Thermistor hot (2)
System voltage / pack voltage (2)
VCC above pack voltage (2)
− current loop
− dpm loop
− voltage loop
− sync/nonsync comparator
− charge overcurrent
− comparator
− charge current reference
− dpm current reference
− break−before−make logic
− duty−cycle limited, 0% to near
100% (99.5%)
− NMOS/NMOS drivers
− Internal soft start
− PWM oscillator 300 kHz/500 kHz
ACN
EAO
EAI
FBO
SYNP
SYNN
ISYNSET
BAT
BTST
HIDRV
(1) always on
(2) enabled when AC is detected
Enabled only when AC is
detected and CHGEN is low
TTL INPUT
BUFFER
ALARM
PH
REGN
LODRV
PVCC
VREG DAC
DECODER
SCL
SMBUS INTERFACE
MEMORY
SBS [b1−b14] to
bq24721 [7bit +1bit]
VREG DAC
1BIT Select Cells
7BIT (6.25mV/bit)
SR IREG DAC
7BIT (1.28mV/bit)
SDA
Always on
Always on
AC IREG DAC
7BIT (1.28mV/bit)
CHGEN
PGND
Figure 52. bq24721 SBS-Like SMBus Controlled Simplified Block Diagram
19
bq24721
www.ti.com
SLUS683 – NOVEMBER 2005
TYPICAL APPLICATION bq24721
Q1
SI4435
Q2
SI4435
R1
0.010
ADAPTER +
C1
10uF
bq24721
PACK+
C6
1uF
ADAPTER D1
BAT54C
C7
0.1uF
R3
464k
1%
C8
0.1uF
ACDRV
VCC
SYS
ACN
BATDRV
ACP
C9
0.1uF
C2
10uF
PVCC
C3
4x10uF
BYPASS
ACDET
R4
33.2k
1%
PACK
THERMISTOR
SENSE
VREF5
C10
1uF
R5
5.6k
1%
VREF5
AGND
Q3
FDS6670A
HIDRV
PH
C12, 0.1uF
D2
BAT54
TS
L1
10uH
C4
2x10uF
Q4
FDS6670A
C17
0.1uF
OPTIONAL
R7
10k
C20
51pF
EAI
FBO
R8
10k
SCL
SDA
SMBus
IRQ
ISYNSET
A/D
C11
0.1uF
IOUT
R10
20k
R9
7.5k
C21
2000pF
ALARM
C14
0.1uF
C5
2x10uF
C18
0.1uF
OPTIONAL
C16
0.1uF
C19
0.1uF
EAO
VREF5
R6
10k
PACK+
PACK-
C15
0.1uF
SRP
SRN
BAT
CHGEN
R2
0.010
C13, 1uF
LODRV
PGND
SYNP
SYNN
ACGOOD
Q5
SI4435
BTST
REGN
R13
118k
1%
EMBEDDED
CONTROLLER
HOST
SYSTEM
C22
130pF
R11
200k
R12
33k
POWERPAD
SHORT POWERPAD TO
PGND AND AGND
Figure 53. bq24721 SBS-Like SMBus Host Control With System Power Selector
(bq24721 With TS Themistor Sense Input Pin)
BOM Key Components (For Figure 53, bq24721 Typical Application Circuit)
Reference Designator
Description (1)
Qty
Q3
1
N-channel MOSFET, 30V, 12.5A, SO-8, FDS6680A
Q4
1
N-channel MOSFET, 30V, 13A, SO-8, FDS6670A
Q1, Q2, Q5
3
P-channel MOSFET, -30V,-6A, SO-8, Vishay-Siliconix, Si4435
D1
1
Diode, Dual Schottky, 30V, 200mA, SOT23, Fairchild, BAT54C
D2
1
Diode, Single Schottky, 30V, 200mA, SOT23, Fairchild, BAT54
L1
1
Inductor, 10µH, 7A, 31mΩ, Vishay-Dale, IHLP5050FD-01
R1, R2
2
Sense Resistor, 10 mΩ, 1%, 1W, 2010, Vishay-Dale, WSL2010R0100F
C1, C2, C3, C4, C5
10
Capacitor, Ceramic, 10µF, 35V, 20%, X5R, 1206, Panasonic,
ECJ-3YB1E106M
C6, C10, C13
3
Capacitor, Ceramic, 1µF, 25V, 10%, X7R, 2012, TDK, C2012X7R1E105K
C7, C8, C9, C12, C14, C15, C16,
C19, (C17 and C18 optional)
10
Capacitor, Ceramic, 0.1µF, 50V, 10%, X7R, 0805, Kemet,
C0805C104K5RACTU
C20
1
Capacitor, Ceramic, 51pF, 50V, 5%, NPO, 0603
(1)
20
The manufacturer's part number are used for test purposes only.
bq24721
www.ti.com
SLUS683 – NOVEMBER 2005
BOM Key Components (For Figure 53, bq24721 Typical Application Circuit) (continued)
Reference Designator
Description (1)
Qty
C21
1
Capacitor, Ceramic, 2000pF, 50V, 5%, X7R, 0805
C22
1
Capacitor, Ceramic, 130pF, 50V, 5%, NPO, 0603
R3
1
Resistor, Chip, 464kΩ, 1/16W, 1%, 0402
R4
1
Resistor, Chip, 33.2kΩ, 1/16W, 1%, 0402
R12
1
Resistor, Chip, 33kΩ, 1/16W, 5%, 0402
R9
1
Resistor, Chip, 7.54kΩ, 1/16W, 1%, 0402
R10
1
Resistor, Chip, 20kΩ, 1/16W, 1%, 0402
R11
1
Resistor, Chip, 200kΩ, 1/16W, 1%, 0402
R6, R7, R8
3
Resistor, Chip, 10kΩ, 1/16W, 5%, 0402
R5
1
Resistor, Chip, 10kΩ, 1/16W, 5%, 0402
R5
1
Resistor, Chip, 5.6kΩ, 1/16W, 1%, 0402
R13
1
Resistor, Chip, 118kΩ, 1/16W, 1%, 0402
Typical bq24721 Narrow VDC (NVDC) Application (2 sense resistors)
Q1
SI4435
SYSTEM
ADAPTER +
C1
10 uF
bq24721
PACK+
C6
1uF
ADAPTER D1
BAT54C
C7
0.1uF
R3
464k
1%
C8
0.1uF
VCC
SYS
ACN
BATDRV
ACP
C9
0.1uF
C2
10uF
ACDRV
PVCC
C3
4x10uF
BYPASS
ACDET
PACK
THERMISTOR
SENSE
R4
33.2k
1%
VREF5
VREF5
C10
1uF
R5
10k
AGND
Q3
FDS6670A
HIDRV
PH
C12, 0.1uF
REGN
D2
BAT54
EMBEDDED
CONTROLLER
HOST
C13, 1uF
C4
2x10uF
Q4
FDS6670A
LODRV
PGND
SYNP
SYNN
CHGEN
VREF5
R6
10k
R7
10k
C20
51pF
R8
10k
SCL
SDA
SMBus
IRQ
ISYNSET
A/D
C11
0.1uF
IOUT
R10
20k
R9
7.5k
C21
2000pF
ALARM
C5
2x10uF
C14
0.1uF
C18
0.1uF
C15
0.1uF
C16
0.1uF
C19
0.1uF
EAO
EAI
FBO
PACK-
C17
0.1uF
SRP
SRN
BAT
ACGOOD
PACK+
BTST
TS
R1
118k
1%
R13
0.010
R2
0.010
L1
10uH
C22
130pF
R11
200k
R12
33k
PowerPAD
Short PowerPAD to
PGND and AGND
Figure 54. bq24721 SBS-Like SMBus Host Control, NVDC (no system power selector) With 2 Sense
Resistors. ACP and ACN Regulating Converter Current Instead of Input Current
21
bq24721
www.ti.com
SLUS683 – NOVEMBER 2005
Typical bq24721 Narrow VDC (NVDC) Application (3 sense resistors)
Q1
SI4435
Q2
SI4435
R1
0.010
ADAPTER +
C1
10uF
bq24721
PACK+
C6
1uF
ADAPTER D1
BAT54C
C7
0.1uF
R3
464k
1%
C8
0.1uF
VCC
SYS
ACN
BATDRV
ACP
C9
0.1uF
C2
10uF
ACDRV
PVCC
C3
4x10uF
BYPASS
ACDET
R4
33.2k
1%
PACK
THERMISTOR
SENSE
VREF5
C10
1uF
R5
5.6k
1%
VREF5
AGND
Q3
FDS6670A
HIDRV
PH
C12, 0.1uF
D2
BAT54
TS
L1
10uH
C4
2x10uF
Q4
FDS6670A
C17
0.1uF
OPTIONAL
R7
10k
C20
51pF
EAI
FBO
R8
10k
SCL
SDA
SMBus
IRQ
ISYNSET
A/D
C11
0.1uF
IOUT
R10
20k
R9
7.5k
C21
2000pF
ALARM
C14
0.1uF
C5
2x10uF
C18
0.1uF
OPTIONAL
C16
0.1uF
C19
0.1uF
EAO
VREF5
R6
10k
PACK+
PACK-
C15
0.1uF
SRP
SRN
BAT
CHGEN
R2
0.010
C13, 1uF
LODRV
PGND
SYNP
SYNN
ACGOOD
Q5
SI4435
BTST
REGN
R13
118k
1%
EMBEDDED
CONTROLLER
HOST
SYSTEM
C22
130pF
R11
200k
R12
33k
POWERPAD
SHORT POWERPAD TO
PGND AND AGND
Figure 55. bq24721 SBS-Like SMBus Host Control, NVDC (no system power selector)
With 3 Sense Resistors
22
bq24721
www.ti.com
SLUS683 – NOVEMBER 2005
5-V LDO
VCC
VREF5
ENA
ACDET
ADAPTER
DETECTED
+
-
BAT
CHGEN
BATDEP
-
SMBUS
BATDEPSET
SYS
+
SYS-BAT
-
250 mV
PVCC-6V
SRP-BAT
+
+
_
1.2 V
ACOC
BAT + 250 mV
PVCC-6V
LDO
PVCC
PVCC
BYPASS
EAO
PVCC-6V
SYSTEM
POWER
SELECTOR
LOGIC
EAI
ACDRV
PVCC-6V
SYS-6V
FBO
ACOC_SET
+
SYS
SYS 6-V
LDO
SYS
ACOC
BATDRV
ACP
+
V(ACP-ACN)
IIN
DAC
ACN
OVP
+
1V
BAT + 250 mV
4 mA
BTST
CHGEN
-
+
+
_
BAT
SYS-6V
SMBUS
CHGEN
COMP
ERROR
AMPLIFIER
+
ACP-BAT
-
250 mV
ICH_ER
-
-
+
VBAT
DAC
-
110% x BAT_DAC
LEVEL
SHIFTER
BAT_ER
+
20 mA
HIDRV
OVP
OCP
PH
SRP
SYNCH
+
V(SRP-SRN)
ICH_ER
-
IBAT
DAC
SRN
ACP-BAT
DC-DC
CONVERTER
PWM LOGIC
+
VCC
20 mA
SUSPEND
REGN
6-V LDO
TSDET
500 kHz
2 x IBAT_DAC
SYNP
+
-
V(SYNP-N)
BTST
OCP
+
+
-
4.5 V
+
SYNN
LODRV
SW FREQ
SELECT
+
_
PH
SYNCH
IC TJ
VREF5
o
145 C
1V
+
_
300 kHz
PGND
-
ISYNSET x 500
ISYNSET
-
REFRESH
CBTST
+
+
+
+
-
-
SRP
+
SRN
-
20x
20x
IOUT
V(IBAT)
TSDET
CHARGE STATUS
REGISTER
LTF
HTF
AGND
ACN
V(IADAPT)
SELECT
+
TS
(bq24721 only)
+
TSHUT
-
-
ACP
SUSPEND
VBAT
DAC
CHARGE MODE
REGISTER
ALARM
SDA
SMBus LOGIC
IBAT
DAC
TCO
SCL
IIN (DPM)
DAC
Figure 56. bq24721 Functional Block Diagram
23
bq24721
www.ti.com
SLUS683 – NOVEMBER 2005
ADAPTER
POWER
external
SYSTEM & CHARGE POWER
SELECTOR
Vin
Bat
Chrg
SYSTEM
Chrg
Dischrg
Dischrg
bq24721
BATTERY
CHARGER
CONTROLLER
IC
&
CONVERTER
PSID
I/O
SMBus
BATTERY
Primary
BATTERY
Secondary
SMBus
SMBus
I/O
HOST - Embedded Controller (EC)
Figure 57. Host Controller
BLOCK DESCRIPTION
Detail Block Diagram
The bq24721 charge controller can be used to charge Li-ion, NiMH, or NiCd batteries. The high efficiency
synchronous buck controller uses n-channel power MOSFETs for both the high-side control device and the
low-side synchronous device. The controller offers high regulation accuracy of the charge current, battery
voltage, and input current limits. The low offset of the current loops allow using sense resistors with low-value,
such as 10 mΩ.
An embedded controller host programs the battery voltage, charge current, and input current regulation limit
thresholds through an SMBus interface using SBS-like DAC registers. The embedded host can control the
operation of the charger through a Charge Control (0x12) register, and monitor the status of the charger through
a Charger Status (0x13) register.
The voltage loop regulates the battery voltage to the programmed value, and prevents the voltage from
exceeding that value when the battery is connected. The charge current loop regulates the battery charge current
to the programmed value, and prevents the charge current from exceeding that value. Through the use of
dynamic power management (DPM), the input current loop regulates the battery charge current to the
programmed value, and prevents the input current from exceeding that value. The three regulation loops operate
independently, yet only require a single loop compensation network.
The system power selector function selects the appropriate power source for the system load. If the adapter is
detected, then the adapter is connected to the system load. When the adapter is removed, the battery is selected
to power the system load. A battery learn cycle can be performed when the adapter is present by setting the
CONTROL(0x12) register into Learn Mode via SMBus by the embedded host. This disconnects the adapter from
the system; and instead, connect the battery to the system. This is typically done for Ni-based batteries.
SMBus Interface
The bq24721 uses all the SMBus communications protocol, except for packet error correction (PEC). The
charger IC address is (0x12), although it is not 100% SBS compliant. In most applications the extra functionality
provided by the differing SBS-Like interface enhances the control of the charger application, while simplifying the
interface block, using only the pertinent functions. Five 16-bit registers are used to interface between the
embedded host and the charge control IC. The Charging Voltage (0x15) register is used to set the battery
regulation voltage. The Charging Current (0x14) register is used to set the battery charge regulation current. The
Input Current (0x3F) register is used to set the input regulation current. The Charger Mode (0x12) control register
is used to set the charger operating modes. Finally, the Charger Status (0x13) register is used to monitor the
operating status of the charger.
24
ADDRESS
REGISTER
DESCRIPTION
0x15
Charging voltage
Used to set the battery regulation voltage.
0x14
Charging current
Used to set the battery charge regulation current.
0x3F
Input current
Used to set the input regulation current.
bq24721
www.ti.com
SLUS683 – NOVEMBER 2005
BLOCK DESCRIPTION (continued)
ADDRESS
REGISTER
DESCRIPTION
0x12
Charger mode
Used to set the charger operating modes.
0x13
Charger status
Used to monitor the operating status of the charger.
The SMBus communications requires only two pins besides the analog ground pin—through the SDA (data) and
SCL (clock) pins. The open-drain SCL and SDA pins require pull-up resistors on the board pulling up to the host
digital output voltage rail. The pins can be pulled up to any rail between 3 V to 5 V.
An alarm is sent to the host through the ALARM open drain pin. This can be used to trigger an interrupt request
(IRQ). A low on the ALARM pin indicates there was a change on the Charger Status (0x13) register. The ALARM
pin stays low until the host reads the Charger Status (0x13) register, then the ALARM pin clears and returns to
the HI state. The open-drain ALARM pin requires a pull-up resistor that pulls up to the host digital input voltage
rail. The pin can be pulled up to any rail between 3 V to 5 V. The charge controller continues to operate whether
the host chooses to read or not to read the Charger Status (0x13) register. There is no communications
watchdog timer, so there is no need to continuously poll the Charger Status (0x13) register or have to
continuously reprogram any of the other registers.
Setting Charge Voltage (VBAT DAC register)
The charge voltage can be programmed by setting Charging Voltage(0x15) register. The SBS specification asks
for 16 bits to set the regulation voltage with a 1-mV LSB—giving a maximum possible voltage of 65.535 V. The
bq24721 uses bits 1 through 14 only, and maps them into the closest value of an internal 7-bit DAC on a per cell
basis using a 6.25-mV per cell LSB for three ranges: 9-V pre-charge voltage; 3 cells Li+ battery pack range; or 4
cells Li+ battery pack range. The 3 cell portion has an LSB of 18.75 mV and a range from 12 V-14.4 V; while the
4 cell portion has an LSB of 25 mV and a range from 16 V-19.2 V. Intermediate programmed voltages between
the internal 7-bit DAC values are truncated to the lower value to avoid an overvoltage on the battery.
Programmed voltages above 19.2 V are automatically set to the maximum 19.2-V limit. The charger is disabled
for programmed voltages below 12 V (except for 9 V), and for programmed voltages between 14.4 V – 16 V. This
triggers a voltage-out-of-range condition and the VOR bit of the Charger Status (0x13) register is set, and an
alarm (ALARM pin pulled low) is sent to the host. The default power-up-reset voltage value is 0 V, charger
disabled.
Setting Charge Current (IBAT DAC register)
The charge current can be programmed using the Charging Current (0x14) register. The SBS specification asks
for 16 bits to set the charge current with a 1-mA LSB—giving a maximum possible current of 65.535 A using a
10-mΩ sense resistor. The bq24721 uses bits 7 – 14 only to limit the range within a practical operating range.
The current range is 0 mA to 16.384 A with an LSB of 128 mA using a 10-mΩ sense resistor. The charger is
disabled when the programmed input current is 0 A. The default power-up-reset current value is 0 A, charger
disabled. Other sense resistors could be used to set the charge current—the user would just need to transform
the DAC current table values to the new current values by dividing the current by 10 mΩ, then multiplying by the
new sense resistor value used.
Setting Input (DPM) Current (IDPM DAC register)
The input current can be similarly programmed using the Input Current (0x3F) register. The SBS specification
asks for 16 bits to set the input current with a 1-mA LSB—giving a maximum possible current of 65.535 A using
a 10-mΩ sense resistor. The bq24721 uses bits 7 – 14 only to limit the range within a practical operating range.
The current range is 0 mA to 16.384 A with an LSB of 128 mA using a 10-mΩ sense resistor. The charger is
disabled when the programmed input current is 0 A. The default power-up-reset current value is 0 A, charger
disabled. Other sense resistors could be used to set the input current—the user would just need to transform the
DAC current table values to the new current values by dividing the current by 10 mΩ, then multiplying by the new
sense resistor value used.
25
bq24721
www.ti.com
SLUS683 – NOVEMBER 2005
Power Up
When the adapter is not detected, the REGN output voltage is 4.6 V and the VREF5 LDO regulator is off, to
lower the power consumption from the battery. The VREF5 LDO is pulled-down to AGND when the adapter is
not detected. The REGN LDO regulator begins to regulate at 4.6 V when the input VCC voltage is greater than 6
V. The REGN output voltage is then 6 V when the adapter is detected, and the VCC is greater than 7 V. If
adapter is detected, but VCC is less than 7 V, then the REGN is in dropout, and REGN output voltage depends
on the VCC voltage and REGN load current. The VREF5 LDO is allowed to turn-on and regulate to 5 V, 5 ms
after REGN is 6 V and the adapter is detected. There is a 500-ms delay from the time the adapter is detected,
until the ACFET from the system power selector is allowed to turn-on, and until the charger is allowed to turn-on.
The battery continues to be connected to the system during this 500-ms delay.
Adapter Detect
The adapter detect threshold is programmed by an external voltage divider resistor from the adapter to the
ACDET pin. The internal ACDET comparator has a 1.2-V rising-edge threshold and a 15-mV falling-edge
hysteresis. The adapter detect value should typically be programmed to a value greater than the maximum
battery voltage, and lower than the minimum allowed adapter voltage. The ACDETECT divider should be placed
before the BYPASS FET in order to sense the true adapter input voltage whether the BYPASS is on or off.
The VREF5 LDO output can also be used to indicate when the adapter is detected, for both the bq24721 and the
bq24721, since the VREF5 LDO only comes up when the adapter is detected.
System Power Selector
The bq24721 can automatically switch between adapter power or battery power to the system load. The battery
is connected to the system when there is no adapter detected. The adapter is connected to the system when the
adapter is detected. An automatic break-before-make logic prevents shoot-through currents when the selector
switches.
When no adapter is detected the ACDRV pin is pulled to the PVCC pin to keep the external ACFET p-channel
power MOSFET off, disconnecting the adapter from system. The break-before-make logic waits until the ACFET
is off and the System to battery voltage comparator indicates the system voltage is within 250 mV of the Battery
(SYS voltage falling-edge, with a 50-mV hysteresis SYS voltage rising-edge). This prevents shoot-through
currents or large discharge currents from going into the battery. The BATDRV pin is then set to the SYS pin
voltage minus 6 V by an internal regulator in order to turn on the external BATFET p-channel power MOSFET,
connecting the battery pack to the system.
When adapter is detected there is a 500-ms delay; then, the BATDRV is set to the SYS pin voltage to turn off the
external BATFET p-channel power MOSFET, in order to disconnect the battery. The break-before-make logic
waits until the BATFET is off to prevent shoot-through currents. The ACDRV pin is then set to the PVCC pin
voltage minus 6 V by an internal regulator in order to turn on the external ACFET p-channel power MOSFET,
connecting the adapter to the system.
The host can override the adapter to system connection when adapter is present, by setting the charger into
Learn Mode. The host can then induce a learn cycle in which the battery is allowed to discharge. A learn cycle is
used to recalibrate the fuel gauge for Ni-based batteries, or for clearing the memory effect of a Ni-cd battery.
After discharging the battery, Learn Mode can be disabled allowing the adapter to be reconnected to the system,
then resuming a normal charge cycle.
Whenever the battery is connected to the system (whether in learn cycle with adapter present, or no adapter
present), there is a Low Battery comparator that monitors the battery voltage, and alerts the host and charge
controller that the battery has been depleted. The BAT_DEP threshold can be programmed through the Charger
Mode control (0x12) register through bits b9-b11. The three bits can program the threshold between 2.2-V per
cell to 2.9-V per cell, in 100-mV increments. The number of cells is determined by the programmed battery
regulation voltage (0x15) register. If the battery voltage falls below the BAT_DEP threshold, then the battery is
disconnected from the system and the adapter is connected to the system. The Battery Voltage Low bit (b11) is
set in the Charger Status (0x13) register, and the ALARM pin is pulled low to alert the host. There is a 1 second
deglitch time to prevent false triggering.
The Charger Status (0x13) register bits b6 and b7 also always indicate whether the battery is connected to the
system (b6), or the adapter is connected to the system (b7). An alarm is triggered whenever these states
change.
26
bq24721
www.ti.com
SLUS683 – NOVEMBER 2005
Asymmetrical gate drives (100 Ω turn-off; 10 kΩ turn-on) for the ACDRV and BATDRV drivers provide fast
turn-off and slow turn-on of the ACFET and BATFET to help the break-before-make logic and to allow a soft-start
at turn-on of either FET. The soft-start time can be further increased by putting a capacitor from gate to source of
the p-channel power MOSFETs.
Input Overcurrent Protection (ACOC)
For solutions using the selector functions, an input overcurrent protection function (ACOC) is provided which
disconnects the ACFET by turning off the ACDRV pin, whenever the sensed input current exceeds the
programmed ACOC threshold. The ACOC threshold is programmed through the SMBus Charge Mode (0x12)
control register, bits b6, b7, b8. The ACOC function is automatically disabled upon power-on-reset. The host
needs to enable it by setting the ACOC bit (b6) HI. The ACOC threshold is set by the SET_ACOC bits (b7, b8),
to thresholds of 130%, 150%, 170%, or 190% of the input current (DPM) regulation limit threshold from the Input
Current (0x3F) register.
The ACFET turns off when the sensed current exceeds the threshold after a 200-µs deglitch time. The ACFET
automatically turns on after 2 ms, to limit the on-time duty cycle, and limit the power dissipation on the ACFET.
Care must be taken to ensure system load power does not exceed the power-up allowable power when the
ACOC function is used.
The function is not intended for system short-circuits, as usually the adapter self protects. Instead, the function is
intended for long-term overcurrent protection of the selector power devices, and to limit start-up peak current.
Bypass FET
The BYPASS pin is used to control an input FET that is off to prevent reverse discharge from the battery to the
adapter, and is on during input current draw to the system or battery, to minimize the power dissipation, as
compared to using a Schottky diode. If no adapter is detected, the BYPASS FET is off, by setting the BYPASS
pin to the PVCC pin. When the adapter is detected there is a 500-ms delay, then an ACP-to-BAT voltage
comparator is used to control the BYPASS pin. The BYPASS driver is set to the PVCC pin voltage when the
adapter voltage (ACP pin) is not more than 250 mV (ACP voltage falling-edge) above the battery voltage (BAT
pin), in order to turn off the external BYPASS p-channel power MOSFET. There is a 50 mV (ACP voltage
rising-edge) hysteresis, to protect from noise and prevent chatter. When adapter is detected and the ACP pin
voltage is greater than 300 mV above the BAT pin voltage, the BYPASS pin voltage is set to PVCC pin voltage
minus 6 V, in order to turn on the external BYPASS p-channel power MOSFET.
The ACP-to-BAT comparator also prevents the battery voltage from holding-up the ACDET sensed value and
falsely detecting ACDET when the adapter is removed, this prevents the system power selector from getting
stuck in an adapter always detected state. When ACP gets near to BAT, the external BYPASS p-channel power
MOSFET is turned off. This isolates the ACDET network from the battery, and allows the adapter input node to
discharge to PGND.
The BYPASS driver has a symmetrical gate drive of 1 kΩ turn-on and turn-off and does not need to be slowed
down.
Enabling Charge
Charge can only be enabled 500 ms after adapter is detected. To initiate charge the CHGEN pin must be low,
and the Charger Mode (0x12) register END CHARGE bit (b0) must be set LO. The power-on-reset default for the
END CHARGE bit is HI, disabling charge.
The Charger Status (0x13) register NOT READY TO CHARGE bit (b0) indicates whether the charger is ready to
charge. A HI indicates the charger is not ready to charge, while a LO indicates the charger is ready to charge.
The NOT READY TO CHARGE bit (b0) must be LO in order for the charger to be enabled. The conditions that
make the charger not ready to charge are: adapter not detected, 500-ms delay after adapter detected not over,
REGN voltage not up, or VREF5 voltage not up.
The Charger Status (0x13) register CHARGER NOT ON bit (b1) indicates whether the charger is not on (HI), or
the charger is on (LO). For charger to be on, the CHGEN pin must be low, the Charger Mode (0x13) register
END CHARGE bit (b0) must be LO, the, IC junction temperature must be below the TSHUT threshold,
overcurrent detected, or Thermistor Sense (TS) indicates battery pack is out of programmed permissible charge
temperature range (bq24721 only).
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Converter Operation
The synchronous buck PWM converter uses a fixed frequency voltage mode with feed-forward control scheme. A
type III compensation network allows using ceramic output capacitors. The compensation input stage is
connected between the feedback output (FBO) pin and the error amplifier input (EAI) pin. The feedback
compensation stage is connected between the error amplifier input (EAI) pin and error amplifier output (EAO) pin.
An internal saw-tooth ramp is compared to the EAO pin error control signal to vary the duty-cycle of the
converter. The ramp height is one-tenth of the input adapter voltage making it always directly proportional to the
input adapter voltage. This cancels out any loop gain variation due to a change in input voltage, and simplifies
the loop compensation. The ramp is offset by 300 mV in order to allow zero percent duty-cycle, when the EAO
signal is below the ramp. The EAO signal is also allowed to exceed the saw-tooth ramp signal in order to get a
100% duty-cycle PWM request. Internal gate drive logic allows achieving 99.98% duty-cycle while ensuring the
N-channel upper device always has enough voltage to stay fully on. If the BTST pin to PH pin voltage falls below
4.5 V for more than 3 cycles, then the high-set n-channel power MOSFET is turned off and the low-side
n-channel power MOSFET is turned on to pull the PH node down and recharge the BTST capacitor. Then the
high-side driver returns to 100% duty-cycle operation until the voltage is detected to fall low again due to leakage
current discharging the BTST capacitor below the 4.5 V, and the reset pulse is reissued.
The fixed frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage,
battery voltage, charge current, and temperature, simplifying output filter design and keeping it out of the audible
noise region. The switching frequency can be changed from 300 kHz to 500 kHz by the Charger Mode (0x12)
register PWM FS bit (b5) – a HI is 500 kHz, a LO is 300 kHz. The switching frequency is 300 kHs by default after
power-on-reset. Typical chargers use 300 kHz, but 500 kHz allows a smaller inductance value
The charge current sense resistor should be placed with at least half or more of the total output capacitance
placed before the sense resistor contacting both sense resistor and the output inductor; and the other half or
remaining capacitance placed after the sense resistor. The output capacitance should be divided and placed
onto both sides of the charge current sense resistor. A ratio of 50:50 percent gives the best performance; but the
node in which the output inductor and sense resistor connect should have a minimum of 50% of the total
capacitance. This capacitance provides sufficient filtering to remove the switching noise and give better sense
accuracy. The type III compensation is already providing phase boost near the cross-over frequency, giving
sufficient phase margin.
ISYNSET
The ISYNSET pin is used to program the charge current threshold at which the charger changes from
non-synchronous operation into synchronous operation. This is important to prevent negative inductor current.
Negative inductor current may cause a boost effect in which the input voltage increases as power is transferred
from the battery to the input capacitors—this can lead to an overvoltage on the PVCC node and potentially cause
some damage to the system.
This programmable value allows setting the current threshold for any inductor current ripple, and avoiding
negative inductor current. The SYNP and SYNN pins are used to sense across the charge current sense resistor.
To program the threshold, a resistor is connected from the ISYNSET pin to AGND. The minimum synchronous
threshold should be set from the inductor current ripple to the full ripple current, where the inductor current ripple
is given by.
I(RIPPLE_MAX)
2
£ I(SYN) £ I(RIPPLE_MAX)
(1)
where
?
?
R(RIPPLE_MAX) =
?
?
?
? V(BAT_MIN) x ?
? V(IN_MAX) ?
L(MIN)
1
¦S
?
?
? V(IN_MAX) - V(BAT_MIN) x
(2)
V(IN_MAX) is the maximum adapter voltage, V(BAT_MIN) is the minimum battery voltage, fS is the switching
frequency, and LMIN is the minimum output inductor value.
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The ISYNSET pin is internally regulated to 1 V. When the R(SYNSET) resistor is connected to AGND, it sets an
ISYNSET current equal to 1 V/R(SYNSET). The ISYNSET current internally flows through a 500 Ω creating a
voltage at which the voltage across R(SENSE) is compared. The ISYN charge current threshold is the voltage
divided by the R(SENSE) sense resistor value. The R(SYNSET) resistor value is calculated by:
R(SYNSET) =
1 V x 500 W
I(SYN) x R(SENSE)
(3)
where ISYN is the charge current threshold at which the converter changes to synchronous operation.
Synchronous versus Nonsynchronous Operation
The charger operates in non-synchronous mode when the sensed charge current is below the ISYNSET
programmed value. When above the ISYNSET programmed value, the charger operates in synchronous mode.
During synchronous mode, the low-side n-channel power MOSFET is on, when the high-side n-channel power
MOSFET is off. The internal gate drive logic ensures there is break-before-make switching to prevent
shoot-through currents. During the dead-time where both FETs are off, the back-diode of the low-side power
MOSFET conducts the inductor current. Having the low-side FET turn-on keeps the power dissipation low, and
allows safely charging at high currents. During Synchronous mode the inductor current is always flowing and
operates in Continuous Conduction Mode (CCM) creating a fixed two-pole system. During non-synchronous
operation: after the high-side n-channel power MOSFET turns off, and after the break-before-make dead-time,
the low-side n-channel power MOSFET turns on for around 80 ns, then the low-side power MOSFET turns off
and stays off until the beginning of the next cycle, where the high-side power MOSFET is turned on again. The
80 ns low-side MOSFET on-time is done to ensure the bootstrap capacitor is always recharged and able to keep
the high-side power MOSFET on during the next cycle. This is important for battery chargers, where unlike
regular dc-dc converters, there is a battery load that maintains a voltage and can both source and sink current.
The 80 ns low-side pulse pulls the PH node (connection between high and low-side MOSFET) down, allowing
the bootstrap capacitor to recharge up to the REGN LDO value. After the 80 ns, the low-side MOSFET is kept off
to prevent negative inductor current from occurring. The inductor current is blocked by the off low-side MOSFET,
and the inductor current becomes discontinuous. This mode is called Discontinuous Conduction Mode (DCM).
During the DCM mode the loop response automatically changes and has a single pole system at which the pole
is proportional to the load current, because the converter does not sink current, and only the load provides a
current sink. This means at very low currents the loop response is slower, as there is less sinking current
available to discharge the output voltage.
At very low currents during non-synchronous operation, there may be a small amount of negative inductor
current during the 80 ns recharge pulse. The charge should be low enough to be absorbed by the input
capacitance.
Whenever the converter goes into zero percent duty-cycle, the high-side MOSFET does not turn-on, and the
low-side MOSFET does not turn-on (no 80 ns recharge pulse), so there is no discharge from the battery.
Battery Regulation Loop
The BAT pin is used to sense the battery voltage and should be connected as close to the battery as possible, or
directly on the output capacitor. A 0.1-µF ceramic capacitor from BAT to AGND is recommended added as close
the BAT pin as possible to decouple high frequency noise.
Charge Current Regulation Loop
The SRP and SRN pins are used to sense across the sense resistor. The charge current DAC is set for a 10-mΩ
sense resistor; however, resistors of other values can also be used. The larger the sense resistance, the larger
the sensed voltage, and the higher the regulation accuracy, but at the expense of higher conduction losses.
Input Current Regulation Loop (DPM)
The ACP and ACN pins are used to sense across the sense resistor. The input current DAC is set for a 10-mΩ
sense resistor; however, resistors of other values can also be used. The larger the sense resistance, the larger
the sensed voltage, and the higher the regulation accuracy, but at the expense of higher conduction losses.
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Automatic Internal Soft-Start Charger Current
The charger automatically soft-starts the charger regulation current every time the charger is enabled, to ensure
there is no overshoot or stress on the output capacitors or the power converter. The soft-start consists of
stepping-up the charge regulation current into eight evenly divided steps up to the programmed charge current of
register (0x14). Each steps last around 1 ms, for a typical rise time of 8 ms. No external components are needed
for this function.
High Accuracy IOUT Input and Charge Current Sense Amplifiers (CSA)
Industry standard, high accuracy current sense amplifiers (CSA) can be used to monitor the input current or the
charge current by the host or some discrete logic through the analog voltage output of the IOUT pin. The current
sense amplifier from the input current and the current sense amplifier of the charge current (voltage across
SRP-SRN pins) amplifies the input sensed voltage by 20x, through the Iout pin. The IOUT output is selectable
between the input current or the charge current, through a multiplexor that is controlled by the Charge Mode
(0x12) control register, IOUT Select bit (b3). The default setting is LO selecting the input current CSA.
Programming a HI selects the charger current CSA.
The IOUT output is a voltage source 20 times the input differential voltage. If the user wants to lower the voltage,
they could use a sense resistor from IOUT to AGND, and still achieve accuracy overtemperature as the resistors
can be matched their thermal coefficients.
A 0.1-µF capacitor connected on the output is recommended for decoupling high-frequency noise. An additional
RC filter is optional if additional filtering is desired. Note that adding filtering also adds additional response delay.
Charger Overcurrent Protection
The charger has a secondary overcurrent protection function that monitors the charge current, and prevents it
from exceeding 200% of the programmed charge current. The high-side gate drive turns off and automatically
resume when the current falls below the overcurrent threshold
Current Regulation Down to Zero Battery Voltage
The bq24721 charger regulates charge current and input current down to zero volts on the battery BAT voltage.
If there is a drop below 2 V, then the converter immediately turns off both high-side and low-side FETs to stop
current flow, then resumes regulating the current. This ensures there is no overcurrent surge that could cause
damage to the battery, charger, or system.
Battery Overvoltage Protection
As an extra level of protection, the bq24721 has an overvoltage protection function, in which the converter is
turned off when the BAT voltage is detected to be above 110% of the programmed battery regulation threshold.
During this overvoltage condition, a 4-mA current sink from the BAT pin to AGND pin turns on to reduce the
response time to bring down the battery voltage during otherwise no-load conditions such as battery removal or
battery disconnect for pulse-charge schemes. This reduces the battery node voltage overshoot and reduce the
battery voltage regulation response time, with low or no load conditions.
The converter stays off and the 4-mA current sink remains on until the battery voltage falls below 102% of the
programmed battery regulation threshold. Afterward, the converter reenables and continues regulating the BAT
voltage as normal.
Thermal Shutdown Protection
The QFN package has low thermal impedance which provides good thermal conduction from the silicon to the
ambient, to keep junctions temperatures low. As added level of protection, the charger converter turns off and
self-protects whenever the junction temperature exceeds the TSHUT threshold of 145°C. The charger stays off
until the junction temperature falls below 130°C.
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BATTERY CHARGE CURRENT
The battery charge current, IO(CHARGE), is established by setting the external sense resistor, R(SRSNS), and the
SMBus Charge current DAC (0 × 14). In order to set the current, first R(SRSNS) should be chosen based on the
regulation threshold V(IREG), across this resistor. The listed SBS current corresponds to a 10 mΩ sense resistor.
R(SRSNS) = V(IREG) / IO(CHARGE)
CURRENT REGULATION REFERENCE RAMP UP/DOWN REFERENCE
The bq24721 current regulation loop reference steps-up whenever charge is enabled, and when returning from
fault/suspend mode into charge where the current regulator is turned on. The loop should take control within a
few hundred micro-seconds with very little overshoot due to the LC output filter and the high compensation loop
bandwidth with 300 kHz or 500 kHz operating frequency; therefore, the reference could ramp up from precharge
to fast-charge within 50 µs to 500 ms. Going into fault/suspend mode, short circuit (V(BAT) < V(UVT)), Sleepmode
(V(ACP) < V(BAT)), or UVLO (VCC < 3.7 V) initiates an immediate shut-off of the high-side PWM FET by setting its
gate to V(PH). The output inductor and battery load determines the ramp-down rate as it freewheels through the
Schottky diode.
BATTERY VOLTAGE REGULATION
The voltage regulation feedback is through the BAT pin. This input is tied directly to the positive side of the
battery pack. The bq24721 monitors the battery-pack voltage between the BAT and VSS pins. The regulation
voltage is programmed through the SBS-like SMBus interface.
The voltage regulation DAC register input is decoded into an internal 7-bit DAC that programs the voltage on a
per-cell basis, then is multiplied by the number of cells. There are a total of 128 voltage steps with a 6.25 mV
step, giving a per cell range of [4 V – (4.8 V–6.25 mV)]. There are 128 steps in the 3-cell voltage range of
[12 V – (14.4 V–18.75 mV)]. There are 128 steps in the 4-cell voltage range of [16 V – (19.2 V–25 mV)].
Valid voltage values are 9 V, 12 V–14.381 V, and 16 V–19.175 V. The internal voltage DAC allows programming
to 9 V which could be used for waking-up or closing the battery pack. A 9 V programmed voltage is interpreted
as a 2-cell voltage by the BATDEP and BATSHORT thresholds. Step size for 3-cell battery programming voltage
is 18.75 mV. The Charger interprets a 3-cell battery for any voltage between 12 V–14.4 V. Step size for 4-cell
battery programming voltage is 25 mV. The charger interprets a 4-cell battery for any voltage programmed
between 16 V–19.2 V.
Invalid DAC voltages are indicated by the VOR (voltage out of range) bit of the status register. Voltages below
12 V (except for 9 V) are out of range and keep the converter disabled. Voltages between 14.4 V–16 V (including
14.4 V, but not including 16 V) are out of range and keep the converter disabled. Voltages above 19.2 V
(including 19.2 V) are out of range and allow the converter to charge, but the voltage is always set to the
maximum allowable voltage of 19.175 V = (19.2 V–25 mV).
BATTERY SHORT-CIRCUIT OR LOW CONDITION
The number of cells determines the value for the BATDEP threshold and for the BATSHORT threshold, as these
values are programmed on a per-cell basis. The programmed regulation voltage determines the number of cells.
The battery depleted (BATDEP) threshold is programmed by the control register bits b9-b11. The three bit dac
sets the voltage between 2.2 V to 2.9 V per cell at 100 mV increments. The BATSHORT threshold is 1.7 V/Cell
falling entering a shorted condition, and 1.9 V/Cell rising leaving shorted condition, and entering normal
condition. BATSHORT has a 1 second deglitch on both edge directions to protect from transient conditions, and
to allow closing deeply discharge battery packs.
The PWM duty-cycle immediately resets to zero percent when the battery voltage is sensed to drop below 2 V,
then the regulation loop allows the duty-cycle to settle in the current regulation value, C. After a 1 second
deglitch, the converter regulates battery current to C/8 when the battery voltage falls below 1.7 V/cell. The
converter regulates back at C after a 1 second deglitch from the time the battery voltage rises above 1.9 V/cell.
Charge Termination for Li-Ion or Li-Polymer
The primary termination method for Li-Ion and Li-Polymer is minimum current. Secondary temperature
termination methods is also provided for additional safety. The host controls the charge initiation and the
termination. A battery pack gas gauge assists the hosts on setting the voltages and determining when to
terminate based on the battery pack state of charge.
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ISYNC FET Charger Undercurrent
Comparator
SYNP
+
500W
−
ISYNC_LOWD
1V
−
+
t_bo
SYNN
40ns
+
−
ISYNSET
R_ISYNSET
CHARGE_ENZ
NOTE: Patent Pending
Figure 58. SRUC Block – Charger Under Current (ISYNC Block – Cycle-by-cycle, prevents negative
inductor current)
TEMPERATURE QUALIFICATION (TS pin)
The bq24721 continuously monitors battery temperature by measuring the voltage between the TS pin and
AGND. A negative temperature coefficient thermistor (NTC) and an external voltage divider typically develop this
voltage. The bq24721 compares this voltage against its internal thresholds to determine if charging is allowed. To
initiate a charge cycle, the battery temperature must be within the V(LTF) to V(HTF) thresholds. If battery
temperature is outside of this range, the bq24721 suspends charge and waits until the battery temperature is
within the V(LTF) to V(HTF) range. During the charge cycle (both precharge and fast charge) the battery
temperature must be within the V(LTF) to V(TCO) thresholds. If battery temperature is outside of this range, the
bq24721 suspends charge and waits until the battery temperature is within the V(LTF) to V(HTF) range. The
bq24721 suspends charge by turning off the PWM charge FETs. Figure 59 summarizes this operation.
Vcc
Vcc
Charge Suspend
V
LTF
Charge Suspend
V LTF
Temperature
Temperature
range to initiate
V
range during a
charge
charge cycle
HTF
V TCO
Charge Suspend
Charge Suspend
Vss
Vss
Figure 59.
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SBS-Like SMBus
SBS-Like interface is not 100% SBS compliant, as control and status registers were changed to simplify and
enhance the charger control device. Address 0x12 is used, but the charger should not to be used on systems
requiring 100% SBS compliance. Effort was taken to use the same commands when possible. Comparison
included on SBS-like vs SBS Spec.
• SBS-Like SMBus
– SBS 1.1 protocol, slave operation only
– No CRC
– Address: 12 (Note SBS-Like is not 100% SBS compliant and has simplified enhancements and
• Smart charger commands implemented
– ChargingCurrent (), with modifications on data byte contents, SBS-Like SMBus
– ChargingVoltage (), with modifications on data byte contents, SBS-Like SMBus
– ChargerStatus (), with modifications on status bits
• Smart charger commands not implemented
– ChargerSpecInfo (),
– AlarmWarning ()
SBS-Like SMBus: Commands Implemented: Charge Current DAC Register
Charging Current, (0x14), Write/Read (1)
Table 1.
BIT
(1)
SBS SPEC
bq24721 SBS-Like
0 (LSB)
1 mA
NA
1
2 mA
NA
2
4 mA
NA
3
8 mA
NA
4
16 mA
NA
5
32 mA
NA
6
64 mA
NA
7
128 mA
128 mA (1.28 mV)
8
256 mA
256 mA (2.56 mV)
9
512 mA
512 mA (5.12 mV)
10
1024 mA
1024 mA (10.24 mV)
11
2048 mA
2048 mA (20.48 mV)
12
4096 mA
4096 mA (40.96 mV)
13
8192 mA
8192 mA (81.92 mV)
14
16384 mA
NA
15 (MSB)
32768 mA
NA
NOTES
Charge current limit setting
16384 mA max
(162.56 mV max)
Note: Shunt drop voltage shown at LO/HI bit state;
DAC current value is based on using 10 mΩ sense resistor.
Max charge current with 10 mΩ sense resistor is 16.256 A.
Bit 13 allows using larger sense resistors for increasing accuracy in low charge current applications.
• Valid charge currents are 0 A–16.256 A using a 10 mΩ sense resistor. Minimum step is 128 mA.
• Programmed charge currents above max 16.256 A → Charger is enabled and the current regulation value is
set to the maximum 16.256 A.
• Programmed charge current = 0 A → Charger is disabled.
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SBS-Like SMBus: Commands Implemented: Input Current DAC Register
Input Current, (0x3F), Write/Read (1)
BIT
(1)
SBS SPEC
bq24721 SBS-Like
0 (LSB)
1 mA
NA
1
2 mA
NA
2
4 mA
NA
3
8 mA
NA
4
16 mA
NA
5
32 mA
NA
6
64 mA
NA
7
128 mA
128 mA (1.28 mV)
8
256 mA
256 mA (2.56 mV)
9
512 mA
512 mA (5.12 mV)
10
1024 mA
1024 mA (10.24 mV)
11
2048 mA
2048 mA (20.48 mV)
12
4096 mA
4096 mA (40.96 mV)
13
8192 mA
8192 mA (81.92 mV)
14
16384 mA
NA
15 (MSB)
32768 mA
NA
NOTES
Input DPM current limit setting
16384 mA max
(162.56 mV max)
Note: Shunt drop voltage shown at LO/HI bit state;
DAC current value is based on using 10 mΩ sense resistor.
Max input current with 10 mΩ sense resistor is 16.256 A.
Bit 13 allows using larger sense resistors for increasing accuracy in low input current applications.
• Valid input currents are 0 A–16.256 A using a 10 mΩ sense resistor. Minimum step is 128 mA.
• Programmed input currents above max 16.256 A → Charger is enabled and the current regulation value is
set to the maximum 16.256 A.
• Programmed input current = 0 A → Charger is disabled.
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SBS-Like SMBus: SBS Translator Voltage DAC Commands Implemented
Charging Voltage, (0x15), Write/Read
BIT
(1)
bq24721 SBS-Like
CHARGE VOLTAGE LOOK-UP TABLE
SBS SPEC
0 (LSB)
1 mV
NA
1
2 mV
0 / 2 mV
2
4 mV
0 / 4 mV
3
8 mV
0 / 8 mV
4
16 mV
0 / 16 mV
5
32 mV
0 / 32 mV
6
64 mV
0 / 64 mV
7
128 mV
0 / 128 mV
8
256 mV
0 / 256 mV
9
512 mV
0 / 512 mV
10
1024 mV
0 / 1024 mV
11
2048 mV
0 / 2048 mV
12
4096 mV
0 / 4096 mV
13
8192 mV
0 / 8192 mV
14
16384 mV
0 / 16384 mV
15 (MSB)
32768 mV
NA
NOTES
Not used
See Notes below for valid voltage range
and minimum step size (resolution (1))
Not used
Note: Battery voltage range: 4 V–4.8 V per cell
3 Cell range: 12 V to (12 V–14.4 V); step size = 18.75 mV
4 Cell range: 16 V to (16 V –19.2 V) ; step size = 25 mV
a. Valid voltages are 9 V, 12 V–14.4 V, and 16 V–19.2 V. Intermediate programmed voltages between Internal DAC values are
truncated to the lower value to avoid overvoltage on battery.
b. Programmed Voltages above max 19.2 V → Charger is enabled and the voltage regulation value is set to the maximum 19.2 V.
c. Programmed voltages below 12 V (except 9 V), and between 14.4 V–16 V → Charger is disabled, VOR bit is triggered, and an alarm
is sent to the host.
d. Programmed 9 V (9000 mV = 2328 Hex) → Charger regulates to 9 V output for battery wakeup.
SBS-Like SMBus: IC Internal Voltage DAC for Reference Only
Internal decoder translates the SBS voltage register value into the internal closest value. Values are truncated to the lower
valid setting.
Charging Voltage, IC Internal Only
bq24721 SBS-Like
CHARGE VOLTAGE INTERNAL
DECODER DAC
BIT
0 (LSB)
0/18.75 mV
0/25 mV
1
0 / 37.5 mV
0 / 50 mV
2
0 / 75 mV
0 / 100 mV
3
0 / 150 mV
0 / 200 mV
4
0 / 300 mV
0 / 400 mV
5
0 / 600 mV
0 / 800 mV
0 / 1.2 V
0 / 1.6 V
LO – 12 V
HI – 16 V
6 (MSB)
(1)
NOTES
Offset that can be added to dc level
See the following notes for valid voltage range and
minimum step size (resolution) (1)
3 Cell or 4 Cell dc level select
Note: Battery voltage range: 4 V–4.8 V per cell
3 Cell range: 12 V to (12 V–14.4 V); step size = 18.75 mV
4 Cell range: 16 V to (16 V –19.2 V) ; step size = 25 mV
a. Valid voltages are 9 V, 12 V–14.4 V, and 16 V–19.2 V. Intermediate programmed voltages between Internal DAC values are
truncated to the lower value to avoid over-voltage on battery.
b. Programmed Voltages above max 19.2 V → Charger is enabled and the voltage regulation value is set to the maximum 19.2 V.
c. Programmed voltages below 12 V (except 9 V), and between 14.4 V–16 V → Charger is disabled, VOR bit is triggered, and an alarm
is sent to the host.
d. Programmed 9 V (9000 mV = 2328 Hex) → Charger regulates to 9 V output for battery wake-up.
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PROGRAMMED VOLTAGE VALUE DIFFERENCE BETWEEN Li-Ion AND NiMH BATTERY PACK
CHARGING
•
Li-Ion based battery packs require both current regulation and voltage regulation loops – where
constant-current and constant voltage is needed to fully charge the battery pack.
NiMH batteries require only a constant current for charging. Thereby, the voltage regulation loop is not
needed. To accomplish this, set the regulation voltage at a value greater than the maximum battery pack
voltage. This will not allow the voltage regulation loop to become active. The maximum value of 19.2 V could
be set for most NiMH battery packs.
•
SBS-Like SMBus: Commands Implemented: Control Register
Charger Mode, (0x12), Write-Only [Default POR and Reset Value in BOLD TYPE]
BIT
SBS SPEC
bq24721 SBS-Like
END CHARGE
0 (LSB)
INHIBIT CHARGE
(1)
1: Disable Charger
0: Enable Charger
This affects STATUS register 0x13, bit 1.
1
ENABLE POLLING
RESERVED: Not Used. Bit always resets to zero.
2
POR_RESET
RESET: (Return to POR values) Charger disabled, DPM active, PWM at 300 kHz, Vout = 0,
CHARGE CURR = 0, IDPM = 0
1: Reset
0: No Reset
IOUT Select: Current Sense Amplifier Output select
1: Charge current is the 20x amplifier output at IOUT pin
3
RESET_TO_ZERO
0: Adapter current is the 20x amplifier output at IOUT pin
The IOUT pin is multiplexed to either the charge current or the input current sense amplifiers. The
Input current (ac) is the default upon power up.
LEARN CYCLE
4
RESERVED
1: Connect Battery to system (learn cycle) even when adapter connected
0: Connect AC adapter to system (no learn) when adapter connected
This bit affects STATUS register 0x13, bits 6 and 7.
5
RESERVED
6
RESERVED
7
RESERVED
8
RESERVED
PWM FS: Switching Frequency Select
1: PWM at 500 kHz
0: PWM at 300 kHz
ACOC – AC (adapter) Over-Current
1: ACOC protection enabled
0: ACOC protection disabled
SET_ACOC <1:0>
00: ACOC=DPM × 1.3
01: ACOC=DPM × 1.5
10: ACOC=DPM × 1.7
11: ACOC=DPM × 1.9
Bit 6 of this Control register 0×12 needs to be high for these bits to take effect.
ACOC threshold is a percentage of the DPM (input current) regulation threshold programmed by
the DPM register 0×3F.
9
RESERVED
SET_BAT_DEPL <2:0> Battery depleted threshold
10
RESERVED
Value set per cell
11
RESERVED
000: [2.2V], 001:[2.3V], 010:[2.4V], 011:[2.5V]
100:[2.6V], 101:[2.7V], 110:[2.8V], 111:[2.9V]
These bits affect STATUS register 0×13, bits 11, 6 and 7.
12
RESERVED
RESERVED: Not Used. Bit always resets to zero.
13–15(MSB)
RESERVED
RESERVED: Not Used. Bit always resets to zero.
(1)
36
END_CHARGE bit must be LO AND the CHRGEN pin must be LO to enable the charger. If the END_CHARGE bit is HI or the
CHRGEN pin is HI, then the charger is disabled.
bq24721
www.ti.com
SLUS683 – NOVEMBER 2005
SBS-Like SMBus: Commands Implemented: Status Register
Charger Status, (0x13), Read-Only
All Status register bits are automatically updated by the IC whenever the system state changes, some bits have
an 8 ms deglitch to prevent false alerts. Whenever a status bit changes, the ALARM open drain output pulls
down to alert the host of a change in the status register. The ALARM stays low until the host performs a
STATUS register (0×13) read, afterward, the ALARM clears and goes high impedance. An external pull-up
resistor is needed at the ALARM pin.
BIT
SBS SPEC
bq24721 SBS-Like
NOT READY TO CHARGE
0 (LSB)
CHARGE_INHIBITED
1=
Charger is not ready to charge (IC comes up in this state)
0=
Charger is ready to charge
(Note: Same logic polarity as SBS spec, but added Feature, Not part of SBS spec.) This bit indicates
all the conditions are met to allow the charger to start charging. Precursers are Power-on-Reset is
completed; adapter is detected, and REGN driver rail is ready.
CHARGER NOT ON
1
MASTER MODE
1=
Charger is Not On (IC comes up in this state)
0=
Charger is On
(Note: same logic polarity and different bit, from SBS spec bit 0) Hi on this bit indicates that the charger
is on . If Low, the charger is off. This bit allows the user to determine if there is a fault that disable the
charger. Bits in this STATUS register 0x13 can be used in conjunction with this bit to determine the
source of charger turning off.
CHARGE VOLTAGE LOOP NOT ACTIVE
2
VOLTAGE_NOTREG
1=
Charge Voltage Loop Not Active (IC comes up in this state, and in this state when charger is not
enabled)
0=
Charge Voltage Loop Active
(Note: same logic polarity as SBS spec bit 2). A Lo on this bit indicates the battery voltage regulation
loop is active and is influencing the charger regulation. There is an overlap as one loop transitions to
another loop to allow for a soft transition knee. This overlap can alert that another loop is getting close
to its limit and is influencing the output.
CHARGE CURRENT LOOP NOT ACTIVE
3
CURRENT_NOTREG
1=
Charge Current Loop Not Active (IC comes up in this state, and in this state when charger is not
enabled)
0=
Charge Current Loop Active
(Note: same logic polarity from SBS spec bit 3) A LO on this bit indicates the charge current regulation
loop is active and is influencing the charger regulation. There is an overlap as one loop transitions to
another loop to allow for a soft transition knee. This overlap can alert that another loop is getting close
to its limit and is influencing the output.
DPM INPUT CURRENT LOOP NOT ACTIVE
4
LEVEL2
1=
DPM Input Current Loop Not Active (IC comes up in this state, and in this state when charger is
not enabled)
0=
DPM Input Current Loop Active
(Note: Added Feature, Not part of SBS spec. Same logic polarity from bits 2&3 of SBS spec) Dynamic
Power Management (DPM) dynamically reduces the charge current when the system current increases
enough to cause the total input current to reach the input power limit. This gives power delivery
precedence to the system current over the charge current. A Lo on this bit indicates the input current
regulation loop is active and is influencing the charger regulation. There is an overlap as one loop
transitions to another loop to allow for a soft transition knee. This overlap can alert that another loop is
getting close to its limit and is influencing the output.
CHARGE OVERCURRENT FAULT
(Note: Added Feature, Not part of SBS spec.)
5
LEVEL3
HI indicates the charge current was higher than the charge overcurrent limit (SROC) which is 1.7 times
the charge regulation setting. This is to protect from shorts or large load transients at the output. If
SROC is detected, the high-side FET is immediately turned-off, and an alarm is sent out. The charger
retres again, allowing the high-side FET to turn-on the next cycle. This fault current limit continues until
the fault is removed.
37
bq24721
www.ti.com
SLUS683 – NOVEMBER 2005
BIT
SBS SPEC
bq24721 SBS-Like
BATTERY CONNECTED TO SYSTEM (by selector BATDRV)
(Note: Added Feature, Not part of SBS spec.)
HI indicates the battery is connected to the system output. LO indicates battery is not connected.
During this HI state, the BATDRV pin is pulled 6V below the SYS pin voltage to turn on the external
PMOS BAT FET. When in LO state, the BATDRV pin voltage is pulled-up to the SYS pin voltage.
6
CURRENT_OR
Battery is connected to system when ac is not present, or when ac is present and LEARN CYCLE is
set at the control register.
FEATURE: If in learn cycle and the battery falls below the BATDEP threshold (programmed by the
control register), then the IC automatically switches from battery power to ac adapter power.
FEATURE: Also, in all cases if system (SYS) voltage is more than 150 mV above the battery (BAT)
voltage then the BAT FET is kept off until SYS discharges to within 150 mV to prevent the system
capacitors from discharging into the battery. This feature protects the battery from extended high surge
currents.
ADAPTER CONNECTED TO SYSTEM (by selector ACDRV)
(Note: Added Feature, Not part of SBS spec.)
HI indicates the adapter is connected to the system output. LO indicates adapter is not connected.
During this HI state, the ACDRV pin is pulled 6 V below the PVCC pin voltage to turn on the external
PMOS AC FET. When in LO state, the ACDRV pin voltage is pulled-up to the PVCC pin voltage.
7
VOLTAGE_OR
AC is connected to system when adapter is present (ACDET voltage is above threshold) and LEARN
CYCLE is not set at the control register.
FEATURE: If in learn cycle and the battery falls below the BATDEP threshold (programmed by the
control register), then the IC automatically switches from battery power to ac adapter power.
FEATURE: If there is an adapter overcurrent (ACOC) is detected, then the AC FET is turned off
immediately to prevent a short-circuit condition or a surge current. This feature protects the battery
from extended high surge currents.
IC THERMAL SHUTDOWN FAULT
(Note: Added Feature, Not part of SBS spec.)
8
THERMISTOR_OR
A HI indicates the IC temperature is too high, and had to turn-off the charger. LO indicates temperature
is safe.
FAULT DETECTION AND PROTECTION FEATURE: The IC monitors its own junction temperature. If
the IC junction temperature exceeds 145°C, then the IC automatically shuts down the charger and an
ALARM is triggered. SMBus communications continues to function. The charger remains off until the IC
junction temperature falls below 130°C. The charger automatically restarts once the temperature falls
below the hysteresis at 130°C.
[THERMISTOR COLD
9
THERMISTOR_COLD
HI indicates the thermistor temperature is too cold to allow charging. The TS pin voltage threshold
would be higher than the TS cold voltage threshold when this bit is HI. A LO means the TS voltage is
below the TS cold voltage threshold. Programmed by a voltage divider pulled up to the VREF5 pin.
Note: VREF5 only comes up when ac is detected to conserve battery power, since no charging would
be required.
THERMISTOR HOT (start) or (operating)
10
THERMISTOR_HOT
HI indicates the thermistor temperature is too hot to allow charging. The TS pin voltage threshold would
be lower than the TS hot voltage threshold when this bit is HI. A LO means the TS voltage is above the
TS hot voltage threshold. There is a different voltage threshold before starting charge than during
charging (operating). Programmed by a voltage divider pulled up to the VREF5 pin.
Note: VREF5 only comes up when AC is detected to conserve battery power, since no charging would
be required.
38
bq24721
www.ti.com
SLUS683 – NOVEMBER 2005
BIT
SBS SPEC
bq24721 SBS-Like
BATTERY VOLTAGE LOW (battery depleted)
(Note: Added Feature, Not part of SBS spec.)
11
THERMISTOR_UR
This bit goes HI when the sensed BAT voltage is below the Battery Depleted threshold programmed by
the CONTROL register 0x12, bits 9,10, and 11. The programmed voltage is per cell, therefore multiply
by the number of cells set by the programmed battery voltage regulation DAC, register 0x15. [3 cell for
voltages between 12V-14.4V; and 4cell for voltages between 16V-19.2V].
FEATURE: the BATDRV is turned off when the battery voltage falls below the BATDEP threshold, and
the AC DRV is turned on if adapter is connected and had previously been in LEARN Cycle (bit 4 of
CONTROL register, 0x12).
VOR, VOLTAGE OUT OF RANGE (Note: moved function from bit7 of SBS spec) A HI indicates the
voltage DAC value from register 0x15 is out of the valid DAC voltage range. The IC either disables the
charge if below, or stays at the maximum possible programmed voltage (19.2 V) according to the
following: Valid voltage DAC range and effect.
• Valid voltages are 9 V, 12 –14.4 V, and 16 V–19.2 V. Intermediate programmed voltages
between Internal DAC values are truncated to the lower value to avoid over-voltage on battery.
12
ALARM_INHIBITED
• Programmed Voltages above max 19.2 V → Charger is enabled and the voltage regulation value
is set to the maximum 19.2 V.
• Programmed voltages below 12 V (except 9 V), and between 14.4–16V → Charger is disabled,
VOR bit is triggered, and an alarm sent to host.
• Programmed 9V (9000 mV = 2328 Hex) → Charger will regulate to 9 V output for battery
wake-up.
ADAPTER VOLTAGE BELOW BATTERY PACK VOLTAGE
13
POWER_FAIL
(Note: Added Feature, Not part of SBS spec.) A HI on this bit indicates the battery voltage is above the
adapter voltage (BAT pin > ACP pin).
FEATURE: If the input falls below 150mV above the Battery voltage, the BYPASS FET immediately
turns off to prevent reverse discharge of the battery into the adapter. There is an 8 ms deglitch and 100
mV to hysteresis before allowing the BYPASS FET to turn-on.
BATTERY DETECTED ( through thermistor pin)
FEATURE: HI indicates a battery is detected through the TS pin. The TS pin voltage threshold is lower
than the TS battery detect threshold when this bit is HI. A LO means the TS voltage is above the TS
battery detect threshold. A resistor to ground inside the battery can be used to distinguish a good
battery from a bad battery as well. Programmed by a voltage divider pulled up to the VREF5 pin.
14
BATTERY PRESENT
Note: VREF5 only comes up when ac is detected to conserve battery power, since no charging would
be required.
(Note: Added Feature. This could be used for detecting proper battery connected by selecting the
proper valid resistance. This is need to be ORed for dual battery pack chargers to make feature
optimal. This feature also is used as a safety feature to stop charge immediately when the battery pack
is not detected – this allows a faster response time by autonomously terminating charge when no
battery is detected, as opposed to waiting until the host detects the battery is removed and then
alerting the charger.
AC ADAPTOR DETECTED
15
(MSB)
AC_PRESENT
This bit is HI when the adapter is detected (ACDET pin voltage is above the acdetect threshold of
2.4V). The voltage can be programmed by an external resistor divider from adapter input to ground.
Charge is not allowed until the ACDET threshold is exceeded. VREF5 LDO output only turns on when
the ACDET threshold is exceeded (adapter detected).
REGN POR and SMBus communication will begin soon after ACDET threshold is above 1.2 V and the
VCC is above 6.5 V.
39
bq24721
www.ti.com
SLUS683 – NOVEMBER 2005
ELECTRICAL CHARACTERISTICS
7 Vdc ≤ V(VCC) ≤ 24 Vdc, –20°C < TJ < 125°C, ref = AGND (unless otherwise noted).
PARAMETER
MIN
TYP
MAX
UNIT
SMBus TIMING CHARACTERISTICS
tR
SCLK/SDATA rise time
1
µs
tF
SCLK/SDATA fall time
tW(H)
SCLK pulse width high
4
tW(L)
SCLK Pulse Width Low
4.7
µs
tSU(STA)
Setup time for START condition
4.7
µs
tH(STA)
START condition hold time after which first clock pulse is generated
4
µs
tSU(DAT)
Data setup time
250
ns
tH(DAT)
Data hold time
300
ns
tSU(STOP)
Setup time for STOP condition
4
µs
t(BUF)
Bus free time between START and STOP condition
4.7
FS(CL)
Clock Frequency
10
100
kHz
6
10
ms
300
ns
50
µs
µs
ALARM LOGIC TIMING CHARACTERISTICS
Time delay from status register bit toggling to ALERT: LO → HI transition
tALM
HOST COMMUNICATION FAILURE
ttimeout
SMBus bus release timeout
tBOOT
Deglitch for watchdog reset signal
tWDI
Watchdog timeout period
25
35
10
140
170
ms
msec
200
s
0.4
V
OUTPUT BUFFER CHARACTERISTICS
V(SDAL)
Output LO voltage at SDA, I(SDA) = 3 mA
Tw(H)
Tsu(STA)
Tf
Tr
Tw(L)
SCL
Tf
Tr
SDA
START
Th(STA)
Th(DAT)
Th(DAT)
STOP
Tsu(DAT)
1
SCL
2
3
7
8
SDA
9
ACK
START
Tsu(STOP)
SCL
1
2
3
7
SDA
8
9
ACK
T(BUF)
STOP
Figure 60.
40
bq24721
www.ti.com
SLUS683 – NOVEMBER 2005
FUNCTIONAL DESCRIPTION
SMBus OVERVIEW
An SMBus communication port provides a simple way for an SMBus compatible host to access system status
information and reset fault modes. Functioning as a SLAVE port enables SMBus compatible hosts to WRITE to
internal registers or READ from internal registers. The bq24721 SMBus port is a 2-wire bidirectional interface
using SCL (clock) and SDA (data) pins; the SDA pin is open drain and requires an external pull-up. The SMBus
is designed to operate at SCL frequencies up to 100 kHz. The standard 8 bit command is supported, the CMD
part of the sequence is the 8 bit register address which is READ from or WRITE to. The bq24721 does not
support packet error correction, PEC, as a mechanism to confirm proper communication between it and the host.
SMBus ADDRESS
The SMBus specification contains several global addresses, to which the slaves on the bus are required to
respond. The bq24721 responds to the SBS charger addresses of 0×12 for writes and 0×13 for reads. The
bq24721 only responds (ACK) to the above listed addresses, and does (NACK) not respond to any other
address.
BIT
BYTE
MSB
6
5
4
3
2
1
LSB
bq24721 SMBus WRITE ADDRESS SBS Charger
0
0
0
1
0
0
1
0
bq24721 SMBus READ ADDRESS SBS Charger
0
0
0
1
0
0
1
1
COMMAND
0
0
0
1
C3
C2
C1
C0
D7
D6
D5
D4
D3
D2
D1
D0
I/O DATA BUS
INTERNAL REGISTER MAP
The status data and control data is referenced by the following Commands.
COMMAND
R/W
0x12
R/W
REGISTER DESCRIPTION
Charger Mode
0x13
R
Charger Status
0x14
R/W
Charging Current
0x15
R/W
Charging Voltage
0x3F
R/W
Input Current
SMBus BUS RELEASE
The bq24721 SMBus engine does not create START or STOP states on the SMBus bus during normal
operation. However, if a 2 second (typical) SDA low timeout is exceeded the bq24721 releases the bus, thus
creating a stop condition.
SMBus COMMUNICATION PROTOCOL
The following conventions is used when describing the communication protocol.
CONDITION
START sent from host
STOP sent from host
bq24721 SMBus slave address sent from host, bus direction set from host to bq24721 (WRITE)
bq24721 register address sent from bq24721, bus direction is from bq24721 to host (READ)
Non-valid SMBus slave address sent from host
Valid bq24721 register address sent from host
Nonvalid bq24721 register address sent from host
CODE
S
P
hA0
hA1
hA_N
HCMD
HCMD_N
I/O data byte (8 bits) sent from host to bq24721
hDATA
I/O data byte (8 bits) sent from bq24721 to host
bqDATA
Acknowledge (ACK) from host
hA
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bq24721
www.ti.com
SLUS683 – NOVEMBER 2005
CONDITION
CODE
Not acknowledge (NACK) from host
hN
Acknowledge (ACK) from bq24721
bqA
Not acknowledge (NACK) from bq24721
bqN
Repeated Start
R
STOP
CONDITION
(P)
START
CONDITION
(S)
BIT 7
MSB
BIT 6
BIT 0
LSB
STOP
ACKNOWLEDGE
CONDITION
(hA or bqA)
(P)
STOP
CONDITION
(P)
START
CONDITION
(S)
BIT 7
MSB
BIT 6
BIT 0
LSB
NOT
STOP
ACKNOWLEDGE CONDITION
(hN or bqN)
(P)
SCL
SDA
SCL
SDA
Figure 61.
SMBus READ/WRITE SEQUENCES
The bq24721 supports the standard SMBus Word Write, as well as the SMBus Word READ. The basic SMBus
word read protocol has the following steps:
1. Host sends a start and bq24721 SMBus slave write address
2. bq24721 ACK’s that this is a valid SMBus address and that the bus is configured for write
3. Host sends bq24721 command
4. bq24721 ACK’s that this is a valid command and stores the command for a possible read
5. Host sends a repeated start and bq24721 SMBus slave read address, reconfiguring the bus for read
6. bq24721 ACK’s that this is a valid address and that bus is reconfigured
7. Bus is in read mode, bq24721 starts sending 2 bytes of data chosen by the command.
The SMBus write protocol is similar to the read, without the need for a repeated start and bus being set in write
mode. If the address sent by host is not a valid address , the command is NACKed. The host can complete a
READ or a WRITE sequence with either a STOP or a START. In a WRITE it is not necessary to end each word
WRITE command with a STOP, a START has the same effect (repeated start).
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bq24721
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SLUS683 – NOVEMBER 2005
VALID WRITE SEQUENCES
The bq24721 will always ACK its own address. If the CMD points to an allowable READ or WRITE data bq24721
writes the command into its command register and send an ACK. If the CMD points to an nonallowed command
bq24721 does NOT write the command into its command register and sends a NACK.
S
hA0
S
hA0
bqA
bqA
hCMD_N
bqN
WORD WRITE
The data is written to a control register at the end of the ACK after the second byte in the sequence. If an word
write sequence is intrupted by a STOP or START, no data is written to the device. The host can cancel a WRITE
by sending a STOP or START before the trailing edge of ACK clock pulse.
S
hA0
bqA
hCMD
bqA
hDATA
bqA
hDATA
bqA
P
VALID READ SEQUENCES
The bq24721 will only ACK its READ address if it occurs following a repeated start where the high SCL clock
time is less then the tW(H), MAX of 50 µs. Upon receiving hA1, bq24721 outputs 2 bytes of data as indicated by
the preceding command. The command sequence is terminated by a STOP. The START and the STOP both act
as priority interrupts. If the host has been interrupted and is not sure where it left off, it sends a STOP and resets
the bq24721 state machine to the Idle state. Once in idle state, bq24721 ignores all activity on the SCL and SDA
lines until it receives a START. If a read sequence is terminated early by a START or STOP, the entire sequence
must be restarted by the host for valid data.
S
hA0
bqA
hCMD
bqA
R
hA1
bqA
bqDATA
hA
bqDATA
hN
P
SMBus WORD READ
A valid Command is required to write to the bq24721, and a valid Command is required to specify the data to be
read. Once a read command is received the register data for the specified command is output to the host.
NONVALID SEQUENCES
START and non-hA0 or non-hA1 Address
A START followed by an address which is not bqA0 or bqA1 is NACKED.
Attempt to Specify Nonallowed Command
If the CMD points to a nonallowed command (reserved registers) , bq24721 sends a NACK back to the host.
Note that bq24721 NACKS whether a stop is sent or not.
S
hA0
S
bqA
hA_N
hCMD_N
bqN
bqN
43
bq24721
www.ti.com
SLUS683 – NOVEMBER 2005
STATUS AND CONTROL REGISTERS
The SMBUS-Like communication engine allows easy access to system status data contained in internal registers
that contain information on current status for system power selection, charger mode and fault conditions. Any
change on the state of those bits generates an interrupt request to the host (ALARM pin = HI).
Table 2. Status Register Latched Bits
ACOC/CHGOC LATCHES
SET
RESET
CONTROL LOGIC ACTION AT DETECTION
Charger overcurrent detected
Host read register
Latches data going to status register, disables further updates on status
register CHGOC bit until reset.
AC adapter overcurrent detected
Host read register
Latches data going to status register, disables further updates on ACOC bit
until reset.
44
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
BQ24721RHBR
ACTIVE
QFN
RHB
32
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24721RHBT
ACTIVE
QFN
RHB
32
250
CU NIPDAU
Level-2-260C-1 YEAR
Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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to Customer on an annual basis.
Addendum-Page 1
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