HUF76009P3, HUF76009D3S
Data Sheet
December 2001
20A, 20V, 0.027 Ohm, N-Channel, Logic
Level Power MOSFETs
THE HUF76009 is an application-specific MOSFET
optimized for switching when used as the upper switch in
synchronous buck applications. The low gate charge and low
input capacitance results in lower driver and lower switching
losses thereby increasing the overall system efficiency.
Symbol
D
Features
• 20A, 20V
- rDS(ON) = 0.027Ω, VGS = 10V
- rDS(ON) = 0.039Ω, VGS = 5V
• PWM optimized for synchronous buck applications
• Fast Switching
• Low Gate Charge
- Qg Total 11nC (Typ)
G
S
Packaging
HUF76009D3S
JEDEC TO-252AA
HUFD76009P3
JEDEC TO-220AB
Ordering Information
SOURCE
DRAIN
GATE
DRAIN (FLANGE)
GATE
SOURCE
DRAIN
(FLANGE)
Absolute Maximum Ratings
• Low Capacitance
- CISS 470pF (Typ)
- CRSS 50pF (Typ)
PART NUMBER
PACKAGE
BRAND
HUF76009P3
TO-220AB
76009P
HUF76009D3S
TO-252AA
76009D
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the HUF76009D3S in tape and reel, e.g., HUF76009D3ST.
TC = 25oC, Unless Otherwise Specified
SYMBOL
PARAMETER
HUF76009P3,
HUF76009D3S
UNITS
20
V
VDSS
Drain to Source Voltage (Note 1)
VDGR
Drain to Gate Voltage (RGS = 20kΩ) (Note 1)
20
V
Gate to Source Voltage
±16
V
20
16
Figure 4
A
A
A
41
0.33
W
W/oC
-55 to 150
oC
300
260
oC
oC
3.04
oC/W
VGS
ID
ID
IDM
PD
TJ, TSTG
TL
Tpkg
Drain Current
Continuous (TC = 25oC, VGS = 10V) (Figure 2)
Continuous (TC = 100oC, VGS = 5V)
Pulsed Drain Current
Power Dissipation
Derate Above 25oC
Operating and Storage Temperature
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s
Package Body for 10s, See Techbrief TB334
THERMAL SPECIFICATIONS
RθJC
Thermal Resistance Junction to Case, TO-220, TO-252
RθJA
Thermal Resistance Junction to Ambient TO-220
62
oC/W
Thermal Resistance Junction to Ambient TO-252
100
oC/W
NOTE:
1. TJ = 25oC to 125oC.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
©2001 Fairchild Semiconductor Corporation
HUF76009P3, HUF76009D3S Rev. B
HUF76009P3, HUF76009D3S
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
20
-
-
V
VDS = 20V, VGS = 0V
-
-
1
µA
VDS = 20V, VGS = 0V, TC = 150oC
-
-
250
µA
VGS = ±16V
-
-
±100
nA
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
BVDSS
IDSS
IGSS
ID = 250µA, VGS = 0V (Figure 11)
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 10)
1
-
3
V
Drain to Source On Resistance
rDS(ON)
ID = 20A, VGS = 10V (Figures 8, 9)
-
0.022
0.027
Ω
ID = 16A, VGS = 5V (Figure 8)
-
0.032
0.039
Ω
VDD = 10V, ID = 16A
VGS = 5V, RGS = 27Ω,
(Figures 14, 18, 19)
-
-
186
ns
-
9
-
ns
tr
-
115
-
ns
td(OFF)
-
19
-
ns
tf
-
34
-
ns
tOFF
-
-
80
ns
-
-
150
ns
-
5.3
-
ns
-
95
-
ns
td(OFF)
-
37
-
ns
tf
-
33
-
ns
tOFF
-
-
105
ns
-
10.7
13
nC
-
5.7
6.9
nC
-
0.5
0.6
nC
SWITCHING SPECIFICATIONS (VGS = 5V)
Turn-On Time
Turn-On Delay Time
tON
td(ON)
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
Turn-On Delay Time
Rise Time
tON
td(ON)
tr
Turn-Off Delay Time
Fall Time
Turn-Off Time
VDD = 10V, ID = 20A
VGS = 10V,
RGS = 27Ω
(Figures 15, 18, 19)
GATE CHARGE SPECIFICATIONS
Total Gate Charge at 10V
Qg(TOT)
VGS = 0V to 10V
Total Gate Charge at 5V
Qg(TOT)
VGS = 0V to 5V
Threshold Gate Charge
Qg(TH)
VGS = 0V to 1V
VDD = 10V,
ID = 16A,
Ig(REF) = 1.0mA,
(Figures 13, 16, 17)
Gate to Source Gate Charge
Qgs
-
1.7
-
nC
Gate to Drain “Miller” Charge
Qgd
-
2.2
-
nC
-
470
-
pF
-
350
-
pF
-
50
-
pF
MIN
TYP
MAX
UNITS
ISD = 20A
-
-
1.25
V
ISD = 10A
-
-
1.0
V
trr
ISD = 16A, dISD/dt = 100A/µs
-
-
33
ns
QRR
ISD = 16A, dISD/dt = 100A/µs
-
-
30
nC
CAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = 20V, VGS = 0V,
f = 1MHz (Figure 12)
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
©2001 Fairchild Semiconductor Corporation
SYMBOL
VSD
TEST CONDITIONS
HUF76009P3, HUF76009D3S Rev. B
HUF76009P3, HUF76009D3S
Typical Performance Curves
POWER DISSIPATION MULTIPLIER
1.2
25
ID, DRAIN CURRENT (A)
1.0
0.8
0.6
0.4
0.2
0
0
25
50
75
125
100
20
VGS = 10V
15
VGS = 5V
10
5
0
25
150
50
TA , AMBIENT TEMPERATURE (oC)
75
100
125
150
TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
IDM, PEAK CURRENT (A)
500
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
100
150 - TC
I = I25
VGS = 10V
125
VGS = 5V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
10-5
10-4
10-3
10-2
10-1
100
101
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
©2001 Fairchild Semiconductor Corporation
HUF76009P3, HUF76009D3S Rev. B
HUF76009P3, HUF76009D3S
Typical Performance Curves
(Continued)
200
40
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
ID , DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
100
100µs
10
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
10ms
SINGLE PULSE
TJ = MAX RATED TC = 25oC
30
20
TJ = 25oC
1
1
TJ = 150oC
10
0
50
10
2
3
VDS , DRAIN TO SOURCE VOLTAGE (V)
5
4
VGS , GATE TO SOURCE VOLTAGE (V)
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
FIGURE 6. TRANSFER CHARACTERISTICS
40
60
VGS = 10V
rDS(ON) , DRAIN TO SOURCE
ON RESISTANCE (mΩ)
VGS = 5V
VGS = 4.5V
ID , DRAIN CURRENT (A)
TJ = -55oC
30
TC = 25oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
20
VGS = 4V
VGS = 3.5V
10
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
ID = 16A
50
ID = 5A
ID = 10A
40
30
20
VGS = 3V
10
0
0
1
2
2
3
FIGURE 7. SATURATION CHARACTERISTICS
6
8
10
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
1.6
1.2
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = VDS, ID = 250µA
1.4
NORMALIZED GATE
THRESHOLD VOLTAGE
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
4
VGS , GATE TO SOURCE VOLTAGE (V)
VDS , DRAIN TO SOURCE VOLTAGE (V)
1.2
1.0
0.8
1.0
0.8
VGS = 10V, ID = 20A
0.6
-80
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
©2001 Fairchild Semiconductor Corporation
160
0.6
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
HUF76009P3, HUF76009D3S Rev. B
HUF76009P3, HUF76009D3S
Typical Performance Curves
(Continued)
1.2
2000
COSS ≅ CDS + CGD
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
ID = 250µA
C, CAPACITANCE (pF)
1000
1.1
1.0
CISS = CGS + CGD
CRSS = CGD
100
0.9
-80
VGS = 0V, f = 1MHz
-40
0
40
80
120
50
0.1
160
1
TJ , JUNCTION TEMPERATURE (oC)
10
20
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
150
VDD = 10V
VGS = 5V, VDD = 10V, ID = 16A
8
125
SWITCHING TIME (ns)
VGS , GATE TO SOURCE VOLTAGE (V)
10
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 16A
ID = 10A
ID = 5A
2
0
0
3
6
9
tr
100
75
tf
50
td(OFF)
25
td(ON)
12
0
0
Qg, GATE CHARGE (nC)
10
20
30
40
50
RGS , GATE TO SOURCE RESISTANCE (Ω)
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
FIGURE 14. SWITCHING TIME vs GATE RESISTANCE
100
SWITCHING TIME (ns)
tr
80
VGS = 10V, VDD = 10V, ID = 20A
60
td(OFF)
40
tf
20
td(ON)
0
0
10
20
30
40
50
RGS , GATE TO SOURCE RESISTANCE (Ω)
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
©2001 Fairchild Semiconductor Corporation
HUF76009P3, HUF76009D3S Rev. B
HUF76009P3, HUF76009D3S
Test Circuits and Waveforms
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 10V
VGS
Qg(TOT)
+
-
VDD
VGS = 5V
VGS
DUT
VGS = 1V
Ig(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORMS
VDS
tON
tOFF
td(ON)
td(OFF)
tr
RL
VDS
tf
90%
90%
+
VGS
-
VDD
10%
0
10%
DUT
90%
RGS
VGS
VGS
0
FIGURE 18. SWITCHING TIME TEST CIRCUIT
©2001 Fairchild Semiconductor Corporation
10%
50%
50%
PULSE WIDTH
FIGURE 19. SWITCHING TIME WAVEFORM
HUF76009P3, HUF76009D3S Rev. B
HUF76009P3, HUF76009D3S
PSPICE Electrical Model
.SUBCKT HUF76009P3 2 1 3 ;
rev 16 March 2000
CA 12 8 5.6e-10
CB 15 14 5.0e-10
CIN 6 8 4.5e-10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
LDRAIN
DPLCAP
DRAIN
2
5
10
5
51
ESLC
11
-
RDRAIN
6
8
EVTHRES
+ 19 8
+
LGATE
GATE
1
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
+
50
-
IT 8 17 1
EVTEMP
RGATE + 18 22
9
20
21
EBREAK
17
18
DBODY
-
16
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1.0e-3
RGATE 9 20 4.0
RLDRAIN 2 5 10
RLGATE 1 9 46
RLSOURCE 3 7 47
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 1.4e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
DBREAK
+
RSLC2
ESG
LDRAIN 2 5 1.0e-9
LGATE 1 9 4.6e-9
LSOURCE 3 7 4.7e-9
RLDRAIN
RSLC1
51
EBREAK 11 7 17 18 25.9
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
RLSOURCE
S1A
12
S2A
14
13
13
8
S1B
CA
RBREAK
15
17
18
RVTEMP
S2B
13
CB
6
8
EGS
-
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
19
-
IT
14
+
+
VBAT
5
8
EDS
-
+
8
22
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*70),3))}
.MODEL DBODYMOD D (IS = 3.4e-13 RS = 1.0e-2 TRS1 = 2e-3 TRS2 = 8e-7 CJO = 1.05e-9 TT = 1.18e-8 XTI = 5 M = 0.42)
.MODEL DBREAKMOD D (RS = 1.3e- 1TRS1 = 0TRS2 = 0)
.MODEL DPLCAPMOD D (CJO = 3.2e-1 0IS = 1e-3 0N = 10 M = 0.6)
.MODEL MMEDMOD NMOS (VTO = 2.38 KP = 12 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RS = 0.03 RG = 4)
.MODEL MSTROMOD NMOS (VTO = 2.87 KP = 28 LAMBDA = 0.02 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.95 KP = 0.08 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 40 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 9.7e- 4TC2 = 0)
.MODEL RDRAINMOD RES (TC1 = 9.8e-3 TC2 = 2.85e-5)
.MODEL RSLCMOD RES (TC1 = 5e-3 TC2 = 5.05e-6)
.MODEL RSOURCEMOD RES (TC1 = 1.5e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -1.48e-3 TC2 = -5e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.68e- 3TC2 = 8e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -4.7 VOFF= -2.0)
VON = -2.0 VOFF= -4.7)
VON = -1.0 VOFF= 0.3)
VON = 0.3 VOFF= -1.0)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2001 Fairchild Semiconductor Corporation
HUF76009P3, HUF76009D3S Rev. B
HUF76009P3, HUF76009D3S
SABER Electrical Model
REV 16 March 2000
template huf76009p3 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 3.4e-13, rs = 1.0e-2, trs1 = 2e-3, trs2 = 8e-7, cjo = 1.05e-9, tt = 1.18e-8, xti = 5, m = 0.42)
dp..model dbreakmod = (rs = 1.3e-1, trs1 = 0, trs2 = 0)
dp..model dplcapmod = (cjo = 3.2e-10, isl = 10e-30, nl = 10, m = 0.6)
m..model mmedmod = (type=_n, vto = 2.38, kp = 12, is = 1e-30, tox = 1, rs = 0.03)
m..model mstrongmod = (type=_n, vto = 2.87, kp = 28, lambda = 0.02, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.95, kp = 0.08, is = 1e-30, tox = 1, rs = 0.1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4.7, voff = -2.0)
DPLCAP 5
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.0, voff = -4.7)
10
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.0, voff = 0.3)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.3, voff = -1.0)
RSLC1
DRAIN
2
RLDRAIN
51
c.ca n12 n8 = 5.6e-10
c.cb n15 n14 = 5.0e-10
c.cin n6 n8 = 4.5e-10
RSLC2
ISCL
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
i.it n8 n17 = 1
LGATE
GATE
1
EVTEMP
RGATE + 18 22
9
20
21
11
DBODY
16
MWEAK
6
EBREAK
+
17
18
MMED
MSTRO
RLGATE
CIN
-
8
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1 = 9.7e-4, tc2 = 0
res.rdrain n50 n16 = 1.0e-3, tc1 = 9.8e-3, tc2 = 2.85e-5
res.rgate n9 n20 = 4.0
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 46
res.rlsource n3 n7 = 47
res.rslc1 n5 n51= 1e-6, tc1 = 5e-3, tc2 = 5.05e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 1.4e-2, tc1 = 1.5e-3, tc2 =1e-6
res.rvtemp n18 n19 = 1, tc1 = -1.68e-3, tc2 = 8e-7
res.rvthres n22 n8 = 1, tc1 = -1.48e-3, tc2 = -5e-6
DBREAK
50
-
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
l.ldrain n2 n5 = 1.0e-9
l.lgate n1 n9 = 4.6e-9
l.lsource n3 n7 = 4.7e-9
LDRAIN
LSOURCE
7
SOURCE
3
RSOURCE
RLSOURCE
S1A
12
S2A
13
8
14
13
S1B
CA
RBREAK
15
17
18
RVTEMP
S2B
13
19
CB
6
8
EGS
-
-
IT
14
+
+
VBAT
5
8
EDS
-
+
8
22
RVTHRES
spe.ebreak n11 n7 n17 n18 = 25.9
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/70))** 3))
}
}
©2001 Fairchild Semiconductor Corporation
HUF76009P3, HUF76009D3S Rev. B
HUF76009P3, HUF76009D3S
SPICE Thermal Model
th
REV 16 March 2000
JUNCTION
T76009
CTHERM1 th 6 9.5e-4
CTHERM2 6 5 2.4e-3
CTHERM3 5 4 3.9e-3
CTHERM4 4 3 4.3e-3
CTHERM5 3 2 5.9e-3
CTHERM6 2 tl 3.0e-2
RTHERM1 th 6 2.0e-2
RTHERM2 6 5 1.1e-1
RTHERM3 5 4 2.75e-1
RTHERM4 4 3 5.3e-1
RTHERM5 3 2 7.1e-1
RTHERM6 2 tl 7.8e-1
SABER Thermal Model
CTHERM1
RTHERM1
6
CTHERM2
RTHERM2
5
CTHERM3
RTHERM3
SABER thermal model T76009
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 9.5e-4
ctherm.ctherm2 6 5 = 2.4e-3
ctherm.ctherm3 5 4 = 3.9e-3
ctherm.ctherm4 4 3 = 4.3e-3
ctherm.ctherm5 3 2 = 5.9e-3
ctherm.ctherm6 2 tl = 3.0e-2
rtherm.rtherm1 th 6 = 2.0e-2
rtherm.rtherm2 6 5 = 1.1e-1
rtherm.rtherm3 5 4 = 2.75e-1
rtherm.rtherm4 4 3 = 5.3e-1
rtherm.rtherm5 3 2 = 7.1e-1
rtherm.rtherm6 2 tl = 7.8e-1
}
4
CTHERM4
RTHERM4
3
CTHERM5
RTHERM5
2
CTHERM6
RTHERM6
tl
©2001 Fairchild Semiconductor Corporation
CASE
HUF76009P3, HUF76009D3S Rev. B
HUF76009P3, HUF76009D3S
TO-252AA
SURFACE MOUNT JEDEC TO-252AA PLASTIC PACKAGE
E
H1
A
b2
INCHES
A1
SEATING
PLANE
D
L2
1
L
3
b1
b
L1
e
e1
MAX
MIN
MAX
A
0.086
0.094
2.19
2.38
-
A1
0.018
0.022
0.46
0.55
4, 5
0.265
(6.7)
L3
0.265 (6.7)
b3
0.070 (1.8)
0.118 (3.0)
BACK VIEW
0.063 (1.6) TYP
0.090 (2.3) TYP
MINIMUM PAD SIZE RECOMMENDED FOR
SURFACE-MOUNTED APPLICATIONS
1.5mm
DIA. HOLE
NOTES
4, 5
b
0.028
0.032
0.72
0.81
b1
0.033
0.045
0.84
1.14
4
b2
0.205
0.215
5.21
5.46
4, 5
b3
0.190
-
4.83
-
2
c
0.018
0.022
0.46
0.55
4, 5
-
D
0.270
0.295
6.86
7.49
E
0.250
0.265
6.35
6.73
e1
J1
TERM. 4
MIN
e
c
MILLIMETERS
SYMBOL
0.090 TYP
0.180 BSC
-
2.28 TYP
7
4.57 BSC
7
H1
0.035
0.045
0.89
1.14
-
J1
0.040
0.045
1.02
1.14
-
L
0.100
0.115
2.54
2.92
-
L1
0.020
-
0.51
-
4, 6
L2
0.025
0.040
0.64
1.01
3
L3
0.170
-
4.32
-
2
NOTES:
1. These dimensions are within allowable dimensions of Rev. B of
JEDEC TO-252AA outline dated 9-88.
2. L3 and b3 dimensions establish a minimum mounting surface for
terminal 4.
3. Solder finish uncontrolled in this area.
4. Dimension (without solder).
5. Add typically 0.002 inches (0.05mm) for solder plating.
6. L1 is the terminal length for soldering.
7. Position of lead to be measured 0.090 inches (2.28mm) from bottom
of dimension D.
8. Controlling dimension: Inch.
9. Revision 11 dated 1-00.
4.0mm
USER DIRECTION OF FEED
2.0mm
TO-252AA
1.75mm
C
L
16mm TAPE AND REEL
16mm
8.0mm
22.4mm
COVER TAPE
13mm
330mm
50mm
GENERAL INFORMATION
1. 2500 PIECES PER REEL.
2. ORDER IN MULTIPLES OF FULL REELS ONLY.
3. MEETS EIA-481 REVISION "A" SPECIFICATIONS.
©2001 Fairchild Semiconductor Corporation
16.4mm
HUF76009P3, HUF76009D3S Rev. B
HUF76009P3, HUF76009D3S
TO-220AB
3 LEAD JEDEC TO-220AB PLASTIC PACKAGE
A
INCHES
E
ØP
A1
Q
H1
TERM. 4
D
45o
E1
D1
L1
b1
L
b
c
MIN
MAX
MIN
MAX
NOTES
A
0.170
0.180
4.32
4.57
-
A1
0.048
0.052
1.22
1.32
-
b
0.030
0.034
0.77
0.86
3, 4
b1
0.045
0.055
1.15
1.39
2, 3
c
0.014
0.019
0.36
0.48
2, 3, 4
D
0.590
0.610
14.99
15.49
-
D1
-
0.160
E
0.395
0.410
E1
-
0.030
e
60o
1
2
e1
3
e
e1
J1
MILLIMETERS
SYMBOL
10.04
-
0.100 TYP
0.200 BSC
H1
0.235
0.255
J1
0.100
0.110
L
0.530
0.550
4.06
-
10.41
-
0.76
-
2.54 TYP
5
5.08 BSC
5
5.97
6.47
-
2.54
2.79
6
13.47
13.97
-
L1
0.130
0.150
3.31
3.81
2
ØP
0.149
0.153
3.79
3.88
-
Q
0.102
0.112
2.60
2.84
-
NOTES:
1. These dimensions are within allowable dimensions of Rev. J of
JEDEC TO-220AB outline dated 3-24-87.
2. Lead dimension and finish uncontrolled in L1.
3. Lead dimension (without solder).
4. Add typically 0.002 inches (0.05mm) for solder coating.
5. Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimension D.
6. Position of lead to be measured 0.100 inches (2.54mm) from bottom of dimension D.
7. Controlling dimensio n :Inch.
8. Revision 2 dated 7-97.
©2001 Fairchild Semiconductor Corporation
HUF76009P3, HUF76009D3S Rev. B
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
Bottomless™
CoolFET™
CROSSVOLT™
DenseTrench™
DOME™
EcoSPARK™
E2CMOSTM
EnSignaTM
FACT™
FACT Quiet Series™
FAST
FASTr™
FRFET™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™
OPTOLOGIC™
OPTOPLANAR™
PACMAN™
POP™
Power247™
PowerTrench
QFET™
QS™
QT Optoelectronics™
Quiet Series™
SILENT SWITCHER
SMART START™
STAR*POWER™
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
TruTranslation™
UHC™
UltraFET
VCX™
STAR*POWER is used under license
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
2. A critical component is any component of a life
systems which, (a) are intended for surgical implant into
support device or system whose failure to perform can
the body, or (b) support or sustain life, or (c) whose
be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance
support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H4