ON NCP5181 High voltage high and low side driver Datasheet

NCP5181
High Voltage High and Low
Side Driver
The NCP5181 is a High Voltage Power MOSFET Driver providing
two outputs for direct drive of 2 N−channel power MOSFETs arranged
in a half−bridge (or any other high−side + low−side) configuration.
It uses the bootstrap technique to insure a proper drive of the
High−side power switch. The driver works with 2 independent inputs
to accommodate any topology (including half−bridge, asymmetrical
half−bridge, active clamp and full−bridge…).
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IN_HI
IN_LO
DRV_HI
GND
BRIDGE
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
High Voltage Range: up to 600 V
dV/dt Immunity ±50 V/nsec
Gate Drive Supply Range from 10 V to 20 V
High and Low DRV Outputs
Output Source / Sink Current Capability 1.1 A / 2.4 A
3.3 V and 5 V Input Logic Compatible
Up to VCC Swing on Input Pins
Matched Propagation Delays between Both Channels
Outputs in Phase with the Inputs
Independent Logic Inputs to Accommodate All Topologies
Under VCC LockOut (UVLO) for Both Channels
Pin to Pin Compatible with IR2181(S)
These are Pb−Free Devices
Applications
• High Power Energy Management
• Half−bridge Power Converters
• Any Complementary Drive Converters (asymmetrical half−bridge,
•
•
active clamp)
Full−bridge Converters
Bridge Inverters for UPS Systems
VBOOT
VCC
DRV_LO
8
1
SOIC−8
D SUFFIX
CASE 751
PDIP−8
P SUFFIX
CASE 626
MARKING DIAGRAMS
8
NCP5181P
AWL
YYWWG
5181
ALYWX
G
1
NCP5181P,
5181
= Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y, YY = Year
W, WW = Work Week
G, G
= Pb−Free Package
PIN ASSIGNMENT
PIN
FUNCTION
ORDERING INFORMATION
IN_HI
Logic Input for High Side Driver Output In Phase
IN_LO
Logic Input for Low Side Driver Output In Phase
GND
Ground
DRV_LO
Low Side Gate Drive Output
VCC
Low Side and Main Power Supply
VBOOT
Bootstrap Power Supply
DRV_HI
High Side Gate Drive Output
BRIDGE
Bootstrap Return or High Side Floating Supply Return
© Semiconductor Components Industries, LLC, 2006
March, 2006 − Rev. 2
1
Shipping †
Device
Package
NCP5181PG
PDIP−8
(Pb−Free)
50 Units/Tube
NCP5181DR2G
SOIC−8
(Pb−Free)
2.500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
NCP5181/D
NCP5181
Vbulk
C1
VCC
D4
GND
5
GND
GND
1
2
3
GND
D1
T1
C3
SG3526
MC34025
TL594
C5
U1
VCC
VBOOT
IN_HI DRV_HI
IN_LO Bridge
GND DRV_LO
8
C4
L1
Out+
Q1
C3
7
Out−
6
4
D2
Q2
C6
NCP51XX
GND
U2
R1
D3
GND
Figure 1. Typical Application
VCC
UV
DETECT
VCC
VBOOT
IN_HI
PULSE
TRIGGER
LEVEL
SHIFTER
S
Q
R
Q
DRV_HI
GND
UV
DETECT
GND
BRIDGE
VCC
DELAY
IN_LO
DRV_LO
GND
GND
GND
GND
Figure 2. Detailed Block Diagram
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2
NCP5181
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VCC
−0.3 to 20
V
VBRIDGE
−1 to 600
V
VBOOT − VBRIDGE
0 to 20
V
VHV: High side output voltage
VDRV_HI
VBRIDGE−0.3 to VBOOT+0.3
V
Low side output voltage
VDRV_LO
−0.3 to VCC+0.3
V
dVBRIDGE/dt
50
V/ns
VIN_XX
−1.0 to VCC+0.3
V
2.0
200
kV
V
Main power supply voltage
VHV: High Voltage BRIDGE pin
VHV: Floating supply voltage
Allowable output slew rate
Inputs IN_HI, IN_LO
ESD Capability:
HBM model (all pins except pins 6−7−8)
Machine model (all pins except pins 6−7−8)
Latch up capability per Jedec JESD78
°C/W
Power dissipation and thermal characteristics
PDIP8: Thermal resistance, Junction−to−Air
SO−8: Thermal resistance, Junction−to−Air
Operating junction temperature
RqJA
RqJA
100
178
TJ_min
TJ_max
−55
+150
°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
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3
NCP5181
ELECTRICAL CHARACTERISTICS (VCC = Vboot = 15 V, Vgnd = Vbridge, −40°C < TA < 125°C, Outputs loaded with 1 nF)
Rating
Symbol
TA −40°C to 125°C
Units
OUTPUT SECTION
Min
Typ
Max
Output high short circuit pulsed current
VDRV = 0 V, PW ≤ 10 ms, (Note 1)
IDRVhigh
−
1.4
−
A
Output low short circuit pulsed current
VDRV = VCC, PW ≤ 10 ms, (Note 1)
IDRVlow
−
2.2
−
A
Output resistor (Typical value @ 25°C only)
Source
ROH
−
5
12
W
Output resistor (Typical value @ 25°C only)
Sink
ROL
−
2
8
W
Symbol
Min
Typ
Max
Units
Turn−on propagation delay (Vbridge = 0 V)
tON
−
100
170
ns
Turn−off propagation delay (Vbridge = 0 V or 50 V) (Note 2)
DYNAMIC OUTPUT SECTION
Rating
tOFF
−
100
170
ns
Output voltage rise time
(from 10% to 90% @ VCC = 15 V) with 1 nF load
tr
−
40
60
ns
Output voltage falling edge
(from 90% to 10% @ VCC = 15 V) with 1 nF load
tf
−
20
40
ns
Propagation delay matching between the High side and the Low side
@ 25°C (Note 3)
Dt
−
20
35
ns
tPW
−
−
100
ns
Low level input voltage threshold
VIN
−
−
0.8
V
Input pull−down resistor (VIN < 0.5 V)
RIN
−
200
−
kW
High level input voltage threshold
VIN
2.3
−
−
V
VCC_stup
7.9
8.9
9.8
V
Minimum input pulse width that changes the output
INPUT SECTION
SUPPLY SECTION
VCC UV Start−up voltage threshold
VCC UV Shut−down voltage threshold
VCC_shtdwn
7.3
8.2
9.0
V
Hysteresis on VCC
VCC_hyst
0.3
0.7
−
V
Vboot Start−up voltage threshold reference to bridge pin
(Vboot_stup = Vboot − Vbridge)
Vboot_stup
7.9
8.9
9.8
V
Vboot UV Shut−down voltage threshold
Vboot_shtdwn
7.3
8.2
9.0
V
Hysteresis on Vboot
Vboot_shtdwn
0.3
0.7
−
V
IHV_LEAK
−
0.5
40
mA
Consumption in active mode
(VCC = Vboot, fsw = 100 kHz and 1 nF load on both driver outputs)
ICC1
−
4.5
6.5
mA
Consumption in inhibition mode (VCC = Vboot)
ICC2
−
250
400
mA
VCC current consumption in inhibition mode
ICC3
−
215
−
mA
Vboot current consumption in inhibition mode
ICC4
−
35
−
mA
Leakage current on high voltage pins to GND
(VBOOT = VBRIDGE = DRV_HI = 600 V)
*Note: see also characterization curves
1. Guaranteed by design.
2. Turn−off propagation delay @ Vbridge = 600 V is guaranteed by design
3. See characterization curve for Dt parameters variation on the full range temperature.
4. Timing diagram definition see Figures 4, 5 and 6.
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4
NCP5181
IN_HI
IN_LO
DRV_HI
DRV_LO
Figure 3. Input/Output Timing Diagram
50%
IN_HI
IN_LO
50%
tr
ton
90%
DRV_HI
DRV_LO
tf
toff
90%
10%
10%
Figure 4. Switching Time Waveform Definitions
IN_LO
50%
50%
IN_HI
ton
toff
Delta_t
DRV_HI
90%
10%
toff
Delta_t
90%
ton
DRV_LO
10%
Figure 5. Delay Matching Waveforms Definition
IN_LO
&
IN_HI
50%
50%
ton_HI
toff_HI
90%
Delta_t
DRV_HI
10%
Delta_t
ton_LO
ton_LO
DRV_LO
10%
Figure 6. Other Delay Matching Waveforms Definition
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5
90%
NCP5181
TYPICAL CHARACTERISTICS
140
Ton PROPAGATION DELAY (ns)
Ton PROPAGATION DELAY (ns)
160
140
ton High Side
120
ton Low Side
100
80
60
40
20
0
−40
0
20
40
60
80
100
ton Low Side
80
60
40
20
120
10
12
14
16
18
TEMPERATURE (°C)
SUPPLY VOLTAGE; VCC = Vboot (V)
Figure 7. Turn−on Propagation Delay vs.
Temperature
Figure 8. Turn−on Propagation Delay vs. VCC
Voltage (VCC = Vboot)
20
160
160
Toff PROPAGATION DELAY (ns)
Toff PROPAGATION DELAY (ns)
100
0
−20
180
toff High Side
140
120
100
toff Low Side
80
60
40
20
0
−40
140
toff High Side
120
100
toff Low Side
80
60
40
20
0
−20
0
20
40
60
80
100
120
10
12
14
16
18
20
TEMPERATURE (°C)
SUPPLY VOLTAGE; VCC = Vboot (V)
Figure 9. Turn−off Propagation Delay vs.
Temperature
Figure 10. Turn−off Propagation Delay vs. VCC
Voltage (VCC = Vboot)
130
Toff PROPAGATION DELAY (ns)
130
Ton PROPAGATION DELAY (ns)
ton High Side
120
110
90
70
50
110
90
70
50
0
10
20
30
40
50
0
10
20
30
40
BRIDGE PIN VOLTAGE (V)
BRIDGE PIN VOLTAGE (V)
Figure 11. High Side Turn−on Propagation
Delay vs. VBRIDGE Voltage
Figure 12. High Side Turn−off Propagation
Delay vs. VBRIDGE Voltage
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50
NCP5181
40
35
35
30
TURN−ON RISE TIME (ns)
TURN−ON RISE TIME (ns)
TYPICAL CHARACTERISTICS
30
tr High Side
25
tr Low Side
20
15
10
5.0
0
−40
tr Low Side
25
20
tr High Side
15
10
5.0
0
−20
0
20
40
60
80
100
120
10
12
14
16
TEMPERATURE (°C)
SUPPLY VOLTAGE; VCC = Vboot (V)
Figure 13. Turn−on Rise Time vs. Temperature
Figure 14. Turn−on Rise Time vs. VCC Voltage
(VCC = Vboot)
30
20
20
18
TURN−OFF FALL TIME (ns)
25
tf Low Side
20
tf High Side
15
10
5.0
0
−40
tf Low Side
16
14
12
10
tf High Side
8.0
6.0
4.0
2.0
0
−20
0
20
40
60
80
100
120
10
12
14
16
18
TEMPERATURE (°C)
SUPPLY VOLTAGE; VCC = Vboot (V)
Figure 15. Turn−off Fall Time vs. Temperature
Figure 16. Turn−off Fall Time vs. VCC Voltage
(VCC = Vboot)
PROPAGATION DELAY MATCHING (ns)
TURN−OFF FALL TIME (ns)
18
40
35
30
25
20
15
10
5
0
−40
−20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 17. Propagation Delay Matching
Between High Side and Low Side Driver
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120
20
NCP5181
1.4
LOW LEVEL INPUT VOLTAGE THRESHOLD (V)
LOW LEVEL INPUT VOLTAGE THRESHOLD (V)
TYPICAL CHARACTERISTICS
1.2
1.0
0.8
0.6
0.4
0.2
0
−40
−20
0
20
40
60
80
100
120
TEMPERATURE (°C)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
10
16
18
20
Figure 19. Low Level Input Voltage Threshold
vs. VCC Voltage
2.5
HIGH LEVEL INPUT VOLTAGE
THRESHOLD (V)
2.5
HIGH LEVEL INPUT VOLTAGE
THRESHOLD (V)
14
SUPPLY VOLTAGE; VCC = Vboot (V)
Figure 18. Low Level Input Voltage Threshold
vs. Temperature
2.0
1.5
1.0
0.5
0
−40
2.0
1.5
1.0
0.5
0
−20
0
20
40
60
80
100
120
10
12
14
16
18
20
TEMPERATURE (°C)
SUPPLY VOLTAGE; VCC = Vboot (V)
Figure 20. High Level Input Voltage Threshold
vs. Temperature
Figure 21. High Level Input Voltage Threshold
vs. VCC Voltage
4.0
0.40
HIGH SIDE LEAKAGE CURRENT
TO GND (mA)
LEAKAGE CURRENT TO GND (mA)
12
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
−40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
−20
0
20
40
60
80
TEMPERATURE (°C)
100
120
0
Figure 22. Leakage Current on High Voltage
Pins (600 V) to Ground vs. Temperature
100
200
300
400
BRIDGE PIN VOLTAGE (V)
500
600
Figure 23. Leakage Current on High Voltage
Pins to Ground vs. Vbridge Voltage
(Vbridge = Vboot = VDRV_HI)
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8
NCP5181
TYPICAL CHARACTERISTICS
100
BOOTSTRAP SUPPLY CURRENT (mA)
BOOTSTRAP SUPPLY CURRENT (mA)
100
80
60
40
20
0
−40
−20
0
20
40
60
80
100
120
0
10
12
14
16
18
Figure 25. High Side Supply Current vs.
Bootstrap Supply Voltage
20
500
VCC SUPPLY CURRENT (mA)
VCC SUPPLY CURRENT (mA)
20
Figure 24. High Side Supply Current vs.
Temperature
300
200
100
400
300
200
100
0
−20
0
20
40
60
80
100
120
10
12
14
16
18
20
TEMPERATURE (°C)
VCC, SUPPLY VOLTAGE (V)
Figure 26. VCC Supply Current vs.
Temperature
Figure 27. VCC Supply Current vs. VCC Supply
Voltage
9.0
UVLO SHUTDOWN VOLTAGE th (V)
10
UVLO STARTUP VOLTAGE th (V)
40
BOOTSTRAP SUPPLY VOLTAGE (V)
400
9.8
9.6
9.4
9.2 Vboot UVLO stup th
9.0
8.8 VCC UVLO stup th
8.6
8.4
8.2
8.0
−40
60
TEMPERATURE (°C)
500
0
−40
80
−20
0
20
40
60
80
100
120
8.8
8.6
8.4
VCC UVLO shtdwn th
8.2
8.0
Vboot UVLO shtdwn th
7.8
7.6
7.4
7.2
7.0
−40 −20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 28. UVLO Start Up Voltage vs.
Temperature
Figure 29. UVLO Shut Down Voltage vs.
Bootstrap Supply Voltage
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120
NCP5181
TYPICAL CHARACTERISTICS
60
Cload = 1 nF / Q = 15 nC
30
ICC + Iboot CURRENT SUPPLY (mA)
ICC + Iboot CURRENT SUPPLY (mA)
35
Rgate = 22 W
25
Rgate = 10 W
20
Rgate = 0 W
15
10
5.0
0
80
100
200
300
400
500
Rgate = 22 W
40
Rgate = 0 W
30
Rgate = 10 W
20
10
0
600
0
100
200
300
400
500
600
SWITCHING FREQUENCY (kHz)
SWITCHING FREQUENCY (kHz)
Figure 30. ICC1 Consumption vs. Switching
Frequency with 15 nC Load on Each Driver
Figure 31. ICC1 Consumption vs. Switching
Frequency with 33 nC Load on Each Driver
ICC + Iboot CURRENT SUPPLY (mA)
ICC + Iboot CURRENT SUPPLY (mA)
0
Cload = 2.2 nF / Q = 33 nC
50
Cload = 3.3 nF / Q = 50 nC
70
Rgate = 22 W
60
Rgate = 10 W
50
Rgate = 0 W
40
30
20
10
0
140
Rgate = 22 W
Cload = 6.6 nF / Q = 100 nC
120
Rgate = 10 W
100
Rgate = 0 W
80
60
40
20
0
0
100
200
300
400
500
600
0
100
200
300
400
500
600
SWITCHING FREQUENCY (kHz)
SWITCHING FREQUENCY (kHz)
Figure 32. ICC1 Consumption vs. Switching
Frequency with 50 nC Load on Each Driver
Figure 33. ICC1 Consumption vs. Switching
Frequency with 100 nC Load on Each Driver
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NCP5181
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AG
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
0.25 (0.010)
S
B
1
M
Y
M
4
K
−Y−
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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11
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8 _
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
NCP5181
PACKAGE DIMENSIONS
8 LEAD PDIP
CASE 626−05
ISSUE L
8
5
−B−
1
4
F
−A−
NOTE 2
L
C
J
−T−
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
9.40
10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
−−−
10_
0.76
1.01
INCHES
MIN
MAX
0.370
0.400
0.240
0.260
0.155
0.175
0.015
0.020
0.040
0.070
0.100 BSC
0.030
0.050
0.008
0.012
0.115
0.135
0.300 BSC
−−−
10_
0.030
0.040
N
SEATING
PLANE
D
H
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
K
G
0.13 (0.005)
M
T A
M
B
M
The product described herein (NCP5181), is covered by U.S. patent: 6,362, 067. There may be some other patent pending.
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NCP5181/D