Hynix GM71S17403C-5 4,194,304 words x 4 bit cmos dynamic ram Datasheet

GM71C(S)17403C/CL
4,194,304 WORDS x 4 BIT
CMOS DYNAMIC RAM
Description
Features
The GM71C(S)17403C/CL is the new
generation dynamic RAM organized 4,194,304
words x 4 bit. GM71C(S)17403C/CL has
realized higher density, higher performance and
various functions by utilizing advanced CMOS
process technology. The GM71C(S)17403C/CL
offers Extended Data Out (EDO) Mode as a
high speed access mode. Multiplexed address
inputs permit the GM71C(S)17403C/CL to be
packaged in a standard 300 mil 24(26) pin SOJ
and a standard 300mil 24(26) pin plastic TSOP
II. The package size provides high system bit
densities and is compatible with widely
available automated testing and insertion
equipment. System oriented features include
single power supply 5V+/-10% tolerance, direct
interfacing capability with high performance
logic families such as Schottky TTL.
* 4,194,304 Words x 4 Bit Organization
* Extended Data Out Mode Capability
* Single Power Supply (5V+/-10%)
* Fast Access Time & Cycle Time
Pin Configuration
tRAC tCAC
(Unit: ns)
tRC
tHPC
GM71C(S)17403C/CL-5
50
13
84
20
GM71C(S)17403C/CL-6
60
15
104
25
GM71C(S)17403C/CL-7
70
18
124
30
* Low Power
Active : 660/605/550mW (MAX)
Standby : 11mW (CMOS level : MAX)
: 0.83mW (L-version : MAX)
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
* All inputs and outputs TTL Compatible
* 2048 Refresh Cycles/32ms
* 2048 Refresh Cycles/128ms (L-version)
* Battery Backup Operation (L-version)
* Test Function : 16bit parallel test mode
24(26) SOJ
24(26) TSOP II
VCC
1
26
VSS
VCC
1
26
VSS
I/O1
2
25
I/O4
I/O1
2
25
I/O4
I/O2
3
24
I/O3
I/O2
3
24
I/O3
WE
4
23
CAS
WE
4
23
CAS
RAS
5
22
OE
RAS
5
22
OE
NC
6
21
A9
A11
6
21
A9
A10
8
19
A8
A10
8
19
A8
A0
9
18
A7
A0
9
18
A7
A1
10
17
A6
A1
10
17
A6
A2
11
16
A5
A2
11
16
A5
A3
12
15
A4
A3
12
15
A4
VCC 13
14
VCC 13
14
VSS
VSS
(Top View)
Rev 0.1 / Apr’01
GM71C(S)17403C/CL
Pin Description
Pin
Function
Pin
Function
A0-A10
Address Inputs
WE
Read/Write Enable
A0-A10
Refresh Address Inputs
OE
Output Enable
I/O1-I/O4
Data-input/Data-output
VCC
Power (+5V)
RAS
Row Address Strobe
VSS
Ground
CAS
Column Address Strobe
NC
No Connection
Ordering Information
Type No.
Access Time
Package
GM71C(S)17403CJ/CLJ-5
GM71C(S)17403CJ/CLJ-6
GM71C(S)17403CJ/CLJ-7
50ns
60ns
70ns
300 Mil
24(26) Pin
Plastic SOJ
GM71C(S)17403CT/CLT-5
GM71C(S)17403CT/CLT-6
GM71C(S)17403CT/CLT-7
50ns
60ns
70ns
300 Mil
24(26) Pin
Plastic TSOP II
Absolute Maximum Ratings*
Symbol
Parameter
Rating
Unit
0 ~ 70
C
TA
Ambient Temperature under Bias
TSTG
Storage Temperature (Plastic)
-55 ~ 125
C
VIN/VOUT
Voltage on any Pin Relative to VSS
-1.0 ~ 7.0
V
VCC
Voltage on VCC Relative to VSS
-1.0 ~ 7.0
V
IOUT
Short Circuit Output Current
50
mA
PD
Power Dissipation
1.0
W
Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability.
Recommended DC Operating Conditions (TA = 0 ~ 70C)
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
4.5
5.0
5.5
V
VIH
Input High Voltage
2.4
-
6.5
V
VIL
Input Low Voltage
-1.0
-
0.8
V
Rev 0.1 / Apr’01
GM71C(S)17403C/CL
DC Electrical Characteristics (VCC = 5.0V+/-10%, VSS = 0V, TOPR = 0 ~ 70C)
Symbol
Parameter
Min
Max
Unit
VOH
Output Level
Output "H" Level Voltage (IOUT = -2mA)
2.0
VCC
V
VOL
Output Level
Output "L" Level Voltage (IOUT = 2mA)
0
0.4
V
ICC1
Operating Current
Average Power Supply Operating Current
(RAS, CAS Cycling : tRC = tRC min)
50ns
-
120
60ns
-
110
70ns
-
100
-
2
ICC2
ICC3
ICC4
ICC5
ICC6
Standby Current (TTL)
Power Supply Standby Current
(RAS, CAS = VIH, DOUT = High-Z)
mA
Note
1, 2
mA
RAS Only Refresh Current
Average Power Supply Current
RAS Only Refresh Mode
(tRC = tRC min)
50ns
-
100
60ns
-
90
70ns
-
80
EDO Page Mode Current
Average Power Supply Current
EDO Page Mode
(tHPC = tHPC min)
50ns
-
90
60ns
-
80
-
1
mA
-
150
uA
50ns
-
100
60ns
-
90
70ns
-
80
-
350
uA
4,5
-
5
mA
1
70ns
Standby Current (CMOS)
Power Supply Standby Current
(RAS, CAS >= VCC - 0.2V, DOUT = High-Z)
CAS-before-RAS Refresh Current
(tRC = tRC min)
mA
2
mA
1, 3
70
mA
ICC7
Battery Backup Operating Current(Standby with CBR Refresh)
(CBR refresh, tRC = 62.5us, tRAS <= 0.3us,
DOUT = High-Z, CMOS interface)
ICC8
Standby Current RAS = VIH
CAS = VIL
DOUT = Enable
IL(I)
Input Leakage Current
Any Input (0V<=VIN<= 6V)
-10
10
uA
IL(O)
Output Leakage Current
(DOUT is Disabled, 0V<=VOUT<= 6V)
-10
10
uA
Note: 1. ICC depends on output load condition when the device is selected.
ICC(max) is specified at the output open condition.
2. Address can be changed once or less while RAS = VIL.
3. Address can be changed once or less while CAS = VIH.
4. CAS = L (<=0.2) while RAS = L (<=0.2).
5. L-version.
Rev 0.1 / Apr’01
5
GM71C(S)17403C/CL
Capacitance (VCC = 5V+/-10%, TA = 25C)
Symbol
Parameter
Min
Max
Unit
Note
CI1
Input Capacitance (Address)
-
5
pF
1
CI2
Input Capacitance (Clocks)
-
7
pF
1
CI/O
Output Capacitance (Data-In/Out)
-
7
pF
1, 2
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = VIH to disable DOUT.
AC Characteristics (VCC = 5V+/-10%, TA = 0 ~ 70C, Notes 1, 2, 18, 19)
Test Conditions
Input rise and fall times: 2 ns
Input timing reference levels: 0.8V, 2.4V
Output timing reference levels: 0.8V, 2.0V
Output load : 1 TTL gate + CL (100pF)
(Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
Symbol
Parameter
GM71C(S)17403 GM71C(S)17403 GM71C(S)17403
C/CL-6
C/CL-7
C/CL-5
Unit
Note
Min Max Min Max Min Max
tRC
Random Read or Write Cycle Time
84
-
104
-
124
-
ns
tRP
RAS Precharge Time
30
-
40
-
50
-
ns
tCP
CAS Precharge Time
7
-
10
-
13
-
ns
tRAS
RAS Pulse Width
50 10,000
60 10,000
70 10,000
ns
21
tCAS
CAS Pulse Width
7 10,000
10 10,000
13 10,000
ns
22
tASR
Row Address Set up Time
0
-
0
-
0
-
ns
tRAH
Row Address Hold Time
7
-
10
-
10
-
ns
tASC
Column Address Set-up Time
0
-
0
-
0
-
ns
tCAH
tRCD
tRAD
tRSH
tCSH
Column Address Hold Time
7
-
10
-
13
-
ns
RAS to CAS Delay Time
11
37
14
45
14
52
ns
3
RAS to Column Address Delay Time
9
25
12
30
12
35
ns
4
RAS Hold Time
10
-
13
-
13
-
ns
CAS Hold Time
35
-
40
-
45
-
ns
tCRP
tODD
CAS to RAS Precharge Time
5
-
5
-
5
-
ns
13
-
15
-
18
-
ns
5
tDZO
tDZC
tT
OE Delay Time from DIN
0
-
0
-
0
-
ns
6
CAS Delay Time from DIN
0
-
0
-
0
-
ns
6
Transition Time (Rise and Fall)
2
50
2
50
2
50
ns
7
OE to DIN Delay Time
Rev 0.1 / Apr’01
24
GM71C(S)17403C/CL
Read Cycle
Symbol
Parameter
GM71C(S)17403 GM71C(S)17403 GM71C(S)17403
C/CL-5
C/CL-6
C/CL-7
Min Max
Unit
Note
Min Max Min Max
tRAC
Access Time from RAS
-
50
-
60
-
70
ns
8,9,19
tCAC
Access Time from CAS
-
13
-
15
-
18
ns
9,10,17,19
tAA
Access Time from Address
-
25
-
30
-
35
ns
9,11,17,19
tOAC
Access Time from OE
-
13
-
15
-
18
ns
9
tRCS
Read Command Setup Time
0
-
0
-
0
-
ns
tRCH
Read Command Hold Time to CAS
0
-
0
-
0
-
ns
12
tRRH
tRAL
Read Command Hold Time to RAS
5
-
5
-
5
-
ns
12
Column Address to RAS Lead Time
25
-
30
-
35
-
ns
tCAL
Column Address to CAS Lead Time
15
-
18
-
23
-
ns
tCLZ
CAS to Output in Low-Z
0
-
0
-
0
-
ns
tOH
Output Data Hold Time
3
-
3
-
3
-
ns
tOHO
Output Data Hold Time from OE
3
-
3
-
3
-
ns
tOFF
Output Buffer Turn-off Time
-
13
-
15
-
15
ns
13
tOEZ
Output Buffer Turn-off Time to OE
-
13
-
15
-
15
ns
13,23
tCDD
CAS to DIN Delay Time
13
-
15
-
18
-
ns
5
tRCHR
Read Command Hold Time from RAS
50
-
60
-
70
-
ns
tOHR
Output Data hold Time from RAS
3
-
3
-
3
-
ns
tOFR
Output Buffer turn off to RAS
-
13
-
15
-
15
ns
13,23
tWEZ
Output Buffer turn off to WE
-
13
-
15
-
15
ns
13
tWDD
WE to DIN Delay Time
13
-
15
-
18
-
ns
tRDD
RAS to DIN Delay Time
13
-
15
-
18
-
ns
Rev 0.1 / Apr’01
GM71C(S)17403C/CL
Write Cycle
Symbol
Parameter
GM71C(S)17403 GM71C(S)17403
C/CL-5
C/CL-6
GM71C(S)17403
C/CL-7
Unit
Note
14
Min Max Min Max Min Max
tWCS
Write Command Setup Time
0
-
0
-
0
-
ns
tWCH
Write Command Hold Time
7
-
10
-
13
-
ns
tWP
Write Command Pulse Width
7
-
10
-
10
-
ns
tRWL
Write Command to RAS Lead Time
7
-
10
-
13
-
ns
tCWL
Write Command to CAS Lead Time
7
-
10
-
13
-
ns
tDS
tD
Data-in Setup Time
0
-
0
-
0
-
ns
15
Data-in Hold Time
7
-
10
-
13
-
ns
15
Unit
Note
H
Read- Modify-Write Cycle
Symbol
Parameter
GM71C(S)17403 GM71C(S)17403 GM71C(S)17403
C/CL-5
C/CL-6
C/CL-7
Min Max Min Max Min Max
tRWC
Read-Modify-Write Cycle Time
tRWD
111
-
136
-
161
-
ns
RAS to WE Delay Time
67
-
79
-
92
-
ns
14
tCWD
CAS to WE Delay Time
30
-
34
-
40
-
ns
14
tAWD
Column Address to WE Delay Time
42
-
49
-
57
-
ns
14
tOEH
OE Hold Time from WE
13
-
15
-
18
-
ns
Refresh Cycle
Parameter
Symbol
GM71C(S)17403
C/CL-5
Min
GM71C(S)17403 GM71C(S)17403
C/CL-6
C/CL-7
Unit
Max Min Max Min Max
tCSR
CAS Setup Time
(CAS-before-RAS Refresh Cycle)
5
-
5
-
5
-
ns
tCHR
CAS Hold Time
(CAS-before-RAS Refresh Cycle)
7
-
10
-
10
-
ns
tWRP
WE Setup Time
(CAS-before-RAS Refresh Cycle)
0
-
0
-
0
-
ns
tWRH
WE Hold Time
(CAS-before-RAS Refresh Cycle)
10
-
10
-
10
-
ns
tRPC
RAS Precharge to CAS Hold Time
5
-
5
-
5
-
ns
Rev 0.1 / Apr’01
Note
GM71C(S)17403C/CL
EDO Page Mode Cycle
Symbol
Parameter
GM71C(S)17403 GM71C(S)17403
C/CL-5
C/CL-6
GM71C(S)17403
C/CL-7
Unit
Note
Min Max Min Max Min Max
tHPC
EDO Page Mode Cycle Time
tRASP
tACP
tRHCP
20
-
25
-
30
-
ns
20
EDO Page Mode RAS Pulse Width
-
100,000
-
100,000
-
100,000
ns
16
Access Time from CAS Precharge
-
30
-
35
-
40
ns
9,17,19
RAS Hold Time from CAS Precharge
30
-
35
-
40
-
ns
tDOH
Output data Hold Time from CAS low
3
-
3
-
3
ns
tCOL
CAS Hold Time referred OE
7
-
10
-
13
ns
tCOP
CAS to OE Setup Time
5
-
5
-
5
ns
tRCHP
Read command Hold Time
from CAS Precharge
30
-
35
-
40
ns
9
EDO Page Mode Read-Modify-Write Cycle
Symbol
Parameter
GM71C(S)17403 GM71C(S)17403
C/CL-5
C/CL-6
GM71C(S)17403
C/CL-7
Unit
Note
Min Max Min Max Min Max
tHPRWC
EDO Page Mode Read-Modify-Write
Cycle Time
57
-
68
-
79
-
ns
tCPW
WE Delay Time from CAS Precharge
45
-
54
-
62
-
ns
14
Unit
Note
Refresh
Symbol
Parameter
GM71C(S)17403 GM71C(S)17403 GM71C(S)17403
C/CL-5
C/CL-6
C/CL-7
Min Max Min Max Min Max
tREF
Refresh period
-
32
-
32
-
32
ms
2048
cycles
tREF
Refresh period (L -Series)
-
128
-
128
-
128
ms
2048
cycles
Unit
Note
Test Mode Cycle ∗19
Symbol
Parameter
GM71C(S)17403 GM71C(S)17403 GM71C(S)17403
C/CL-5
C/CL-6
C/CL-7
Min Max Min Max Min Max
tWTS
Test Mode WE Setup Time
0
-
0
-
0
-
ns
tWTH
Test Mode WE Hold Time
10
-
10
-
10
-
ns
Rev 0.1 / Apr’01
GM71C(S)17403C/CL
Notes:
1. AC Measurements assume tT = 2ns.
2. An initial pause of 200us is required after power up followed by a minimum of eight
initialization cycles (any combination of cycles containing RAS-only refresh or CAS-beforeRAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS
refresh cycles are required.
3. Operation with the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a
reference point only; if tRCD is greater than the specified tRCD(max) limit, then access time is
controlled exclusively by tCAC.
4. Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a
reference point only; if tRAD is greater than the specified tRAD(max) limit, then access time is
controlled exclusively by tAA.
5. Either tODD or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
7. VIH (min) and VIL(max) are reference levels for measuring timing of input signals. Also,
transition times are measured between VIH(min) and VIL(max).
8. Assume that tRCD<=tRCD(max) and tRAD<=tRAD(max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100pF.
10. Assume that tRCD>=tRCD(max) and tRAD<=tRAD(max).
11. Assume that tRCD<=tRCD(max) and tRAD>=tRAD(max).
12. Either tRCH or tRRH must be satisfied for a read cycles.
13. tOFF(max) and tOEZ(max) define the time at which the outputs achieve the open circuit condition
and are not referenced to output voltage levels.
14. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only; if tWCS>=tWCS(min), the cycles is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if
tRWD>=tRWD(min), the tCWD>=tCWD(min), and tAWD>=tAWD(min), or tCWD>=tCWD(min), tAWD>=
tAWD(min) and tCPW>=tCPW(min), the cycle is a read-modify-write and the data output will contain
data read from the selected cell; if neither of the above sets of conditions is satisfied, the
condition of the data out (at access time) is indeterminate.
15. These parameters are referenced to CAS leading edge in early write cycles and to WE leading
edge in delayed write or read-modify-write cycles.
16. tRASP defines RAS pulse width in fast page mode cycles.
17. Access time is determined by the longer of tAA or tCAC or tACP
Rev 0.1 / Apr’01
GM71C(S)17403C/CL
18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying
data to the device. After RAS is reset, if tOEH>=tCWL, the I/O pin will remain open circuit (high
impedance); if tOEH<=tCWL, invalid data will be out at each I/O.
19. The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0 and CA1 for the
4M x 4 are don't care during test mode. Test mode is set by performing a WE-and-CAS-beforeRAS (WCBR) cycle. In 16-bit parallel test mode, data is written into 4 bits in parallel at each I/O
(I/O1 to I/O4) and read out from each I/O. If 4 bits of each I/O are equal (all 1s or 0s), data
output pin is high state during test mode read cycle, then the device has passed. If they are not
equal, data output pin is a low state, then the device has failed. Refresh during test mode
operation can be performed by normal read cycles or by WCBR refresh cycles. To get out of test
mode and enter a normal operation mode, perform either a regular CAS-before-RAS refresh
cycle or RAS-only refresh cycle.
20. In a test mode read cycle, the value of tRAC, tAA, tCAC and tACP is delayed by 2ns to 5ns for the
specified value. These parameters should be specified in test mode cycles by adding the above
value to the specified value in this data sheet.
21. tRAS(min) = tRWD(min) + tRWL(min) + tT in Read - Modify - Write cycle.
22. tCAS(min) = tCWD(min) + tCWL(min) + tT in Read - Modify - Write cycle.
23. tOFF and tOFR are determined by the later rising edge of RAS or CAS.
24. tCSH(min) can be achieved when tRCD <= tCSH(min) - tCAS(min).
Rev 0.1 / Apr’01
GM71C(S)17403C/CL
Package Dimension
Unit: Inches (mm)
24(26) SOJ
0.025(0.64)
0.260(6.60) MIN
0.275(6.99) MAX
0.329(8.38) MIN
0.340(8.64) MAX
0.295(7.49) MIN
0.305(7.75) MAX
MIN
0.085(2.16)
0.661(16.80) MIN
0.669(17.00) MAX
MIN
0.128(3.25) MIN
0.147(3.75) MAX
0.026(0.66) MIN
0.032(0.81) MAX
0.050(1.27)
TYP
0.015(0.38) MIN
0.020(0.50) MAX
24(26) TSOP (TYPE II)
0.670(17.04) MIN
0.678(17.24) MAX
0.008(0.21) MAX
0.047(1.20)
MAX
Rev 0.1 / Apr’01
0.016(0.40) MIN
0.024(0.60) MAX
0.004(0.12) MIN
0.037(0.95) MIN
0.041(1.05) MAX
0.012(0.30) MIN
0.020(0.50) MAX
o
0.355(9.02) MIN
0.371(9.42) MAX
0.296(7.52) MIN
0.303(7.72) MAX
0~5
0.050(1.27)
TYP
0.003(0.08) MIN
0.007(0.18) MAX
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