Microchip MCP3301T-BI/SN 13-bit differential input, low power a/d converter with spiâ ¢ serial interface Datasheet

MCP3301
13-Bit Differential Input, Low Power A/D Converter
with SPI™ Serial Interface
Features
General Description
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The Microchip Technology Inc. MCP3301 13-bit A/D
converter features full differential inputs and low power
consumption in a small package that is ideal for battery
powered systems and remote data acquisition
applications.
Full Differential Inputs
±1 LSB max DNL
±1 LSB max INL (MCP3301-B)
±2 LSB max INL (MCP3301-C)
Single supply operation: 2.7V to 5.5V
100 ksps sampling rate with 5V supply voltage
50 ksps sampling rate with 2.7V supply voltage
50 nA typical standby current, 1 µA max
450 µA max active current at 5V
Industrial temp range: -40°C to +85 °C
8-pin MSOP, PDIP and SOIC packages
MXDEV™ Evaluation kit available
Applications
• Remote Sensors
• Battery Operated Systems
• Transducer Interface
Package Types
MSOP, PDIP, SOIC
VSS
1
2
3
4
MCP3301
VREF
IN(+)
IN(-)
8
VDD
7
6
5
CLK
DOUT
CS/SHDN
© 2007 Microchip Technology Inc.
Incorporating a successive approximation architecture
with on-board sample and hold circuitry, this 13-bit A/
D converter is specified to have ±1 LSB Differential
Nonlinearity (DNL) and ±1 LSB Integral Nonlinearity
(INL) for B-grade devices and ±2 LSB for C-grade
devices. The industry-standard SPI™ serial interface
enables 13-bit A/D converter capability to be added to
any PIC® microcontroller.
The MCP3301 features a low current design that permits operation with typical standby and active currents
of only 50 nA and 300 µA, respectively. The device
operates over a broad voltage range of 2.7V to 5.5V
and is capable of conversion rates of up to 100 ksps.
The reference voltage can be varied from 400 mV to
5V, yielding input-referred resolution between 98 µV
and 1.22 mV.
The MCP3301 is available in 8-pin PDIP, 150 mil SOIC
and MSOP packages. The full differential inputs of this
device enable a wide variety of signals to be used in
applications such as remote data acquisition, portable
instrumentation and battery operated applications.
DS21700C-page 1
MCP3301
Functional Block Diagram
VDD
VREF
VSS
CDAC
IN+
IN-
Sample
& Hold
Circuits
-
Comparator
13-Bit SAR
+
Control Logic
CS/SHDN
DS21700C-page 2
CLK
Shift
Register
DOUT
© 2007 Microchip Technology Inc.
MCP3301
1.0
ELECTRICAL
CHARACTERISTICS
PIN FUNCTION TABLE
Name
Function
Maximum Ratings*
VREF
Reference Voltage Input
VDD ........................................................................ 7.0V
IN(+)
Positive Analog Input
All inputs and outputs w.r.t. VSS .......-0.3V to VDD +0.3V
IN(-)
Negative Analog Input
VSS
Ground
CS/SHDN
Chip Select / Shutdown Input
DOUT
Serial Data Out
CLK
Serial Clock
VDD
+2.7V to 5.5V Power Supply
Storage temperature .......................... -65°C to +150°C
Ambient temp. with power applied ..... -65°C to +125°C
Maximum Junction Temperature ....................... 150°C
ESD protection on all pins (HBM)......................... > 4 kV
*Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VSS = 0V, and VREF = 5V. Full differential input
configuration (Figure 3-4) with fixed common mode voltage of 2.5V. All parameters apply over temperature with
TAMB = -40°C to +85°C (Note 7). Conversion speed (fSAMPLE) is 100 ksps with fCLK = 17*fSAMPLE
Parameter
Symbol
Min
Typ
Max
Units
Conditions
fSAMPLE
—
—
100
ksps
Note 8
—
—
50
ksps
VDD = VREF = 2.7V, VCM =1.35V
Conversion Rate
Maximum Sampling Frequency
Conversion Time
tCONV
13
CLK
periods
Acquisition Time
tACQ
1.5
CLK
periods
12 data bits + sign
bits
DC Accuracy
Resolution
Integral Nonlinearity
INL
—
—
±0.5
±1
±1
±2
LSB
MCP3301-B
MCP3301-C
Differential Nonlinearity
DNL
—
±0.5
±1
LSB
Monotonic with no missing codes
over temperature
Positive Gain Error
-3
-0.75
+2
LSB
Negative Gain Error
-3
-0.5
+2
LSB
Offset Error
-3
+3
+6
LSB
THD
—
-91
—
dB
Note 3
SINAD
—
78
—
dB
Note 3
Dynamic Performance
Total Harmonic Distortion
Signal to Noise and Distortion
Spurious Free Dynamic Range
SFDR
—
92
—
dB
Note 3
Common-Mode Rejection
CMRR
—
79
—
dB
Note 6
PSR
—
74
—
dB
Note 4
Power Supply Rejection
Note 1:
2:
3:
4:
5:
6:
7:
8:
This specification is established by characterization and not 100% tested.
See characterization graphs that relate converter performance to VREF level.
VIN = 0.1V to 4.9V @ 1 kHz.
VDD = 5VDC ±500 mVP-P @ 1 kHz, see test circuit Figure 3-3.
Maximum clock frequency specification must be met.
VREF = 400 mV, VIN = 0.1V to 4.9V @ 1 kHz
MSOP devices are only specified at 25°C and +85°C.
For slow sample rates, see Section 6.2.1 for limitations on clock frequency.
© 2007 Microchip Technology Inc.
DS21700C-page 3
MCP3301
ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VSS = 0V, and VREF = 5V. Full differential input
configuration (Figure 3-4) with fixed common mode voltage of 2.5V. All parameters apply over temperature with
TAMB = -40°C to +85°C (Note 7). Conversion speed (fSAMPLE) is 100 ksps with fCLK = 17*fSAMPLE
Parameter
Symbol
Min
Typ
Max
Units
Conditions
Reference Input
Voltage Range
0.4
—
VDD
V
Current Drain
—
—
100
0.001
150
3
µA
µA
Note 2
CS = VDD = 5V
Analog Inputs
Full-Scale Input Span
IN(+)-IN(-)
-VREF
—
VREF
V
Absolute Input Voltage
IN(+)
-0.3
—
VDD + 0.3
V
IN(-)
-0.3
—
VDD + 0.3
V
—
0.001
±1
µA
Leakage Current
Switch Resistance
RS
—
1
—
kΩ
See Figure 6-3
Sample Capacitor
CSAMPLE
—
25
—
pF
See Figure 6-3
High Level Input Voltage
VIH
0.7 VDD
—
—
V
Low Level Input Voltage
VIL
—
—
0.3 VDD
V
High Level Output Voltage
VOH
4.1
—
—
V
IOH = -1 mA, VDD = 4.5V
Low Level Output Voltage
VOL
—
—
0.4
V
IOL = 1 mA, VDD = 4.5V
Input Leakage Current
ILI
-10
—
10
µA
VIN = VSS or VDD
Output Leakage Current
ILO
-10
—
10
µA
VOUT = VSS or VDD
CIN, COUT
—
—
10
pF
TAMB = 25°C, f = 1 MHz, Note 1
fCLK
0.085
0.085
—
—
1.7
0.85
MHz
MHz
VDD = 5V, fSAMPLE = 100 ksps
VDD = 2.7V, fSAMPLE = 50 ksps
Clock High Time
tHI
275
—
—
ns
Note 5
Clock Low Time
tLO
275
—
—
ns
Note 5
tSUCS
100
—
—
ns
CLK Fall To Output Data Valid
tDO
—
—
125
200
ns
ns
VDD = 5V, see Figure 3-1
VDD = 2.7V, see Figure 3-1
CLK Fall To Output Enable
tEN
—
—
125
200
ns
ns
VDD = 5V, see Figure 3-1
VDD = 2.7V, see Figure 3-1
CS Rise To Output Disable
tDIS
—
—
100
ns
See test circuits, Figure 3-1
(Note 1)
CS Disable Time
Digital Input/Output
Data Coding Format
Pin Capacitance
Binary Two’s Complement
Timing Specifications
Clock Frequency (Note 8)
CS Fall To First Rising CLK Edge
tCSH
580
—
—
ns
DOUT Rise Time
tR
—
—
100
ns
See test circuits, Figure 3-1; Note 1
DOUT Fall Time
tF
—
—
100
ns
See test circuits, Figure 3-1; Note 1
Note 1:
2:
3:
4:
5:
6:
7:
8:
This specification is established by characterization and not 100% tested.
See characterization graphs that relate converter performance to VREF level.
VIN = 0.1V to 4.9V @ 1 kHz.
VDD = 5VDC ±500 mVP-P @ 1 kHz, see test circuit Figure 3-3.
Maximum clock frequency specification must be met.
VREF = 400 mV, VIN = 0.1V to 4.9V @ 1 kHz
MSOP devices are only specified at 25°C and +85°C.
For slow sample rates, see Section 6.2.1 for limitations on clock frequency.
DS21700C-page 4
© 2007 Microchip Technology Inc.
MCP3301
ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VSS = 0V, and VREF = 5V. Full differential input
configuration (Figure 3-4) with fixed common mode voltage of 2.5V. All parameters apply over temperature with
TAMB = -40°C to +85°C (Note 7). Conversion speed (fSAMPLE) is 100 ksps with fCLK = 17*fSAMPLE
Parameter
Symbol
Min
Typ
Max
Units
Conditions
Power Requirements
Operating Voltage
VDD
2.7
—
5.5
V
Operating Current
IDD
—
—
300
200
450
—
µA
VDD , VREF = 5V, DOUT unloaded
VDD, VREF = 2.7V, DOUT unloaded
Standby Current
IDDS
—
0.05
1
µA
CS = VDD = 5.0V
Temperature Ranges
Specified Temperature Range
TA
-40
—
+85
°C
Operating Temperature Range
TA
-40
—
+85
°C
Storage Temperature Range
TA
-65
—
+150
°C
Thermal Package Resistance
Thermal Resistance, 8L-MSOP
θJA
—
206
—
°C/W
Thermal Resistance, 8L-PDIP
θJA
—
85
—
°C/W
Thermal Resistance, 8L-SOIC
θJA
—
163
—
°C/W
Note 1:
2:
3:
4:
5:
6:
7:
8:
This specification is established by characterization and not 100% tested.
See characterization graphs that relate converter performance to VREF level.
VIN = 0.1V to 4.9V @ 1 kHz.
VDD = 5VDC ±500 mVP-P @ 1 kHz, see test circuit Figure 3-3.
Maximum clock frequency specification must be met.
VREF = 400 mV, VIN = 0.1V to 4.9V @ 1 kHz
MSOP devices are only specified at 25°C and +85°C.
For slow sample rates, see Section 6.2.1 for limitations on clock frequency.
.
tCSH
CS
tSUCS
tHI
tLO
CLK
tEN
tDO
tR
DOUT
FIGURE 1-1:
HI-Z
Null Bit
Sign Bit
tDIS
tF
LSB
HI-Z
Timing Parameters
© 2007 Microchip Technology Inc.
DS21700C-page 5
MCP3301
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V,
fSAMPLE = 100 ksps, fCLK = 17*fSAMPLE, TA = 25°C.
1.0
1
0.8
0.8
VDD=VREF=2.7V
0.6
0.6
0.4
0.4
0.2
0.2
INL(LSB)
INL(LSB)
Positive INL
0.0
-0.2
-0.4
Positive INL
0
-0.2
-0.4
Negative INL
-0.6
-0.6
-0.8
-0.8
Negative INL
-1
-1.0
0
50
100
150
0
200
10
20
FIGURE 2-1:
vs. Sample Rate.
30
40
50
60
70
Sample Rate (ksps)
Sample Rate (ksps)
FIGURE 2-4:
Integral Nonlinearity (INL)
vs. Sample Rate (VDD = 2.7V).
Integral Nonlinearity (INL)
2.0
2.0
VDD = 2.7V
1.5
1.5
1.0
INL (LSB)
INL (LSB)
1.0
Positive INL
0.5
0.0
-0.5
Negative INL
Positive INL
0.5
0.0
-0.5
Negative INL
-1.0
-1.0
-1.5
-1.5
-2.0
-2.0
0
1
2
3
4
0
5
0.5
1
1.5
FIGURE 2-2:
vs. VREF.
Integral Nonlinearity (INL)
2
2.5
3
VREF (V)
VREF (V)
FIGURE 2-5:
Integral Nonlinearity (INL)
vs. VREF (VDD = 2.7V).
1
1
0.8
0.8
0.6
0.6
0.4
INL (LSB)
INL(LSB)
0.4
0.2
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-1
-4096
VDD=VREF=2.7V
FSAMPLE = 50 ksps
-0.8
-3072
-2048
-1024
0
1024
2048
3072
4096
Code
FIGURE 2-3:
Integral Nonlinearity (INL)
vs. Code (Representative Part).
DS21700C-page 6
-1
-4096
-3072
-2048
-1024
0
1024
2048
3072
4096
Code
FIGURE 2-6:
Integral Nonlinearity (INL)
vs. Code (Representative Part, VDD = 2.7V).
© 2007 Microchip Technology Inc.
MCP3301
Note:
Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V,
fSAMPLE = 100 ksps, fCLK = 17*fSAMPLE, TA = 25°C.
1.0
1.0
0.6
0.6
Positive INL
Positive INL
0.4
INL (LSB)
0.4
INL(LSB)
VDD=VREF=2.7V
FSAMPLE = 50 ksps
0.8
0.8
0.2
0.0
-0.2
0.2
0.0
-0.2
-0.4
-0.4
-0.6
-0.6
Negative INL
Negative INL
-0.8
-0.8
-1.0
-1.0
-50
-25
0
25
50
75
100
125
-50
150
0
50
FIGURE 2-7:
vs. Temperature.
150
FIGURE 2-10:
Integral Nonlinearity (INL)
vs. Temperature (VDD = 2.7V).
Integral Nonlinearity (INL)
1.0
1.0
VDD=VREF=2.7V
FSAMPLE = 50 ksps
0.8
0.8
0.6
0.6
0.4
0.4
Positive INL
DNL (LSB)
DNL (LSB)
100
Temperature (°C)
Temperature(°C)
0.2
0.0
-0.2
Negative INL
Positive INL
0.2
0.0
-0.2
Negative INL
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
50
100
150
0
200
10
20
30
40
50
60
70
Sample Rate (ksps)
Sample Rate(ksps)
FIGURE 2-11:
Differential Nonlinearity
(DNL) vs. Sample Rate (VDD = 2.7V).
FIGURE 2-8:
Differential Nonlinearity
(DNL) vs. Sample Rate.
2.0
VDD=2.7V
FSAMPLE = 50 ksps
2.0
1.5
1.5
1.0
DNL (LSB)
DNL (LSB)
1.0
Positive INL
0.5
0.0
Positive DNL
0.5
0.0
Negative DNL
-0.5
-0.5
-1.0
Negative INL
-1.0
-1.5
-1.5
-2.0
0
-2.0
0
1
2
3
4
5
6
0.5
1
1.5
2
2.5
3
VREF (V)
VREF (V)
FIGURE 2-9:
(DNL) vs. VREF.
Differential Nonlinearity
© 2007 Microchip Technology Inc.
FIGURE 2-12:
Differential Nonlinearity
(DNL) vs. VREF (VDD = 2.7V).
DS21700C-page 7
MCP3301
Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V,
fSAMPLE = 100 ksps, fCLK = 17*fSAMPLE, TA = 25°C.
1
1
0.8
0.8
0.6
0.6
0.4
0.4
0.2
DNL (LSB)
DNL(LSB)
Note:
0
-0.2
-0.4
VDD=VREF=2.7V
FSAMPLE = 50 ksps
0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1
-4096
-3072
-2048
-1024
0
1024
2048
3072
-1
-4096
4096
-3072
-2048
-1024
Code
FIGURE 2-13:
Differential Nonlinearity
(DNL) vs. Code (Representative Part).
1024
2048
3072
4096
FIGURE 2-16:
Differential Nonlinearity
(DNL) vs. Code (Representative Part,
VDD = 2.7V).
1.0
1.0
0.8
0.8
0.6
VDD=VREF=2.7V
FSAMPLE = 50 ksps
0.6
0.4
Positive DNL
DNL Error (LSB)
DNL Error (LSB)
0
Code
0.2
0.0
-0.2
Negative DNL
-0.4
0.4
0.0
-0.2
Negative DNL
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
Positive DNL
0.2
-1.0
-50
0
50
100
150
-50
-25
0
25
Temperature (°C)
50
75
100
125
150
Temperature (°C)
FIGURE 2-14:
Differential Nonlinearity
(DNL) vs. Temperature.
FIGURE 2-17:
Differential Nonlinearity
(DNL) vs. Temperature (VDD = 2.7V)
20
5
18
16
3
14
Offset Error (LSB)
Positive Gain Error (LSB)
4
12
VDD=5V
FSAMPLE = 100 ksps
2
VDD=5V
FSAMPLE = 100 ksps
10
1
0
8
6
4
-1
VDD=2.7V
FSAMPLE = 50 ksps
VDD=2.7V
FSAMPLE = 50 ksps
2
-2
0
0
1
2
3
4
5
6
0
1
VREF (V)
FIGURE 2-15:
DS21700C-page 8
Positive Gain Error vs. VREF.
2
3
4
5
6
VREF (V)
FIGURE 2-18:
Offset Error vs. VREF.
© 2007 Microchip Technology Inc.
MCP3301
Note:
Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V,
fSAMPLE = 100 ksps, fCLK = 17*fSAMPLE, TA = 25°C.
0.0
3.5
VDD=VREF=5V
FSAMPLE = 100 ksps
VDD=VREF=5V
FSAMPLE = 100 ksps
3
-0.4
Offset Error (LSB)
Positive Gain Error (LSB)
-0.2
-0.6
VDD=VREF=2.7V
FSAMPLE = 50 ksps
-0.8
-1.0
-1.2
-1.4
2.5
VDD=VREF=2.7V
FSAMPLE = 50 ksps
2
1.5
1
0.5
-1.6
-1.8
-50
0
50
100
0
150
-50
0
50
Temperature (°C)
FIGURE 2-19:
Temperature.
Positive Gain Error vs.
FIGURE 2-22:
Temperature.
150
Offset Error vs.
90
100
VDD=VREF=5V
FSAMPLE = 100 ksps
90
80
80
70
70
60
60
SINAD (dB)
SNR (dB)
100
Temperature (°C)
VDD=VREF=2.7V
FSAMPLE = 50 ksps
50
40
VDD=VREF=2.7V
FSAMPLE = 50 ksps
50
VDD=VREF=5V
FSAMPLE = 100 ksps
40
30
30
20
20
10
10
0
0
1
10
1
100
10
Input Frequency (kHz)
100
Input Frequency (kHz)
FIGURE 2-20:
Signal to Noise Ratio (SNR)
vs. Input Frequency.
FIGURE 2-23:
Signal to Noise and
Distortion (SINAD) vs. Input Frequency.
0
80
-10
70
-20
60
VDD=VREF=2.7V
FSAMPLE = 50 ksps
-40
SINAD (dB)
THD (dB)
-30
VDD=VREF=5V
FSAMPLE = 100 ksps
-50
-60
-70
50
40
30
20
-80
VDD=VREF=5V
FSAMPLE = 100 ksps
VDD=VREF=2.7V
FSAMPLE = 50 ksps
10
-90
0
-100
1
10
100
Input Frequency (kHz)
FIGURE 2-21:
Total Harmonic Distortion
(THD) vs. Input Frequency.
© 2007 Microchip Technology Inc.
-40
-35
-30
-25
-20
-15
-10
-5
0
Input Signal Level (dB)
FIGURE 2-24:
Signal to Noise and
Distortion (SINAD) vs. Input Signal Level.
DS21700C-page 9
MCP3301
Note:
Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V,
fSAMPLE = 100 ksps, fCLK = 17*fSAMPLE, TA = 25°C.
13
13
VDD=VREF=5V
FSAMPLE = 100 ksps
12.8
12
VDD=5V
FSAMPLE = 100 ksps
VDD=2.7V
FSAMPLE = 50 ksps
ENOB (rms)
ENOB (rms)
12.6
11
10
9
12.4
12.2
VDD=VREF=2.7V
FSAMPLE = 50 ksps
12
11.8
11.6
8
11.4
7
11.2
0
1
2
3
4
5
1
6
10
VREF (V)
FIGURE 2-25:
(ENOB) vs. VREF.
Effective Number of Bits
FIGURE 2-28:
Effective Number of Bits
(ENOB) vs. Input Frequency.
100
-30
VDD=VREF=5V
FSAMPLE = 100 ksps
90
-40
70
-45
60
PSR(dB)
SFDR (dB)
0.1 µF Bypass
Capacitor
-35
80
VDD=VREF=2.7V
FSAMPLE = 50 ksps
50
40
-50
-55
-60
30
-65
20
-70
10
-75
-80
0
1
10
1
100
10
FIGURE 2-26:
Spurious Free Dynamic
Range (SFDR) vs. Input Frequency.
5000
10000
15000
20000
25000
Frequency (Hz)
FIGURE 2-27:
Frequency Spectrum of
10 kHz Input (Representative Part).
DS21700C-page 10
1000
10000
FIGURE 2-29:
Power Supply Rejection
(PSR) vs. Ripple Frequency.
Amplitude (dB)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
0
100
Ripple Frequency (kHz)
Input Frequency (kHz)
Amplitude (dB)
100
Input Frequency (kHz)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
0
5000
10000
15000
20000
25000
Frequency (Hz)
FIGURE 2-30:
Frequency Spectrum of
1 kHz Input (Representative Part, VDD = 2.7V).
© 2007 Microchip Technology Inc.
MCP3301
Note:
Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V,
fSAMPLE = 100 ksps, fCLK = 17*fSAMPLE, TA = 25°C.
450
120
400
100
350
80
IREF (µA)
IDD (µA)
300
250
200
60
150
40
100
20
50
0
0
2
2.5
3
3.5
4
4.5
5
5.5
6
2
2.5
3
3.5
VDD (V)
FIGURE 2-31:
FIGURE 2-34:
IDD vs. VDD.
500
90
5
5.5
6
IREF vs. VDD.
VDD=VREF=5V
VDD=VREF=5V
400
80
350
70
300
60
IREF (µA)
IDD (µA)
4.5
100
450
250
200
150
50
40
30
VDD=VREF=2.7V
100
20
50
10
0
VDD=VREF=2.7V
0
0
50
100
150
200
0
50
Sample Rate (ksps)
150
200
IREF vs. Sample Rate.
FIGURE 2-35:
400
80
350
70
VDD=VREF=5V
FSAMPLE = 100 ksps
300
100
Sample Rate (ksps)
IDD vs. Sample Rate.
FIGURE 2-32:
VDD=VREF=5V
FSAMPLE = 100 ksps
60
50
IREF (µA)
250
IDD (µA)
4
VDD (V)
200
VDD=VREF=2.7V
FSAMPLE = 50 ksps
150
40
VDD=VREF=2.7V
FSAMPLE = 50 ksps
30
100
20
50
10
0
0
-50
0
50
100
150
-50
Temperature (°C)
FIGURE 2-33:
IDD vs. Temperature.
© 2007 Microchip Technology Inc.
0
50
100
150
Temperature (°C)
FIGURE 2-36:
IREF vs. Temperature.
DS21700C-page 11
MCP3301
Note:
Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V,
fSAMPLE = 100 ksps, fCLK = 17*fSAMPLE, TA = 25°C.
1
70
0.8
Negative Gain Error (LSB)
80
IDDS (pA)
60
50
40
30
20
10
0.6
VDD=VREF=5V
FSAMPLE = 100 ksps
0.4
0.2
0
-0.2
VDD=VREF=2.7V
FSAMPLE = 50 ksps
-0.4
-0.6
-0.8
0
-1
2
2.5
3
3.5
4
4.5
5
5.5
6
-50
VDD (V)
FIGURE 2-37:
50
100
150
Temperature (°C)
IDDS vs. VDD.
FIGURE 2-40:
Temperature.
100
Negative Gain Error vs.
Common Mode Rejection Ration(dB)
80
10
IDDS (nA)
0
1
0.1
0.01
0.001
79
78
77
76
75
74
73
72
71
70
-50
-25
0
25
50
75
100
1
Temperature (°C)
FIGURE 2-38:
IDDS vs. Temperature.
FIGURE 2-41:
vs. Frequency.
10
100
Input Frequency (kHz)
1000
Common Mode Rejection
8
Negative Gain Error (LSB)
7
6
5
VDD=5V
FSAMPLE = 100 ksps
4
3
2
VDD=2.7V
FSAMPLE = 50 ksps
1
0
-1
0
1
2
3
4
5
6
VREF (V)
FIGURE 2-39:
Negative Gain Error vs.
Reference Voltage.
DS21700C-page 12
© 2007 Microchip Technology Inc.
MCP3301
3.0
TEST CIRCUITS
1 kΩ
1/2 MCP602
+
MCP3301
1.4V
FIGURE 3-1:
3 kΩ
DOUT
-
20 kΩ
Test Point
5VP-P
2.63V
5V ±500 mVp-p
To VDD on DUT
1 kΩ
1 kΩ
CL = 100 pF
Load circuit for TR, TF, TDO
FIGURE 3-3:
Power Supply Sensitivity
Test Circuit (PSRR).
Test Point
MCP3301
VDD
DOUT
3 kΩ
VDD = 5V
VREF = 5V
VDD/2
tDIS Waveform 2
1 µF
tEN Waveform
100 pF
5VP-P
tDIS Waveform 1
VSS
IN(+)
IN(-)
5VP-P
0.1 µF
0.1 µF
VREF VDD
MCP3301
VSS
Voltage Waveforms for tDIS
VIH
CS
DOUT
Waveform 1*
VCM = 2.5V
90%
TDIS
FIGURE 3-4:
Full Differential Test
Configuration Example.
10%
DOUT
Waveform 2†
VREF=2.5V
1 µF
*Waveform 1 is for an output with internal conditions such that the output is high, unless disabled by the output control.
†Waveform 2 is for an output with internal conditions such that the output is low, unless dis-
FIGURE 3-2:
VDD=5V
0.1 µF
0.1 µF
5VP-P
IN(+)
VREF VDD
MCP3301
IN(-)
VSS
Load circuit for TDIS and TEN.
VCM=2.5V
FIGURE 3-5:
Pseudo Differential Test
Configuration Example.
© 2007 Microchip Technology Inc.
DS21700C-page 13
MCP3301
4.0
PIN DESCRIPTIONS
4.5
Chip Select/Shutdown (CS/SHDN)
VREF
Reference Voltage Input
IN(+)
Positive Analog Input
The CS/SHDN pin is used to initiate communication
with the device when pulled low. This pin will end a conversion and put the device in low power standby when
pulled high. The CS/SHDN pin must be pulled high
between conversions and cannot be tied low for multiple conversions. See Figure 7-2 for serial communication protocol.
IN(-)
Negative Analog Input
4.6
VSS
Ground
CS/SHDN
Chip Select / Shutdown Input
DOUT
Serial Data Out
The descriptions of the pins are listed in Table 4-1.
TABLE 4-1:
PIN FUNCTION TABLE.
Name
Function
CLK
Serial Clock
VDD
+2.7V to 5.5V Power Supply
4.1
Voltage Reference (VREF)
Serial Data Output (DOUT)
The SPI serial data output pin is used to shift out the
results of the A/D conversion. Data will always change
on the falling edge of each clock as the conversion
takes place. See Figure 7-2 for serial communication
protocol.
4.7
Serial Clock (CLK)
This input pin provides the reference voltage for the
device, which determines the maximum range of the
analog input signal and the LSB size.
The SPI clock pin is used to initiate a conversion as well
as to clock out each bit of the conversion as it takes
place. See Section 6.2 for constraints on clock speed
and Figure 7-2 for serial communication protocol.
The LSB size is determined by the equation shown
below. As the reference input is reduced, the LSB size
is reduced accordingly.
4.8
EQUATION
LSB Size =
2 x VREF
8192
VDD
The voltage on this pin can range from 2.7 to 5.5V. To
ensure accuracy, a 0.1 µF ceramic bypass capacitor
should be placed as close as possible to the pin. See
Section 6.6 for more information regarding circuit
layout.
When using an external voltage reference device, the
system designer should always refer to the manufacturer’s recommendations for circuit layout. Any instability in the operation of the reference device will have a
direct effect on the accuracy of the ADC conversion
results.
4.2
IN(+)
Positive analog input. This pin has an absolute voltage
range of VSS-0.3V to VDD+0.3V. The full scale input
range is defined as the absolute value of (IN+) - (IN-).
4.3
IN(-)
Negative analog input. This pin has an absolute voltage
range of VSS-0.3V to VDD+0.3V. The full scale input
range is defined as the absolute value of (IN+) - (IN-).
4.4
VSS
Ground connection to internal circuitry. If an analog
ground plane is available, it is recommended that this
device be tied to the analog ground plane in the circuit.
See Section 6.6, “Layout Considerations”, for more
information regarding circuit layout.
DS21700C-page 14
© 2007 Microchip Technology Inc.
MCP3301
5.0
DEFINITION OF TERMS
Bipolar Operation - This applies to either a differential
or single ended input configuration, where both positive
and negative codes are output from the A/D converter.
Full bipolar range includes all 8192 codes. For bipolar
operation on a single ended input signal, the A/D converter must be configured to operate in pseudo differential mode.
Unipolar Operation - This applies to either a single
ended or differential input signal where only one side of
the device transfer is being used. This could be either
the positive or negative side, depending on which input
(IN+ or IN-) is being used for the DC bias. Full unipolar
operation is equivalent to a 12-bit converter.
Full Differential Operation - Applying a full differential
signal to both the IN(+) and IN(-) inputs is referred to as
full differential operation. This configuration is
described in Figure 3-4.
Pseudo-Differential Operation - Applying a single
ended signal to only one of the input channels with a
bipolar output is referred to as pseudo differential operation. To obtain a bipolar output from a single ended
input signal the inverting input of the A/D converter
must be biased above VSS. This operation is described
in Figure 3-5.
Integral Nonlinearity - The maximum deviation from a
straight line passing through the endpoints of the bipolar transfer function is defined as the maximum integral
nonlinearity error. The endpoints of the transfer function are a point 1/2 LSB above the first code transition
(0x1000) and 1/2 LSB below the last code transition
(0x0FFF).
Differential Nonlinearity - The difference between two
measured adjacent code transitions and the 1 LSB
ideal is defined as differential nonlinearity.
Positive Gain Error - This is the deviation between the
last positive code transition (0x0FFF) and the ideal voltage level of VREF-1/2 LSB, after the bipolar offset error
has been adjusted out.
Negative Gain Error - This is the deviation between
the last negative code transition (0X1000) and the ideal
voltage level of -VREF-1/2 LSB, after the bipolar offset
error has been adjusted out.
Offset Error - This is the deviation between the first
positive code transition (0x0001) and the ideal 1/2 LSB
voltage level.
Acquisition Time - The acquisition time is defined as
the time during which the internal sample capacitor is
charging. This occurs for 1.5 clock cycles of the external CLK as defined in Figure 7-2.
Conversion Time - The conversion time occurs immediately after the acquisition time. During this time, successive approximation of the input signal occurs as the
13-bit result is being calculated by the internal circuitry.
This occurs for 13 clock cycles of the external CLK as
defined in Figure 7-2.
© 2007 Microchip Technology Inc.
Signal to Noise Ratio - Signal to Noise Ratio (SNR) is
defined as the ratio of the signal to noise measured at
the output of the converter. The signal is defined as the
rms amplitude of the fundamental frequency of the
input signal. The noise value is dependant on the
device noise as well as the quantization error of the
converter and is directly affected by the number of bits
in the converter. The theoretical signal to noise ratio
limit based on quantization error only for an N-bit converter is defined as:
EQUATION
SNR = ( 6.02N + 1.76 )dB
For a 13-bit converter, the theoretical SNR limit is
80.02 dB.
Total Harmonic Distortion - Total Harmonic Distortion
(THD) is the ratio of the rms sum of the harmonics to
the fundamental, measured at the output of the converter. For the MCP3301, it is defined using the first 9
harmonics, as shown in the following equation:
EQUATION
2
2
2
2
2
V2 + V 3 + V 4 + ..... + V 8 + V9
THD(-dB) = – 20 log -------------------------------------------------------------------------2
V1
Here V1 is the rms amplitude of the fundamental and V2
through V9 are the rms amplitudes of the second
through ninth harmonics.
Signal to Noise plus Distortion (SINAD) - Numerically defined, SINAD is the calculated combination of
SNR and THD. This number represents the dynamic
performance of the converter, including any harmonic
distortion.
EQUATION
SINAD(dB) = 20 log 10
( SNR ⁄ 10 )
+ 10
– ( THD ⁄ 10 )
EffectIve Number of Bits - Effective Number of Bits
(ENOB) states the relative performance of the ADC in
terms of its resolution. This term is directly related to
SINAD by the following equation:
EQUATION
SINAD – 1.76
ENOB ( N ) = ---------------------------------6.02
For SINAD performance of 78 dB, the effective number
of bits is 12.66.
Spurious Free Dynamic Range - Spurious Free
Dynamic Range (SFDR) is the ratio of the rms value of
the fundamental to the next largest component in
ADC’s output spectrum. This is, typically, the first harmonic, but could also be a noise peak.
DS21700C-page 15
MCP3301
6.0
APPLICATIONS INFORMATION
6.2
6.1
Conversion Description
The analog input of the MCP3301 is easily driven either
differentially or single-ended. Any signal that is common to the two input channels will be rejected by the
common mode rejection of the device. During the
charging time of the sample capacitor, a small charging
current will be required. For low source impedances,
this input can be driven directly. For larger source
impedances, a larger acquisition time will be required
due to the RC time constant that includes the source
impedance. For the A/D Converter to meet specification, the charge holding capacitor (CSAMPLE) must be
given enough time to acquire a 13-bit accurate voltage
level during the 1.5 clock cycle acquisition period.
The MCP3301 A/D converter employs a conventional
SAR architecture. With this architecture, the potential
between the IN+ and IN- inputs are simultaneously
sampled and stored with the internal sample circuits for
1.5 clock cycles (tACQ). Following this sample time, the
input hold switches of the converter open and the
device uses the collected charge to produce a serial
13-bit binary two’s complement output code. This conversion process is driven by the external clock and
must include 13 clock cycles, one for each bit. During
this process, the most significant bit (MSB) is output
first. This bit is the sign bit and indicates if the IN+ or INinput is at a higher potential.
CDAC
Hold
CSAMP
+
Comp
-
13-Bit SAR
CSAMP
IN-
Shift
Register
Hold
FIGURE 6-1:
An analog input model is shown in Figure 6-3. This
model is accurate for an analog input, regardless if it is
configured as a single-ended input or the IN+ and INinput in differential mode. In this diagram, it is shown
that the source impedance (RS) adds to the internal
sampling switch (RSS) impedance, directly affecting the
time that is required to charge the capacitor (CSAMPLE).
Consequently, a larger source impedance with no additional acquisition time increases the offset, gain and
integral linearity errors of the conversion. To overcome
this, a slower clock speed can be used to allow for the
longer charging time. Figure 6-2 shows the maximum
clock speed associated with source impedances.
DOUT
Simplified Block Diagram.
1.8
Max Clock Frequency (MHz)
IN+
Driving the Analog Input
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
100
1000
10000
100000
Input Resistance (ohms)
FIGURE 6-2:
Maximum Clock Frequency
vs. Source Resistance (RSS) to maintain ±1 LSB
INL.
DS21700C-page 16
© 2007 Microchip Technology Inc.
MCP3301
VDD
RSS
VT = 0.6V
CHx
CPIN
7 pF
VA
Sampling
Switch
VT = 0.6V
SS
RS = 1 kΩ
CSAMPLE
= DAC capacitance
= 25 pF
ILEAKAGE
±1 nA
VSS
Legend
VA
Rss
CHx
Cpin
Vt
Ileakage
SS
Rs
Csample
FIGURE 6-3:
6.2.1
=
=
=
=
=
=
=
=
=
signal source
source impedance
input channel pad
input pin capacitance
threshold voltage
leakage current at the pin
due to various junctions
sampling switch
sampling switch resistor
sample/hold capacitance
Analog Input Model.
MAINTAINING MINIMUM CLOCK
SPEED
When the MCP3301 initiates, charge is stored on the
sample capacitor. When the sample period is complete,
the device converts one bit for each clock that is
received. It is important for the user to note that a slow
clock rate will allow charge to bleed off the sample
capacitor while the conversion is taking place. For the
MCP330X devices, the recommended minimum clock
speed during the conversion cycle (tCONV) is 85 kHz.
Failure to meet this criteria may introduce linearity
errors into the conversion outside the rated specifications. It should be noted that, during the entire conversion cycle, the A/D converter does not have
requirements for clock speed or duty cycle as long as
all timing specifications are met.
6.3
Biasing Solutions
For pseudo-differential bipolar operation, the biasing
circuit shown in Figure 6-4 shows a single-ended input
AC coupled to the converter. This configuration will give
a digital output range of -4096 to +4095. With the 2.5V
reference, the LSB size is equal to 610 µV.
Although the ADC is not production tested with a 2.5V
reference as shown, linearity will not change more than
0.1 LSB. See Figure 2-2 and 2-9 for DNL and INL
errors versus VREF at VDD = 5V. A trade-off exists
between the high pass corner and the acquisition time.
The value of C will need to be quite large in order to
bring down the high pass corner. The value of R needs
to be 1 kΩ or less, since higher input impedances
© 2007 Microchip Technology Inc.
require additional acquisition time. Using the values in
Figure 6-4, we have a 100 Hz corner frequency. See
Figure 2-12 for the relationship between input impedance and acquisition time.
VDD = 5V
0.1 µF
10 µF C
IN+
VIN
1 kΩ
Ρ
IN-
VOUT
1 µF
MCP3301
VREF
VIN
MCP1525
0.1 µF
FIGURE 6-4:
Pseudo-differential biasing
circuit for bipolar operation.
Using an external operational amplifier on the input
allows for gain and buffers the input signal from the
input to the ADC, allowing for a higher source
impedance. This circuit is shown in Figure 6-5.
DS21700C-page 17
MCP3301
6.4
VDD = 5V
10 kΩ
MCP6022
1 kΩ
VIN
0.1 µF
+
IN+
IN-
1 µF
MCP3301
VREF
1 MΩ
1 µF
VOUT
VIN
MCP1525
Common Mode Input Range
The common mode input range has no restriction and
is equal to the absolute input voltage range: VSS -0.3V
to VDD +0.3V. However, for a given VREF, the common
mode voltage has a limited swing if the entire range of
the A/D converter is to be used. Figure 6-7 and
Figure 6-8 show the relationship between VREF and the
common mode voltage. A smaller VREF allows for wider
flexibility in a common mode voltage. VREF levels down
to 400 mV and exhibits less than 0.1 LSB change in
DNL and INL. See Figure 2-9 and Figure 2-12 for characterization graphs that illustrate this performance
relationship.
0.1 µF
VDD = 5V
FIGURE 6-5:
Adding an amplifier allows
for gain and also buffers the input from any high
impedance sources.
This circuit shows that some headroom will be lost due
to the amplifier output not being able to swing all the
way to the rail. An example would be for an output
swing of 0V to 5V. This limitation can be overcome by
supplying a VREF that is slightly less than the common
mode voltage. Using a 2.048V reference for the A/D
converter, while biasing the input signal at 2.5V solves
the problem. This circuit is shown in Figure 6-6.
VDD = 5V
10 kΩ
VIN
1 MΩ
2.3V
1
0.95V
0
1.0
2.5
VREF (V)
5.0
4.0
VDD = 5V
MCP3301
VREF
VIN
VOUT
MCP1525
4.05V
4
2.048V
0.1 µF
FIGURE 6-6:
Circuit solution to overcome
amplifier output swing limitation.
DS21700C-page 18
2
5
10 kΩ
1 µF
2.8V
3
FIGURE 6-7:
Common Mode Range of
Full Differential input signal versus VREF.
IN+
IN-
1 µF
4.05V
4
-1
0.25
Common Mode Range (V)
MCP606
+
1 kΩ
0.1 µF
Common Mode Range (V)
5
2.8V
3
2
2.3V
1
0.95V
0
-1
0.25
0.5
1.25
2.0
2.5
VREF (V)
FIGURE 6-8:
Common Mode Range
versus VREF for Pseudo Differential Input.
© 2007 Microchip Technology Inc.
MCP3301
6.5
Buffering/Filtering the Analog
Inputs
Inaccurate conversion results may occur if the signal
source for the A/D converter is not a low impedance
source. Buffering the input will solve the impedance
issue. It is also recommended that an analog filter be
used to eliminate any signals that may be aliased back
into the conversion results. Using an op amp to drive
the analog input of the MCP3301 is illustrated in
Figure 6-9. This amplifier provides a low impedance
source for the converter input and low pass filter, which
eliminates unwanted high frequency noise. Values
shown are for a 10 Hz Butterworth Low pass filter.
Low pass (anti-aliasing) filters can be designed using
Microchip’s interactive FilterLab® software. FilterLab
will calculate capacitor and resistor values as well as
determine the number of poles that are required for the
application. For more information on filtering signals,
see AN-699 “Anti-Aliasing Analog Filters for Data
Acquisition Systems”.
VDD
6.6
Layout Considerations
When laying out a printed circuit board for use with
analog components, care should be taken to reduce
noise wherever possible. A bypass capacitor from VDD
to ground should always be used with this device and
should be placed as close as possible to the device pin.
A bypass capacitor value of 0.1 µF is recommended.
Digital and analog traces should be separated as much
as possible on the board with no traces running underneath the device or bypass capacitor. Extra precautions should be taken to keep traces with high
frequency signals (such as clock lines) as far as
possible from analog traces.
Use of an analog ground plane is recommended in
order to keep the ground potential the same for all
devices on the board. Providing VDD connections to
devices in a “star” configuration can also reduce noise
by eliminating current return paths and associated
errors (Figure 6-10). For more information on layout
tips when using the MCP3301 or other ADC devices,
refer to AN-688 “Layout Tips for 12-Bit A/D Converter
Applications”.
10 µF
4.096V
Reference
VDD
Connection
1 µF
0.1 µF
MCP1541
CL
0.1 µF
VREF
IN+
MCP3301
2.2 µF
7.86 kΩ
VIN
14.6 kΩ
1 µF
MCP601
IN-
Device 4
+
-
Device 1
FIGURE 6-9:
The MCP601 Operational
Amplifier is used to implement a 2nd order antialiasing filter for the signal being converted by
the MCP3301.
Device 3
Device 2
FIGURE 6-10:
VDD traces arranged in a
‘Star’ configuration in order to reduce errors
caused by current return paths.
© 2007 Microchip Technology Inc.
DS21700C-page 19
MCP3301
7.0
SERIAL COMMUNICATIONS
7.1
Output Code Format
TABLE 7-1:
The output code format is a binary two’s complement
scheme with a leading sign bit that indicates the sign of
the output. If the IN+ input is higher than the IN- input,
the sign bit will be a zero. If the IN- input is higher, the
sign bit will be a ‘1’.
The diagram shown in Figure 7-1 shows the output
code transfer function. In this diagram, the horizontal
axis is the analog input voltage and the vertical axis is
the output code of the ADC. It shows that when IN+ is
equal to IN-, both the sign bit and the data word are
zero. As IN+ gets larger, with respect to IN-, the sign bit
is a zero and the data word gets larger. The full scale
output code is reached at +4095 when the input [(IN+)
- (IN-)] reaches VREF - 1 LSB. When IN- is larger than
IN+, the two’s complement output codes will be seen
with the sign bit being a one. Some examples of analog
input levels and corresponding output codes are shown
in Table 7-1
BINARY TWO’S
COMPLEMENT OUTPUT
CODE EXAMPLES.
Analog Input Levels
Sign
Bit
Binary Data
Decimal
DATA
Full Scale Positive
(IN+)-(IN-) = VREF-1 LSB
0
1111 1111 1111
+4095
(IN+)-(IN-) = VREF-2 LSB
0
1111 1111 1110
+4094
IN+ = (IN-) +2 LSB
0
0000 0000 0010
+2
IN+ = (IN-) +1 LSB
0
0000 0000 0001
+1
IN+ = IN-
0
0000 0000 0000
0
IN+ = (IN-) - 1 LSB
1
1111 1111 1111
-1
IN+ = (IN-) - 2 LSB
1
1111 1111 1110
-2
(IN+)-(IN-) = VREF-2 LSB
1
0000 0000 0001
-4095
Full Scale Negative
(IN+)-(IN-) = VREF-1 LSB
1
0000 0000 0000
-4096
Output
Code
Positive Full
Scale Output = VREF -1 LSB
0 + 1111 1111 1111 (+4095)
0 + 1111 1111 1110 (+4094)
0 + 0000 0000 0011 (+3)
0 + 0000 0000 0010 (+2)
0 + 0000 0000 0001 (+1)
IN+ > IN-
0 + 0000 0000 0000 (0)
IN+ < IN-
-VREF
1 + 1111 1111 1111 (-1)
1 + 1111 1111 1110 (-2)
Analog Input
Voltage
IN+ - IN-
VREF
1 + 1111 1111 1101 (-3)
1 + 0000 0000 0001 (-4095)
1 + 0000 0000 0000 (-4096)
Negative Full
Scale Output = -VREF
FIGURE 7-1:
DS21700C-page 20
Output Code Transfer Function.
© 2007 Microchip Technology Inc.
MCP3301
7.2
Communicating with the MCP3301
12 remaining data bits, as shown in Figure 7-2. Data is
always output from the device on the falling edge of the
clock. If all 13 data bits have been transmitted and the
device continues to receive clocks while the CS is held
low, the device will output the conversion result LSB
first, as shown in Figure 7-3. If more clocks are provided to the device while CS is still low (after the LSB
first data has been transmitted), the device will clock
out zeros indefinitely.
Communication with the device is completed using a
standard SPI compatible serial interface. Initiating communication with the MCP3301 begins with the CS
going low. If the device was powered up with the CS pin
low, it must be brought high and back low to initiate
communication. The device will begin to sample the
analog input on the first rising edge of CLK after CS
goes low. The sample period will end in the falling edge
of the second clock, at which time the device will output
a low null bit. The next 13 clocks will output the result
of the conversion with the sign bit first, followed by the
tSAMPLE
tCSH
CS
Power
Down
tSUCS
CLK
DOUT
tDATA**
tCONV
tACQ
HI-Z
NULL
BIT
SB B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
HI-Z
B0*
NULL
BIT
SB B11 B10 B9
* After completing the data transfer, if further clocks are applied with CS low, the ADC will output LSB first data,
followed by zeros indefinitely. See Figure 7-2 below.
** tDATA: during this time, the bias current and the comparator power down and the reference input becomes a
high impedance node, leaving the CLK running to clock out the LSB-first data or zeros.
FIGURE 7-2:
Communication with MCP3301 (MSB first Format).
tSAMPLE
tCSH
CS
tSUCS
Power Down
CLK
tACQ
DOUT
tDATA**
tCONV
HI-Z
NULL
BIT SB
B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10 B11
SB*
HI-Z
* After completing the data transfer, if further clocks are applied with CS low, the ADC will output zeros indefinitely.
** tDATA: during this time, the bias current and the comparator power down and the reference input becomes a
high impedance node, leaving the CLK running to clock out the LSB-first data or zeros.
FIGURE 7-3:
Communication with MCP3301 (LSB first Format).
© 2007 Microchip Technology Inc.
DS21700C-page 21
MCP3301
7.3
Using the MCP3301 with
Microcontroller (MCU) SPI Ports
falling edge of the third clock pulse, followed by the
remaining 12 data bits (MSB first). Once the first eight
clocks have been sent to the device, the microcontroller’s receive buffer will contain two unknown bits (for
the first two clocks, the output is high impedance), followed by the null bit, the sign bit and the highest order
four bits of the conversion. After the second eight
clocks have been sent to the device, the MCU receive
register will contain the lowest order 8 data bits. Notice
that, on the falling edge of clock 16, the ADC has begun
to shift out LSB first data.
With most microcontroller SPI ports, it is required to
clock out eight bits at a time. Using a hardware SPI port
with the MCP3301 is very easy because each conversion requires 16 clocks. For example, Figure 7-4 and
Figure 7-5 show how the MCP3301 can be interfaced
to a microcontroller with a standard SPI port. Since the
MCP3301 always clocks data out on the falling edge of
clock, the MCU SPI port must be configured to match
this operation. SPI Mode 0,0 (clock idles low) and SPI
Mode 1,1 (clock idles high) are both compatible with
the MCP3301. Figure 7-4 depicts the operation shown
in SPI Mode 0,0, which requires that the CLK from the
microcontroller idles in the ‘low’ state. As shown in the
diagram, the sign bit is clocked out of the ADC on the
Figure 7-5 shows the same scenario in SPI Mode 1,1,
which requires that the clock idles in the high state. As
with mode 0,0, the ADC outputs data on the falling
edge of the clock and the MCU latches data from the
ADC in on the rising edge of the clock.
CS
MCU latches data from ADC
on rising edges of SCLK
1
CLK
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Data is clocked out of
ADC on falling edges
DOUT
HI-Z
NULL SB B11 B10
BIT
B9
B7
B8
B6
B5
B4
B3
B2
B1
B0 B1
HI-Z
LSB first data begins
to come out
?
?
0
SB
B11 B10 B9
B8
B7
Data stored into MCU receive register
after transmission of first 8 bits
B6
B5
B4
B3
B2
B1
B0
X = Don’t Care Bits
? = Unknown Bits
Data stored into MCU receive register
after transmission of second 8 bits
FIGURE 7-4:
SPI Communication with the MCP3301 using 8-bit segments
(Mode 0,0: SCLK idles low).
CS
MCU latches data from ADC
on rising edges of SCLK
1
CLK
2
3
4
5
6
8
7
9
10
11
12
13
14
15
16
Data is clocked out of
ADC on falling edges
DOUT
HI-Z
NULL SB
BIT
B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
HI-Z
LSB first data begins
to come out
?
?
0
SB
B11 B10 B9
B8
Data stored into MCU receive register
after transmission of first 8 bits
B7
B6
B5
B4
B3
B2
B1
B0
Data stored into MCU receive register
after transmission of second 8 bits
X = Don’t Care Bits
? = Unknown Bits
FIGURE 7-5:
SPI Communication with the MCP3301 using 8-bit segments
(Mode 1,1: SCLK idles high).
DS21700C-page 22
© 2007 Microchip Technology Inc.
MCP3301
8.0
PACKAGING INFORMATION
8.1
Package Marking Information
Example:
8-Lead MSOP
3301C e3
XXXXXX
YWWNNN
725NNN
8-Lead PDIP (300 mil)
3301-B e3
I/PNNN
0725
XXXXXXXX
XXXXXNNN
YYWW
8-Lead SOIC (150 mil)
XXXXXXXX
XXXXYYWW
NNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Example:
Example:
3301-B
I/SN e3 0723
NNN
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3)
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available characters
for customer-specific information.
© 2007 Microchip Technology Inc.
DS21700C-page 23
MCP3301
8-Lead Plastic Micro Small Outline Package (MS) [MSOP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
1
2
e
b
A2
A
c
φ
L
L1
A1
Units
Dimension Limits
Number of Pins
MILLIMETERS
MIN
N
NOM
MAX
8
Pitch
e
Overall Height
A
–
0.65 BSC
–
Molded Package Thickness
A2
0.75
0.85
0.95
Standoff
A1
0.00
–
0.15
Overall Width
E
Molded Package Width
E1
3.00 BSC
Overall Length
D
3.00 BSC
Foot Length
L
Footprint
L1
1.10
4.90 BSC
0.40
0.60
0.80
0.95 REF
Foot Angle
φ
0°
–
8°
Lead Thickness
c
0.08
–
0.23
Lead Width
b
0.22
–
0.40
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-111B
DS21700C-page 24
© 2007 Microchip Technology Inc.
MCP3301
8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
N
NOTE 1
E1
1
3
2
D
E
A2
A
L
A1
c
e
eB
b1
b
Units
Dimension Limits
Number of Pins
INCHES
MIN
N
NOM
MAX
8
Pitch
e
Top to Seating Plane
A
–
–
.210
Molded Package Thickness
A2
.115
.130
.195
Base to Seating Plane
A1
.015
–
–
Shoulder to Shoulder Width
E
.290
.310
.325
Molded Package Width
E1
.240
.250
.280
Overall Length
D
.348
.365
.400
Tip to Seating Plane
L
.115
.130
.150
Lead Thickness
c
.008
.010
.015
b1
.040
.060
.070
b
.014
.018
.022
eB
–
–
Upper Lead Width
Lower Lead Width
Overall Row Spacing §
.100 BSC
.430
Notes:
1. Pin 1 visual index feature may vary, but must be located with the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-018B
© 2007 Microchip Technology Inc.
DS21700C-page 25
MCP3301
8-Lead Plastic Small Outline (SN) – Narrow, 3.90 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
e
N
E
E1
NOTE 1
1
2
3
α
h
b
h
A2
A
c
φ
L
A1
L1
Units
Dimension Limits
Number of Pins
β
MILLMETERS
MIN
N
NOM
MAX
8
Pitch
e
Overall Height
A
–
1.27 BSC
–
Molded Package Thickness
A2
1.25
–
–
Standoff §
A1
0.10
–
0.25
Overall Width
E
Molded Package Width
E1
3.90 BSC
Overall Length
D
4.90 BSC
1.75
6.00 BSC
Chamfer (optional)
h
0.25
–
0.50
Foot Length
L
0.40
–
1.27
Footprint
L1
1.04 REF
Foot Angle
φ
0°
–
8°
Lead Thickness
c
0.17
–
0.25
Lead Width
b
0.31
–
0.51
Mold Draft Angle Top
α
5°
–
15°
Mold Draft Angle Bottom
β
5°
–
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-057B
DS21700C-page 26
© 2007 Microchip Technology Inc.
MCP3301
APPENDIX A:
REVISION HISTORY
Revision C (January 2007)
This revision includes updates to the packaging
diagrams.
© 2007 Microchip Technology Inc.
DS21700C-page 27
MCP3301
NOTES:
DS21700C-page 28
© 2007 Microchip Technology Inc.
MCP3301
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X
X
/XX
Device
Grade
Temperature
Range
Package
Device:
MCP3301: 13-Bit Serial A/D Converter
MCP3301T: 13-Bit Serial A/D Converter (Tape and Reel)
Grade:
B
C
= ±1 LSB INL
= ±2 LSB INL
Temperature Range:
I
= -40°C to +85°C
Package:
MS = Plastic MSOP, 8-lead
P
= Plastic DIP (300 mil Body), 8-lead
SN = Plastic SOIC (150 mil Body), 8-lead
© 2007 Microchip Technology Inc.
Examples:
a)
MCP3301-BI/P: ±1 LSB INL, Industrial
Temperature, PDIP package
b)
MCP3301-BI/SN: ±1 LSB INL, Industrial
Temperature, SOIC package
c)
MCP3301-CI/MS: ±2 LSB INL, Industrial
Temperature, MSOP package
DS21700C-page29
MCP3301
NOTES:
DS21700C-page 30
© 2007 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active
Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC®
MCUs and dsPIC DSCs, KEELOQ® code hopping devices, Serial
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.
© 2007 Microchip Technology Inc.
DS21700C-page 31
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Habour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-4182-8400
Fax: 91-80-4182-8422
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
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Tel: 630-285-0071
Fax: 630-285-0075
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
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Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
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Tel: 765-864-8360
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Tel: 949-462-9523
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Santa Clara, CA
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Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Korea - Gumi
Tel: 82-54-473-4301
Fax: 82-54-473-4302
China - Fuzhou
Tel: 86-591-8750-3506
Fax: 86-591-8750-3521
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Penang
Tel: 60-4-646-8870
Fax: 60-4-646-5086
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
China - Shunde
Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xian
Tel: 86-29-8833-7250
Fax: 86-29-8833-7256
12/08/06
DS21700C-page 32
© 2007 Microchip Technology Inc.