Fairchild DM74ALS175M Hex/quad d-type flip-flops with clear Datasheet

DM74ALS174, DM74ALS175
Hex/Quad D-Type Flip-Flops with Clear
tm
Features
General Description
■ Advanced oxide-isolated ion-implanted Schottky
These positive-edge-triggered flip-flops utilize TTL
circuitry to implement D-type flip-flop logic. Both have an
asynchronous clear input, and the quad (DM74ALS175)
version features complementary outputs from each
flip-flop.
TTL process
■ Pin and functional compatible with LS family
counterpart
■ Typical clock frequency maximum is 80MHz
■ Switching performance guaranteed over full
temperature and VCC supply range
Information at the D inputs meeting the setup time
requirements is transferred to the Q outputs on the
positive-going edge of the clock pulse. Clock triggering
occurs at a particular voltage level and is not directly
related to the transition time of the positive-going pulse.
When the clock input is at either the HIGH or LOW level,
the D input signal has no effect at the output.
Ordering Information
Ordering
Code
Package
Number
Package Description
DM74ALS174M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
DM74ALS174SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74ALS175M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
DM74ALS175SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74ALS175N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering number.
©1986 Fairchild Semiconductor Corporation
DM74ALS174, DM74ALS175 Rev. 1.2
www.fairchildsemi.com
DM74ALS174, DM74ALS175 Hex/Quad D-Type Flip-Flops with Clear
May 2007
DM74ALS174, DM74ALS175 Hex/Quad D-Type Flip-Flops with Clear
Connection Diagrams
DM74ALS174
DM74ALS175
©1986 Fairchild Semiconductor Corporation
DM74ALS174, DM74ALS175 Rev. 1.2
www.fairchildsemi.com
2
DM74ALS174, DM74ALS175 Hex/Quad D-Type Flip-Flops with Clear
Function Table
Inputs
Outputs
Clear
Clock
D
Q
Q(1)
L
X
X
L
H
H
↑
H
H
L
H
↑
L
L
H
H
L
X
Q0
Q0
H = HIGH Level (steady state)
L = LOW Level (steady state)
X = Don't Care
↑ = Transition from LOW-to-HIGH Level
Q0 = the level of Q before the indicated steady-state input conditions were established.
Note:
1. Applies to DM74ALS175 only.
Logic Diagrams
DM74ALS174
©1986 Fairchild Semiconductor Corporation
DM74ALS174, DM74ALS175 Rev. 1.2
DM74ALS175
www.fairchildsemi.com
3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VCC
Parameter
Rating
Supply Voltage
7V
VI
Input Voltage
7V
TA
Operating Free Air Temperature Range
TSTG
Storage Temperature Range
θJA
Typical Thermal Resistance
0°C to +70°C
–65°C to +150°C
N Package
77.9°C/W
M Package
107.3°C/W
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
VCC
Supply Voltage
VIH
HIGH Level Input Voltage
Min.
Nom.
Max.
Units
4.5
5
5.5
V
2
V
VIL
LOW Level Input Voltage
0.8
V
IOH
HIGH Level Output Current
–0.4
mA
IOL
LOW Level Output Current
8
mA
tW
Pulse Width
Clock HIGH or LOW
10
Clear LOW
10
Data Input
10↑
ns
tSETUP
Setup Time(2)
tHOLD
Data Hold Time(2)
0↑
fCLOCK
Clock Frequency
0
50
MHz
Free Air Operating Temperature
0
70
°C
6↑
Clear, Inactive State
TA
ns
ns
Note:
2. The symbol ↑ indicates that the rising edge of the clock is used as reference.
©1986 Fairchild Semiconductor Corporation
DM74ALS174, DM74ALS175 Rev. 1.2
www.fairchildsemi.com
4
DM74ALS174, DM74ALS175 Hex/Quad D-Type Flip-Flops with Clear
Absolute Maximum Ratings
Over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25°C.
Symbol
VIK
Parameter
Input Clamp Voltage
Conditions
Min.
Typ.
Max.
Units
–1.5
V
VCC = 4.5V, IIN = –18 mA
VOH
HIGH Level Output Voltage
IOH = –400µA, VCC = 4.5V to 5.5V
VOL
LOW Level Output Voltage
VCC = 4.5V, IOL = 8mA
II
Input Current at Max. Input
Voltage
IIH
VCC – 2
VCC – 1.6
V
0.35
0.5
V
VCC = 5.5V, VIN = 7V
0.1
mA
HIGH Level Input Current
VCC = 5.5V, VIH = 2.7V
20
µA
IIL
LOW Level Input Current
VCC = 5.5V, VIN = 0.4V
–0.1
mA
IO
Output Drive Current
VCC = 5.5V, VO = 2.25V
–112
mA
ICC
Supply Current
VCC = 5.5V,
Clock = 4.5V,
Clear = GND,
D Input = GND
mA
–30
DM74ALS174
11
19
DM74ALS175
8
14
Switching Characteristics
Over recommended operating free air temperature range.
Symbol
Parameter
fMAX
Maximum Clock Frequency
tPLH
Propagation Delay Time, LOW-to-HIGH Level
Output From Clear (175 Only)
tPHL
Conditions
Min.
RL = 500Ω,
CL = 50pF,
VCC = 4.5V to 5.5V
50
Max.
Units
MHz
5
18
ns
Propagation Delay Time, HIGH-to-LOW Level
Output From Clear
8
23
ns
tPLH
Propagation Delay Time, LOW-to-HIGH Level
Output From Clock
3
15
ns
tPHL
Propagation Delay Time, HIGH-to-LOW Level
Output From Clock
5
17
ns
©1986 Fairchild Semiconductor Corporation
DM74ALS174, DM74ALS175 Rev. 1.2
www.fairchildsemi.com
5
DM74ALS174, DM74ALS175 Hex/Quad D-Type Flip-Flops with Clear
Electrical Characteristics
DM74ALS174, DM74ALS175 Hex/Quad D-Type Flip-Flops with Clear
Physical Dimensions
Dimensions are in millimeters unless otherwise noted.
Figure 1. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
©1986 Fairchild Semiconductor Corporation
DM74ALS174, DM74ALS175 Rev. 1.2
www.fairchildsemi.com
6
DM74ALS174, DM74ALS175 Hex/Quad D-Type Flip-Flops with Clear
Physical Dimensions (Continued)
Dimensions are in millimeters unless otherwise noted.
Figure 2. 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
©1986 Fairchild Semiconductor Corporation
DM74ALS174, DM74ALS175 Rev. 1.2
www.fairchildsemi.com
7
DM74ALS174, DM74ALS175 Hex/Quad D-Type Flip-Flops with Clear
Physical Dimensions (Continued)
Dimensions are in inches (millimeters) unless otherwise noted.
Figure 3. 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N16E
©1986 Fairchild Semiconductor Corporation
DM74ALS174, DM74ALS175 Rev. 1.2
www.fairchildsemi.com
8
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In Design
This datasheet contains the design specifications for product development.
Specifications may change in any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to make
changes at any time without notice to improve design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild Semiconductor reserves
the right to make changes at any time without notice to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product that has been
discontinued by Fairchild semiconductor. The datasheet is printed for
reference information only.
Rev. I28
©1986 Fairchild Semiconductor Corporation
DM74ALS174, DM74ALS175 Rev. 1.2
www.fairchildsemi.com
9
DM74ALS174, DM74ALS175 Hex/Quad D-Type Flip-Flops with Clear
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