LINER LTC4264 High power pd interface controller with 750ma current limit Datasheet

LTC4264
High Power PD Interface
Controller with 750mA
Current Limit
DESCRIPTION
FEATURES
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Complete High Power PD Interface Controller
IEEE 802.3af® Compliant
Onboard 750mA Power MOSFET
Complementary Power Good Outputs
Flexible Auxiliary Power Options
Precision Dual Current Limit with Disable
Programmable Classification Current to 75mA
Onboard 25k Signature Resistor with Disable
Undervoltage Lockout
Complete Thermal Overload Protection
Available in Low Profile (4mm × 3mm) DFN Package
APPLICATIONS
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802.11n Access Points
High Power VoIP Video Phones
RFID Reader Systems
PTZ Security Cameras and Surveillance Equipment
The LTC®4264 is an integrated Powered Device (PD) interface controller intended for IEEE 802.3af Power over
Ethernet (PoE) and high power PoE applications up to 35W.
By including a precision dual current limit, the LTC4264
keeps inrush below the IEEE802.3af current limit levels
to ensure interoperability success while allowing for high
power PD operation. The LTC4264 includes a field-proven
power MOSFET delivering up to 750mA to the PD load while
maintaining compliance with the IEEE802.3af standard.
Complementary power good outputs allow the LTC4264 to
interface directly with a host of DC/DC converter products.
The LTC4264 provides a complete signature and power
interface solution for PD designs by incorporating the 25k
signature resistor, classification circuitry, input current
limit, undervoltage lockout, thermal overload protection,
signature disable and power good signaling.
The LTC4264 PD interface controller can be used along with
a variety of Linear Technology DC/DC converter products
to provide a complete, cost effective power solution for
high power PD applications.
The LTC4264 is available in the space-saving low profile
(4mm × 3mm) DFN package.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
Turn On vs Time
VIN
50V/DIV
–54V FROM
DATA PAIR
~
+
DF1501S
~
LTC4264
SHDN
GND
0.1µF
–
SMAJ58A
+
RCLASS
RCLASS PWRGD
~
–54V FROM
SPARE PAIR
PWRGD
DF1501S
ILIM_EN
~
VIN
–
VOUT
5µF
MIN
+
VIN
SWITCHING
POWER
SUPPLY
RUN
RTN
CLOAD = 100µF
VOUT
50V/DIV
+
3.3V
TO LOGIC
4264 TA01a
PWRGD – VOUT
50V/DIV
–
IIN
200mA/DIV
TIME (5ms/DIV)
4264 TA01b
4264f
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LTC4264
ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
(Notes 1, 2)
TOP VIEW
VIN Voltage ................................................. 0.3V to –90V
VOUT Voltage ......... VIN + 90V (and ≤ GND) to VIN – 0.3V
SHDN Voltage ............................ VIN + 90V to VIN – 0.3V
RCLASS, ILIM_EN Voltage ............... VIN + 7V to VIN – 0.3V
PWRGD Voltage (Note 3)
Low Impedance Source ....VOUT + 11V to VOUT – 0.3V
Current Fed ..........................................................5mA
PWRGD Voltage ......................... VIN + 80V to VIN – 0.3V
PWRGD Current .....................................................10mA
RCLASS Current.....................................................100mA
Operating Ambient Temperature Range
LTC4264C ................................................ 0°C to 70°C
LTC4264I ............................................. –40°C to 85°C
Junction Temperature ........................................... 150°C
Storage Temperature Range................... –65°C to 150°C
SHDN
1
12 GND
NC
2
11 NC
10 PWRGD
RCLASS
3
ILIM_EN
4
9
PWRGD
VIN
5
8
VOUT
VIN
6
7
VOUT
13
DE12 PACKAGE
12-LEAD (4mm × 3mm) PLASTIC DFN
TJMAX = 150°C, θJA = 43°C/W, θJC = 4.3°C/W
EXPOSED PAD (PIN 13) MUST BE SOLDERED TO
AN ELECTRICALLY ISOLATED HEAT SINK
ORDER PART NUMBER
DE PART MARKING*
LTC4264CDE
LTC4264IDE
4264
4264
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VIN
Supply Voltage
IEEE 802.3af System
Signature Range
Classification Range
UVLO Turn-On Voltage
UVLO Turn-Off Voltage
Voltage with Respect to GND Pin
(Notes 5, 6, 7, 8)
–1.5
–12.5
–37.7
–29.8
–38.9
–30.6
–57
–10.1
–21
–40.2
–31.5
V
V
V
V
V
IIN_ON
IC Supply Current when On
VIN = –54V
●
IIN_CLASS
IC Supply Current During Classification
VIN = –17.5V (Note 9)
●
3
mA
0.55
0.62
0.70
mA
ΔICLASS
Current Accuracy During Classification
10mA < ICLASS < 75mA, –12.5V ≤ VIN ≤ –21V
(Notes 10,11)
●
±3.5
%
tCLASSRDY
Classification Stability Time
VIN Stepped 0V to –17.5V, IIN_CLASS ≤3.5% of
Ideal, 10mA < ICLASS < 75mA (Notes 10, 11)
●
1
ms
RSIGNATURE
Signature Resistance
–1.5V ≤ VIN ≤ –10.1V, IEEE 802.3af 2-Point
Measurement, SHDN Tied to VIN (Notes 6, 7)
●
26.00
kΩ
RINVALID
Invalid Signature Resistance
–1.5V ≤ VIN ≤ –10.1V, IEEE 802.3af 2-Point
Measurement, SHDN Tied to GND (Notes 6, 7)
●
11.8
kΩ
VIH_SHDN
SHDN High Level Input Voltage
With Respect to VIN, High Level = Shutdown
(Note 12)
●
VIL_SHDN
SHDN Low Level Input Voltage
With Respect to VIN
●
RINPUT_SHDN
SHDN Input Resistance
With Respect to VIN
●
100
kΩ
VIH_ILIM
ILIM_EN High Level Input Voltage
With Repect to VIN, High Level Enables Current
Limit (Note 13)
●
4
V
●
●
●
●
●
23.25
10
3
57
V
0.45
V
4264f
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LTC4264
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
VIL_ILIM
ILIM_EN Low Level Input Voltage
With Respect to VIN (Note 13)
●
1
V
VPWRGD_OUT
Active Low Power Good
Output Low Voltage
IPWRGD = 1mA, VIN = –54V, ⎯P⎯W⎯R⎯G⎯D
Referenced to VIN
●
0.5
V
IPWRGD_LEAK
Active Low Power Good Leakage
VIN = 0V, VPWRGD = 57V
●
1
µA
VPWRGD_OUT
Active High Power Good
Output Low Voltage
IPWRGD = 0.5mA, VIN = –52V, VOUT = –4V,
PWRGD Referenced to VOUT (Note 14)
●
0.35
V
VPWRGD_VCLAMP Active High Power Good
Voltage-Limiting Clamp
IPWRGD = 2mA, VOUT = 0V,
With Respect to VOUT (Note 3)
●
16.5
V
IPWRGD_LEAK
Active High Power Good Leakage
VPWRGD = 11V, with Respect to VOUT,
VOUT = VIN = –54V
●
1
µA
RON
On Resistance
I = 700mA, VIN = –54V
Measured from VIN to VOUT (Note 11)
●
0.6
0.8
Ω
Ω
IOUT_LEAK
VOUT Leakage
VIN = –57V, GND = SHDN = VOUT = 0V
●
1
µA
ILIMIT_HIGH
Input Current Limit During Normal
Operation
VIN = –54V, VOUT = –53V, ILIM_EN Floating
(Notes 15, 16)
●
700
750
800
mA
ILIMIT_LOW
Inrush Current Limit
VIN = –54V, VOUT = –53V (Notes 15, 16)
●
250
300
350
mA
ILIMIT_DISA
Safeguard Current Limit when
ILIMIT_HIGH Disabled
VIN = –54V, VOUT = –52.5V, ILIM_EN Tied to VIN
(Notes 15, 16, 17)
1.20
1.45
1.65
A
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to any Absolute Maximum
Rating condition for extended periods may affect device reliability and
lifetime.
Note 2: All voltages are with respect to GND pin unless otherwise noted.
Note 3: Active high PWRGD pin internal clamp circuit self-regulates to 14V
with respect to VOUT.
Note 4: The LTC4264 operates with a negative supply voltage in the range of
–1.5V to –57V. To avoid confusion, voltages in this data sheet are referred to
in terms of absolute magnitude.
Note 5: In IEEE 802.3af systems, the maximum voltage at the PD jack is
defined to be –57V. See Applications Information.
Note 6: The LTC4264 is designed to work with two polarity protection
diodes in series with the input. Parameter ranges specified in the Electrical
Characteristics are with respect to LTC4264 pins and are designed to meet
IEEE 802.3af specifications when the drop from the two diodes is included.
See Applications Information.
Note 7: Signature resistance is measured via the two-point ΔV/ΔI method
as defined by IEEE 802.3af. The LTC4264 signature resistance is offset
from 25k to account for diode resistance. With two series diodes, the total
PD resistance will be between 23.75k and 26.25k and meet IEEE 802.3af
specifications. The minimum probe voltages measured at the LTC4264 pins
are – 1.5V and – 2.5V. The maximum probe voltages are –9.1V and –10.1V.
Note 8: The LTC4264 includes hysteresis in the UVLO voltages to preclude
any start-up oscillation. Per IEEE 802.3af requirements, the LTC4264 will
power up from a voltage source with 20Ω series resistance on the first trial.
Note 9: IIN_CLASS does not include classification current programmed at
Pin 3. Total supply current in classification mode will be IIN_CLASS + ICLASS
(see Note 10).
Note 10: ICLASS is the measured current flowing through RCLASS. ΔICLASS
accuracy is with respect to the ideal current defined as ICLASS = 1.237/RCLASS.
MIN
12.0
TYP
14.0
0.5
MAX
UNITS
tCLASSRDY is the time for ICLASS to settle to within ±3.5% of ideal. The current
accuracy specification does not include variations in RCLASS resistance. The
total classification current for a PD also includes the IC quiescent current
(IIN_CLASS). See Applications Information.
Note 11: This parameter is assured by design and wafer level testing.
Note 12: To disable the 25k signature, tie SHDN to GND (±0.1V) or hold SHDN
pin high with respect to VIN. See Applications Information.
Note13: ILIM_EN pin is pulled high internally and for normal operation should
be left floating. To disable high level current limit, tie ILIM_EN to VIN. See
Applications Information.
Note 14: Active high power good is referenced to VOUT and is valid for
GND-VOUT ≥ 4V. Measured at –52V due to test hardware limitations.
Note 15: The LTC4264 includes a dual current limit. At turn-on, before C1 is
charged, the LTC4264 current level is set to ILIMIT_LOW. After C1 is charged
and with ILIM_EN floating, the LTC4264 switches to ILIMIT_HIGH. With ILIM_EN
pin tied low, the LTC4264 switches to ILIMIT_DISA. The LTC4264 stays in
ILIMIT_HIGH or ILIMIT_DISA until the input voltage drops below the UVLO turnoff threshold or a thermal overload occurs.
Note 16: The LTC4264 features thermal overload protection. In the event of
an overtemperature condition, the LTC4264 will turn off the power MOSFET,
disable the classification load current and present an invalid power good
signal. Once the LTC4264 cools below the overtemperature limit, the
LTC4264 current limit switches to ILIMIT_LOW and normal operation resumes.
Thermal overload protection is intended to protect the device during
momentary fault conditions and continuous operation in thermal overload
should be avoided as it may impair device reliability.
Note 17: ILIMIT_DISA is a safeguard current limit that is activated when the
normal input current limit (ILIMIT_HIGH) is defeated using the ILIM_EN pin.
Currents at or near ILIMIT_DISA will cause significant package heating and may
require a reduced maximum ambient operating temperature in order to avoid
tripping the thermal overload protection. See Applications Information.
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LTC4264
TYPICAL PERFORMANCE CHARACTERISTICS
Input Current vs Input Voltage
25k Detection Range
Input Current vs Input Voltage
100
0.5
TA = 25°C
TA = 25°C
0.2
CLASS 5*
60
CLASS 4
40
CLASS 3
CLASS 2
CLASS 1
20
0.1
INPUT CURRENT (mA)
INPUT CURRENT (mA)
0.3
CLASS 1 OPERATION
11.5
80
0.4
INPUT CURRENT (mA)
Input Current vs Input Voltage
12.0
11.0
85°C
10.5
–40°C
10.0
9.5
CLASS 0
0
0
0
–2
–4
–6
INPUT VOLTAGE (V)
–10
–8
4264 G01
– 20
–30
–40
INPUT VOLTAGE (V)
*OPTIONAL CLASS CURRENT
0
–20
–18
–16
INPUT VOLTAGE (V)
–22
On Resistance vs Temperature
1.0
RESISTANCE = ∆V = V2 – V1
∆I I2 – I1
27 DIODES: HD01
TA = 25°C
IEEE UPPER LIMIT
TA = 25°C
INPUT
VOLTAGE
10V/DIV
0.8
RESISTANCE (Ω)
26
LTC4264 + 2 DIODES
CLASS
CURRENT
20mA/DIV
24
LTC4264 ONLY
–14
4264 G03
Class Operation vs Time
28
25
9.0
–12
–60
4264 G02
Signature Resistance
vs Input Voltage
SIGNATURE RESISTANCE (kΩ)
–50
–10
IEEE LOWER LIMIT
0.6
0.4
0.2
23
22
V1: –1
V2: –2
–3
–4
TIME (10µs/DIV)
–9
–10
–7
–5
–8
–6
INPUT VOLTAGE (V)
0
–50
4264 G05
0
25
50
75
–25
JUNCTION TEMPERATURE (°C)
4264 G06
4264 G04
Active Low PWRGD
Output Low Voltage vs Current
Active High PWRGD
Output Low Voltage vs Current
1.0
4
Current Limit vs Input Voltage
800
TA = 25°C
GND – VOUT = 4V
TA = 25°C
–40°C
85°C
HIGH CURRENT MODE
1
CURRENT LIMIT (mA)
PWRGD (V)
VPWRGD_OUT – VIN (V)
0.8
3
2
100
0.6
0.4
600
400
–40°C
0.2
LOW CURRENT MODE
85°C
0
0
0
2
6
4
CURRENT (mA)
8
10
4264 G07
0
0.5
1
IIN (mA)
1.5
2
4264 G08
200
–40
–55
–45
–50
INPUT VOLTAGE (V)
–60
4264 G09
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LTC4264
PIN FUNCTIONS
SHDN (Pin 1): Shutdown Input. Used to command the
LTC4264 to present an invalid signature. Connecting
SHDN to GND lowers the signature resistance to an invalid
value and disables other LTC4264 operations. If unused,
tie SHDN to VIN.
NC (Pin 2): No Internal Connection.
RCLASS (Pin 3): Class Select Input. Used to set the current
the LTC4264 maintains during classification. Connect a
resistor between RCLASS and VIN. (See Table 2.)
ILIM_EN (Pin 4): Input Current Limit Enable. Used to control
LTC4264 current limit behavior during powered operation.
For normal operation, float ILIM_EN to enable ILIMIT_HIGH
current. Tie ILIM_EN to VIN to disable input current limit.
Note that the inrush current limit does not change with
ILIM_EN selection. See Applications Information.
VIN (Pins 5, 6): Power Input. Tie to the PD input through
the diode bridge. Pins 5 and 6 must be electrically tied
together.
VOUT (Pins 7, 8): Power Output. Supplies power to the
PD load through the internal power MOSFET. VOUT is high
impedance until the input voltage rises above the UVLO
turn-on threshold. The output is then connected to VIN
through a current-limited internal MOSFET switch. Pins 7
and 8 must be electrically tied together.
PWRGD (Pin 9): Active High Power Good Output, Open
Collector. Signals to the DC/DC converter that the LTC4264
MOSFET is on and that the converter can start operation.
High impedance indicates power is good. PWRGD is referenced to VOUT and is low impedance during inrush and
in the event of a thermal overload. PWRGD is clamped
14V above VOUT.
PWRGD (Pin 10): Active Low Power Good Output, OpenDrain. Signals to the DC/DC converter that the LTC4264
MOSFET is on and that the converter can start operation.
Low impedance indicates power is good. PWRGD is
referenced to VIN and is high impedance during detection, classification and in the event of a thermal overload.
PWRGD has no internal clamps.
NC (Pin11): No Internal Connection.
GND (Pin 12): Ground. Tie to system ground and power
return through the input diode bridge.
Exposed Pad (Pin 13): Must be soldered to electrically
isolated heat sink.
4264f
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LTC4264
BLOCK DIAGRAM
CLASSIFICATION
CURRENT LOAD
SHDN 1
1.237V
+
12 GND
16k
NC 2
25k
–
RCLASS 3
11 NC
10 PWRGD
ILIM_EN 4
CONTROL
CIRCUITS
1400mA
750mA
300mA
VIN 5
VIN 6
INPUT
CURRENT
LIMIT
+
–
9
PWRGD
8
VOUT
7
VOUT
14V
BOLD LINE INDICATES
HIGH CURRENT PATH
4264 BD
4264f
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LTC4264
APPLICATIONS INFORMATION
OVERVIEW
Power over Ethernet (PoE) continues to gain popularity as
more products are taking advantage of having DC power
and high speed data available from a single RJ45 connector. As PoE is becoming established in the marketplace,
Powered Device (PD) equipment vendors are running into
the 12.95W power limit established by the IEEE 802.3af
standard. To solve this problem and expand the application
of PoE, the LTC4264 breaks the power barrier by allowing
custom PoE applications to deliver up to 35W for powerhungry PoE applications such as dual band and 802.11n
access points, RFID readers and PTZ security cameras.
The LTC4264 is designed to interface with custom Power
Sourcing Equipment (PSE) to deliver higher power levels
to the PD load. Off-the-shelf high power PSEs are available
today from a variety of vendors for use with the LTC4264
to allow quick implementation of a custom system. Alternately, the system vendor can choose to build their own
high power PSE. Linear Technology provides complete
application information for high power PSE solutions
delivering up to 35W for 2-pair systems and as much as
70W when used in 4-pair systems.
One of the basic architectural decisions associated with
a high power PoE system is whether to deliver power
PSE
RJ45
4
using four conductors (2-pair) or all eight conductors
(4-pair). Each method provides advantages and the
system vendor needs to decide which method best suits
their application.
2-pair power is used today in 802.3af systems (see
Figure 1). One pair of conductors is used to deliver the
current and a second pair is used for the return while two
conductor pairs are not powered. This architecture offers
the simplest implementation method but suffers from
higher cable loss than an equivalent 4-pair system.
4-pair power delivers current to the PD via two conductor
pairs in parallel (Figure 2). This lowers the cable resistance
but raises the issue of current balance between each conductor pair. Differences in resistance of the transformer,
cable and connectors along with differences in diode bridge
forward voltage in the PD can cause an imbalance in the
currents flowing through each pair. The 4-pair system in
Figure 2 solves this problem by using two independent
DC/DC converters in the PD. Using this architecture solves
the balancing issue and allows the PD to be driven by two
independent PSEs, for example an Endpoint PSE and a
Midspan PSE. Contact Linear Technology applications
support for detailed information on implementing 2-pair
and 4-pair PoE systems.
CAT 5
5
5
SPARE PAIR
GND
0.1µF
100V
DGND BYP
3.3V
PD
RJ45
4
VDD
0.1µF
CMPD3003
0.47µF
100V
10k
0.25Ω
–54V
S1B
SMAJ58A
58V
Rx
2
1k
DATA PAIR
3
2
3
Rx
SENSE GATE OUT
IRLR3410
1
Tx
DETECT
1/4
LTC4259A-1
VEE
1
AGND
DF1501S
5µF
MIN
0.1µF
Tx
6
DATA PAIR
GND
6
RCLASS PWRGD
SMAJ58A
58V
LTC4264
7
7
8
8
VIN
VOUT
DC/DC
CONVERTER
+
VOUT
–
DF1501S
SPARE PAIR
4264 F01
Figure 1. 2-Pair High Power PoE System Diagram
4264f
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LTC4264
APPLICATIONS INFORMATION
PSE
RJ45
PD
GND
RJ45
0.1µF
0.1µF
DGND BYP
3.3V
VDD
AUTO
1
AGND
DETECT
CMPD3003
1/4
LTC4259A
CAT5
1
Tx1
1k
0.47µF
Rx1
2
2
3
3
6
6
Rx1
VEE
SENSE GATE OUT
10k S1B
0.25Ω
0.1µF
DF1501S
5µF
MIN
SMAJ58A
GND
RCLASS PWRGD
DC/DC
CONVERTER
LTC4264
Tx1
VIN
VOUT
SMAJ58A
–
+ +
+
– –
VOUT
–54V
IRLR3410
0.1µF
GND
0.1µF
AGND
DETECT
CMPD3003
1/4
LTC4259A
4
Rx2
5
1k
7
7
8
8
Rx2
SENSE GATE OUT
10k S1B
0.25Ω
DC/DC
CONVERTER
LTC4264
5
VIN
0.47µF
VEE
GND
RCLASS PWRGD
4
Tx2
5µF
MIN
SMAJ58A
VOUT
DF1501S
Tx2
SMAJ58A
–54V
4264 F02
IRLR3410
Figure 2. 4-Pair High Power PoE Gigabit Ethernet System Diagram
The LTC4264 is specifically designed to implement the
front end of a high power PD for power-hungry PoE applications that must operate beyond the power limits of
IEEE 802.3af. LTC4264 uses a precision, dual current limit
that keeps inrush below IEEE 803.2af levels to ensure
interoperability with any PSE. After inrush is complete,
the LTC4264 input current limit switches to the ILIMIT_HIGH
level, using an onboard, 750mA power MOSFET. This allows a PD (supplied by a custom PSE) to deliver power
above the IEEE 802.3af 12.95W maximum, sending up
to 35W to the PD load. The LTC4264 uses established
IEEE 802.3af detection and classification methods to
maintain compliance and includes an extended programmable Class 5 range for use in custom PoE applications.
The LTC4264 features both active-high and active-low
power good signaling for simplified interface to any DC/DC
converter. The SHDN pin on the LTC4264 can be used to
provide a seamless interface for external wall adapter or
other auxiliary power options. The ILIM_EN pin provides the
option to remove the high current limit, ILIMIT_HIGH. The
LTC4264 includes an onboard signature resistor, precision
UVLO, thermal overload protection and is available in a
thermally-enhanced 12-lead 4mm × 3mm DFN package
for superior high current performance.
OPERATION
The LTC4264 high power PD interface controller has several modes of operation depending on the applied input
voltage as shown in Figure 3 and summarized in Table 1.
These various modes satisfy the requirements defined
in the IEEE 802.3af specification. The input voltage is
applied to the VIN pin with reference to the GND pin and
is always negative.
Table 1. LTC4264 Operational Mode as a Function
of Input Voltage
INPUT VOLTAGE
LTC4264 MODE OF OPERATION
0V to –1.4V
Inactive
–1.5V to –10.1V
25k Signature Resistor Detection
–10.3V to –12.4V
Classification Load Current Ramps Up from 0% to
100%
–12.5V to UVLO*
Classification Load Current Active
UVLO* to –57V
Power Applied to PD Load
*UVLO includes hysteresis.
Rising input threshold ≅ –38.9V
Falling input threshold ≅ –30.6V
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LTC4264
APPLICATIONS INFORMATION
DETECTION V1
–10
VIN (V)
SERIES DIODES
TIME
DETECTION V2
CLASSIFICATION
–20
UVLO
TURN-ON
–30
The IEEE 802.3af-defined operating modes for a PD reference the input voltage at the RJ45 connector on the PD.
The PD must be able to handle power received in either
polarity. For this reason, it is common to install diode
bridges BR1 and BR2 between the RJ45 connector and
the LTC4264 (Figure 4). The diode bridges introduce an
offset that affects the threshold points for each range of
operation. The LTC4264 meets the IEEE 802.3af-defined
operating modes by compensating for the diode drops
in the threshold points. For the signature, classification,
and the UVLO thresholds, the LTC4264 extends two diode
drops below the IEEE 802.3af specifications. Note that
the voltage ranges specified in the LTC4264 Electrical
Specifications are referenced with respect to the IC pins.
The LTC4264 threshold points support the use of either
traditional or Schottky diode bridges.
UVLO
TURN-OFF
–40
–50
TIME
τ = RLOAD C1
VOUT (V)
–10
–20
UVLO
OFF
UVLO
ON
UVLO
OFF
–30
–40
–50
dV =ILIMIT_LOW
dt
C1
TIME
PWRGD (V)
–10
POWER
BAD
–20
POWER
GOOD
POWER
BAD
–30
–40
PWRGD TRACKS
VIN
PWRGD – VOUT (V)
–50
20
POWER
BAD
10
POWER
GOOD
POWER
BAD
TIME
ILIMIT_HIGH
LOAD, ILOAD
(UP TO ILIMIT_HIGH)
PD CURRENT
ILIMIT_LOW
ICLASS
CLASSIFICATION
TIME
DETECTION I2
DETECTION I1
V1 – 2 DIODE DROPS
V2 – 2 DIODE DROPS
I1 =
I2 =
25kΩ
25kΩ
ICLASS DEPENDENT ON RCLASS SELECTION
ILIMIT_LOW = 300mA, ILIMIT_HIGH = 750mA
ILOAD =
VIN
RLOAD
GND
LTC4264
IIN
PSE
RCLASS GND
PWRGD
RCLASS
RLOAD
C1
VOUT
PWRGD
VIN
VOUT
4264 F03
Figure 3. Output Voltage, PWRGD, PWRGD and
PD Current as a Function of Input Voltage
DETECTION
During detection, the PSE will apply a voltage in the range
of –2.8V to –10V on the cable and look for a 25k signature
resistor. This identifies the device at the end of the cable
as a PD. With the PSE voltage in the detection range, the
LTC4264 presents an internal 25k resistor between the GND
and VIN pins. This precision, temperature-compensated
resistor provides the proper characteristics to alert the PSE
that a PD is present and requests power to be applied.
The IEEE 802.3af specification requires the PSE to use
a ΔV/ΔI measurement technique to keep the DC offset
voltage of the diode bridge from affecting the signature
resistance measurement. However, the diode resistance
appears in series with the signature resistor and must
be included in the overall signature resistance of the PD.
The LTC4264 compensates for the two series diodes in
the signature path by offsetting the internal resistance so
that a PD built with the LTC4264 meets the IEEE 802.3af
specification.
In some designs that include an auxiliary power option,
such as an external wall adapter, it is necessary to control
whether or not the PD is detected by a PSE. With the
LTC4264, the 25k signature resistor can be enabled or
disabled with the SHDN pin (Figure 5). Taking the SHDN
4264f
9
LTC4264
APPLICATIONS INFORMATION
RJ45
1
2
3
POWERED
DEVICE (PD)
INTERFACE
AS DEFINED
BY IEEE 802.3af
6
TX +
T1
BR1
TX –
RX +
TO PHY
RX –
GND
4
SPARE +
BR2
5
7
8
LTC4264
0.1µF
100V
D3
VIN
SPARE –
4264 F04
Figure 4. PD Front End Using Diode Bridges on Main and Spare Inputs
LTC4264
TO
PSE
GND
16k
25k SIGNATURE
RESISTOR
SHDN
VIN
4264 F05
SIGNATURE DISABLE
Figure 5. 25k Signature Resistor with Disable
pin high will reduce the signature resistor to 10k which is
an invalid signature per the IEEE 802.3af specifications.
This will prevent a PSE from detecting and powering the
PD. This invalid signature is present in the PSE probing
range of –2.8V to –10V. When the input rises above –10V,
the signature resistor reverts to 25k to minimize power
dissipation in the LTC4264. To disable the signature, tie
SHDN to GND. Alternately, the SHDN pin can be driven
high with respect to VIN. When SHDN is high, all functions
are disabled. For normal operation tie SHDN to VIN.
CLASSIFICATION
Once the PSE has detected a PD, the PSE may optionally classify the PD. Classification provides a method for
more efficient allocation of power by allowing the PSE
to identify lower-power PDs and assign the appropriate
power level to these devices. For each class, there is an
associated load current that the PD asserts onto the line
during classification probing. The PSE measures the PD
load current in order to assign the proper PD classification. Class 0 is included in the IEEE 802.3af specification
to cover PDs that do not support classification. Class 1-3
partition PDs into three distinct power ranges as shown in
Table 2. Class 4 is reserved by the IEEE 802.3af committee
for future use. The new Class 5 defined here is available
for system vendors to implement a unique classification
for use in closed systems and is not defined or supported
by the IEEE 802.3af. With the extended classification
range available in the LTC4264, it is possible for system
designers to define multiple classes using load currents
between 40mA and 75mA.
4264f
10
LTC4264
APPLICATIONS INFORMATION
During classification, the PSE presents a fixed voltage
between –15.5V and –20.5V to the PD (Figure 6). With
the input voltage in this range, the LTC4264 asserts a load
current from the GND pin through the RCLASS resistor. The
magnitude of the load current is set with the selection of
the RCLASS resistor. The resistor value associated with
each class is shown in Table 2.
Table 2. Summary of IEEE 802.3af Power Classifications and
LTC4264 RCLASS Resistor Selection
CLASS
USAGE
MAXIMUM
POWER LEVELS
AT INPUT OF PD
(W)
NOMINAL
CLASSIFICATION
LOAD CURRENT
(mA)
LTC4264
RCLASS
RESISTOR
(Ω, 1%)
0
Default
0.44 to 12.95
<5
Open
1
Optional
0.44 to 3.84
10.5
124
2
Optional
3.84 to 6.49
18.5
69.8
3
Optional
6.49 to 12.95
28
45.3
4
Reserved by IEEE. See Apps
40
30.9
5
Undefined IEEE. See Apps
56
22.1
from power cycling or getting “stuck” during signature
or classification probing. In the event a PSE overshoots
beyond the classification voltage range, the available load
current aids in returning the PD back into the classification
voltage range. (The PD input may otherwise be “trapped”
by a reverse-biased diode bridge and the voltage held by
the 0.1µF capacitor.) By gently ramping the classification
current on and maintaining a positive I-V slope until UVLO
turn-on, the LTC4264 provides a well behaved load, assuring interoperability with any PSE.
CURRENT PATH
PSE
PROBING
VOLTAGE
SOURCE
–15.5V TO –20.5V
LTC4264
RCLASS
GND
CONSTANT
LOAD
CURRENT
INTERNAL
TO LTC4264
RCLASS
VIN
4264 F06a
V
PSE CURRENT MONITOR
Classification presents a challenging stability problem
for the PSE due to the wide range of loads possible. The
LTC4264 has been designed to avoid PSE interoperability
problems by maintaining a positive I-V slope throughout
the signature and classification ranges up to UVLO turnon as shown in Figure 6b. The positive I-V slope avoids
areas of negative resistance and helps prevent the PSE
PSE
PD
Figure 6a. PSE Probing PD During Classification
INPUT CURRENT (mA)
A substantial amount of power is dissipated in the LTC4264
during classification. The IEEE 802.3af specification limits
the classification time to 75ms in order avoid excessive
heating. The LTC4264 is designed to handle the power
dissipation during the probe period. If the PSE probing
exceeds 75ms, the LTC4264 may overheat. In this situation, the thermal protection circuit will engage and disable
the classification current source, protecting the LTC4264
from damage. When the die cools, classification is automatically resumed.
0
–10
–20
–30
INPUT VOLTAGE (V)
–40
4264 F06b
Figure 6b. LTC4264 Positive I-V Slope
4264f
11
LTC4264
APPLICATIONS INFORMATION
UNDERVOLTAGE LOCKOUT
INPUT CURRENT LIMIT
The IEEE 802.3af specification dictates a maximum turnon voltage of 42V and a minimum turn-off voltage of 30V
for the PD. In addition, the PD must maintain large on-off
hysteresis to prevent current-resistance (I-R) drops in the
wiring between the PSE and the PD from causing start-up
oscillation. The LTC4264 incorporates an undervoltage
lockout (UVLO) circuit that monitors line voltage at VIN to
determine when to apply power to the PD load (Figure 7).
Before power is applied to the load, the VOUT pin is high
impedance and there is no charge on capacitor C1. When
the input voltage rises above the UVLO turn-on threshold, the LTC4264 removes the classification load current
and turns on the internal power MOSFET. C1 charges up
under LTC4264 inrush current limit control and the VOUT
pin transitions from 0V to VIN as shown in Figure 3. The
LTC4264 includes a hysteretic UVLO circuit on VIN that
keeps power applied to the load until the magnitude of the
input voltage falls below the UVLO turn-off threshold. Once
VIN falls below UVLO turn-off, the internal power MOSFET
disconnects VOUT from VIN and the classification current
is re-enabled. C1 will discharge through the PD circuitry
and the VOUT pin will go to a high impedance state.
IEEE 802.3af specifies a maximum inrush current and also
specifies a minimum load capacitor between the GND and
VOUT pins. To control turn-on surge currents in the system
the LTC4264 integrates a dual current limit circuit using an
onboard power MOSFET and sense resistor to provide a
complete inrush control circuit without additional external
components.
LTC4264
TO
PSE
At turn-on, the LTC4264 will limit the inrush current to
ILIMIT_LOW, allowing the load capacitor to ramp up to the line
voltage in a controlled manner without interference from
the PSE current limit. By keeping the PD current limit below
the PSE current limit, PD power up characteristics are well
controlled and independent of PSE behavior. This ensures
interoperability regardless of PSE output characteristics.
After load capacitor C1 is charged up, the LTC4264 switches
to the high input current limit, ILIMIT_HIGH. This allows the
LTC4264 to deliver up to 35W to the PD load for high power
applications. To maintain compatibility with IEEE 802.3af
power levels, it is necessary for the PD designer to ensure
the PD steady-state power consumption remains below
the limits shown in Table 2. The LTC4264 maintains the
high input current limit until the port voltage drops below
the UVLO turn-off threshold.
GND
C1
5µF
MIN
+
PD
LOAD
UNDERVOLTAGE
LOCKOUT
CIRCUIT
VIN
VOUT
INPUT
LTC4264
VOLTAGE
POWER MOSFET
0V TO UVLO*
OFF
>UVLO*
ON
*UVLO INCLUDES HYSTERESIS
RISING INPUT THRESHOLD ≅ –38.9V
FALLING INPUT THRESHOLD ≅ –30.6V
4264 F07
CURRENT-LIMITED
TURN ON
Figure 7. LTC4264 Undervoltage Lockout
4264f
12
LTC4264
APPLICATIONS INFORMATION
During the inrush event as C1 is being charged, a large
amount of power is dissipated in the MOSFET. The LTC4264
is designed to accept this load and is thermally protected
to avoid damage to the onboard power MOSFET. If a
thermal overload does occur, the power MOSFET turns
off, allowing the die to cool. Once the die has returned to
a safe temperature, the LTC4264 automatically switches
to ILIMIT_LOW, and load capacitor C1 charging resumes.
The LTC4264 has the option of disabling the normal operating input current limit, ILIMIT_HIGH, for custom high power
PoE applications. To disable the current limit, connect
ILIM_EN to VIN. To protect the LTC4264 from damage when
the normal current limit is disabled, a safeguard current
limit, ILIMIT_DISA keeps the current below destructive
levels, typically 1.4A. Note that continuous operation at
or near the safeguard current limit will rapidly overheat
the LTC4264, engaging the thermal protection circuit. For
normal operations, float the ILIM_EN pin. The LTC4264
maintains the ILIMIT_LOW inrush current limit for charging
the load capacitor regardless of the state of ILIM_EN. The
operation of the ILIM_EN pin is summarized in Table 3.
LTC4264
Table 3. Current Limit as a Function of ILIM_EN
STATE OF ILIM_EN
INRUSH CURRENT
LIMT
OPERATING INPUT
CURRENT LIMIT
Floating
ILIMIT_LOW
ILIMT_HIGH
Tied to VIN
ILIMIT_LOW
ILIMIT_DISA
POWER GOOD
The LTC4264 includes complementary power good outputs
(Figure 8) to simplify connection to any DC/DC converter.
Power Good is asserted at the end of the inrush event when
load capacitor C1 is fully charged and the DC/DC converter
can safely begin operation. The power good signal stays
active during normal operation and is de-asserted at power
off when the port drops below the UVLO threshold or in
the case of a thermal overload event.
For PD designs that use a large load capacitor and also
consume a lot of power, it is important to delay activation of the DC/DC converter with the power good signal.
If the converter is not disabled during the current-limited
turn-on sequence, the DC/DC converter will rob current
intended for charging up the load capacitor and create a
slow rising input, possibly causing the LTC4264 to go into
thermal shutdown.
10 PWRGD
UVLO
THERMAL SD
CONTROL
CIRCUIT
INRUSH COMPLETE
AND NOT IN THERMAL SHUTDOWN
9
PWRGD
VIN 5
8
VOUT
VIN 6
7
VOUT
REF
BOLD LINE INDICATES HIGH CURRENT PATH
POWER
NOT
GOOD
POWER
GOOD
VIN < UVLO OFF
OR THERMAL SHUTDOWN
4264 BD
Figure 8. LTC4264 Power Good Functional and State Diagram
4264f
13
LTC4264
APPLICATIONS INFORMATION
The active high PWRGD pin features an internal, opencollector output referenced to VOUT. During inrush, the
active high PWRGD pin pulls low until the load capacitor
is fully charged. At that point, PWRGD becomes high
impedance, indicating the converter may begin running.
The active high PWRGD pin can interface directly with the
“Run” pin of converter products. The PWRGD pin features
an internal 14V clamp to VOUT which protects the DC/DC
converter from excessive voltage. During a power supply
ramp down event, PWRGD becomes low impedance when
VIN drops below the UVLO turn-off threshold, then goes
high impedance when the VIN voltages fall to within the
detection voltage range.
The active low PWRGD pin connects to an internal, open
drain MOSFET referenced to VIN which can sink 1mA.
During inrush, PWRGD is high impedance. Once the load
capacitor is fully charged, PWRGD is pulled low and DC/DC
converter operation can begin. The active low PWRGD
pin can connect directly to the shutdown pin of converter
products. PWRGD is referenced to the VIN pin and when
active will be near the VIN potential. The converter will
typically be referenced to VOUT and care must be taken to
ensure that the difference in potential of the PWRGD pin
does not cause a problem for the DC/DC converter. The
use of diode clamp D9 and RS, as shown in Figure 11,
alleviates any problems.
the instantaneous power dissipated by the LTC4264 can
be as high as 16W.
The LTC4264 protects itself from damage by monitoring
die temperature. If the die exceeds the overtemperature
trip point, the power MOSFET and classification transistors are disabled until the part cools down. Once the die
cools below the overtemperature trip point, all functions
are enabled automatically.
During classification, excessive heating of the LTC4264
can occur if the PSE violates the 75ms probing time limit.
In addition, the IEEE 802.3af specification requires a PD
to withstand application of any voltage from 0V to 57V
indefinitely. To protect the LTC4264 in these situations,
the thermal protection circuitry disables the classification
circuit if the die temperature exceeds the overtemperature
trip point. When the die cools down, classification current
is enabled.
Once the LTC4264 has charged up the load capacitor
and the PD is powered and running, there will be some
residual heating due to the DC load current of the PD
flowing through the internal MOSFET. In some high current applications, the LTC4264 power dissipation may be
significant. The LTC4264 uses a thermally enhanced DFN12
package that includes an Exposed Pad which should be
soldered to an electrically isolated heat sink on the printed
circuit board.
THERMAL PROTECTION
The LTC4264 includes thermal overload protection in
order to provide full device functionality in a miniature
package while maintaining safe operating temperatures.
At turn-on, before load capacitor C1 has charged up, the
instantaneous power dissipated by the LTC4264 can be
as high as 20W. As the load capacitor charges, the power
dissipation in the LTC4264 will decrease until it reaches
a steady-state value dependent on the DC load current.
The LTC4264 can also experience device heating after
turn-on if the PD experiences a fast input voltage rise. For
example, if the PD input voltage steps from –37V to –57V,
MAXIMUM AMBIENT TEMPERATURE
The LTC4264 ILIM_EN pin allows the PD designer to disable
the normal operating current limit. With the normal current limit disabled, it is possible to pass currents as high
as 1.4A through the LTC4264. In this mode, significant
package heating may occur. Depending on the current,
voltage, ambient temperature, and waveform characteristics, the LTC4264 may shut down. To avoid nuisance
trips of the thermal shutdown, it may be necessary to
limit the maximum ambient temperature. Limiting the die
temperature to 125°C will keep the LTC4264 from hitting
4264f
14
LTC4264
APPLICATIONS INFORMATION
thermal shutdown. For DC loads the maximum ambient
temperature can be calculated as:
TMAX = 125 – θJA • PWR (°C)
where TMAX is the maximum ambient operating temperature, θJA is the junction-to-ambient thermal resistance
(43°C/W), and PWR is the power dissipation for the
LTC4264 in Watts (IPD2RON).
such as Bel Fuse, Coilcraft, Halo, Pulse, and Tyco (Table 4)
can provide assistance with selection of an appropriate
isolation transformer and proper termination methods.
These vendors have transformers specifically designed
for use in high power PD applications.
Table 4. Power over Ethernet Transformer Vendors
VENDOR
CONTACT INFORMATION
Bel Fuse Inc.
206 Van Vorst Street
Jersey City, NJ 07302
Tel: 201-432-0463
www.belfuse.com
Coilcraft Inc.
1102 Silver Lake Road
Gary, IL 60013
Tel: 847-639-6400
www.coilcraft.com
Halo Electronics
1861 Landings Drive
Mountain View, CA 94043
Tel: 650-903-3800
www.haloelectronics.com
Pulse Engineering
12220 World Trade Drive
San Diego, CA 92128
Tel: 858-674-8100
www.pulseeng.com
Tyco Electronics
308 Constitution Drive
Menlo Park, CA 94025-1164
Tel: 800-227-7040
www.circuitprotection.com
EXTERNAL INTERFACE AND COMPONENT SELECTION
Transformer
Nodes on an Ethernet network commonly interface to
the outside world via an isolation transformer (Figure 9).
For powered devices, the isolation transformer must
include a center tap on the media (cable) side. Proper
termination is required around the transformer to provide
correct impedance matching and to avoid radiated and
conducted emissions. For high power applications beyond
IEEE 802.3af limits, the increased current levels increase
the current imbalance in the magnetics. This imbalance
reduces the perceived inductance and can interfere with
data transmission. Transformers specifically designed for
high current applications are required. Transformer vendors
RJ45
1
2
3
6
4
TX +
TX –
RX +
RX –
8
15
2
14
11
3
6
10
7
9
8
BR1
HD01
TO PHY
PULSE H2019
SPARE +
5
7
16 T1 1
SPARE –
GND
BR2
HD01
C14
0.1µF
100V
D3
SMAJ58A
TVS
C1
LTC4264
VIN
VOUT
4264 F09
VOUT
Figure 9. PD Front-End with Isolation Transformer, Diode Bridges, Capacitors and TVS
4264f
15
LTC4264
APPLICATIONS INFORMATION
Diode Bridge
IEEE 802.3af allows power wiring in either of two configurations on the TX/RX wires, and power can be applied to
the PD via the spare wire pair in the RJ45 connector. The
PD is required to accept power in either polarity on both
the data and spare inputs; therefore it is common to install
diode bridges on both inputs in order to accommodate
the different wiring configurations. Figure 9 demonstrates
an implementation of the diode bridges. The IEEE 802.3af
specification also mandates that the leakage back through
the unused bridge be less than 28µA when the PD is
powered with 57V.
The PD may be configured to handle 2-pair or 4-pair
power delivery over the Ethernet cable. In a 2-pair power
delivery system, one of the two pairs is delivering power
to the PD—either the main pair or the spare pair, but not
both. In a 4-pair system, both the main and spare pairs
deliver power to the PD simultaneously (see Figures 1
and 2). In either case, a diode bridge is needed on the
front end to accept power in either polarity. Contact LTC
applications for more information about implementing a
4-pair PoE system.
bridges while maintaining proper threshold points for IEEE
802.3af compliance.
Figure 4 shows how two diode bridges are typically connected in a PD application. One bridge is dedicated to the
data pair while the second bridge is dedicated to the spare
pair. For high power applications, a diode bridge typically
used in an IEEE 802.3af system cannot handle the higher
currents because the operating current is derated at the
upper temperature range. To solve this problem, the PD
application can utilize larger diode bridges, use discrete
diodes or consider the following alternative option.
Realizing that the two diode bridges do not need to be
exclusive to the data and spare pairs, the bridges may
be reconnected so that current is shared between them.
The new configuration extends the maximum operating
current while maintaining the smaller package profiles.
Figure 9 shows an example of how the two diode bridges
may be reconnected. Consult the diode bridge vendors for
operating current derating curves when only one of four
diodes is in operation.
Auxiliary Power Source
The IEEE standard includes an AC impedance requirement
in order to implement the AC disconnect function. Capacitor C14 in Figure 9 is used to meet this AC impedance
requirement. A 0.1µF capacitor is recommended for this
application.
In some applications, it may be necessary to power the PD
from an auxiliary power source such as a wall adapter. The
auxiliary power can be injected into the PD at several locations and various trade-offs exist. Figure 10 demonstrates
four methods of connecting external power to a PD.
The LTC4264 has several different modes of operation
based on the voltage present between the VIN and GND
pins. The forward voltage drop of the input diodes in a
PD design subtracts from the input voltage and will affect the transition point between modes. When using the
LTC4264, it is necessary to pay close attention to this
forward voltage drop. Selection of oversized diodes will
help keep the PD thresholds from exceeding IEEE 802.3af
specifications.
Option 1 in Figure 10 inserts power before the LTC4264
interface controller. In this configuration, it is necessary
for the wall adapter to exceed the LTC4264 UVLO turnon requirement. This option provides input current limit
for the adapter, provides a valid power good signal and
simplifies power priority issues. As long as the adapter
applies power to the PD before the PSE, it will take priority
and the PSE will not power up the PD because the external
power source will corrupt the 25k signature. If the PSE
is already powering the PD, the adapter power will be in
parallel with the PSE. In this case, priority will be given to
the higher supply voltage. If the adapter voltage is higher,
the PSE should remove the port voltage since no current
The input diode bridge of a PD can consume over 4% of
the available power in some applications. Schottky diodes
can be used in order to reduce power loss. The LTC4264 is
designed to work with both standard and Schottky diode
4264f
16
LTC4264
APPLICATIONS INFORMATION
OPTION 1: AUXILIARY POWER INSERTED BEFORE LTC4264
RJ45
1
2
3
6
TX +
T1
~
TX –
RX +
TO PHY
RX –
D3
SMAJ58A
TVS
+
BR1
~
–
~
+
C14
0.1µF
100V
C1
PD
LOAD
GND
4
SPARE +
5
7
8
• 42V ≤ VWW ≤ 57V
• NO POWER PRIORITY ISSUES
• LTC4264 CURRENT LIMITS FOR BOTH PoE AND VWW
LTC4264
BR2
SPARE –
~
–
+
VOUT
VIN
D8
S1B
ISOLATED
WALL
VWW
TRANSFORMER
–
OPTION 2: AUXILIARY POWER INSERTED AFTER LTC4264 WITH SIGNATURE DISABLED
RJ45
1
2
3
6
TX +
T1
~
TX –
RX +
TO PHY
RX –
+
D3
SMAJ58A
TVS
BR1
~
–
~
+
C14
0.1µF
100V
C1
PD
LOAD
GND
100k
4
SPARE +
5
7
8
100k
BR2
SPARE –
~
BSS63
LTC4264
D9
S1B
SHDN
–
VIN
VOUT
+
D10
S1B
ISOLATED
VWW
WALL
TRANSFORMER
• VWW ANY VOLTAGE BASED ON PD LOAD
• REQUIRES EXTRA DIODE
• SEE APPS REGARDING POWER PRIORITY
–
OPTION 3: AUXILIARY POWER APPLIED TO LTC4264 AND PD LOAD
RJ45
1
2
3
6
TX +
T1
~
TX –
RX +
TO PHY
+
BR1
~
RX –
D3
SMAJ58A
TVS
C14
0.1µF
100V
C1
–
PD
LOAD
GND
4
SPARE +
~
5
7
8
+
• 42V ≤ VWW ≤ 57V
• NO POWER PRIORITY ISSUES
• NO LTC4264 CURRENT LIMITS FOR VWW
LTC4264
BR2
SPARE –
~
–
VIN
+
VOUT
D10
S1B
ISOLATED
WALL
VWW
TRANSFORMER
–
OPTION 4: AUXILIARY POWER APPLIED TO ISOLATED LOAD
RJ45
1
2
3
6
TX +
T1
~
TX –
RX +
TO PHY
+
BR1
~
RX –
D3
SMAJ58A
TVS
C14
0.1µF
100V
C1
ISOLATED DC/DC CONVERTER
–
DRIVE
LOAD
GND
4
SPARE +
~
5
7
8
+
BR2
SPARE –
~
LTC4264
SHDN
–
VIN
• VWW ANY VOLTAGE BASED ON PD LOAD
• SEE APPS REGARDING POWER PRIORITY
• BEST ISOLATION
VOUT
+
ISOLATED
VWW
WALL
TRANSFORMER
–
Figure 10. Interfacing Auxiliary Power Source to the PD
4264f
17
LTC4264
APPLICATIONS INFORMATION
will be drawn from the PSE. On the other hand, if the
adapter voltage is lower, the PSE will continue to supply
power to the PD and the adapter will not be used. Proper
operation will occur in either scenario.
Option 2 applies power directly to the DC/DC converter.
In this configuration the adapter voltage does not need to
exceed the LTC4264 turn-on UVLO requirement and can
be selected based solely on the PD load requirements. It
is necessary to include diode D9 to prevent the adapter
from applying power to the LTC4264. Power priority issues require more intervention. If the adapter voltage is
below the PSE voltage, then the priority will be given to the
PSE power. The PD will draw power from the PSE while
the adapter will remain unused. This configuration is acceptable in a typical PoE system. However, if the adapter
voltage is higher than the PSE voltage, the PD will draw
power from the adapter. In this situation, it is necessary
to address the issue of power cycling that may occur if
a PSE is present. The PSE will detect the PD and apply
power. If the PD is being powered by the adapter, then
the PD will not meet the minimum load requirement and
the PSE may subsequently remove power. The PSE will
again detect the PD and power cycling will start. With an
adapter voltage above the PSE voltage, it is necessary to
either disable the signature as shown in option 2, or install
a minimum load on the output of the LTC4264 to prevent
power cycling. A 3k, 1W resistor connected between GND
and VOUT will present the required minimum load.
Option 3 applies power directly to the DC/DC converter
bypassing the LTC4264 and omitting diode D9. With the
diode omitted, the adapter voltage is applied to the LTC4264
in addition to the DC/DC converter. For this reason, it is
necessary to ensure that the adapter maintain the voltage
between 42V and 57V to keep the LTC4264 in its normal
operating range. The third option has the advantage of
corrupting the 25k signature resistance when the external
voltage exceeds the PSE voltage and thereby solving the
power priority issue.
Option 4 bypasses the entire PD interface and injects
power at the output of the low voltage power supply. If
the adapter output is below the low voltage output there
are no power priority issues. However, if the adapter is
above the internal supply, then option 4 suffers from the
same power priority issues as option 2 and the signature
should be disabled or a minimum load should be installed.
Shown in option 4 is one method to disable to the signature
while maintaining isolation.
If employing options 1 through 3, it is necessary to ensure
that the end-user cannot access the terminals of the auxiliary power jack on the PD since this would compromise
IEEE 802.3af isolation requirements and may violate local
safety codes. Using option 4 along with an isolated power
supply addresses the isolation issue and it is no longer
necessary to protect the end-user from the power jack.
The above power cycling scenarios have assumed the
PSE is using DC disconnect methods. For a PSE using
AC disconnect, a PD with less than minimum load will
continue to be powered.
Wall adapters have been known to generate voltage spikes
outside their expected operating range. Care should be
taken to ensure no damage occurs to the LTC4264 or any
support circuitry from extraneous spikes at the auxiliary
power interface.
Classification Resistor Selection (RCLASS)
The IEEE 802.3af specification allows classifying PDs
into four distinct classes with class 4 being reserved
for future use (Table 2). The LTC4264 supports all IEEE
classes and implements an additional Class 5 for use in
custom PoE applications. An external resistor connected
from RCLASS to VIN (Figure 6) sets the value of the load
current. The designer should determine which class the
PD is to advertise and then select the appropriate value of
4264f
18
LTC4264
APPLICATIONS INFORMATION
RCLASS from Table 2. If a unique load current is required,
the value of RCLASS can be calculated as:
RCLASS = 1.237V/(ILOAD – IIN_CLASS)
IIN_CLASS is the LTC4264 IC supply current during classification given in the electrical specifications. The RCLASS
resistor must be 1% or better to avoid degrading the overall
accuracy of the classification circuit. Resistor power dissipation will be 100mW maximum and is transient so heating
is typically not a concern. In order to maintain loop stability, the layout should minimize capacitance at the RCLASS
node. The classification circuit can be disabled by floating
the RCLASS pin. The RCLASS pin should not be shorted to
VIN as this would force the LTC4264 classification circuit
to attempt to source very large currents. In this case, the
LTC4264 will quickly go into thermal shutdown.
Power Good Interface
The LTC4264 provides complimentary power good signals
to simplify the DC/DC converter interface. Using the power
good signal to delay converter operation until the load
capacitor is fully charged is recommended as this will help
ensure trouble free start up. The active high PWRGD pin
is controlled by an open collector transistor referenced to
VOUT while the active low PWRGD pin is controlled by a
high voltage, open-drain MOSFET referenced to VIN. The
designer has the option of using either of these signals to
enable the DC/DC converter and example interface circuits
are shown in Figure 11. When using PWRGD, diode D9
and resistor RS protects the converter shutdown pin from
excessive reverse voltage.
ACTIVE-HIGH ENABLE
GND
PD
LOAD
LTC4264
TO
PSE
PWRGD
–54V
VIN
RUN
VOUT
ACTIVE-LOW ENABLE
GND
RS
10k
LTC4264
TO
PSE
R9
100k
PD
LOAD
SHDN
PWRGD
D9
5.1V
MMBZ5231B
–54V
VIN
VOUT
ACTIVE-LOW ENABLE
GND
LTC4264
TO
PSE
R10
100k
RS
10k
PWRGD
Q1
FMMT2222
D9
MMBD4148
–54V
VIN
VOUT
V+
PD
LOAD
4264 F11
Figure 11. Power Good Interface Examples
4264f
19
LTC4264
APPLICATIONS INFORMATION
Shutdown Interface
To disable the 25k signature resistor, connect SHDN to
the GND pin. Alternately, the SHDN pin can be driven
high with respect to VIN. Examples of interface circuits
that disable the signature and all LTC4264 functions are
shown in Figure 10, options 2 and 4. Note that the SHDN
input resistance is relatively large and the threshold voltage is fairly low. Because of high voltages present on the
printed circuit board, leakage currents from the GND pin
could inadvertently pull SHDN high. To ensure trouble-free
operation, use high voltage layout techniques in the vicinity
of SHDN. If unused, connect SHDN directly to VIN.
Load Capacitor
The IEEE 802.3af specification requires that the PD maintain
a minimum load capacitance of 5µF. It is permissible to
have a much larger load capacitor and the LTC4264 can
charge very large load capacitors before thermal issues
become a problem. However, the load capacitor must not
be too large or the PD design may violate IEEE 802.3af
requirements. The LTC4264 maintains IEEE 802.3af compliance when the load capacitor is 180µF or less. A larger
capacitor can be employed in a proprietary, close-system
high power application.
If the load capacitor is too large, there can be a problem with inadvertent power shutdown by the PSE. For
example, if the PSE is running at –57V (IEEE 802.3af
maximum allowed) and the PD is detected and powered
up, the load capacitor will be charged to nearly –57V. If
for some reason the PSE voltage is suddenly reduced to
–44V (IEEE 802.3af minimum allowed), the input bridge
will reverse bias and the PD power will be supplied by the
load capacitor. Depending on the size of the load capacitor
and the DC load of the PD, the PD will not draw any power
from the PSE for a period of time. If this period of time
exceeds the IEEE 802.3af 300ms disconnect delay, the
PSE will remove power from the PD. For this reason, it is
necessary to evaluate the load current and capacitance to
ensure that inadvertent shutdown cannot occur.
Refer also to Thermal Protection in this data sheet for
further discussion on load capacitor selection.
MAINTAIN POWER SIGNATURE
In an IEEE 802.3af system, the PSE uses the maintain
power signature (MPS) to determine if a PD continues to
require power. The MPS requires the PD to periodically
draw at least 10mA and also have an AC impedance less
than 26.25kΩ in parallel with 0.05µF. If either the DC
current is less than 10mA or the AC impedance is above
26.25kΩ, the PSE may disconnect power. The DC current
must be less than 5mA and the AC impedance must be
above 2MΩ to guarantee power will be removed. The PD
application circuits shown in this data sheet present the
required AC impedance necessary to maintain power.
LAYOUT CONSIDERATIONS FOR THE LTC4264
The LTC4264 is relatively immune to layout problems.
Excessive parasitic capacitance on the RCLASS pin should
be avoided. Include an electrically isolated heat sink to
which the exposed pad on the bottom of the package can
be soldered. For optimum thermal performance, make the
heat sink as large as possible. Voltages in a PD can be as
large as –57V for PoE applications, so high voltage layout
techniques should be employed. The SHDN pin should
be separated from other high voltage pins, like GND and
4264f
20
LTC4264
APPLICATIONS INFORMATION
VOUT, to avoid the possibility of leakage shutting down the
LTC4264. If not used, tie SHDN to VIN.
The load capacitor connected between GND and VOUT
of the LTC4264 can store significant energy when fully
charged. The design of a PD must ensure that this energy is not inadvertently dissipated in the LTC4264. The
polarity-protection diodes prevent an accidental short
on the cable from causing damage. However, if the VIN
pin is shorted to GND inside the PD while the capacitor
is charged, current will flow through the parasitic body
diode of the internal MOSFET and may cause permanent
damage to the LTC4264.
ELECTRO STATIC DISCHARGE AND SURGE
PROTECTION
The LTC4264 is specified to operate with an absolute
maximum voltage of –90V and is designed to tolerate brief
over-voltage events. However, the pins that interface to the
outside world (primarily VIN and GND) can routinely see
peak voltages in excess of 10kV. To protect the LTC4264,
it is highly recommended that the SMAJ58A unidirectional
58V transient voltage suppressor be installed between the
diode bridge and the LTC4264 (D3 in Figure 4).
ISOLATION
The 802.3 standard requires Ethernet ports to be electrically
isolated from all other conductors that are user accessible.
This includes the metal chassis, other connectors and
any auxiliary power connection. For PDs, there are two
common methods to meet the isolation requirement. If
there will be any user accessible connection to the PD,
then an isolated DC/DC converter is necessary to meet
the isolation requirements. If user connections can be
avoided, then it is possible to meet the safety requirement
by completely enclosing the PD in an insulated housing.
In all PD applications, there should be no user accessible
electrical connections to the LTC4264 or support circuitry
other than the RJ-45 port.
4264f
21
22
–54V FROM
SPARE PAIR
–54V FROM
DATA PAIR
B2100 × 8 PLCS
RCLASS
0.1µF
100V
3.01k
1%
FB
VCC
20k
1/4W
22µF
16V
100k
2.1k
1%
150k
33pF
PG
0.1µF
VC
SENSE–
SENSE+
OSC SFST CCMP GND
LT3825
ENDLY
SG
SG
0.1µF
3300pF
0.1µF
0.015Ω
1/8W
Si4488DY
10k
680pF
1000pF
100V
10Ω
Figure 12. High Efficiency, Triple Output Power Supply
15k
PGDLY
tON SYNC RCMP
VOUT
20k
29.4k
1%
91Ω
BAS21
2.2µF
100V
VIN
12µF
100V
UVLO
402k
+
ILIM_EN PWRGD
RCLASS PWRGD
LTC4264
SHDN
GND
SMAJ58A
4.7µH
•
2200pF
4264 F12
10k
15Ω
FMMT618
220pF 100V
1500pF 100V
BAT54
FMMT718
Si4362DY
•
Si4488DY
•
Si4470EY
4700pF
250VAC
•
330Ω
PA0184
SG
•
•
•
PA1558NL
47µF
1µF
25V
47Ω
B0540W
10Ω
1/4W
10Ω
1/4W
47µF
0.33µH
22µF
16V
47µF
0.33µH
+
+
100µF
6.3V
22µF
16V
100µF
6.3V
3.3V
4A
11.8V
0.4A
5V
2.4A
LTC4264
APPLICATIONS INFORMATION
4264f
LTC4264
PACKAGE DESCRIPTION
DE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1695 Rev C)
0.70 ±0.05
3.60 ±0.05
1.70 ±0.05
2.20 ±0.05 (2 SIDES)
PACKAGE OUTLINE
0.25 ± 0.05
3.30 ±0.05
(2 SIDES)
0.50
BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
4.00 ±0.10
(2 SIDES)
7
R = 0.115
TYP
0.40 ± 0.10
12
R = 0.05
TYP
3.00 ±0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
1.70 ± 0.05
(2 SIDES)
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
0.200 REF
0.75 ±0.05
0.00 – 0.05
6
0.25 ± 0.05
3.30 ±0.05
(2 SIDES)
1
(UE12/DE12) DFN 0905 REV C
0.50
BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
4264f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC4264
TYPICAL APPLICATION
LTC4264 with Auxiliary Supply
VOUT+
OUT TO DC/DC
CONVERTER
+
AC ADAPTER
24V
30W
D1
SMAJ58A
–
B2100 4 PLCS
PD IN
36V TO 57V
14
1
2
3
6
IN
FROM
HIGH
POWER
PSE
T3 ETH1-230LD
13
12
11
10
4
5
7
8
9
•
•
•
•
•
•
•
•
•
•
•
•
D3
D4
D2
D5
1
+
2
3
TO
4
PHY
5
6
D7
Q5
FMMT23
D8
R18
100k
D6
R5
R6
75Ω
75Ω
C14
C15
0.01µF 0.01µF
200V
200V
R7
75Ω
C16
0.01µF
200V
C5
12µF
100V
R14
100k
J1
SS-6488-NF-K1
R4
75Ω
C13
0.01µF
200V
C8
0.1µF
100V
D9
B2100 4 PLCS
R21
100k
RCLASS
22.1Ω
1%
1
2
3
4
5
6
LTC4264
SHDN
NC
RCLASS
ILIM_EN
VIN
VIN
GND
NC
PWRGD
PWRGD
VOUT
VOUT
NC
13
12
11
10
9
8
7
R12
100k
PWRGD
D15 B2100
VOUT–
D12 B2100
C17
1000pF
2kV
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Burst Mode is a registered trademark of Linear Technology Corporation. No RSENSE and ThinSOT are trademarks of Linear Technology Corporation.
4264f
24 Linear Technology Corporation
LT 0307 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
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