LTC3850-2 Dual, 2-Phase Synchronous Step-Down Switching Controller DESCRIPTION FEATURES n n n n n n n n n n n n n The LTC®3850-2 is a high performance dual synchronous step-down switching regulator controller that drives all N-channel power MOSFET stages. A constant-frequency current mode architecture allows a phase-lockable frequency of up to 780kHz. Power loss and supply noise are minimized by operating the two controller output stages out of phase. Dual, 180° Phased Controllers Reduce Required Input Capacitance and Power Supply Induced Noise High Efficiency: Up to 95% RSENSE or DCR Current Sensing ±1% 0.8V Output Voltage Accuracy Phase-Lockable Fixed Frequency 250kHz to 780kHz Supports Pre-Biased Output Dual N-Channel MOSFET Synchronous Drive Wide VIN Range: 4V to 30V Operation Adjustable Soft-Start Current Ramping or Tracking Foldback Output Current Limiting Output Overvoltage Protection Power Good Output Voltage Monitor 28-Pin Narrow SSOP Package OPTI-LOOP® compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. The LTC3850-2 features a precision 0.8V reference and a power good output indicator. A wide 4V to 30V input supply range encompasses most battery chemistries and intermediate bus voltages. Independent TK/SS pins for each controller ramp the output voltages during start-up. Current foldback limits MOSFET heat dissipation during short-circuit conditions. The MODE/PLLIN pin selects among Burst Mode® operation, pulse-skipping mode, or continuous inductor current mode and allows the IC to be synchronized to an external clock. APPLICATIONS n n n n Notebook and Palmtop Computers Portable Instruments Battery-Operated Digital Devices DC Power Distribution Systems L, LT, LTC, LTM, OPTI-LOOP and Burst Mode are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066, 6580258. The LTC3850-2 is identical to the LTC3850-1, except they have different pin assignments. TYPICAL APPLICATION High Efficiency Dual 3.3V/2.5V Step-Down Converter Efficiency 22μF 50V 4.7μF VIN PGOOD INTVCC 500kHz MODE/PLLIN EXTVCC 0.1μF 63.4k 20k 15k TK/SS1 0.1μF 2.2μH 2.2k PGND TK/SS2 0.1μF 1000 80 75 70 100 65 POWER LOSS 55 0.1μF 43.2k ITH2 SGND 85 60 SENSE2+ RUN2 SENSE2– VFB2 ITH1 220pF 100μF 6V 90 FREQ/PLLFLTR SENSE1+ RUN1 SENSE1– VFB1 10000 EFFICIENCY POWER LOSS (mW) 2.2k VIN = 12V 95 VOUT = 3.3V 0.1μF BOOST1 BOOST2 SW1 SW2 LTC3850-2 BG2 BG1 2.2μH VOUT1 3.3V 5A TG2 100 EFFICIENCY (%) TG1 0.1μF VIN 7V TO 26V 10nF 10k VOUT2 2.5V 5A 220pF 15k 50 10 100 1000 LOAD CURRENT (mA) 10 10000 38502 TA01b 100μF 6V 20k 38502 TA01 38502f 1 LTC3850-2 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) Input Supply Voltage (VIN) ......................... 30V to –0.3V Input Supply Transient Voltage (VIN) < 500ms, with INTVCC ≥ 5V ........................................... 34V to –0.3V Top Side Driver Voltages BOOST1, BOOST2.................................. 34V to –0.3V Switch Voltage (SW1, SW2) ......................... 30V to –5V INTVCC , RUN1, RUN2, PGOOD, EXTVCC, (BOOST1-SW1), (BOOST2-SW2) ................. 6V to –0.3V SENSE1+, SENSE2+, SENSE1–, SENSE2– Voltages..................................... 5.5V to –0.3V MODE/PLLIN, TK/SS1,TK/SS2, FREQ/PLLFLTR Voltages ................................................ INTVCC to –0.3V ITH1 , ITH2 , VFB1 , VFB2 Voltages .................. 2.7V to –0.3V INTVCC Peak Output Current ................................100mA Operating Temperature Range (Note 2)....–40°C to 85°C Junction Temperature (Note 3) ............................. 125°C Storage Temperature Range...................–65°C to 125°C Lead Temperature (Soldering, 10 sec) (GN Package) .................................................... 300°C TOP VIEW RUN1 1 28 FREQ/PLLFLTR SENSE1+ 2 27 MODE/PLLIN SENSE1– 3 26 SW1 VFB1 4 25 TG1 TK/SS1 5 24 BOOST1 ITH1 6 23 BG1 SGND 7 22 VIN ITH2 8 21 INTVCC TK/SS2 9 20 BG2 VFB2 10 19 PGND SENSE2– 11 18 BOOST2 SENSE2+ 12 17 TG2 RUN2 13 16 SW2 EXTVCC 14 15 PGOOD GN PACKAGE 28-LEAD NARROW PLASTIC SSOP TJMAX = 125°C, θJA = 95°C/W ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3850IGN-2#PBF LTC3850IGN-2#TRPBF LTC3850GN-2 28-Lead Narrow Plastic SSOP –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 38502f 2 LTC3850-2 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C, VIN = 15V, VRUN1,2 = 5V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 0.792 0.800 0.808 V –10 –50 nA 0.002 0.02 %/V 0.01 –0.01 0.1 –0.1 % % Main Control Loops VFB1,2 Regulated Feedback Voltage ITH1,2 Voltage = 1.2V; (Note 4) IFB1,2 Feedback Current (Note 4) VREFLNREG Reference Voltage Line Regulation VIN = 6V to 24V (Note 4) VLOADREG Output Voltage Load Regulation (Note 4) Measured in Servo Loop; ΔITH Voltage = 1.2V to 0.7V Measured in Servo Loop; ΔITH Voltage = 1.2V to 1.6V l l l gm1,2 Transconductance Amplifier gm ITH1,2 = 1.2V; Sink/Source 5μA; (Note 4) 2.2 IQ Input DC Supply Current Normal Mode Shutdown (Note 5) VIN = 15V; EXTVCC Tied to VOUT1; VOUT1 = 5V VRUN1,2 = 0V 850 30 UVLO Undervoltage Lockout on INTVCC VINTVCC Ramping Down UVLOHYS UVLO Hysteresis DFMAX Maximum Duty Factor In Dropout VOVL Feedback Overvoltage Lockout Measured at VFB1,2 ISENSE Sense Pin Bias Current (Each Channel) VSENSE1,2 = 3.3V l mmho 50 μA μA 3 V 0.5 V 96 97.2 % 0.84 0.86 0.88 V ±1 ±2 μA ITK/SS1,2 Soft-Start Charge Current VTK/SS1,2 = 0V VRUN1,2 RUN Pin ON Threshold VRUN1, VRUN2 Rising VRUN1,2HYS RUN Pin ON Hysteresis VSENSE(MAX) Maximum Current Sense Threshold VFB1,2 = 0.7V, VSENSE1,2 = 3.3V TG RUP TG Driver Pull-Up On-Resistance TG High TG RDOWN TG Driver Pulldown On-Resistance TG Low 1.5 Ω BG RUP BG Driver Pull-Up On-Resistance BG High 2.4 Ω BG RDOWN BG Driver Pulldown On-Resistance BG Low 1.1 Ω TG1,2 tr TG1,2 tf TG Transition Time: Rise Time Fall Time (Note 6) CLOAD = 3300pF CLOAD = 3300pF 25 25 ns ns BG1,2 tr BG1,2 tf BG Transition Time: Rise Time Fall Time (Note 6) CLOAD = 3300pF CLOAD = 3300pF 25 25 ns ns TG/BG t1D Top Gate Off to Bottom Gate On Delay Synchronous Switch-On Delay Time CLOAD = 3300pF Each Driver 30 ns BG/TG t2D Bottom Gate Off to Top Gate On Delay Top Switch-On Delay Time CLOAD = 3300pF Each Driver 30 ns tON(MIN) Minimum On-Time (Note 7) 90 ns l 0.9 1.3 1.7 μA 1.1 1.22 1.35 V 80 l 40 50 mV 60 2.6 mV Ω INTVCC Linear Regulator VINTVCC Internal VCC Voltage 7V < VIN < 24V VLDO INT INTVCC Load Regulation ICC = 0mA to 50mA VEXTVCC EXTVCC Switchover Voltage EXTVCC Ramping Positive VLDO EXT EXTVCC Voltage Drop ICC = 20mA, VEXTVCC = 5V VLDOHYS EXTVCC Hysteresis 4.8 l 4.5 5 5.2 V 0.5 2 % 100 mV 4.7 50 200 V mV 38502f 3 LTC3850-2 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C, VIN = 15V, VRUN1,2 = 5V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Oscillator and Phase-Locked Loop fNOM Nominal Frequency VFREQ = 1.2V 450 500 550 kHz fLOW Lowest Frequency VFREQ = 0V 210 250 290 kHz fHIGH Highest Frequency VFREQ ≥ 2.4V 700 780 860 kHz RMODE/PLLIN MODE/PLLIN Input Resistance IFREQ Phase Detector Output Current Sinking Capability Sourcing Capability 250 kΩ fMODE < fOSC fMODE > fOSC –13 13 μA μA 0.1 PGOOD Output VPGL PGOOD Voltage Low IPGOOD = 2mA IPGOOD PGOOD Leakage Current VPGOOD = 5V VPG PGOOD Trip Level VFB with Respect to Set Regulated Voltage VFB Ramping Negative VFB Ramping Positive Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3850I-2 is guaranteed to meet performance specifications over the –40°C to 85°C operating temperature range. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formulas: LTC3850IGN-2: TJ = TA + (PD • 95°C/W) –5 5 – 7.5 7.5 0.3 V ±2 μA –10 10 % % Note 4: The LTC3850I-2 is tested in a feedback loop that servos VITH1,2 to a specified voltage and measures the resultant VFB1,2. Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information. Note 6: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels. Note 7: The minimum on-time condition is specified for an inductor peak-to-peak ripple current ≥40% of IMAX (see Minimum On-Time Considerations in the Applications Information section). TYPICAL PERFORMANCE CHARACTERISTICS Efficiency vs Output Current and Mode Efficiency vs Output Current and Mode 100 90 BURST DCM 50 40 30 DCM 60 50 40 30 CCM 20 20 10 10 0 0 10 95 70 100 1000 LOAD CURRENT (mA) CIRCUIT OF FIGURE 14 10000 38502 G01 CCM EFFICIENCY 100 1000 LOAD CURRENT (mA) CIRCUIT OF FIGURE 14 10000 38502 G02 1500 1000 90 POWER LOSS 85 VIN = 12V VOUT = 3.3V 10 2000 VOUT = 3.3V IOUT = 2A BURST 80 EFFICIENCY (%) 70 60 100 POWER LOSS (mW) EFFICIENCY (%) 80 100 EFFICIENCY (%) VIN = 12V 90 VOUT = 1.8V Efficiency and Power Loss vs Input Voltage 500 80 5 10 15 20 INPUT VOLTAGE (V) 0 25 38502 G03 CIRCUIT OF FIGURE 14 38502f 4 LTC3850-2 TYPICAL PERFORMANCE CHARACTERISTICS Load Step (Burst Mode Operation) Load Step (Forced Continuous Mode) ILOAD 2A/DIV 200mA TO 2.5A ILOAD 2A/DIV 200mA TO 2.5A IL 2A/DIV IL 2A/DIV VOUT 100mV/DIV AC COUPLED VOUT 100mV/DIV AC COUPLED 40μs/DIV 38502 G04 CIRCUIT OF FIGURE 14 VIN = 12V, VOUT = 1.8V Load Step (Pulse-Skipping Mode) Inductor Current at Light Load FORCED CONTINUOUS MODE 2A/DIV ILOAD 2A/DIV 200mA TO 2.5A IL 2A/DIV Burst Mode OPERATION 2A/DIV VOUT 100mV/DIV AC COUPLED PULSE-SKIPPING MODE 2A/DIV 40μs/DIV VOUT 2V/DIV 38502 G05 40μs/DIV CIRCUIT OF FIGURE 14 VIN = 12V, VOUT = 1.8V 38502 G06 1μs/DIV CIRCUIT OF FIGURE 14 VIN = 12V, VOUT = 1.8V CIRCUIT OF FIGURE 14 VIN = 12V, VOUT = 1.8V ILOAD = 100μA Prebiased Output at 2V Coincident Tracking RUN1 2V/DIV VTK/SS 500mV/DIV 38502 G07 VOUT1, 3.3V 3Ω LOAD, 1V/DIV VOUT2, 1.8V 1.5Ω LOAD 1V/DIV VFB 500mV/DIV 2.5ms/DIV 38502 G08 1ms/DIV 38502 G09 38502f 5 LTC3850-2 TYPICAL PERFORMANCE CHARACTERISTICS Tracking Up and Down with External Ramp Quiescent Current vs Input Voltage without EXTVCC INTVCC Line Regulation 5.25 5 TK/SS1 TK/SS2 2V/DIV 5.00 VOUT1 3.3V 3Ω LOAD 1V/DIV VOUT2 1.8V 1.5Ω LOAD 1V/DIV 3 2 4.75 4.50 4.25 4.00 1 38502 G10 10ms/DIV INTVCC VOLTAGE (V) SUPPLY CURRENT (mA) 4 3.75 0 3.50 15 10 5 20 0 25 5 10 INPUT VOLTAGE (V) 15 20 38502 G11 VSENSE (mV) 60 40 20 0 –20 –40 0.5 1 VITH (V) 1.5 2 80 100 70 90 60 50 40 30 20 10 0 80 70 60 50 40 30 20 10 0 1 2 4 3 VSENSE COMMON MODE VOLTAGE (V) 38502 G13 5 0 0 20 40 60 DUTY CYCLE (%) 38502 G14 80 100 38502 G15 TK/SS Pull-Up Current vs Temperature Maximum Current Sense Voltage vs Feedback Voltage (Current Foldback) 2.00 80 70 60 TK/SS CURRENT (μA) MAXIMUM CURRENT SENSE VOLTAGE (mV) Maximum Current Sense Threshold vs Duty Cycle CURRENT SENSE THRESHOLD (mV) CURRENT SENSE THRESHOLD (mV) 80 0 38502 G12 Maximum Current Sense Threshold vs Common Mode Voltage Current Sense Threshold vs ITH Voltage 25 INPUT VOLTAGE (V) 50 40 30 1.75 1.50 1.25 20 10 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 FEEDBACK VOLTAGE (V) 38502 G16 1.00 –50 –25 50 25 0 TEMPERATURE (°C) 75 100 38502 G17 38502f 6 LTC3850-2 TYPICAL PERFORMANCE CHARACTERISTICS Regulated Feedback Voltage vs Temperature Shutdown (RUN) Threshold vs Temperature RUN PIN VOLTAGE (V) 1.4 1.3 ON 1.2 OFF 1.1 1.0 –50 –25 50 25 0 TEMPERATURE (°C) 900 804 800 802 800 798 796 –25 50 25 0 TEMPERATURE (°C) 4 75 100 Shutdown Current vs Input Voltage 50 40 INPUT CURRENT (μA) FREQUENCY (kHz) 2 50 25 0 TEMPERATURE (°C) –25 38502 G20 410 FALLING VFREQ = 0V 200 –50 100 75 420 3 VFREQ = 1.2V 500 Oscillator Frequency vs Input Voltage 5 400 390 30 20 10 1 380 50 25 0 TEMPERATURE (°C) 75 100 0 10 5 15 20 15 20 25 38502 G23 Quiescent Current vs Temperature without EXTVCC 5 VIN = 15V 40 30 20 10 –25 10 38502 G22 Shutdown Current vs Temperature 0 –50 5 INPUT VOLTAGE (V) 38502 G21 50 25 INPUT VOLTAGE (V) QUIESCENT CURRENT (mA) –25 SHUTDOWN CURRENT (μA) INTVCC VOLTAGE (V) 600 38502 G19 Undervoltage Lockout Threshold (INTVCC) vs Temperature 0 –50 700 300 38502 G18 RISING VFREQ = INTVCC 400 794 –50 100 75 806 FREQUENCY (kHz) REGULATED FEEDBACK VOLTAGE (mV) 1.5 Oscillator Frequency vs Temperature 50 25 0 TEMPERATURE (°C) 75 100 38502 G24 4 3 2 1 0 –50 –25 50 25 0 TEMPERATURE (°C) 75 100 38502 G25 38502f 7 LTC3850-2 PIN FUNCTIONS RUN1, RUN2 (Pin 1, Pin 13): Run Control Inputs. A voltage above 1.2V on either pin turns on the IC. However, forcing either of these pins below 1.2V causes the IC to shut down that particular channel. There are 0.5μA pull-up currents for these pins. Once the RUN pin rises above 1.2V, an additional 4.5μA pull-up current is added to the pin. SENSE1+, SENSE2+ (Pin 2, Pin 12): Current Sense Comparator Inputs. The (+) inputs to the current comparators are normally connected to DCR sensing networks or current sensing resistors. SENSE1–, SENSE2– (Pin 3, Pin 11): Current Sense Comparator Inputs. The (–) inputs to the current comparators are connected to the outputs. TK/SS1, TK/SS2 (Pin 5, Pin 9): Output Voltage Tracking and Soft-Start Inputs. When one channel is configured to be master of the two channels, a capacitor to ground at this pin sets the ramp rate for the master channel’s output voltage. When the channel is configured to be the slave of two channels, the VFB voltage of the master channel is reproduced by a resistor divider and applied to this pin. Internal soft-start currents of 1.3μA charge the soft-start capacitors. ITH1, ITH2 (Pin 6, Pin 8): Current Control Thresholds and Error Amplifier Compensation Points. Each associated channels’ current comparator tripping threshold increases with its ITH control voltage. VFB1, VFB2 (Pin 4, Pin 10): Error Amplifier Feedback Inputs. These pins receive the remotely sensed feedback voltages for each channel from external resistive dividers across the outputs. SGND (Pin 7): Signal Ground. All small-signal components and compensation components should connect to this ground, which in turn connects to PGND at one point. EXTVCC (Pin 14): External Power Input to an Internal Switch Connected to INTVCC. This switch closes and supplies the IC power, bypassing the internal low dropout regulator, whenever EXTVCC is higher than 4.7V. Do not exceed 6V on this pin and ensure VIN > VEXTVCC at all times. PGOOD (Pin 15): Power Good Indicator Output. Open-drain logic out that is pulled to ground when either channel output exceeds the ±7.5% regulation window, after the internal 17μs power bad mask timer expires. PGND (Pin 19): Power Ground Pin. Connect this pin closely to the sources of the bottom N-channel MOSFETs, the (–) terminal of CVCC and the (–) terminal of CIN. INTVCC (Pin 21): Internal 5V Regulator Output. The control circuits are powered from this voltage. Decouple this pin to PGND with a 4.7μF low ESR tantalum or ceramic capacitor. VIN (Pin 22): Main Input Supply. Decouple this pin to PGND with a capacitor (0.1μF to 1μF). For applications where the main input power is 5V, tie the VIN and INTVCC pins together. BG1, BG2 (Pins 23, 20): Bottom Gate Driver Outputs. These pins drive the gates of the bottom N-Channel MOSFETs and swings between PGND and INTVCC. BOOST1, BOOST2 (Pins 24, 18): Boosted Floating Driver Supplies. The (+) terminal of the boost-strap capacitors connect to these pins. These pins swing from a diode voltage drop below INTVCC up to VIN + INTVCC. TG1, TG2 (Pins 25, 17): Top Gate Driver Outputs. These are the outputs of floating drivers with a voltage swing equal to INTVCC superimposed on the switch nodes voltages. SW1, SW2 (Pins 26, 16): Switch Node Connections to Inductors. Voltage swing at these pins are from a body diode voltage drop below ground to VIN. MODE/PLLIN (Pin 27): Force Continuous Mode, Burst Mode, or Pulse-Skipping Mode Selection Pin and External Synchronization Input to Phase Detector Pin. Connect this pin to SGND to force both channels into the continuous mode of operation. Connect to INTVCC to enable pulse-skipping mode of operation. Leaving the pin floating will enable Burst Mode operation. A clock on the pin will force the controller into continuous mode of operation and synchronize the internal oscillator. FREQ/PLLFLTR (Pin 28): The Phase-Locked Loop’s Low-Pass Filter is Tied to This Pin. Alternatively, this pin can be driven with a DC voltage to vary the frequency of the internal oscillator. 38502f 8 LTC3850-2 FUNCTIONAL DIAGRAM FREQ/PLLFLTR MODE/PLLIN EXTVCC VIN VIN 4.7V F 0.8V 5V REG + – PLL-SYNC CIN + – MODE/SYNC DETECT + INTVCC INTVCC F BOOST OSC BURSTEN S R 3k + ON – ICMP IREV + – CB TG FCNT Q M1 SW SWITCH LOGIC AND ANTISHOOT THROUGH L1 VOUT SENSE+ DB SENSE– + COUT RUN BG OV M2 CVCC SLOPE COMPENSATION PGND PGOOD INTVCC UVLO + 1 51k ITHB SLOPE RECOVERY ACTIVE CLAMP UV R2 – + SLEEP VIN 0.74V VFB R1 OV – – – + SS + – RUN + 0.86V SGND 1.3μA EA – + + 0.8V REF 0.64V 1.2V 0.5μA 0.55V ITH RC CC1 RUN TK/SS CSS 38502 FD 38502f 9 LTC3850-2 OPERATION Main Control Loop The LTC3850-2 is a constant-frequency, current mode step-down controller with two channels operating 180 degrees out-of-phase. During normal operation, each top MOSFET is turned on when the clock for that channel sets the RS latch, and turned off when the main current comparator, ICMP, resets the RS latch. The peak inductor current at which ICMP resets the RS latch is controlled by the voltage on the ITH pin, which is the output of each error amplifier EA. The VFB pin receives the voltage feedback signal, which is compared to the internal reference voltage by the EA. When the load current increases, it causes a slight decrease in VFB relative to the 0.8V reference, which in turn causes the ITH voltage to increase until the average inductor current matches the new load current. After the top MOSFET has turned off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by the reverse current comparator IREV, or the beginning of the next cycle. INTVCC/EXTVCC Power Power for the top and bottom MOSFET drivers and most other internal circuitry is derived from the INTVCC pin. When the EXTVCC pin is left open or tied to a voltage less than 4.7V, an internal 5V linear regulator supplies INTVCC power from VIN. If EXTVCC is taken above 4.7V, the 5V regulator is turned off and an internal switch is turned on connecting EXTVCC. Using the EXTVCC pin allows the INTVCC power to be derived from a high efficiency external source such as one of the LTC3850-2 switching regulator outputs. Each top MOSFET driver is biased from the floating bootstrap capacitor CB, which normally recharges during each off cycle through an external diode when the top MOSFET turns off. If the input voltage VIN decreases to a voltage close to VOUT, the loop may enter dropout and attempt to turn on the top MOSFET continuously. The dropout detector detects this and forces the top MOSFET off for about one-twelfth of the clock period every third cycle to allow CB to recharge. However, it is recommended that a load be present during the drop-out transition to ensure CB is recharged. Shutdown and Start-Up (RUN1, RUN2 and TK/SS1, TK/SS2 Pins) The two channels of the LTC3850-2 can be independently shut down using the RUN1 and RUN2 pins. Pulling either of these pins below 1.2V shuts down the main control loop for that controller. Pulling both pins low disables both controllers and most internal circuits, including the INTVCC regulator. Releasing either RUN pin allows an internal 0.5μA current to pull up the pin and enable that controller. Alternatively, the RUN pin may be externally pulled up or driven directly by logic. Be careful not to exceed the Absolute Maximum Rating of 6V on this pin. The start-up of each controller’s output voltage VOUT is controlled by the voltage on the TK/SS1 and TK/SS2 pins. When the voltage on the TK/SS pin is less than the 0.8V internal reference, the LTC3850-2 regulates the VFB voltage to the TK/SS pin voltage instead of the 0.8V reference. This allows the TK/SS pin to be used to program a soft-start by connecting an external capacitor from the TK/SS pin to SGND. An internal 1.3μA pull-up current charges this capacitor, creating a voltage ramp on the TK/SS pin. As the TK/SS voltage rises linearly from 0V to 0.8V (and beyond), the output voltage VOUT rises smoothly from zero to its final value. Alternatively the TK/SS pin can be used to cause the start-up of VOUT to “track” that of another supply. Typically, this requires connecting to the TK/SS pin an external resistor divider from the other supply to ground (see the Applications Information section). When the corresponding RUN pin is pulled low to disable a controller, or when INTVCC drops below its undervoltage lockout threshold of 3V, the TK/SS pin is pulled low by an internal MOSFET. When in undervoltage lockout, both controllers are disabled and the external MOSFETs are held off. Light Load Current Operation (Burst Mode Operation, Pulse-Skipping, or Continuous Conduction) The LTC3850-2 can be enabled to enter high efficiency Burst Mode operation, constant-frequency pulse-skipping mode, or forced continuous conduction mode. To select forced continuous operation, tie the MODE/PLLIN pin to a DC voltage below 0.8V (e.g., SGND). To select pulse-skipping 38502f 10 LTC3850-2 OPERATION mode of operation, tie the MODE/PLLIN pin to INTVCC. To select Burst Mode operation, float the MODE/PLLIN pin. When a controller is enabled for Burst Mode operation, the peak current in the inductor is set to approximately one-third of the maximum sense voltage even though the voltage on the ITH pin indicates a lower value. If the average inductor current is higher than the load current, the error amplifier EA will decrease the voltage on the ITH pin. When the ITH voltage drops below 0.5V, the internal sleep signal goes high (enabling “sleep” mode) and both external MOSFETs are turned off. In sleep mode, the load current is supplied by the output capacitor. As the output voltage decreases, the EA’s output begins to rise. When the output voltage drops enough, the sleep signal goes low, and the controller resumes normal operation by turning on the top external MOSFET on the next cycle of the internal oscillator. When a controller is enabled for Burst Mode operation, the inductor current is not allowed to reverse. The reverse current comparator (IREV) turns off the bottom external MOSFET just before the inductor current reaches zero, preventing it from reversing and going negative. Thus, the controller operates in discontinuous operation. In forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is determined by the voltage on the ITH pin, just as in normal operation. In this mode, the efficiency at light loads is lower than in Burst Mode operation. However, continuous mode has the advantages of lower output ripple and less interference with audio circuitry. When the MODE/PLLIN pin is connected to INTVCC, the LTC3850-2 operates in PWM pulse-skipping mode at light loads. At very light loads, the current comparator ICMP may remain tripped for several cycles and force the external top MOSFET to stay off for the same number of cycles (i.e., skipping pulses). The inductor current is not allowed to reverse (discontinuous operation). This mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced RF interference as compared to Burst Mode operation. It provides higher low current efficiency than forced continuous mode, but not nearly as high as Burst Mode operation. Frequency Selection and Phase-Locked Loop (FREQ/PLLFLTR and MODE/PLLIN Pins) The selection of switching frequency is a trade-off between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. The switching frequency of the LTC3850-2’s controllers can be selected using the FREQ/PLLFLTR pin. If the MODE/PLLIN pin is not being driven by an external clock source, the FREQ/PLLFLTR pin can be used to program the controller’s operating frequency from 250kHz to 780kHz. A phase-locked loop (PLL) is available on the LTC3850-2 to synchronize the internal oscillator to an external clock source that is connected to the MODE/PLLIN pin. The controller is operating in forced continuous mode when it is synchronized. A series R-C should be connected between the FREQ/PLLFLTR pin and SGND to serve as the PLL’s loop filter. Power Good (PGOOD Pin) The PGOOD pin is connected to an open drain of an internal N-channel MOSFET. The MOSFET turns on and pulls the PGOOD pin low when either VFB pin voltage is not within ±7.5% of the 0.8V reference voltage. The PGOOD pin is also pulled low when either RUN pin is below 1.2V or when the LTC3850-2 is in the soft-start or tracking phase. When the VFB pin voltage is within the ±7.5% requirement, the MOSFET is turned off and the pin is allowed to be pulled up by an external resistor to a source of up to 6V. The PGOOD pin will flag power good immediately when both VFB pins are within the ±7.5% window. However, there is an internal 17μs power bad mask when either VFB goes out of the ±7.5% window. Output Overvoltage Protection An overvoltage comparator, OV, guards against transient overshoots (> 7.5%) as well as other more serious conditions that may overvoltage the output. In such cases, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared. 38502f 11 LTC3850-2 APPLICATIONS INFORMATION The Typical Application on the first page is a basic LTC38502 application circuit. LTC3850-2 can be configured to use either DCR (inductor resistance) sensing or low value resistor sensing. The choice between the two current sensing schemes is largely a design trade-off between cost, power consumption, and accuracy. DCR sensing is becoming popular because it saves expensive current sensing resistors and is more power efficient, especially in high current applications. However, current sensing resistors provide the most accurate current limits for the controller. Other external component selection is driven by the load requirement, and begins with the selection of RSENSE (if RSENSE is used) and inductor value. Next, the power MOSFETs are selected. Finally, input and output capacitors are selected. SENSE+ and SENSE– Pins The SENSE+ and SENSE– pins are the inputs to the current comparators. The common mode input voltage range of the current comparators is 0V to 5V. Both SENSE pins are high impedance inputs with small base currents of less than 1μA. When the SENSE pins ramp up from 0V to 1.4V, the small base currents flow out of the SENSE pins. When the SENSE pins ramp down from 5V to 1.1V, the small base currents flow into the SENSE pins. The high impedance inputs to the current comparators allow accurate DCR sensing. However, care must be taken not to float these pins during normal operation. VIN INTVCC BOOST TG LTC3850-2 Low Value Resistors Current Sensing A typical sensing circuit using a discrete resistor is shown in Figure 2a. RSENSE is chosen based on the required output current. The current comparator has a maximum threshold VSENSE(MAX). The input common mode range of the current comparator is 0V to 5V. The current comparator threshold TO SENSE FILTER, NEXT TO THE CONTROLLER COUT INDUCTOR OR RSENSE VIN INTVCC SENSE RESISTOR PLUS PARASITIC INDUCTANCE BOOST ESL VIN INDUCTOR TG VOUT 38502 F01 Figure 1. Sense Lines Placement with Inductor or Sense Resistor VIN RS SW Filter components mutual to the sense lines should be placed close to the LTC3850-2, and the sense lines should run close together to a Kelvin connection underneath the current sense element (shown in Figure 1). Sensing current elsewhere can effectively add parasitic inductance and capacitance to the current sense element, degrading the information at the sense terminals and making the programmed current limit unpredictable. If DCR sensing is used (Figure 2b), sense resistor R1 should be placed close to the switching node, to prevent noise from coupling into sensitive small-signal nodes. The capacitor C1 should be placed close to the IC pins. LTC3850-2 L SW DCR VOUT BG BG PGND RF SENSE+ SENSE– SGND CF • 2RF ≤ ESL/RS POLE-ZERO CANCELLATION PGND R1 SENSE+ C1* CF R2 SENSE– SGND RF 38502 F02b 38502 F02a *PLACE C1 NEAR SENSE+, SENSE– PINS FILTER COMPONENTS PLACED NEAR SENSE PINS (2a) Using a Resistor to Sense Current R1||R2 × C1 = L DCR RSENSE(EQ) = DCR R2 R1 + R2 (2b) Using the Inductor DCR to Sense Current Figure 2. Two Different Methods of Sensing Current 38502f 12 LTC3850-2 APPLICATIONS INFORMATION sets the peak of the inductor current, yielding a maximum average output current IMAX equal to the peak value less half the peak-to-peak ripple current, ΔIL. To calculate the sense resistor value, use the equation: VSENSE(MAX) ΔI I(MAX) + L 2 Because of possible PCB noise in the current sensing loop, the AC current sensing ripple of ΔVSENSE = ΔIL • RSENSE also needs to be checked in the design to get a good signal-to-noise ratio. In general, for a reasonably good PCB layout, a 15mV ΔVSENSE voltage is recommended as a conservative number to start with, either for RSENSE or DCR sensing applications. RSENSE = For previous generation current mode controllers, the maximum sense voltage was high enough (e.g., 75mV for the LTC1628 / LTC3728 family) that the voltage drop across the parasitic inductance of the sense resistor represented a relatively small error. For today’s highest current density solutions, however, the value of the sense resistor can be less than 1mΩ and the peak sense voltage can be as low as 20mV. In addition, inductor ripple currents greater than 50% with operation up to 1MHz are becoming more common. Under these conditions the voltage drop across the sense resistor’s parasitic inductance is no longer negligible. A typical sensing circuit using a discrete resistor is shown in Figure 2a. In previous generations of controllers, a small RC filter placed near the IC was commonly used to reduce the effects of capacitive and inductive noise coupled inthe sense traces on the PCB. A typical filter consists of two series 10Ω resistors connected to a parallel 1000pF capacitor, resulting in a time constant of 20ns. This same RC filter, with minor modifications, can be used to extract the resistive component of the current sense signal in the presence of parasitic inductance. For example, Figure 3 illustrates the voltage waveform across a 2mΩ sense resistor with a 2010 footprint for the 1.2V/15A converter shown in Figure 18 operating at 100% load. The waveform is the superposition of a purely resistive component and a purely inductive component. It was measured using two scope probes and waveform math to obtain a differential measurement. Based on additional measurements of the inductor ripple current and the on-time and off-time of the top switch, the value of the parasitic inductance was determined to be 0.5nH using the equation: ESL = VESL(STEP) tON • tOFF ΔIL tON + tOFF If the RC time constant is chosen to be close to the parasitic inductance divided by the sense resistor (L/R), the resulting waveform looks resistive again, as shown in Figure 4. For applications using low maximum sense voltages, check the sense resistor manufacturer’s data sheet for information about parasitic inductance. In the absence of data, measure the voltage drop directly across the sense resistor to extract the magnitude of the ESL step and use the equation above to determine the ESL. However, do not over-filter. Keep the RC time constant less than or equal to the inductor time constant to maintain a high enough ripple voltage on VRSENSE. The above generally applies to high density / high current applications where I(MAX) > 10A and low values of inductors are used. For applications where I(MAX) < 10A, set RF to 10Ω and CF to 1000pF. This will provide a good starting point. The filter components need to be placed close to the IC. The positive and negative sense traces need to be routed as a differential pair and Kelvin connected to the sense resistor. Inductor DCR Sensing For applications requiring the highest possible efficiency at high load currents, the LTC3850-2 is capable of sensing the voltage drop across the inductor DCR, as shown in Figure 2b. The DCR of the inductor represents the small amount of DC winding resistance of the copper, which can be less than 1mΩ for today’s low value, high current inductors. In a high current application requiring such an inductor, conduction loss through a sense resistor would cost several points of efficiency compared to DCR sensing. 38502f 13 LTC3850-2 APPLICATIONS INFORMATION VESL(STEP) VSENSE 20mV/DIV 500ns/DIV 38502 F03 Figure 3. Voltage Waveform Measured Directly Across the Sense Resistor. To ensure that the application will deliver full load current over the full operating temperature range, choose the minimum value for the Maximum Current Sense Threshold (VSENSE(MAX)) in the Electrical Characteristics table (40mV). Next, determine the DCR of the inductor. Where provided, use the manufacturer’s maximum value, usually given at 20°C. Increase this value to account for the temperature coefficient of resistance, which is approximately 0.4%/°C. A conservative value for TL(MAX) is 100°C. To scale the maximum inductor DCR to the desired sense resistor value, use the divider ratio: RD = VSENSE 20mV/DIV 500ns/DIV 38502 F04 Figure 4. Voltage Waveform Measured After the Sense Resistor Filter. CF = 1000pF, RF = 100Ω. If the external R1|| R2 • C1 time constant is chosen to be exactly equal to the L/DCR time constant, the voltage drop across the external capacitor is equal to the drop across the inductor DCR multiplied by R2/(R1 + R2). R2 scales the voltage across the sense terminals for applications where the DCR is greater than the target sense resistor value. To properly dimension the external filter components, the DCR of the inductor must be known. It can be measured using a good RLC meter, but the DCR tolerance is not always the same and varies with temperature; consult the manufacturers’ datasheets for detailed information. Using the inductor ripple current value from the Inductor Value Calculation section, the target sense resistor value is: RSENSE(EQUIV) = VSENSE(MAX) ΔI I(MAX) + L 2 RSENSE(EQUIV) DCR(MAX) at TL(MAX) C1 is usually selected to be in the range of 0.047μF to 0.47μF. This forces R1|| R2 to around 2kΩ, reducing error that might have been caused by the SENSE pins’ ±1μA current. The equivalent resistance R1|| R2 is scaled to the room temperature inductance and maximum DCR: R1||R2 = L (DCR at 20°C) • C1 The sense resistor values are: R1= R1|| R2 R1 • RD ; R2 = RD 1− RD The maximum power loss in R1 is related to duty cycle, and will occur in continuous mode at the maximum input voltage: PLOSS R1= (V IN(MAX) − VOUT )• V OUT R1 Ensure that R1 has a power rating higher than this value. If high efficiency is necessary at light loads, consider this power loss when deciding whether to use DCR sensing or 38502f 14 LTC3850-2 APPLICATIONS INFORMATION sense resistors. Light load power loss can be modestly higher with a DCR network than with a sense resistor, due to the extra switching losses incurred through R1. However, DCR sensing eliminates a sense resistor, reduces conduction losses and provides higher efficiency at heavy loads. Peak efficiency is about the same with either method. To maintain a good signal to noise ratio for the current sense signal, use a minimum ΔVSENSE of 10mV to 15mV. For a DCR sensing application, the actual ripple voltage will be determined by the equation: V −V VOUT ΔVSENSE = IN OUT R1• C1 VIN • fOSC Slope Compensation and Inductor Peak Current Slope compensation provides stability in constantfrequency architectures by preventing subharmonic oscillations at high duty cycles. It is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. Normally, this results in a reduction of maximum inductor peak current for duty cycles > 40%. However, the LTC3850-2 uses a patented scheme that counteracts this compensating ramp, which allows the maximum inductor peak current to remain unaffected throughout all duty cycles. Inductor Value Calculation Given the desired input and output voltages, the inductor value and operating frequency fOSC directly determine the inductor’s peak-to-peak ripple current: IRIPPLE = VOUT ⎛ VIN – VOUT ⎞ VIN ⎜⎝ fOSC •L ⎟⎠ Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors, and output voltage ripple. Thus, highest efficiency operation is obtained at low frequency with a small ripple current. Achieving this, however, requires a large inductor. A reasonable starting point is to choose a ripple current that is about 40% of IOUT(MAX). Note that the largest ripple current occurs at the highest input voltage. To guarantee that ripple current does not exceed a specified maximum, the inductor should be chosen according to: L≥ VIN – VOUT VOUT • fOSC •IRIPPLE VIN Inductor Core Selection Once the inductance value is determined, the type of inductor must be selected. Core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Power MOSFET and Schottky Diode (Optional) Selection Two external power MOSFETs must be selected for each controller in the LTC3850-2: one N-channel MOSFET for the top (main) switch, and one N-channel MOSFET for the bottom (synchronous) switch. The peak-to-peak drive levels are set by the INTVCC voltage. This voltage is typically 5V during start-up (see EXTVCC Pin Connection). Consequently, logic-level threshold MOSFETs must be used in most applications. The only exception is if low input voltage is expected (VIN < 5V); then, sub-logic level threshold MOSFETs (VGS(TH) < 3V) should be used. Pay close attention to the BVDSS specification for the MOSFETs as well; most of the logic level MOSFETs are limited to 30V or less. 38502f 15 LTC3850-2 APPLICATIONS INFORMATION Selection criteria for the power MOSFETs include the on-resistance RDS(ON), Miller capacitance CMILLER, input voltage and maximum output current. Miller capacitance, CMILLER, can be approximated from the gate charge curve usually provided on the MOSFET manufacturers’ data sheet. CMILLER is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in VDS. This result is then multiplied by the ratio of the application applied VDS to the gate charge curve specified VDS. When the IC is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by: Main Switch Duty Cycle = VOUT VIN Synchronous Switch Duty Cycle = VIN – VOUT VIN The MOSFET power dissipations at maximum output current are given by: PMAIN = VOUT 2 IMAX ) (1+ δ )RDS(ON) + ( VIN ⎞ ( VIN)2 ⎛⎜⎝ IMAX (R )(C )• 2 ⎟⎠ DR MILLER ⎡ 1 1 ⎤ + ⎥ • fOSC ⎢ ⎢⎣ VINTVCC – VTH(MIN) VTH(MIN) ⎥⎦ V –V 2 PSYNC = IN OUT (IMAX ) (1+ δ )RDS(ON) VIN where δ is the temperature dependency of RDS(ON) and RDR (approximately 2Ω) is the effective driver resistance at the MOSFET’s Miller threshold voltage. VTH(MIN) is the typical MOSFET minimum threshold voltage. Both MOSFETs have I2R losses while the topside N-channel equation includes an additional term for transition losses, which are highest at high input voltages. For VIN < 20V the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CMILLER actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. The term (1 + δ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs Temperature curve, but δ = 0.005/°C can be used as an approximation for low voltage MOSFETs. The optional Schottky diodes conduct during the dead time between the conduction of the two power MOSFETs. These prevent the body diodes of the bottom MOSFETs from turning on, storing charge during the dead time and requiring a reverse recovery period that could cost as much as 3% in efficiency at high VIN. A 1A to 3A Schottky is generally a good compromise for both regions of operation due to the relatively small average current. Larger diodes result in additional transition losses due to their larger junction capacitance. Soft-Start and Tracking The LTC3850-2 has the ability to either soft-start by itself with a capacitor or track the output of another channel or external supply. When one particular channel is configured to soft-start by itself, a capacitor should be connected to its TK/SS pin. This channel is in the shutdown state if its RUN pin voltage is below 1.2V. Its TK/SS pin is actively pulled to ground in this shutdown state. Once the RUN pin voltage is above 1.2V, the channel powers up. A soft-start current of 1.3μA then starts to charge its soft-start capacitor. Note that soft-start or tracking is achieved not by limiting the maximum output current of the controller but by controlling the output ramp voltage according to the ramp rate on the TK/SS pin. Current foldback is disabled during this phase to ensure smooth soft-start or tracking. The soft-start or tracking range is defined to be the voltage range from 0V to 0.8V on the TK/SS pin. The total soft-start time can be calculated as: CSS 1.3µA Regardless of the mode selected by the MODE/PLLIN pin, the regulator will always start in pulse-skipping mode up t SOFTSTART = 0.8 • 38502f 16 LTC3850-2 APPLICATIONS INFORMATION to TK/SS = 0.64V. Between TK/SS = 0.64V and 0.74V, it will operate in forced continuous mode and revert to the selected mode once TK/SS > 0.74V. The output ripple is minimized during the 100mV forced continuous mode window ensuring a clean PGOOD signal. When the channel is configured to track another supply, the feedback voltage of the other supply is duplicated by a resistor divider and applied to the TK/SS pin. Therefore, the voltage ramp rate on this pin is determined by the ramp rate of the other supply’s voltage. Note that the small soft-start capacitor charging current is always flowing, producing a small offset error. To minimize this error, select the tracking resistive divider value to be small enough to make this error negligible. In order to track down another channel or supply after the soft-start phase expires, the LTC3850-2 is forced into continuous mode of operation as soon as VFB is below the undervoltage threshold of 0.74V regardless of the setting on the MODE/PLLIN pin. However, the LTC3850-2 should always be set in force continuous mode tracking down when there is no load. After TK/SS drops below 0.1V, its channel will operate in discontinuous mode. Output Voltage Tracking The LTC3850-2 allows the user to program how its output ramps up and down by means of the TK/SS pins. Through these pins, the output can be set up to either coincidentally or ratiometrically track another supply’s output, as shown in Figure 5. In the following discussions, VOUT1 refers to the LTC3850-2’s output 1 as a master channel and VOUT2 refers to the LTC3850-2’s output 2 as a slave channel. In practice, though, either phase can be used as the master. To implement the coincident tracking in Figure 5a, connect an additional resistive divider to VOUT1 and connect its midpoint to the TK/SS pin of the slave channel. The ratio of this divider should be the same as that of the slave channel’s feedback divider shown in Figure 6a. In this tracking mode, VOUT1 must be set higher than VOUT2. To implement the ratiometric tracking, the ratio of the VOUT2 divider should be exactly the same as the master channel’s feedback divider. By selecting different resistors, the LTC3850-2 can achieve different modes of tracking including the two in Figure 5. So which mode should be programmed? While either mode in Figure 5 satisfies most practical applications, some tradeoffs exist. The ratiometric mode saves a pair of resistors, but the coincident mode offers better output regulation. This can be better understood with the help of Figure 7. At the input stage of the slave channel’s error amplifier, two common anode diodes are used to clamp the equivalent reference voltage and an additional diode is used to match the shifted common mode voltage. The top two current sources are of the same amplitude. In the coincident mode, the TK/SS voltage is substantially higher than 0.8V at steady state and effectively turns off D1. D2 and D3 will therefore conduct the same current and offer tight matching between VFB2 and the internal precision 0.8V reference. In the ratiometric mode, however, TK/SS equals 0.8V at steady state. D1 will divert part of the bias current to make VFB2 slightly lower than 0.8V. Although this error is minimized by the exponential I-V characteristic of the diode, it does impose a finite amount of output voltage deviation. Furthermore, when the master channel’s output experiences dynamic excursion (under load transient, for example), the slave channel output will be affected as well. For better output regulation, use the coincident tracking mode instead of ratiometric. INTVCC Regulators and EXTVCC The LTC3850-2 features an NPN linear regulator that supplies power to INTVCC from the VIN supply. INTVCC powers the gate drivers and much of the LTC3850-2’s internal circuitry. The linear regulator regulates the voltage at the INTVCC pin to 5V when VIN is greater than 6.5V. EXTVCC connects to INTVCC through a P-channel MOSFET and can supply the needed power when its voltage is higher than 4.7V. Each of these can supply a peak current of 100mA and must be bypassed to ground with a minimum of 1μF ceramic capacitor or low ESR electrolytic capacitor. No matter what type of bulk capacitor is used, an additional 0.1μF ceramic capacitor placed directly adjacent to the INTVCC and PGND pins is highly recommended. Good bypassing is needed to supply the high transient currents required by the MOSFET gate drivers and to prevent interaction between the channels. 38502f 17 LTC3850-2 APPLICATIONS INFORMATION VOUT1 OUTPUT VOLTAGE OUTPUT VOLTAGE VOUT1 VOUT2 TIME VOUT2 TIME 38502 F03a (5a) Coincident Tracking 38502 F03b (5b) Ratiometric Tracking Figure 5. Two Different Modes of Output Voltage Tracking VOUT1 VOUT1 VOUT2 R3 R1 R3 TO VFB1 PIN TO TK/SS2 PIN R4 TO TK/SS2 PIN TO VFB2 PIN R2 VOUT2 R1 R4 R2 R3 TO VFB1 PIN TO VFB2 PIN R4 38502 F06 (6a) Coincident Tracking Setup (6b) Ratiometric Tracking Setup Figure 6. Setup for Coincident and Ratiometric Tracking I I + D1 D2 EA2 TK/SS2 – 0.8V VFB2 D3 38502 F07 Figure 7. Equivalent Input Circuit of Error Amplifier 38502f 18 LTC3850-2 APPLICATIONS INFORMATION High input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maximum junction temperature rating for the LTC3850-2 to be exceeded. The INTVCC current, which is dominated by the gate charge current, may be supplied by either the 5V linear regulator or EXTVCC. When the voltage on the EXTVCC pin is less than 4.7V, the linear regulator is enabled. Power dissipation for the IC in this case is highest and is equal to VIN • IINTVCC. The gate charge current is dependent on operating frequency as discussed in the Efficiency Considerations section. The junction temperature can be estimated by using the equations given in Note 3 of the Electrical Characteristics. For example, the LTC3850-2 INTVCC current is limited to less than 24mA from a 24V supply in the GN package and not using the EXTVCC supply: TJ = 70°C + (24mA)(24V)(95°C/W) = 125°C To prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous conduction mode (MODE/PLLIN = SGND) at maximum VIN. When the voltage applied to EXTVCC rises above 4.7V, the INTVCC linear regulator is turned off and the EXTVCC is connected to the INTVCC. The EXTVCC remains on as long as the voltage applied to EXTVCC remains above 4.5V. Using the EXTVCC allows the MOSFET driver and control power to be derived from one of the LTC3850-2’s switching regulator outputs during normal operation and from the INTVCC when the output is out of regulation(e.g., start-up, short-circuit). If more current is required through the EXTVCC than is specified, an external Schottky diode can be added between the EXTVCC and INTVCC pins. Do not apply more than 6V to the EXTVCC pin and make sure that EXTVCC < VIN. Significant efficiency and thermal gains can be realized by powering INTVCC from the output, since the VIN current resulting from the driver and control currents will be scaled by a factor of (Duty Cycle)/(Switcher Efficiency). Tying the EXTVCC pin to a 5V supply reduces the junction temperature in the previous example from 125°C to: TJ = 70°C + (24mA)(5V)(95°C/W) = 81°C However, for 3.3V and other low voltage outputs, additional circuitry is required to derive INTVCC power from the output. The following list summarizes the four possible connections for EXTVCC: 1. EXTVCC left open (or grounded). This will cause INTVCC to be powered from the internal 5V regulator resulting in an efficiency penalty of up to 10% at high input voltages. 2. EXTVCC connected directly to VOUT. This is the normal connection for a 5V regulator and provides the highest efficiency. 3. EXTVCC connected to an external supply. If a 5V external supply is available, it may be used to power EXTVCC providing it is compatible with the MOSFET gate drive requirements. 4. EXTVCC connected to an output-derived boost network. For 3.3V and other low voltage regulators, efficiency gains can still be realized by connecting EXTVCC to an output-derived voltage that has been boosted to greater than 4.7V. For applications where the main input power is 5V, tie the VIN and INTVCC pins together and tie the combined pins to the 5V input with a 1Ω or 2.2Ω resistor as shown in Figure 8 to minimize the voltage drop caused by the gate charge current. This will override the INTVCC linear regulator and will prevent INTVCC from dropping too low due to the dropout voltage. Make sure the INTVCC voltage is at or exceeds the RDS(ON) test voltage for the MOSFET which is typically 4.5V for logic level devices. LTC3850-2 VIN RVIN INTVCC 5V CINTVCC 4.7μF 1Ω + CIN 38502 F08 Figure 8. Setup for a 5V Input 38502f 19 LTC3850-2 APPLICATIONS INFORMATION Topside MOSFET Driver Supply (CB, DB) CIN and COUT Selection External bootstrap capacitors CB connected to the BOOST pins supply the gate drive voltages for the topside MOSFETs. Capacitor CB in the Functional Diagram is charged though external diode DB from INTVCC when the SW pin is low. When one of the topside MOSFETs is to be turned on, the driver places the CB voltage across the gate source of the desired MOSFET. This enhances the MOSFET and turns on the topside switch. The switch node voltage, SW, rises to VIN and the BOOST pin follows. With the topside MOSFET on, the boost voltage is above the input supply: VBOOST = VIN + VINTVCC. The value of the boost capacitor CB needs to be 100 times that of the total input capacitance of the topside MOSFET(s). The reverse breakdown of the external Schottky diode must be greater than VIN(MAX). When adjusting the gate drive level, the final arbiter is the total input current for the regulator. If a change is made and the input current decreases, then the efficiency has improved. If there is no change in input current, then there is no change in efficiency. The selection of CIN is simplified by the 2-phase architecture and its impact on the worst-case RMS current drawn through the input network (battery/fuse/capacitor). It can be shown that the worst-case capacitor RMS current occurs when only one controller is operating. The controller with the highest (VOUT)(IOUT) product needs to be used in the formula below to determine the maximum RMS capacitor current requirement. Increasing the output current drawn from the other controller will actually decrease the input RMS ripple current from its maximum value. The out-ofphase technique typically reduces the input capacitor’s RMS ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. Undervoltage Lockout The LTC3850-2 has two functions that help protect the controller in case of undervoltage conditions. A precision UVLO comparator constantly monitors the INTVCC voltage to ensure that an adequate gate-drive voltage is present. It locks out the switching action when INTVCC is below 3V. To prevent oscillation when there is a disturbance on the INTVCC, the UVLO comparator has 500mV of precision hysteresis. Another way to detect an undervoltage condition is to monitor the VIN supply. Because the RUN pins have a precision turn-on reference of 1.2V, one can use a resistor divider to VIN to turn on the IC when VIN is high enough. An extra 4.5μA of current flows out of the RUN pin once the RUN pin voltage passes 1.2V. One can program the hysteresis of the run comparator by adjusting the values of the resistive divider. For accurate VIN undervoltage detection, VIN needs to be higher than 4V. In continuous mode, the source current of the top MOSFET is a square wave of duty cycle (VOUT)/(VIN). To prevent large voltage transients, a low ESR capacitor sized for the maximum RMS current of one channel must be used. The maximum RMS capacitor current is given by: CIN Required IRMS ≈ 1/2 IMAX ⎡⎣( VOUT ) ( VIN – VOUT ) ⎤⎦ VIN This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturers’ ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may be paralleled to meet size or height requirements in the design. Due to the high operating frequency of the LTC3850-2, ceramic capacitors can also be used for CIN. Always consult the manufacturer if there is any question. The benefit of the LTC3850-2 2-phase operation can be calculated by using the equation above for the higher power controller and then calculating the loss that would have resulted if both controller channels switched on at the same time. The total RMS power lost is lower when 38502f 20 LTC3850-2 APPLICATIONS INFORMATION both controllers are operating due to the reduced overlap of current pulses required through the input capacitor’s ESR. This is why the input capacitor’s requirement calculated above for the worst-case controller is adequate for the dual controller design. Also, the input protection fuse resistance, battery resistance, and PC board trace resistance losses are also reduced due to the reduced peak currents in a 2phase system. The overall benefit of a multiphase design will only be fully realized when the source impedance of the power supply/battery is included in the efficiency testing. The sources of the top MOSFETs should be placed within 1cm of each other and share a common CIN(s). Separating the sources and CIN may produce undesirable voltage and current resonances at VIN. A small (0.1μF to 1μF) bypass capacitor between the chip VIN pin and ground, placed close to the LTC3850-2, is also suggested. A 2.2Ω – 10Ω resistor placed between CIN (C1) and the VIN pin provides further isolation between the two channels. The selection of COUT is driven by the effective series resistance (ESR). Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple (ΔVOUT) is approximated by: ⎛ 1 ⎞ ΔVOUT ≈IRIPPLE ⎜ ESR + 8fCOUT ⎟⎠ ⎝ where f is the operating frequency, COUT is the output capacitance and IRIPPLE is the ripple current in the inductor. The output ripple is highest at maximum input voltage since IRIPPLE increases with input voltage. VOUT RB 1/2 LTC3850-2 CFF VFB RA 38502 F09 Figure 9. Setting Output Voltage To improve the frequency response, a feed-forward capacitor, CFF , may be used. Great care should be taken to route the VFB line away from noise sources, such as the inductor or the SW line. Fault Conditions: Current Limit and Current Foldback The LTC3850-2 includes current foldback to help limit load current when the output is shorted to ground. If the output falls below 50% of its nominal output level, then the maximum sense voltage is progressively lowered from its maximum programmed value to one-third of the maximum value. Foldback current limiting is disabled during the soft-start or tracking up. Under short-circuit conditions with very low duty cycles, the LTC3850-2 will begin cycle skipping in order to limit the short-circuit current. In this situation the bottom MOSFET will be dissipating most of the power but less than in normal operation. The short-circuit ripple current is determined by the minimum on-time tON(MIN) of the LTC3850-2 (≈ 90ns), the input voltage and inductor value: ΔIL(SC) = tON(MIN) • VIN L The resulting short-circuit current is: Setting Output Voltage The LTC3850-2 output voltages are each set by an external feedback resistive divider carefully placed across the output, as shown in Figure 9. The regulated output voltage is determined by: ⎛ R ⎞ VOUT = 0.8V • ⎜ 1+ B ⎟ ⎝ R ⎠ A ISC = 1/3 VSENSE(MAX) RSENSE 1 – ΔIL(SC) 2 Phase-Locked Loop and Frequency Synchronization The LTC3850-2 has a phase-locked loop (PLL) comprised of an internal voltage-controlled oscillator (VCO) and a phase detector. This allows the turn-on of the top MOSFET of controller 1 to be locked to the rising edge of an external clock signal applied to the MODE/PLLIN pin. The turn-on 38502f 21 LTC3850-2 APPLICATIONS INFORMATION of controller 2’s top MOSFET is thus 180 degrees outof-phase with the external clock. The phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. This type of phase detector does not exhibit false lock to harmonics of the external clock. The output of the phase detector is a pair of complementary current sources that charge or discharge the external filter network connected to the FREQ/PLLFLTR pin. The relationship between the voltage on the FREQ/PLLFLTR pin and operating frequency is shown in Figure 10 and specified in the Electrical Characteristics table. Note that the LTC3850-2 can only be synchronized to an external clock whose frequency is within range of the LTC3850-2’s internal VCO. This is guaranteed to be between 250kHz and 780kHz. A simplified block diagram is shown in Figure 11. 900 800 FREQUENCY (kHz) 700 600 If no clock is applied to MODE/PLLIN pin, the FREQ/ PLLFLTR pin will be high impedance. If the external clock frequency is greater than the internal oscillator’s frequency, fOSC , then current is sourced continuously from the phase detector output, pulling up the FREQ/PLLFLTR pin. When the external clock frequency is less than fOSC , current is sunk continuously, pulling down the FREQ/PLLFLTR pin. If the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. The voltage on the FREQ/PLLFLTR pin is adjusted until the phase and frequency of the internal and external oscillators are identical. At the stable operating point, the phase detector output is high impedance and the filter capacitor CLP holds the voltage. The loop filter components, CLP and RLP, smooth out the current pulses from the phase detector and provide a stable input to the voltage-controlled oscillator. The filter components CLP and RLP determine how fast the loop acquires lock. Typically RLP = 10k and CLP is 2200pF to 0.01μF. Typically, the external clock (on MODE/PLLIN pin) input high threshold is 1.6V, while the input low thres-hold is 1V. 500 400 300 Minimum On-Time Considerations 200 Minimum on-time tON(MIN) is the smallest time duration that the LTC3850-2 is capable of turning on the top MOSFET. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that 100 0 0 0.5 1 1.5 2 FREQ/PLLFLTR PIN VOLTAGE (V) 2.5 38502 F10 Figure 10. Relationship Between Oscillator Frequency and Voltage at the FREQ/PLLFLTR Pin 2.4V tON(MIN) < RLP VOUT VIN (f) CLP MODE/ PLLIN EXTERNAL OSCILLATOR FREQ/ PLLFLTR DIGITAL PHASE/ FREQUENCY DETECTOR VCO If the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. The output voltage will continue to be regulated, but the ripple voltage and current will increase. The minimum on-time for the LTC3850-2 is approximately 90ns, with reasonably good PCB layout, minimum 30% inductor current ripple and at least 10mV – 15mV ripple 38502 F11 Figure 11. Phase-Locked Loop Block Diagram 38502f 22 LTC3850-2 APPLICATIONS INFORMATION on the current sense signal. The minimum on-time can be affected by PCB switching noise in the voltage and current loop. As the peak sense voltage decreases the minimum on-time gradually increases to 130ns. This is of particular concern in forced continuous applications with low ripple current at light loads. If the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3850-2 circuits: 1) IC VIN current, 2) INTVCC regulator current, 3) I2R losses, 4) Topside MOSFET transition losses. 1. The VIN current is the DC supply current given in the Electrical Characteristics table, which excludes MOSFET driver and control currents. VIN current typically results in a small (<0.1%) loss. 2. INTVCC current is the sum of the MOSFET driver and control currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from INTVCC to ground. The resulting dQ/dt is a current out of INTVCC that is typically much larger than the control circuit current. In continuous mode, IGATECHG = f(QT + QB), where QT and QB are the gate charges of the topside and bottom side MOSFETs. Supplying INTVCC power through EXTVCC from an output-derived source will scale the VIN current required for the driver and control circuits by a factor of (Duty Cycle)/(Efficiency). For example, in a 20V to 5V application, 10mA of INTVCC current results in approximately 2.5mA of VIN current. This reduces the mid-current loss from 10% or more (if the driver was powered directly from VIN) to only a few percent. 3. I2R losses are predicted from the DC resistances of the fuse (if used), MOSFET, inductor, current sense resistor. In continuous mode, the average output current flows through L and RSENSE, but is “chopped” between the topside MOSFET and the synchronous MOSFET. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L and RSENSE to obtain I2R losses. For example, if each RDS(ON) = 10mΩ, RL = 10mΩ, RSENSE = 5mΩ, then the total resistance is 25mΩ. This results in losses ranging from 2% to 8% as the output current increases from 3A to 15A for a 5V output, or a 3% to 12% loss for a 3.3V output. Efficiency varies as the inverse square of VOUT for the same external components and output power level. The combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4. Transition losses apply only to the topside MOSFET(s), and become significant only when operating at high input voltages (typically 15V or greater). Transition losses can be estimated from: Transition Loss = (1.7) VIN2 IO(MAX) CRSS f Other “hidden” losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. It is very important to include these “system” level losses during the design phase. The internal battery and fuse resistance losses can be minimized by making sure that CIN has adequate charge storage and very low ESR at the switching frequency. A 25W supply will typically require 38502f 23 LTC3850-2 APPLICATIONS INFORMATION a minimum of 20μF to 40μF of capacitance having a maximum of 20mΩ to 50mΩ of ESR. The LTC3850-2 2-phase architecture typically halves this input capacitance requirement over competing solutions. Other losses including Schottky conduction losses during dead time and inductor core losses generally account for less than 2% total additional loss. Checking Transient Response The regulator loop response can be checked by looking at the load current transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to ΔILOAD (ESR), where ESR is the effective series resistance of COUT. ΔILOAD also begins to charge or discharge COUT generating the feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state value. During this recovery time VOUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem. The availability of the ITH pin not only allows optimization of control loop behavior but also provides a DC coupled and AC filtered closed loop response test point. The DC step, rise time and settling at this test point truly reflects the closed loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The ITH external components shown in the Typical Application circuit will provide an adequate starting point for most applications. The ITH series RC-CC filter sets the dominant pole-zero loop compensation. The values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be selected because the various types and values determine the loop gain and phase. An output current pulse of 20% to 80% of full-load current having a rise time of 1μs to 10μs will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. Placing a power MOSFET directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. The initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. This is why it is better to look at the ITH pin signal which is in the feedback loop and is the filtered and compensated control loop response. The gain of the loop will be increased by increasing RC and the bandwidth of the loop will be increased by decreasing CC. If RC is increased by the same factor that CC is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. A second, more severe transient is caused by switching in loads with large (>1μF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT , causing a rapid drop in VOUT . No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. If the ratio of CLOAD to COUT is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 • CLOAD. Thus a 10μF capacitor would require a 250μs rise time, limiting the charging current to about 200mA. 38502f 24 LTC3850-2 APPLICATIONS INFORMATION PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the IC. These items are also illustrated graphically in the layout diagram of Figure 12. Figure 13 illustrates the current waveforms present in the various branches of the 2-phase synchronous regulators operating in the continuous mode. Check the following in your layout: 1. Are the top N-channel MOSFETs M1 and M3 located within 1 cm of each other with a common drain connection at CIN? Do not attempt to split the input decoupling for the two channels as it can cause a large resonant loop. 2. Are the signal and power grounds kept separate? The combined IC signal ground pin and the ground return of CINTVCC must return to the combined COUT (–) terminals. The VFB and ITH traces should be as short as possible. The path formed by the top N-channel MOSFET, Schottky diode and the CIN capacitor should have short leads and PC trace lengths. The output capacitor (–) terminals should be connected as close as possible to the (–) terminals of the input capacitor by placing the capacitors next to each other and away from the Schottky loop described above. 3. Do the LTC3850-2 VFB pins’ resistive dividers connect to the (+) terminals of COUT? The resistive divider must be connected between the (+) terminal of COUT and signal ground. The feedback resistor connections should not be along the high current input feeds from the input capacitor(s). 4. Are the SENSE+ and SENSE– leads routed together with minimum PC trace spacing? The filter capacitor between SENSE+ and SENSE– should be as close as possible to the IC. Ensure accurate current sensing with Kelvin connections at the sense resistor or inductor, whichever is used for current sensing. 5. Is the INTVCC decoupling capacitor connected close to the IC, between the INTVCC and the power ground pins? This capacitor carries the MOSFET drivers current peaks. An additional 1μF ceramic capacitor placed immediately next to the INTVCC and PGND pins can help improve noise performance substantially. 6. Keep the switching nodes (SW1, SW2), top gate nodes (TG1, TG2), and boost nodes (BOOST1, BOOST2) away from sensitive small-signal nodes, especially from the opposite channel’s voltage and current sensing feedback pins. All of these nodes have very large and fast moving signals and therefore should be kept on the “output side” of the LTC3850-2 and occupy minimum PC trace area. If DCR sensing is used, place the top resistor (Figure 2b, R1) close to the switching node. 7. Use a modified “star ground” technique: a low impedance, large copper area central grounding point on the same side of the PC board as the input and output capacitors with tie-ins for the bottom of the INTVCC decoupling capacitor, the bottom of the voltage feedback resistive divider and the SGND pin of the IC. PC Board Layout Debugging Start with one controller at a time. It is helpful to use a DC-50MHz current probe to monitor the current in the inductor while testing the circuit. Monitor the output switching node (SW pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. Check for proper performance over the operating voltage and current range expected in the application. The frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation threshold—typically 10% of the maximum designed current level in Burst Mode operation. 38502f 25 LTC3850-2 APPLICATIONS INFORMATION TK/SS1 RPU2 PGOOD PGOOD VPULL-UP ITH1 VFB1 L1 SENSE1+ TG1 SENSE1– SW1 VOUT1 CB1 LTC3850-2 fIN M1 BOOST1 PLLLPF RSENSE M2 BG1 D1 1μF CERAMIC MODE/PLLIN COUT1 + VIN RIN CVIN RUN1 PGND RUN2 INTVCC SENSE2+ BG2 VFB2 + SENSE2– CIN CINTVCC COUT2 1μF CERAMIC M3 BOOST2 GND + EXTVCC + VIN SGND M4 D2 CB2 ITH2 TK/SS2 SW2 RSENSE TG2 VOUT2 L2 38502 F12 Figure 12. Recommended Printed Circuit Layout Diagram SW1 L1 D1 RSENSE1 VOUT1 COUT1 RL1 VIN RIN CIN SW2 BOLD LINES INDICATE HIGH SWITCHING CURRENT. KEEP LINES TO A MINIMUM LENGTH. D2 L2 RSENSE2 VOUT2 COUT2 RL2 38502 F13 Figure 13. Branch Current Waveforms 38502f 26 LTC3850-2 APPLICATIONS INFORMATION 4.7μF D3 M1 0.1μF L1 3.3μH 22μF 50V 1μF 2.2Ω VIN PGOOD EXTVCC INTVCC TG1 TG2 BOOST1 SW1 D4 M2 0.1μF L2 2.2μH BOOST2 SW2 LTC3850-2 BG1 6.19k 1% BG2 4.12k 1% 10k, 1% MODE/PLLIN VIN 7V TO 20V PGND FREQ/PLLFLTR 1.33k 1% SENSE2+ – SENSE2– 0.1μF 0.1μF SENSE1 33pF VOUT1 3.3V 5A SENSE1+ RUN1 COUT1 100μF X2 1800pF 20k 1% 4.75k 1% 100pF TK/SS1 33pF RUN2 VFB1 ITH1 63.4k 1% 1.5k 1% VFB2 ITH2 SGND 0.1μF 0.1μF 25.5k 1% 2200pF TK/SS2 3.16k 1% 5.49k 1% 100pF VOUT2 1.8V 5A COUT2 100μF X2 20k 1% 38502 F14 L1, L2: COILTRONICS HCP0703 M1, M2: VISHAY SILICONIX Si4816BDY COUT1, COUT2: TAIYO YUDEN JMK325BJ107MM Figure 14. High Efficiency Dual 500kHz 3.3V/1.8V Step-Down Converter The duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise PCB implementation. Variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. Overcompensation of the loop can be used to tame a poor PC layout if regulator bandwidth optimization is not required. Only after each controller is checked for its individual performance should both controllers be turned on at the same time. A particularly difficult region of operation is when one controller channel is nearing its current comparator trip point when the other channel is turning on its top MOSFET. This occurs around 50% duty cycle on either channel due to the phasing of the internal clocks and may cause minor duty cycle jitter. Reduce VIN from its nominal level to verify operation of the regulator in dropout. Check the operation of the undervoltage lockout circuit by further lowering VIN while monitoring the outputs to verify operation. Investigate whether any problems exist only at higher output currents or only at higher input voltages. If problems coincide with high input voltages and low output currents, look for capacitive coupling between the BOOST, SW, TG, and possibly BG connections and the sensitive voltage and current pins. The capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the IC. This capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. If problems are encountered with high current output loading at lower input voltages, look for inductive coupling between CIN, Schottky and the top MOSFET components to the sensitive current and voltage sensing traces. In addition, investigate common ground path voltage pickup between these components and the SGND pin of the IC. 38502f 27 LTC3850-2 APPLICATIONS INFORMATION Design Example As a design example for a two channel medium current regulator, assume VIN = 12V(nominal), VIN = 20V(maximum), VOUT1 = 3.3V, VOUT2 = 1.8V, IMAX1,2 = 5A, and f = 500kHz (see Figure 14). The regulated output voltages are determined by: ⎛ R ⎞ VOUT = 0.8V • ⎜ 1+ B ⎟ ⎝ RA ⎠ Using 20k 1% resistors from both VFB nodes to ground, the top feedback resistors are (to the nearest 1% standard value) 63.4k and 25.5k. The frequency is set by biasing the FREQ/PLLFLTR pin to 1.2V (see Figure 10), using a divider from INTVCC. This voltage will decrease as VIN approaches 5V, lowering the switching frequency. If a separate 5V supply is connected to EXTVCC, INTVCC will remain at 5V even if VIN decreases. The inductance values are based on a 35% maximum ripple current assumption (1.75A for each channel). The highest value of ripple current occurs at the maximum input voltage: ⎛ VOUT VOUT ⎞ L= ⎟ ⎜ 1− ƒ • ΔIL(MAX) ⎝ VIN(MAX) ⎠ Channel 1 will require 3.2μH, and Channel 2 will require 1.9μH. The next highest standard values are 3.3μH and 2.2μH. At the nominal input voltage (12V), the ripple will be: ΔIL(NOM) = VOUT ⎛ VOUT ⎞ ⎟ ⎜ 1− ƒ•L ⎝ VIN(NOM) ⎠ Channel 1 will have 1.45A (29%) ripple, and Channel 2 will have 1.4A (28%) ripple. The peak inductor current will be the maximum DC value plus one-half the ripple current, or 5.725A for Channel 1 and 5.7A for Channel 2. The minimum on-time occurs on Channel 1 at the maximum VIN, and should not be less than 90ns: tON(MIN) = VOUT VIN(MAX) ƒ = 1.8V = 180ns 20V(500kHz) The equivalent RSENSE resistor value can be calculated by using the minimum value for the maximum current sense threshold (40mV). RSENSE(EQUIV) = VSENSE(MIN) = ΔIL(NOM) ILOAD(MAX) + 2 40mV ≅ 7mΩ 1.5A 5A + 2 The equivalent RSENSE is the same for Channel 2. The Coiltronics (Cooper) HCP0703-2R2 (20mΩ DCRMAX at 20°C) and HCP0703-3R3 (30mΩ DCRMAX at 20°C) are chosen. At 100°C, the estimated maximum DCR values are 26.4mΩ and 39.6mΩ. The divider ratios are: RD = and RSENSE(EQUIV) DCRMAX at TL(MAX) = 7mΩ = 0.26; 26.4mΩ 7mΩ ≅ 0.18 39.6mΩ For each channel, 0.1μF is selected for C1. L 2.2µH = (DCRMAX at 20°C) • C1 20mΩ • 0.1µF 3.3µH = 1.1k ; and = 1.1k 30mΩ • 0.1µF R1||R2 = For channel 1, the DCRSENSE filter/divider values are: R1||R2 1.1k = ≅ 6.19k; RD 0.18 R1 • RD 6.19k • 0.18 R2 = = ≅ 1.33k 1− RD 1− 0.18 R1= 38502f 28 LTC3850-2 APPLICATIONS INFORMATION The power loss in R1 at the maximum input voltage is: PLOSS R1= (VIN(MAX) − VOUT ) • VOUT R1 = (20V − 3.3V) • 3.3V = 9mW 6.19k The power dissipation on the topside MOSFET can be easily estimated. Choosing a Siliconix Si4816BDY dual MOSFET results in: RDS(ON) = 0.023Ω/0.016Ω, CMILLER ≅ 100pF. At maximum input voltage with T(estimated) = 50°C: 3.3V 2 (5) [1+(0.005)(50°C – 25°C)] • 20V ⎞ (0.023Ω) + (20V )2 ⎛⎜⎝ 5A (2Ω)(100pF ) • 2 ⎟⎠ PMAIN = The respective values for Channel 2 are R1 = 4.12k, R2 = 1.5k; and PLOSS R1 = 8mW. Burst Mode operation is chosen for high light load efficiency (Figure 15) by floating the MODE/PLLIN pin. Power loss due to the DCR sensing network is slightly higher at light loads than would have been the case with a suitable sense resistor (7mΩ). At heavier loads, DCR sensing provides higher efficiency. 1 ⎤ ⎡ 1 ⎢ 5 – 2.3 + 2.3 ⎥ ( 500kHz ) = 186mW ⎣ ⎦ A short-circuit to ground will result in a folded back current of: I SC = 100 10 (1/ 3) 50mV – 1 ⎛ 90ns(20V) ⎞ = 2.1A 0.007Ω 2 ⎜⎝ 3.3µH ⎟⎠ DCR 80 7mΩ 1 DCR 70 0.1 60 POWER LOSS (mW) EFFICIENCY (%) 90 50 40 0.01 EFFICIENCY POWER LOSS 0.1 1 LOAD CURRENT (mA) with a typical value of RDS(ON) and δ = (0.005/°C)(20) = 0.1. The resulting power dissipated in the bottom MOSFET is: 20V – 3.3V 2 2.1A ) (1.125) ( 0.016Ω ) ( 20V = 66mW PSYNC = which is less than under full-load conditions. 0.01 10 38502 F15 Figure 15. Design Example Efficiency vs Load CIN is chosen for an RMS current rating of at least 2A at temperature assuming only channel 1 or 2 is on. COUT is chosen with an ESR of 0.02Ω for low output ripple. The output ripple in continuous mode will be highest at the maximum input voltage. The output voltage ripple due to ESR is approximately: VORIPPLE = RESR (ΔIL) = 0.02Ω(1.5A) = 30mVP–P 38502f 29 LTC3850-2 TYPICAL APPLICATIONS VIN 7V TO 24V 22μF 50V 2.2Ω 1μF 4.7μF D3 M1 0.1μF L2 2.2μH TG1 TG2 BOOST1 BOOST2 SW1 SW2 LTC3850-2 BG2 BG1 MODE/PLLIN 10Ω 15pF 10Ω COUT1 220μF SENSE1– SENSE2– L2 3.3μH 10k 1% 10Ω 1000pF RUN1 20k 1% 1000pF 100pF 10k 1% TK/SS1 0.1μF 6mΩ 10pF 10Ω RUN2 EXTVCC VFB2 ITH2 VFB1 ITH1 63.4k 1% + SENSE1+ PGND FREQ/PLLFLTR SENSE2+ M2 0.1μF 1000pF 6mΩ VOUT1 3.3V 5A D4 VIN PGOOD INTVCC SGND 0.1μF 105k 1% 1000pF TK/SS2 3.16k 1% 15k 1% 100pF 20k 1% VOUT2 5V 5A + COUT2 150μF 38502 F16 L1: TDK RLF 7030T-2R2M5R4 L2: TDK ULF10045T-3R3N6R9 COUT1: SANYO 4TPE220MF COUT2: SANYO 6TPE150MI Figure 16. 3.3V/5A, 5V/5A Converter Using Sense Resistors 38502f 30 25.5k 20k C12 100pF C11 1000pF C7 1000pF C6 100pF CSS 0.1μF R18 4.99k R12 7.5k 2.10k C15 47pF C10 33pF C5 0.1μF SENSE2+ SGND SENSE2– TK/SS2 ITH2 VFB2 EXTVCC RPG 100k PGOOD PGOOD SW2 TG2 CVCC 4.7μF CB2 0.1μF D4 CMDSH-3 D3 CMDSH-3 CB1 0.1μF CVIN 1μF M4 RJK0301DPB + 38502 F17 L2 0.68μH R30 4.02k M3 HAT2168H PGND GND M2 RJK0301DPB R27 L1 4.02k 0.68μH M1 HAT2168H Figure 17. 2.5V/15A, 1.8V/15A Converter with DCR Sensing and Coincident Rail Tracking FSW = 350kHz RUN2 BOOST2 PGND BG2 INTVCC VIN VFB1 LTC3850-2 BG1 BOOST1 ITH1 TK/SS1 SENSE1– SENSE1+ RUN1 FREQ/ MODE/ SW1 TG1 PLLFLTR PLLIN L1, L2: VISHAY IHLP5050EZ-01 0.68μH COUT1, COUT2: SANYO 4TPD330M R4 25.5k R3 20k R2 20k R1 43.2k C4 0.1μF 10k + RVIN 2.2Ω COUT2 330μF 4V 2X COUT1 330μF 4V 2X 10μF 2x + VOUT2 1.8V/ 15A VOUT1 2.5V/ 15A CIN 180μF VIN 7V TO 14V LTC3850-2 TYPICAL APPLICATIONS 38502f 31 32 CSS2 0.1μF C12 100pF C11 1000pF C7 1000pF C6 100pF CSS1 0.1μF R18 5.9k R12 5.9k R20 100Ω R10 100Ω R5 10k PLLIN 400kHz C5 1000pF RUN2 EXTVCC RPG 100k PGOOD PGOOD SW2 TG2 BOOST2 PGND BG2 INTVCC CVCC 4.7μF CB2 0.1μF D4 CMDSH-3 D3 CMDSH-3 CB1 0.1μF RVIN 2.2Ω CVIN 1μF M4 RJK0301DPB M3 RJK0305DPB PGND GND M2 RJK0301DPB M1 RJK0305DPB L2 0.4μH L1 0.4μH Figure 18. 1.5V/15A, 1.2V/15A Core-I/O Converter with Sense Resistor Synchronized at 400kHz R22 100Ω SENSE2+ SGND SENSE2– TK/SS2 ITH2 VFB2 VIN VFB1 LTC3850-2 BG1 BOOST1 ITH1 TK/SS1 SENSE1– SENSE1+ RUN1 FREQ/ MODE/ SW1 TG1 PLLFLTR PLLIN L1, L2: VITEC 59PR9875 COUT1, COUT2: 2R5TPE330M9 R4 10k R3 20k R2 20k R1 17.8k C4 1000pF R9 100Ω C2 0.01μF 38502 F18 RSENSE2 0.002Ω RSENSE1 0.002Ω + COUT2 330μF 2.5V 2X COUT1 330μF 2.5V 2X + 10μF 2x + C1 1000pF VOUT2 1.2V/15A VOUT1 1.5V/15A CIN 180μF VIN 7V TO 14V LTC3850-2 TYPICAL APPLICATIONS 38502f LTC3850-2 TYPICAL APPLICATIONS 5V ± 0.5V 4.7μF 6.3V 2x 1Ω 4.7μF D3 M1 TG1 0.1μF L1 0.75μH VIN PGOOD EXTVCC INTVCC BG1 PLLIN 750kHz M2 TG2 BOOST1 SW1 1.2k 1% D4 0.1μF L2 0.75μH BOOST2 SW2 LTC3850-2 MODE/PLLIN BG2 1.2k 1% PGND FREQ/PLLFLTR SENSE1+ 2.94k 1% 0.047μF SENSE1– 47pF VOUT1 1.8V 5A SENSE2+ 0.047μF SENSE2– RUN1 COUT1 100μF X2 2200pF 20k 1% 14k 1% 100pF 0.1μF TK/SS1 100pF RUN2 VFB1 ITH1 25.5k 1% 4.99k 1% VFB2 ITH2 SGND TK/SS2 0.1μF 1nF 10nF 10k 1% 2200pF 14k 1% 100pF 10k 1% COUT2 100μF X2 20k 1% L1, L2: TOKO FDV0630 0.75μH M1, M2: VISHAY SILICONIX Si4816BDY COUT1, COUT2: TAIYO YUDEN JMK325BJ107MM VOUT2 1.2V 5A 38502 F19 Figure 19. 1.8V/5A, 1.2V/5A Core-I/O Converter with a 5V Input Synchronized at 750kHz 38502f 33 LTC3850-2 TYPICAL APPLICATIONS 2.2Ω VIN1 12V VIN2 3.3V 1μF 4.7μF 4.7μF D3 M1 VIN PGOOD EXTVCC INTVCC TG1 0.1μF L1 2.2μH 4.7μF 2x 13.0k TG2 BOOST1 SW1 M2 0.1μF L2 0.75μH BOOST2 SW2 LTC3850-2 BG1 3.74k 1% 10k D4 MODE/PLLIN BG2 PGND 1.2k 1% 10k 1% FREQ/PLLFLTR 1.40k 1% SENSE2+ – SENSE2– 0.1μF SENSE1 47pF VOUT1 2.5V 5A SENSE1+ 0.1μF RUN1 COUT1 100μF X2 2200pF 20k 1% 10k 1% 100pF TK/SS1 0.1μF 100pF RUN2 VFB1 ITH1 43.2k 1% 4.32k 1% VFB2 ITH2 SGND 2200pF TK/SS2 0.1μF 3.16k 1% 6.04k 1% L1: TOKO FDV0630 2.2μH L2: TOKO FDV0630 0.75μH M1, M2: VISHAY SILICONIX Si4816BDY COUT1, COUT2: TAIYO YUDEN JMK325BJ107MM 10k 1% 100pF VOUT2 1.2V 5A COUT2 100μF X2 20k 1% 38502 F20 Figure 20. 2.5V/5A, 1.2V/5A Core-I/O Converter with Dual Inputs 38502f 34 LTC3850-2 PACKAGE DESCRIPTION GN Package 28-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .386 – .393* (9.804 – 9.982) .045 p.005 28 27 26 25 24 23 22 21 20 19 18 17 1615 .254 MIN .033 (0.838) REF .150 – .165 .229 – .244 (5.817 – 6.198) .0165 p.0015 .150 – .157** (3.810 – 3.988) .0250 BSC 1 RECOMMENDED SOLDER PAD LAYOUT .015 p .004 s 45o (0.38 p 0.10) .0075 – .0098 (0.19 – 0.25) 2 3 4 5 6 7 8 9 10 11 12 13 14 .0532 – .0688 (1.35 – 1.75) .004 – .0098 (0.102 – 0.249) 0o – 8o TYP .016 – .050 (0.406 – 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) .008 – .012 (0.203 – 0.305) TYP .0250 (0.635) BSC GN28 (SSOP) 0204 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 38502f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 35 LTC3850-2 TYPICAL APPLICATION 20k 2.55k 10k RUN 1nF RJK0305DPB 0.1μF 7.5k 0.1μF SENSE1– SENSE1+ RUN1 FREQ MODE SW1 TG1 0.1μF 2.21k L1 0.56μH 10μF 2x VIN 7V TO 14V + 180μF RJK0301DPB CMDSH-3 220pF TK/SS1 2.2nF BOOST1 ITH1 BG1 VFB1 VIN 2.74k 20k LTC3850-2 VFB2 2.2Ω INTVCC ITH2 BG2 4.7μF 1μF VOUT 1.1V/30A PGND TK/SS2 100μF 2x CMDSH-3 SENSE2– BOOST2 RJK0305DPB SENSE2+ + SGND RUN2 EXTVCC PGOOD SW2 TG2 0.1μF 0.1μF COUT1 330μF 2.5V 4x L2 0.56μH RJK0301DPB 2.21k PGOOD 20k 100k 38502 TA02 RUN L1, L2: VISHAY IHLP4040DZ-01 0.56μH COUT: SANYO 2R5TPE330M9 FOR SINGLE OUTPUT, DUAL PHASE OPERATION, TIE THE FOLLOWING PINS TOGETHER: TK/SS1 TO TK/SS2 VFB1 TO VFB1 RUN1 TO RUN2 ITH1 TO ITH2 Figure 21. 1.1V/30A Dual Phase Core Converter, FSW = 400kHz RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1625/ LTC1775 No RSENSE™ Current Mode Synchronous Step-Down Controllers 97% Efficiency, No Sense Resistor, 16-Pin SSOP LTC1735 Synchronous Step-Down Switching Regulator Controller Programmable Fixed Frequency from 200kHz to 550kHz LTC1778 No RSENSE Wide Input Range Synchronous Step-Down Controller Up to 97% Efficiency, 4V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ (0.9)(VIN), IOUT Up to 20A, Extremely Fast Transient Response LTC3727A-1 Dual, 2-Phase Synchronous Controller Very Low Dropout; VOUT ≤ 14V, 4V ≤ VIN ≤ 36V LTC3728 2-Phase 550kHz, Dual Synchronous Step-Down Controller 20A to 200A PolyPhase® Synchronous Controller QFN and SSOP Packages LTC3729L-6 Expandable from 2-Phase to 12-Phase, 4V ≤ VIN ≤ 30V, 0.6V ≤ VOUT ≤ 7V LTC3731 3-Phase, Single Output From 250kHz to 600kHz Synchronous Step-Down Controller 0.6V ≤ VOUT ≤ 6V, 4.5V ≤ VIN ≤ 32V, Expandable PolyPhase from 3-Phase to 12-Phase LTC3810 100V Current Mode Synchronous Step-Down Switching Controller 0.8V ≤ VOUT ≤ 0.93VIN, 6.2V ≤ VIN ≤ 100V, No RSENSE LTC3826 Low IQ, Dual, 2-Phase Synchronous Step-Down Controller 30μA IQ, 0.8V ≤ VOUT ≤ 10V, 4V ≤ VIN ≤ 36V LTC3828 Dual, 2-Phase Synchronous Step-Down Controller with Tracking Up to Six Phases, 0.8V ≤ VOUT ≤ 7V, 4.5V ≤ VIN ≤ 28V LTC3834/ LTC3834-1 Low IQ, Synchronous Step-Down Controller 30μA IQ, 0.8V ≤ VOUT ≤ 10V, 4V ≤ VIN ≤ 36V LT3845 Low IQ, High Voltage Single Output Synchronous Step-Down DC/DC Controller 1.23V ≤ VOUT ≤ 36V, 4V ≤ VIN ≤ 60V, 120μA IQ LTC3851 High Efficiency Synchronous Step-Down Switching Regulator Controller Single Output Version of LTC3850-2 4V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 5.5V PolyPhase is a registered trademark of Linear Technology Corporation. No RSENSE is a trademark of Linear Technology Corporation. 36 Linear Technology Corporation 38502f LT 0908 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2007