Cypress CY7C1339G-200BGXI 4 - mbit ( 128k x 32 ) pipelined sync sram Datasheet

CY7C1339G
PRELIMINARY
4-Mbit (128K x 32) Pipelined Sync SRAM
Functional Description[1]
Features
• Registered inputs and outputs for pipelined operation
• 128K × 32 common I/O architecture
• 3.3V core power supply
• 2.5V / 3.3V I/O operation
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 2.8 ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
The CY7C1339G SRAM integrates 131,072 x 32 SRAM cells
with advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE1), depth-expansion Chip Enables (CE2 and CE3), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW[A:D], and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
— 4.0 ns (for 133-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel®
Pentium® interleaved or linear burst sequences
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
controlled by the byte write control inputs. GW when active
LOW causes all bytes to be written.
The CY7C1339G operates from a +3.3V core power supply
while all outputs may operate with either a +2.5 or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Lead-Free 100-pin TQFP and 119-ball BGA packages
• “ZZ” Sleep Mode Option
Logic Block Diagram
A 0, A 1, A
A DDRESS
REGISTER
2
A [1:0]
M ODE
A DV
CLK
Q1
BURST
COUNTER
A ND Q0
LOGIC
CLR
A DSC
A DSP
BW D
DQ D
BYTE
W RITE REGISTER
DQ D
BYTE
W RITE DRIVER
BW C
DQ C
BYTE
W RITE REGISTER
DQ C
BYTE
W RITE DRIVER
DQ B
BYTE
W RITE REGISTER
DQ B
BYTE
W RITE DRIVER
BW B
BW A
BW E
ZZ
ENA BLE
REGISTER
SENSE
A M PS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQ A
BYTE
W RITE DRIVER
DQ A
BYTE
W RITE REGISTER
GW
CE 1
CE 2
CE 3
OE
M EM ORY
A RRA Y
INPUT
REGISTERS
PIPELINED
ENABLE
SLEEP
CONTROL
1
Note:
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05520 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised November 10, 2004
PRELIMINARY
CY7C1339G
Selection Guide
250 MHz
200 MHz
166 MHz
133 MHz
Unit
Maximum Access Time
2.6
2.8
3.5
4.0
ns
Maximum Operating Current
325
265
240
225
mA
Maximum CMOS Standby Current
40
40
40
40
mA
Shaded area contains advanced information. Please contact your local Cypress sales representative for availability of these parts.
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
Pin Configurations
BYTE C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100-pin TQFP
CY7C1339G
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
NC
BYTE B
BYTE A
Document #: 38-05520 Rev. *A
NC
NC
VSS
VDD
NC
NC
A
A
A
A
A
A
A
MODE
A
A
A
A
A1
A0
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
BYTE D
NC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
NC
Page 2 of 17
PRELIMINARY
CY7C1339G
Pin Configurations (continued)
119-ball BGA
CY7C1339G (128K × 32)
1
2
3
4
5
6
7
VDDQ
A
NC
NC
CE2
A
A
ADSP
A
A
ADSC
VDD
A
A
VDDQ
A
A
NC
A
NC
NC
D
E
DQC
DQC
NC
DQC
VSS
VSS
NC
CE1
VSS
VSS
NC
DQB
DQB
DQB
F
G
H
J
VDDQ
DQC
DQC
VDDQ
DQC
DQC
DQC
VDD
VSS
BWc
VSS
NC
OE
ADV
GW
VDD
VSS
BWB
VSS
NC
DQB
DQB
DQB
VDD
VDDQ
DQB
DQB
VDDQ
K
DQD
DQD
VSS
CLK
VSS
DQA
DQA
L
DQD
DQD
BWD
NC
BWA
DQA
DQA
M
N
VDDQ
DQD
DQD
DQD
VSS
VSS
BWE
A1
VSS
VSS
DQA
DQA
VDDQ
DQA
P
DQD
NC
VSS
A0
VSS
NC
DQA
R
T
NC
NC
A
MODE
VDD
A
A
NC
A
A
NC
NC
NC
ZZ
U
VDDQ
NC
NC
NC
NC
NC
VDDQ
A
B
C
Pin Definitions
I/O
Description
A0, A1, A
Name
InputSynchronous
Address Inputs used to select one of the 128K address locations. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1, A0
are fed to the two-bit counter..
BWA,BWB
InputSynchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
GW
InputSynchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE).
BWE
InputSynchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
CLK
InputClock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
BWC,BWD
CE1
CE2
CE3
OE
InputSynchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only
when a new external address is loaded.
InputChip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE3 to select/deselect the device.CE2 is sampled only when a new external address is
loaded.
InputChip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE2 to select/deselect the device. CE3 is sampled only when a new external address is
loaded.Not connected for BGA. Where referenced, CE3 is assumed active throughout this
document for BGA.
InputOutput Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
Asynchronous LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the first clock of a read cycle when emerging from a
deselected state.
Document #: 38-05520 Rev. *A
Page 3 of 17
PRELIMINARY
CY7C1339G
Pin Definitions (continued)
Name
I/O
Description
ADV
InputSynchronous
Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
automatically increments the address in a burst cycle.
ADSP
InputSynchronous
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A1, A0
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
InputSynchronous
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A1, A0
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized.
ZZ
InputZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical
Asynchronous “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or
left floating. ZZ pin has an internal pull-down.
DQs
I/OSynchronous
VDD
VSS
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the read cycle. The direction
of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When
HIGH, DQs are placed in a tri-state condition.
Power Supply Power supply inputs to the core of the device.
Ground
Ground for the core of the device.
VDDQ
I/O Power
Supply
Power supply for the I/O circuitry.
VSSQ
I/O Ground
Ground for the I/O circuitry.
MODE
InputStatic
NC
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left
floating selects interleaved burst sequence. This is a strap pin and should remain static during
device operation. Mode Pin has an internal pull-up.
No Connects. Not internally connected to the die
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (tCO) is 2.6 ns
(250-MHz device).
The CY7C1339G supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write
Enable (GW) overrides all Byte Write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
Document #: 38-05520 Rev. *A
selection and output tri-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE2, CE3 are all asserted active, and (3) the Write
signals (GW, BWE) are all deserted HIGH. ADSP is ignored if
CE1 is HIGH. The address presented to the address inputs (A)
is stored into the address advancement logic and the Address
Register while being presented to the memory array. The
corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 2.6 ns (250-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always tri-stated during the first cycle of the access. After the
first cycle of the access, the outputs are controlled by the OE
signal. Consecutive single Read cycles are supported. Once
the SRAM is deselected at clock rise by the chip select and
either ADSP or ADSC signals, its output will tri-state immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) CE1, CE2, CE3 are all asserted active. The address
presented to A is loaded into the address register and the
Page 4 of 17
PRELIMINARY
address advancement logic while being delivered to the
memory array. The Write signals (GW, BWE, and BW[A:D]) and
ADV inputs are ignored during this first cycle.
ADSP-triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the corresponding address location in the memory array. If GW is HIGH,
then the Write operation is controlled by BWE and BW[A:D]
signals. The CY7C1339G provides Byte Write capability that
is described in the Write Cycle Descriptions table. Asserting
the Byte Write Enable input (BWE) with the selected Byte
Write (BW[A:D]) input, will selectively write to only the desired
bytes. Bytes not selected during a Byte Write operation will
remain unaltered. A synchronous self-timed Write mechanism
has been provided to simplify the Write operations.
Because the CY7C1339G is a common I/O device, the Output
Enable (OE) must be deserted HIGH before presenting data
to the DQs inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQs are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and
(4) the appropriate combination of the Write inputs (GW, BWE,
and BW[A:D]) are asserted active to conduct a Write to the
desired byte(s). ADSC-triggered Write accesses require a
single clock cycle to complete. The address presented to A is
loaded into the address register and the address
advancement logic while being delivered to the memory array.
The ADV input is ignored during this cycle. If a global Write is
conducted, the data presented to the DQs is written into the
corresponding address location in the memory core. If a Byte
Write is conducted, only the selected bytes are written. Bytes
not selected during a Byte Write operation will remain
unaltered. A synchronous self-timed Write mechanism has
been provided to simplify the Write operations.
Because the CY7C1339G is a common I/O device, the Output
Enable (OE) must be deserted HIGH before presenting data
to the DQs inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQs are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE.
CY7C1339G
Burst Sequences
The CY7C1339G provides a two-bit wraparound counter, fed
by A1, A0, that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
IDDZZ
Snooze mode standby current
ZZ > VDD – 0.2V
40
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2V
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2V
tZZI
ZZ active to snooze current
This parameter is sampled
tRZZI
ZZ Inactive to exit snooze current
This parameter is sampled
Document #: 38-05520 Rev. *A
2tCYC
ns
2tCYC
0
ns
ns
Page 5 of 17
PRELIMINARY
CY7C1339G
Truth Table [ 2, 3, 4, 5, 6, 7]
Operation
Add. Used
CE1 CE2 CE3 ZZ
H
X
X
L
Deselect Cycle, Power-down
None
Deselect Cycle, Power-down
None
L
L
X
Deselect Cycle, Power-down
None
L
X
Deselect Cycle, Power-down
None
L
WRITE OE CLK
X
X L-H
DQ
ADSP
X
ADSC
L
ADV
X
L
L
X
X
X
X
L-H
tri-state
H
L
L
X
X
X
X
L-H
tri-state
L
X
L
H
L
X
X
X
L-H
tri-state
tri-state
Deselect Cycle, Power-down
None
L
X
H
L
H
L
X
X
X
L-H
tri-state
Snooze Mode, Power-down
None
X
X
X
H
X
X
X
X
X
X
tri-state
READ Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
L
L-H
Q
READ Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
H
L-H
tri-state
WRITE Cycle, Begin Burst
External
L
H
L
L
H
L
X
L
X
L-H
D
READ Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
L
L-H
Q
READ Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
H
L-H
tri-state
Next
X
X
X
L
H
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
READ Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L-H
tri-state
READ Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L-H
tri-state
WRITE Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L-H
D
WRITE Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L-H
D
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L-H
tri-state
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L-H
tri-state
WRITE Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L-H
D
WRITE Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L-H
D
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW= L. WRITE = H when all Byte write enable signals
(BWA, BWB, BWC, BWD), BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has only 2 chip selects CE1 and CE2.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: D]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05520 Rev. *A
Page 6 of 17
PRELIMINARY
CY7C1339G
Partial Truth Table for Read/Write [2, 8]
Function
Read
GW
H
BWE
H
BWD
X
BWC
X
BWB
X
BWA
X
Read
H
L
H
H
H
H
Write Byte A – DQA
Write Byte B – DQB
H
L
H
H
H
L
H
L
H
H
L
H
Write Bytes B, A
H
L
H
H
L
L
Write Byte C– DQC
H
L
H
L
H
H
Write Bytes C, A
H
L
H
L
H
L
Write Bytes C, B
H
L
H
L
L
H
Write Bytes C, B, A
H
L
H
L
L
L
Write Byte D– DQD
H
L
L
H
H
H
Write Bytes D, A
H
L
L
H
H
L
Write Bytes D, B
H
L
L
H
L
H
Write Bytes D, B, A
H
L
L
H
L
L
Write Bytes D, C
H
L
L
L
H
H
Write Bytes D, C, A
H
L
L
L
H
L
Write Bytes D, C, B
H
L
L
L
L
H
Write All Bytes
H
L
L
L
L
L
Write All Bytes
L
X
X
X
X
X
Note:
8.Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.
Document #: 38-05520 Rev. *A
Page 7 of 17
PRELIMINARY
Maximum Ratings
CY7C1339G
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Latch-up Current.................................................... > 200 mA
Storage Temperature ................................. –65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
Range
Ambient
Temperature
DC Voltage Applied to Outputs
in tri-state ............................................ –0.5V to VDDQ + 0.5V
Commercial
0°C to +70°C
Industrial
VDD
VDDQ
3.3V –5%/+10% 2.5V –5%
to VDD
–40°C to +85°C
DC Input Voltage....................................–0.5V to VDD + 0.5V
Electrical Characteristics Over the Operating Range
Parameter
Description
[9, 10]
Test Conditions
Min.
Max.
Unit
VDD
Power Supply Voltage
3.135
3.6
V
VDDQ
I/O Supply Voltage
2.375
VDD
V
VOH
Output HIGH Voltage
VOL
VIH
VIL
IX
Output LOW Voltage
Input HIGH
Input LOW
Voltage[9]
Voltage[9]
Input Load Current
except ZZ and MODE
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
2.4
V
VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA
2.0
V
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
0.4
V
VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA
0.4
V
VDDQ = 3.3V
2.0
VDD + 0.3V
V
VDDQ = 2.5V
1.7
VDD + 0.3V
V
VDDQ = 3.3V
–0.3
0.8
V
VDDQ = 2.5V
–0.3
0.7
V
–5
5
µA
GND ≤ VI ≤ VDDQ
Input = VDD
Input Current of ZZ
5
Input = VSS
IOZ
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
VDD Operating Supply
Current
ISB1
Automatic CE
Power-down
Current—TTL Inputs
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
30
5
µA
325
mA
5-ns cycle, 200 MHz
265
mA
6-ns cycle, 166 MHz
240
mA
7.5-ns cycle, 133 MHz
225
mA
4-ns cycle, 250 MHz
120
mA
5-ns cycle, 200 MHz
110
mA
6-ns cycle, 166 MHz
100
mA
–5
7.5-ns cycle, 133 MHz
90
mA
All speeds
40
mA
105
mA
95
mA
VDD = Max, Device Deselected,
Automatic CE
Power-down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
Current—CMOS Inputs f = 0
ISB3
VDD = Max, Device Deselected, or 4-ns cycle, 250 MHz
Automatic CE
Power-down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V 5-ns cycle, 200 MHz
Current—CMOS Inputs f = fMAX = 1/tCYC
6-ns cycle, 166 MHz
Automatic CE
Power-down
Current—TTL Inputs
Document #: 38-05520 Rev. *A
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0
µA
4-ns cycle, 250 MHz
ISB2
ISB4
µA
µA
–5
Input = VDD
IDD
µA
–30
Input Current of MODE Input = VSS
85
mA
7.5-ns cycle, 133 MHz
75
mA
All Speeds
45
mA
Page 8 of 17
PRELIMINARY
CY7C1339G
Electrical Characteristics Over the Operating Range (continued)[9, 10]
Parameter
Description
Test Conditions
Min.
Max.
Unit
Shaded area contains advanced information.
Notes:
9. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2).
10. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200ms. During this time VIH < VDD and VDDQ < VDD.
Thermal Resistance[11]
Parameter
ΘJA
Description
Test Conditions
Thermal Resistance
(Junction to Ambient)
ΘJC
TQFP
Package
BGA
Package
Unit
TBD
TBD
°C/W
TBD
TBD
°C/W
Test conditions follow standard test
methods and procedures for
measuring thermal impedance, per
EIA / JESD51.
Thermal Resistance
(Junction to Case)
Capacitance[11]
Parameter
Description
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CI/O
Input/Output Capacitance
TQFP
Package
Test Conditions
TA = 25°C, f = 1 MHz,
VDD = 3.3V.
VDDQ = 3.3V
BGA
Package
Unit
5
5
pF
5
5
pF
5
7
pF
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50Ω
Z0 = 50Ω
10%
GND
5 pF
R = 351Ω
VT = 1.5V
INCLUDING
JIG AND
SCOPE
(a)
(c)
R = 1667Ω
2.5V
OUTPUT
10%
R =1538Ω
VT = 1.25V
INCLUDING
JIG AND
SCOPE
90%
10%
90%
GND
5 pF
(a)
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50Ω
Z0 = 50Ω
≤ 1ns
≤ 1ns
(b)
2.5V I/O Test Load
90%
10%
90%
(b)
≤ 1ns
≤ 1ns
(c)
Note:
11. Tested initially and after any design or process change that may affect these parameters
Document #: 38-05520 Rev. *A
Page 9 of 17
PRELIMINARY
CY7C1339G
Switching Characteristics Over the Operating Range[12, 13, 14, 15, 16, 17]
250 MHz
Parameter
tPOWER
Description
VDD(Typical) to the first Access[12]
Min.
Max
200 MHz
Min.
Max
166 MHz
Min.
Max
133 MHz
Min.
Max
Unit
1
1
1
1
ms
Clock
tCYC
Clock Cycle Time
4.0
5.0
6.0
7.5
ns
tCH
Clock HIGH
1.7
2.0
2.5
3.0
ns
tCL
Clock LOW
1.7
2.0
2.5
3.0
ns
Output Times
tCO
Data Output Valid After CLK Rise
tDOH
Data Output Hold After CLK Rise
tCLZ
Clock to Low-Z[13, 14, 15]
tCHZ
High-Z[13, 14, 15]
tOEV
tOELZ
tOEHZ
Clock to
OE LOW to Output Valid
OE LOW to Output Low-Z[13, 14, 15]
2.6
2.8
3.5
4.0
ns
1.0
1.0
1.5
1.5
ns
0
0
0
0
ns
2.6
2.8
3.5
4.0
ns
2.6
2.8
3.5
4.0
ns
4.0
ns
0
[13, 14, 15]
0
2.6
OE HIGH to Output High-Z
0
2.8
0
3.5
ns
Set-up Times
tAS
Address Set-up Before CLK Rise
1.2
1.2
1.5
1.5
ns
tADS
ADSC, ADSP Set-up Before CLK Rise
1.2
1.2
1.5
1.5
ns
1.2
1.5
1.5
ns
tWES
ADV Set-up Before CLK Rise
GW, BWE, BWX Set-up Before CLK Rise
1.2
1.2
1.2
1.5
1.5
ns
tDS
Data Input Set-up Before CLK Rise
1.2
1.2
1.5
1.5
ns
tCES
Chip Enable Set-Up Before CLK Rise
1.2
1.2
1.5
1.5
ns
Address Hold After CLK Rise
0.3
0.5
0.5
0.5
ns
0.5
0.5
0.5
ns
0.3
0.5
0.5
0.5
ns
tWEH
ADSP , ADSC Hold After CLK Rise
ADV Hold After CLK Rise
GW,BWE, BWX Hold After CLK Rise
0.3
0.3
0.5
0.5
0.5
ns
tDH
Data Input Hold After CLK Rise
0.3
0.5
0.5
0.5
ns
tCEH
Chip Enable Hold After CLK Rise
0.3
0.5
0.5
0.5
ns
tADVS
Hold Times
tAH
tADH
tADVH
Shaded areas contain advance information.
Notes:
12. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write
operation can be initiated.
13. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state
voltage.
14. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the
same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is
designed to achieve High-Z prior to Low-Z under the same system conditions
15. This parameter is sampled and not 100% tested.
16. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
17. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05520 Rev. *A
Page 10 of 17
PRELIMINARY
CY7C1339G
Switching Waveforms
Read Cycle Timing[18]
t CYC
CLK
t
CH
t
ADS
t
CL
t
ADH
ADSP
tADS
tADH
ADSC
tAS
tAH
A1
ADDRESS
A2
tWES
A3
Burst continued with
new base address
tWEH
GW, BWE,
BW[A:D]
tCES
Deselect
cycle
tCEH
CE
tADVS tADVH
ADV
ADV
suspends
burst.
OE
t OEHZ
t CLZ
Data Out (Q)
High-Z
Q(A1)
tOEV
tCO
t OELZ
tDOH
Q(A2)
t CHZ
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
t CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Notes:
18. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
19. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW.
Document #: 38-05520 Rev. *A
Page 11 of 17
PRELIMINARY
CY7C1339G
Switching Waveforms (continued)
Write Cycle Timing[18, 19]
t CYC
CLK
tCH
tADS
tCL
tADH
ADSP
tADS
ADSC extends burst
tADH
tADS
tADH
ADSC
tAS
tAH
A1
ADDRESS
A2
A3
Byte write signals are
ignored for first cycle when
ADSP initiates burst
tWES tWEH
BWE,
BW[A :D]
tWES tWEH
GW
tCES
tCEH
CE
t
t
ADVS ADVH
ADV
ADV suspends burst
OE
tDS
Data In (D)
High-Z
t
OEHZ
tDH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Document #: 38-05520 Rev. *A
Extended BURST WRITE
UNDEFINED
Page 12 of 17
PRELIMINARY
CY7C1339G
Switching Waveforms (continued)
Read/Write Cycle Timing[18, 20, 21]
tCYC
CLK
tCL
tCH
tADS
tADH
tAS
tAH
ADSP
ADSC
ADDRESS
A1
A2
A3
A4
A5
A6
D(A5)
D(A6)
tWES tWEH
BWE,
BW[A:D]
tCES
tCEH
CE
ADV
OE
tDS
tCO
tDH
tOELZ
Data In (D)
High-Z
tCLZ
Data Out (Q)
High-Z
Q(A1)
Back-to-Back READs
tOEHZ
D(A3)
Q(A2)
Q(A4)
Single WRITE
Q(A4+1)
Q(A4+2)
BURST READ
DON’T CARE
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Note:
20. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
21. GW is HIGH.
Document #: 38-05520 Rev. *A
Page 13 of 17
PRELIMINARY
CY7C1339G
Switching Waveforms (continued)
ZZ Mode Timing [22, 23]
CLK
t
ZZ
I
t
t
ZZ
ZZREC
ZZI
SUPPLY
I
DDZZ
t RZZI
ALL INPUTS
DESELECT or READ Only
(except ZZ)
Outputs (Q)
High-Z
DON’T CARE
Ordering Information
Speed
(MHz)
250
200
166
133
Ordering Code
Package
Name
Package Type
CY7C1339G-250AXC
A101
CY7C1339G-250BGC
BG119
119-ball BGA (14 x 22 x 2.4mm)
CY7C1339G-250BGXC
BG119
Lead-Free 119-ball BGA (14 x 22 x 2.4mm)
Operating
Range
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial
CY7C1339G-250AXI
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
CY7C1339G-250BGI
BG119
119-ball BGA (14 x 22 x 2.4mm)
CY7C1339G-250BGXI
BG119
Lead-Free 119-ball BGA (14 x 22 x 2.4mm)
CY7C1339G-200AXC
A101
CY7C1339G-200BGC
BG119
119-ball BGA (14 x 22 x 2.4mm)
CY7C1339G-200BGXC
BG119
Lead-Free 119-ball BGA (14 x 22 x 2.4mm)
Industrial
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial
CY7C1339G-200AXI
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
CY7C1339G-200BGI
BG119
119-ball BGA (14 x 22 x 2.4mm)
CY7C1339G-200BGXI
BG119
Lead-Free 119-ball BGA (14 x 22 x 2.4mm)
CY7C1339G-166AXC
A101
CY7C1339G-166BGC
BG119
119-ball BGA (14 x 22 x 2.4mm)
CY7C1339G-166BGXC
BG119
Lead-Free 119-ball BGA (14 x 22 x 2.4mm)
Industrial
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial
CY7C1339G-166AXI
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
CY7C1339G-166BGI
BG119
119-ball BGA (14 x 22 x 2.4mm)
CY7C1339G-166BGXI
BG119
Lead-Free 119-ball BGA (14 x 22 x 2.4mm)
CY7C1339G-133AXC
A101
CY7C1339G-133BGC
BG119
119-ball BGA (14 x 22 x 2.4mm)
CY7C1339G-133BGXC
BG119
Lead-Free 119-ball BGA (14 x 22 x 2.4mm)
Industrial
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial
CY7C1339G-133AXI
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
CY7C1339G-133BGI
BG119
119-ball BGA (14 x 22 x 2.4mm)
CY7C1339G-133BGXI
BG119
Lead-Free 119-ball BGA (14 x 22 x 2.4mm)
Industrial
Shaded areas contain advanced information. Please contact your local Cypress sales representative for availability of these parts.
Notes:
22. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
23. DQs are in high-Z when exiting ZZ sleep mode
Document #: 38-05520 Rev. *A
Page 14 of 17
PRELIMINARY
CY7C1339G
Ordering Information (continued)
Speed
(MHz)
Ordering Code
Package
Name
Operating
Range
Package Type
Notes:
24. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
25. DQs are in high-Z when exiting ZZ sleep mode
Package Diagrams
100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
51-85050-*A
Document #: 38-05520 Rev. *A
Page 15 of 17
PRELIMINARY
CY7C1339G
Package Diagrams (continued)
9 ead
G (
)
G
9
51-85115-*B
i486 is a trademark, and Intel and Pentium are registered trademarks, of Intel Corporation. PowerPC is a registered trademark
of IBM Corporation. All product and company names mentioned in this document may be trademarks of their respective holders.
Document #: 38-05520 Rev. *A
Page 16 of 17
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
PRELIMINARY
CY7C1339G
Document History Page
Document Title: CY7C1339G 4-Mbit (128K x 32) Pipelined Sync SRAM
Document Number: 38-05520
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
224368
See ECN
RKF
New data sheet
*A
288909
See ECN
VBL
In Ordering Info section, Changed TQFP to PB-free TQFP
Added PB-free BG package
Document #: 38-05520 Rev. *A
Page 17 of 17