GS840F18/32/36AT-7.5/8/8.5/10/12 TQFP Commercial Temp Industrial Temp 256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs Features • Flow Through mode operation • 3.3 V +10%/–5% core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipelined mode • Byte Write (BW) and/or Global Write (GW) operation • Common data inputs and data outputs • Clock Control, registered, address, data, and control • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC standard 100-lead TQFP • Pb-Free 100-lead TQFP package available Functional Description Applications The GS840F18/32/36A is a 4,718,592-bit (4,194,304-bit for x32 version) high performance synchronous SRAM with a 2bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. The GS840F18/32/36A is available in a JEDEC standard 100-lead TQFP package. Controls Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In 7.5 ns – 12 ns 3.3 V VDD 3.3 V and 2.5 V I/O Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Designing For Compatibility The JEDEC Standard for Burst RAMS calls for a FT mode pin option (pin 14 on TQFP). Board sites for Flow Through Burst RAMS should be designed with VSS connected to the FT pin location to ensure the broadest access to multiple vendor sources. Boards designed with FT pin pads tied low may be stuffed with GSI’s Pipeline/Flow Through-configurable Burst RAMS or any vendor’s Flow Through or configurable Burst SRAM. Bumps designed with the FT pin location tied high or floating must employ a non-configurable Flow Through Burst RAM, like this RAM, to achieve flow through functionality. Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. Sleep Mode Low power (Sleep mode) is attained through the assertion (high) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS840F18/32/36A operates on a 3.3 V power supply and all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuit. Parameter Synopsis –7.5 -8 -8.5 -10 -12 Flow tKQ 7.5 ns 8 ns 8.5 ns 10 ns 12 ns Through tCycle 8.5 ns 9 ns 10 ns 12 ns 15 ns 2-1-1-1 IDD 245 mA 210 mA 190 mA 165 mA 135 mA Rev: 1.09 10/2004 1/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840F18/32/36AT-7.5/8/8.5/10/12 A A E1 E2 NC NC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A GS840F18A 100-Pin TQFP Pinout NC NC NC VDDQ A NC NC VDDQ VSS NC DQPA DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC LBO A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A VSS NC NC DQB DQB VSS VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 256K x 18 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Rev: 1.09 10/2004 2/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840F18/32/36AT-7.5/8/8.5/10/12 A A E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A GS840F32A 100-Pin TQFP Pinout NC DQC DQC VDDQ NC DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA NC LBO A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A VSS DQC DQC DQC DQC VSS VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 128K x 32 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Rev: 1.09 10/2004 3/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840F18/32/36AT-7.5/8/8.5/10/12 A A E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A GS840F36A 100-Pin TQFP Pinout DQPC DQC DQC VDDQ DQPB DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA DQPA LBO A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A VSS DQC DQC DQC DQC VSS VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD DQPD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 128K x 36 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Rev: 1.09 10/2004 4/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840F18/32/36AT-7.5/8/8.5/10/12 TQFP Pin Description Symbol Type Description A 0, A 1 I Address field LSBs and Address Counter preset Inputs A I Address Inputs DQA DQB DQC DQD I/O Data Input and Output pins BW I Byte Write—Writes all enabled bytes; active low BA , BB I Byte Write Enable for DQA, DQB Data I/Os; active low BC , BD I Byte Write Enable for DQC, DQD Data I/Os; active low CK I Clock Input Signal; active high GW I Global Write Enable—Writes all bytes; active low E 1, E 3 I Chip Enable; active low E2 I Chip Enable; active high G I Output Enable; active low ADV I Burst address counter advance enable; active low ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low ZZ I Sleep Mode control; active high LBO I Linear Burst Order mode; active low VDD I Core power supply VSS I I/O and Core Ground VDDQ I Output driver power supply NC — No Connect Rev: 1.09 10/2004 5/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840F18/32/36AT-7.5/8/8.5/10/12 GS840F18/32/36A Block Diagram Register A0–An D Q A0 A0 D0 A1 Q0 A1 D1 Q1 Counter Load A LBO ADV Memory Array CK ADSC ADSP Q D Register GW BW BA D Q Register D 36 Q BB 36 4 Register D Q D Q D Q Register Register D Q Register BC BD Register D Q Register E1 E3 E2 D Q Register D Q 0 G ZZ 1 Power Down DQx0–DQx9 Control Note: Only x36 version shown for simplicity. Rev: 1.09 10/2004 6/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840F18/32/36AT-7.5/8/8.5/10/12 Mode Pin Functions Mode Name Pin Name Burst Order Control LBO Power Down Control ZZ State Function L Linear Burst H or NC Interleaved Burst L or NC Active H Standby, IDD = ISB Note: There is a pull-up device on the LBO pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. Burst Counter Sequences Linear Burst Sequence Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 Note: The burst counter wraps to initial state on the 5th clock. A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00 Note: The burst counter wraps to initial state on the 5th clock. Byte Write Truth Table Function GW BW BA BB BC BD Notes Read H H X X X X 1 Read H L H H H H 1 Write byte A H L L H H H 2, 3 Write byte B H L H L H H 2, 3 Write byte C H L H H L H 2, 3, 4 Write byte D H L H H H L 2, 3, 4 Write all bytes H L L L L L 2, 3, 4 Write all bytes L X X X X X Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes “C” and “D” are only available on the x32 and x36 versions. Rev: 1.09 10/2004 7/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840F18/32/36AT-7.5/8/8.5/10/12 Synchronous Truth Table Operation Address Used State Diagram Key5 E1 E2 Deselect Cycle, Power Down None X H X X Deselect Cycle, Power Down None X L F Deselect Cycle, Power Down None X L Read Cycle, Begin Burst External R Read Cycle, Begin Burst External Write Cycle, Begin Burst ADV W3 DQ4 L X X High-Z L X X X High-Z F H L X X High-Z L T L X X X Q R L T H L X F Q External W L T H L X T D Read Cycle, Continue Burst Next CR X X H H L F Q Read Cycle, Continue Burst Next CR H X X H L F Q Write Cycle, Continue Burst Next CW X X H H L T D Write Cycle, Continue Burst Next CW H X X H L T D Read Cycle, Suspend Burst Current X X H H H F Q Read Cycle, Suspend Burst Current H X X H H F Q Write Cycle, Suspend Burst Current X X H H H T D ADSP ADSC Write Cycle, Suspend Burst Current H X X H H T D Notes: 1. X = Don’t Care, H = High, L = Low. 2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1. 3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding. 4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above). 5. 6. 7. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.09 10/2004 8/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840F18/32/36AT-7.5/8/8.5/10/12 Simplified State Diagram X Deselect W R Simple Burst Synchronous Operation Simple Synchronous Operation W X R R First Write CW First Read CR CR W X R R X Burst Write Burst Read X CR CW CR Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, E3) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and assumes ADSP is tied high and ADV is tied low. Rev: 1.09 10/2004 9/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840F18/32/36AT-7.5/8/8.5/10/12 Simplified State Diagram with G X Deselect W R W X R R First Write CR CW W CW W X First Read X CR R Burst Write R CR CW W Burst Read X CW CR Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles. 3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.09 10/2004 10/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840F18/32/36AT-7.5/8/8.5/10/12 Absolute Maximum Ratings (All voltages reference to VSS) Symbol Description Value Unit VDD Voltage on VDD Pins –0.5 to 4.6 V VDDQ Voltage in VDDQ Pins –0.5 to VDD V VCK Voltage on Clock Input Pin –0.5 to 6 V VI/O Voltage on I/O Pins –0.5 to VDDQ+0.5 (≤ 4.6 V max.) V VIN Voltage on Other Input Pins –0.5 to VDD+0.5 (≤ 4.6 V max.) V IIN Input Current on Any Pin +/–20 mA Output Current on Any I/O Pin +/–20 mA IOUT PD Package Power Dissipation 1.5 W TSTG Storage Temperature –55 to 125 oC TBIAS Temperature Under Bias –55 to 125 o C Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Recommended Operating Conditions Parameter Symbol Min. Typ. Max. Unit Notes Supply Voltage VDD 3.135 3.3 3.6 V I/O Supply Voltage VDDQ 2.375 2.5 VDD V 1 Input High Voltage VIH 1.7 — VDD+0.3 V 2 Input Low Voltage VIL –0.3 — 0.8 V 2 Ambient Temperature (Commercial Range Versions) TA 0 25 70 °C 3 TA –40 25 85 °C 3 Ambient Temperature (Industrial Range Versions) Notes: 1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V ≤ VDDQ ≤ 2.375 V (i.e., 2.5 V I/O) and 3.6 V ≤ VDDQ ≤ 3.135 V (i.e., 3.3 V I/O) and quoted at whichever condition is worst case. 2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers. 3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 4. Input Under/overshoot voltage must be –2 V > Vi < VDD+2 V with a pulse width not to exceed 20% tKC. Rev: 1.09 10/2004 11/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840F18/32/36AT-7.5/8/8.5/10/12 Undershoot Measurement and Timing Overshoot Measurement and Timing VIH 20% tKC VDD +– 2.0 V VSS 50% 50% VDD VSS – 2.0 V 20% tKC VIL Capacitance (TA = 25oC, f = 1 MHZ, VDD = 3.3 V) Parameter Symbol Test conditions Typ. Max. Unit Control Input Capacitance CI VDD = 3.3 V 3 4 pF Input Capacitance CIN VIN = 0 V 4 5 pF COUT VOUT = 0 V 6 7 pF Output Capacitance Note: This parameter is sample tested. Rev: 1.09 10/2004 12/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840F18/32/36AT-7.5/8/8.5/10/12 AC Test Conditions Parameter Conditions Input high level 2.3 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level 1.25 V Output reference level 1.25 V Output load Fig. 1& 2 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Output Load 2 for tLZ, tHZ, tOLZ, and tOHZ. 4. Device is deselected as defined by the Truth Table. Output Load 2 Output Load 1 DQ 2.5 V 50Ω 225Ω DQ 30pF* 5pF* VT = 1.25 V 225Ω * Distributed Test Jig Capacitance DC Electrical Characteristics Parameter Symbol Test Conditions Min Max IIL VIN = 0 to VDD –1 uA 1 uA ZZ Input Current IINZZ VDD ≥ VIN ≥ VIH 0V ≤ VIN ≤ VIH –1 uA –1 uA 1 uA 300 uA Mode Pin Input Current IINM VDD ≥ VIN ≥ VIL 0V ≤ VIN ≤ VIL –300 uA –1 uA 1 uA 1 uA Output Leakage Current IOL Output Disable, VOUT = 0 to VDD –1 uA 1 uA Output High Voltage VOH IOH = –4 mA, VDDQ = 2.375 V 1.7 V — Output High Voltage VOH IOH = –4 mA, VDDQ = 3.135 V 2.4 V — Output Low Voltage VOL IOL = 4 mA — 0.4 V Input Leakage Current (except mode pins) Rev: 1.09 10/2004 13/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840F18/32/36AT-7.5/8/8.5/10/12 Operating Currents -7.5 -8 -8.5 -10 -12 0 -40 0 -40 0 -40 0 -40 0 -40 to to to to to to to to to to 70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C Parameter Test Conditions Symbol Unit Operating Current All other inputs ≥VIH or ≤ VIL Output open IDD Flow Through 245 255 210 220 190 200 165 175 135 145 mA Standby Current ZZ ≥ VDD – 0.2 V ISB Flow Through 20 30 20 30 20 30 20 30 20 30 mA Deselect Current Device Deselected; All other inputs ≥ VIH or ≤ VIL IDD Flow Through 45 55 40 50 40 50 35 45 35 45 mA AC Electrical Characteristics Flow Through Parameter Symbol Clock Cycle Time -7.5 -8 -8.5 -10 -12 Unit Min Max Min Max Min Max Min Max Min Max tKC 8.5 — 9.0 — 10.0 — 10.0 — 15.0 — ns Clock to Output Valid tKQ — 7.5 — 8.0 — 8.5 — 10 — 12 ns Clock to Output Invalid tKQX 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns Clock to Output in Low-Z 1 tLZ 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns Clock HIGH Time tKH 1.3 — 1.3 — 1.3 — 1.3 — 1.3 — ns Clock LOW Time tKL 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns Clock to Output in High-Z tHZ1 1.5 3.0 1.5 3.2 1.5 3.5 1.5 3.8 1.5 5 ns G to Output Valid tOE — 3.0 — 3.2 — 3.5 — 3.8 — 5 ns G to output in Low-Z tOLZ1 0 — 0 — 0 — 0 — 0 — ns G to output in High-Z tOHZ1 — 3.0 — 3.2 — 3.5 — 3.8 — 5 ns Setup time tS 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns Hold time tH 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns ZZ setup time tZZS2 5 — 5 — 5 — 5 — 5 — ns ZZ hold time tZZH2 1 — 1 — 1 — 1 — 1 — ns ZZ recovery tZZR 20 — 20 — 20 — 20 — 20 — ns Notes: 1. These parameters are sampled and are not 100% tested 2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.09 10/2004 14/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840F18/32/36AT-7.5/8/8.5/10/12 Flow Through Mode Timing Begin Read A Cont Cont Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont Deselect tKL tKH tKC CK ADSP Fixed High tS tH tS tH ADSC initiated read ADSC tS tH ADV tS tH A0–An A B C tS tH GW tS tH BW tS tH Ba–Bd tS Deselected with E1 tH E1 tS tH E2 and E3 only sampled with ADSC E2 tS tH E3 G tH tS tOE DQa–DQd Rev: 1.09 10/2004 tOHZ Q(A) D(B) tKQ tLZ tHZ tKQX Q(C) Q(C+1) Q(C+2) 15/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Q(C+3) Q(C) © 1999, GSI Technology GS840F18/32/36AT-7.5/8/8.5/10/12 Sleep Mode Timing Diagram tKH tKC tKL CK Setup Hold ADSP ADSC tZZR tZZS tZZH ZZ Rev: 1.09 10/2004 16/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840F18/32/36AT-7.5/8/8.5/10/12 GS840F18/32/36A Output Driver Characteristics 60 Pull Down Drivers 40 20 VDDQ I Out 0 I Out (mA) VOut VSS -20 -40 Pull Up Drivers -60 -80 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 V Out (Pull Dow n) VDDQ - V Out (Pull Up) 3.6V PD LD Rev: 1.09 10/2004 3.3V PD LD 3.1V PD LD 3.1V PU LD 3.3V PU LD 17/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 3.6V PU LD © 1999, GSI Technology GS840F18/32/36AT-7.5/8/8.5/10/12 TQFP Package Drawing (Package T) L Min. Nom. Max A1 Standoff 0.05 0.10 0.15 A2 Body Thickness 1.35 1.40 1.45 b Lead Width 0.20 0.30 0.40 c Lead Thickness 0.09 — 0.20 D Terminal Dimension 21.9 22.0 22.1 D1 Package Body 19.9 20.0 20.1 E Terminal Dimension 15.9 16.0 16.1 E1 Package Body 13.9 14.0 14.1 e Lead Pitch — 0.65 — L Foot Length 0.45 0.60 0.75 L1 Lead Length — 1.00 — Y Coplanarity θ Lead Angle L1 c e D D1 Description Pin 1 Symbol θ b A1 A2 0.10 Y 0° — 7° E1 E Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. Rev: 1.09 10/2004 18/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840F18/32/36AT-7.5/8/8.5/10/12 Ordering Information for GSI Synchronous Burst RAMs Org Part Number1 Type Package Speed2 (Mhz/ns) TA3 256K x 18 GS840F18AT-7.5 Flow Through TQFP 7.5 C 256K x 18 GS840F18AT-8 Flow Through TQFP 8 C 256K x 18 GS840F18AT-8.5 Flow Through TQFP 8.5 C 256K x 18 GS840F18AT-10 Flow Through TQFP 10 C 256K x 18 GS840F18AT-12 Flow Through TQFP 12 C 128K x 32 GS840F32AT-7.5 Flow Through TQFP 7.5 C 128K x 32 GS840F32AT-8 Flow Through TQFP 8 C 128K x 32 GS840F32AT-8.5 Flow Through TQFP 8.5 C 128K x 32 GS840F32AT-10 Flow Through TQFP 10 C 128K x 32 GS840F32AT-12 Flow Through TQFP 12 C 128K x 36 GS840F36AT-7.5 Flow Through TQFP 7.5 C 128K x 36 GS840F36AT-8 Flow Through TQFP 8 C 128K x 36 GS840F36AT-8.5 Flow Through TQFP 8.5 C 128K x 36 GS840F36AT-10 Flow Through TQFP 8.5 C 128K x 36 GS840F36AT-12 Flow Through TQFP 8.5 C 256K x 18 GS840F18AT-7.5I Flow Through TQFP 7.5 I 256K x 18 GS840F18AT-8I Flow Through TQFP 8 I 256K x 18 GS840F18AT-8.5I Flow Through TQFP 8.5 I 256K x 18 GS840F18AT-10I Flow Through TQFP 10 I 256K x 18 GS840F18AT-12I Flow Through TQFP 12 I 128K x 32 GS840F32AT-7.5I Flow Through TQFP 7.5 I 128K x 32 GS840F32AT-8I Flow Through TQFP 8 I 128K x 32 GS840F32AT-8.5I Flow Through TQFP 8.5 I 128K x 32 GS840F32AT-10I Flow Through TQFP 10 I 128K x 32 GS840F32AT-12I Flow Through TQFP 12 I 128K x 36 GS840F36AT-7.5I Flow Through TQFP 7.5 I 128K x 36 GS840F36AT-8I Flow Through TQFP 8 I 128K x 36 GS840F36AT-8.5I Flow Through TQFP 8.5 I 128K x 36 GS840F36AT-10I Flow Through TQFP 10 I Status 128K x 36 GS840F36AT-12I Flow Through TQFP 12 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS840F32AT-8T. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.09 10/2004 19/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840F18/32/36AT-7.5/8/8.5/10/12 Ordering Information for GSI Synchronous Burst RAMs Org Part Number1 Type Package Speed2 (Mhz/ns) TA3 256K x 18 GS840F18AGT-7.5 Flow Through Pb-free TQFP 7.5 C 256K x 18 GS840F18AGT-8 Flow Through Pb-free TQFP 8 C 256K x 18 GS840F18AGT-8.5 Flow Through Pb-free TQFP 8.5 C 256K x 18 GS840F18AGT-10 Flow Through Pb-free TQFP 10 C 256K x 18 GS840F18AGT-12 Flow Through Pb-free TQFP 12 C 128K x 32 GS840F32AGT-7.5 Flow Through Pb-free TQFP 7.5 C 128K x 32 GS840F32AGT-8 Flow Through Pb-free TQFP 8 C 128K x 32 GS840F32AGT-8.5 Flow Through Pb-free TQFP 8.5 C 128K x 32 GS840F32AGT-10 Flow Through Pb-free TQFP 10 C 128K x 32 GS840F32AGT-12 Flow Through Pb-free TQFP 12 C 128K x 36 GS840F36AGT-7.5 Flow Through Pb-free TQFP 7.5 C 128K x 36 GS840F36AGT-8 Flow Through Pb-free TQFP 8 C 128K x 36 GS840F36AGT-8.5 Flow Through Pb-free TQFP 8.5 C 128K x 36 GS840F36AGT-10 Flow Through Pb-free TQFP 8.5 C 128K x 36 GS840F36AGT-12 Flow Through Pb-free TQFP 8.5 C 256K x 18 GS840F18AGT-7.5I Flow Through Pb-free TQFP 7.5 I 256K x 18 GS840F18AGT-8I Flow Through Pb-free TQFP 8 I 256K x 18 GS840F18AGT-8.5I Flow Through Pb-free TQFP 8.5 I 256K x 18 GS840F18AGT-10I Flow Through Pb-free TQFP 10 I 256K x 18 GS840F18AGT-12I Flow Through Pb-free TQFP 12 I 128K x 32 GS840F32AGT-7.5I Flow Through Pb-free TQFP 7.5 I 128K x 32 GS840F32AGT-8I Flow Through Pb-free TQFP 8 I 128K x 32 GS840F32AGT-8.5I Flow Through Pb-free TQFP 8.5 I 128K x 32 GS840F32AGT-10I Flow Through Pb-free TQFP 10 I 128K x 32 GS840F32AGT-12I Flow Through Pb-free TQFP 12 I 128K x 36 GS840F36AGT-7.5I Flow Through Pb-free TQFP 7.5 I 128K x 36 GS840F36AGT-8I Flow Through Pb-free TQFP 8 I 128K x 36 GS840F36AGT-8.5I Flow Through Pb-free TQFP 8.5 I 128K x 36 GS840F36AGT-10I Flow Through Pb-free TQFP 10 I Status 128K x 36 GS840F36AGT-12I Flow Through Pb-free TQFP 12 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS840F32AT-8T. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.09 10/2004 20/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840F18/32/36AT-7.5/8/8.5/10/12 4Mb Burst Datasheet Revision History Rev. Code: Old; New GS84018/32/362/2000G; 840F18A_r1_02 Types of Changes Page /Revisions;Reason Format or Content Content • Updated pin description table Content/Format • Added “non-A” speed bins to Operating Currents table, AC Electrical Characteristics table, and Ordering Information table • Updated format to fit Technical Documentation standards 840F18A_r1_03; 840F18A_r1_04 Content/Format • Updated table on page 1 • Updated Operating Currents table on page 14 • Updated AC Electrical Characteristics table on page 14 • Updated format to comply with present Technical Documentation standards 840F18A_r1_04; 840F18A_r1_05 Content 840F18A_r1_05; 840F18A_r1_06 Content 840F18A_r1_06; 840F18A_r1_07 Content • Updated format • Added 7.5 ns speed bin 840F18A_r1_07; 840F18A_r1_08 Content • Updated format • Matched current numbers to NBT parts • Removed Preliminary banner 840F18A_r1_08; 840F18A_r1_09 Content 840F18A_r1_02; 840F18A_r1_03 Rev: 1.09 10/2004 • Reduced IDD by 20 mA in table on page 1 and Operating Currents table • Removed 7.5 ns references from entire datasheet • Added Pb-free TQFP information 21/21 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology