Intersil ISL28110FUZ Precision low noise jfet operational amplifier Datasheet

ISL28110, ISL28210
Features
The ISL28110, ISL28210, are single and dual JFET
amplifiers featuring low noise, high slew rate, low input
bias current and offset voltage, making them the ideal
choice for high impedance applications where precision
and low noise are important. The combination of
precision, low noise, and high speed combined with a
small footprint provides the user with outstanding value
and flexibility relative to similar competitive parts.
• Wide Supply Range. . . . . . . . . . . . . . . . . 9V to 40V
Applications for these amplifiers include precision medical
and analytical instrumentation, sensor conditioning,
precision power supply controls, industrial controls and
photodiode amplifiers.
• Low Current Consumption . . . . . . . . . . . . . 2.55mA
The ISL28110 single amplifier is available in the 8 Ld
SOIC, TDFN, and MSOP packages. The ISL28210 dual
amplifier is available in the 8 Ld SOIC and TDFN
packages. All devices are offered in standard pin
configurations and operate over the extended
temperature range from -40°C to +125°C.
• Low Voltage Noise . . . . . . . . . . . . . . . . . . 6nV/√Hz
• Input Bias Current . . . . . . . . . . . . . . . . . . . . . 2pA
• High Slew Rate. . . . . . . . . . . . . . . . . . . . . . 23V/µs
• High Bandwidth . . . . . . . . . . . . . . . . . . . .12.5MHz
• Low Input Offset . . . . . . . . . . . . . . . . .300µV, Max
• Offset Drift . . . . . . . . . . . . . . . . Grade C 10µV/°C
• Operating Temperature Range . . . -40°C to +125°C
• Small Package Offerings in Single, and Dual
• Pb-Free (RoHS compliant)
Applications*(see page 16)
• Precision Instruments
• Photodiode Amplifiers
• High Impedance Buffers
• Medical Instrumentation
• Active Filter Blocks
• Industrial Controls
Input Bias Current vs Common
Mode Input Voltage
RF
CF
V+
PHOTO
DIODE
RSH
CT
OUTPUT
+
V-
BASIC APPLICATION CIRCUIT - PHOTODIODE AMPLIFIER
September 13, 2010
FN6639.0
1
NORMALIZED INPUT BIAS CURRENT (pA)
Typical Application
10
8
VS = ±15V
6
4
2
0
-2
-4
-6
-8
-10
-15
-10
-5
0
5
10
15
VCM (V)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL28110, ISL28210
Precision Low Noise JFET Operational Amplifiers
ISL28110, ISL28210
Pin Configurations
ISL28110
(8 LD, SOIC, MSOP)
TOP VIEW
ISL28110
(8 LD TDFN)
TOP VIEW
NC 1
-IN A 2
- +
+IN A 3
V- 4
8 NC
NC
1
7 V+
-IN A
2
+IN A
3
6 VOUT A
V-
4
5 NC
6 VOUT A
PAD
5 NC
1
-IN A
2
+IN A
3
V-
4
8 V+
7 VOUT B
- +
PAD
6 -IN B
+ -
7 V+
- +
ISL28210
(8 LD SOIC)
TOP VIEW
ISL28210
(8 LD TDFN)
TOP VIEW
VOUT A
8 NC
5 +IN B
VOUT A
1
-IN A
2
+IN A
3
V-
4
8 V+
7 VOUT B
- +
+ -
6 -IN B
5 +IN B
Pin Descriptions
ISL28110
(8 Ld TDFN)
ISL28110
(8 Ld SOIC,
ISL28210
8 Ld MSOP) (8 Ld TDFN)
ISL28210
(8 Ld SOIC)
PIN
NAME
EQUIVALENT
CIRCUIT
DESCRIPTION
3
3
3
3
+IN A
Circuit 1
Amplifier A non-inverting input
2
2
2
2
-IN A
Circuit 1
Amplifier A inverting input
6
6
1
1
VOUT A
Circuit 2
Amplifier A output
4
4
4
4
V-
Circuit 3
Negative power supply
5
5
+IN B
Circuit 1
Amplifier B non-inverting input
6
6
-IN B
Circuit 1
Amplifier B inverting input
7
7
VOUT B
Circuit 2
Amplifier B output
8
8
V+
Circuit 3
Positive power supply
7
7
1, 5, 8
1, 5, 8
No connect
PAD
PAD
IN-
PAD
V+
V+
IN+
OUT
V-
V-
CIRCUIT 1
CIRCUIT 2
2
Thermal Pad is electrically
isolated from active circuitry. Pad
can float, connect to Ground or to
a potential source that is free
from signals or noise sources.
V+
CAPACITIVELY
TRIGGERED
ESD CLAMP
VCIRCUIT 3
FN6639.0
September 13, 2010
ISL28110, ISL28210
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TCVOS
(µV/°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
Coming Soon
ISL28110FBZ
28110 FBZ -C
10 (C Grade)
8 Ld SOIC
M8.15E
ISL28210FBZ
28210 FBZ -C
10 (C Grade)
8 Ld SOIC
M8.15E
Coming Soon
ISL28110FRTZ
-C 8110
10 (C Grade)
8 Ld TDFN
L8.3x3A
Coming Soon
ISL28210FRTZ
-C 8210
10 (C Grade)
8 Ld TDFN
L8.3x3A
Coming Soon
ISL28110FRTBZ
8110
4 (B Grade)
8 Ld TDFN
L8.3x3A
Coming Soon
ISL28210FRTBZ
8210
4 (B Grade)
8 Ld TDFN
L8.3x3A
Coming Soon
ISL28110FBBZ
28110 FBZ -C
4 (B Grade)
8 Ld SOIC
M8.15E
Coming Soon
ISL28210FBBZ
28210 FBZ
4 (B Grade)
8 Ld SOIC
M8.15E
Coming Soon
ISL28110FUBZ
8110Z
4 (B Grade)
8 Ld MSOP
M8.118
Coming Soon
ISL28110FUZ
8110Z
10 (C Grade)
8 Ld MSOP
M8.118
NOTES:
1. Add “-T7”, “-T13” or “-T7A” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28110, ISL28210. For more information on
MSL please see techbrief TB363.
3
FN6639.0
September 13, 2010
ISL28110, ISL28210
Absolute Voltage Ratings
Thermal Information
Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 42V
Maximum Supply Turn On Voltage Slew Rate . . . . . . . . 1V/µs
Maximum Differential Input Voltage . . . . . . . . . . . . . . . 33V
Min/Max Input Voltage . . . . . . . . . . . V- - 0.5V to V+ + 0.5V
Max/Min Input current for input voltage >V+ or <V- . ±20mA
Output Short-Circuit Duration
(1 output at a time) . . . . . . . . . . . . . . . . . . . . Indefinite
ESD Ratings
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . 4000V
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 400V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . 2000V
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
8 Ld SOIC (Notes 5, 7)
ISL28110 . . . . . . . . . . . . . . . . .
125
70
ISL28210 . . . . . . . . . . . . . . . . .
120
50
8 Ld TDFN (Notes 4, 6)
ISL28110 . . . . . . . . . . . . . . . . .
48
7.8
ISL28210 . . . . . . . . . . . . . . . . .
46
4.5
8 Ld MSOP (Notes 5, 7)
ISL28110 . . . . . . . . . . . . . . . . .
158
60
Ambient Operating Temperature Range . . . -40°C to +125°C
Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
6. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
7. For θJC, the “case temp” location is taken at the package top center.
Electrical Specifications
PARAMETER
VS = ±5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply
over the operating temperature range, -40°C to +125°C.
DESCRIPTION
CONDITIONS
MIN
(Note 8)
MAX
(Note 8)
UNITS
-300
300
µV
-1300
1300
µV
1
10
µV/C
±0.3
2
pA
TYP
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
-40°C < TA < +125°C
TCVOS
IB
IOS
Input Offset Voltage
Temperature Coefficient
-40°C < TA < +125°C
Input Bias Current (Note 9)
-2
-40°C < TA < +60°C
-4.5
4.5
pA
-40°C < TA < +85°C
-50
50
pA
-40°C < TA < +125°C
-245
245
pA
1
pA
Input Offset Current (Note 9)
-1
-40°C < TA < +60°C
-2.25
2.25
pA
-40°C < TA < +85°C
-30
30
pA
-105
105
pA
-40°C < TA < +125°C
CIN-DIFF
±0.15
8.3
pF
Common Mode Input
Capacitance
11.8
pF
Differential Input Resistance
530
GΩ
RIN-CM
Common Mode Input Resistance
560
GΩ
VCMIR
Common Mode Input Voltage
Range
CIN-CM
RIN-DIFF
Differential Input Capacitance
4
Guaranteed by CMRR test
V- + 1.5
V+ - 1.5
V
V- + 2.5
V+ - 2.5
V
FN6639.0
September 13, 2010
ISL28110, ISL28210
Electrical Specifications
PARAMETER
CMRR
AVOL
VS = ±5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply
over the operating temperature range, -40°C to +125°C. (Continued)
DESCRIPTION
Common Mode Rejection Ratio
Open-loop Gain
CONDITIONS
MIN
(Note 8)
VCM = -3.5V to +3.5V
TYP
MAX
(Note 8)
UNITS
90
dB
VCM = -2.5V to +2.5V
88
100
dB
RL = 10kΩ to ground
VO = -3V to +3V
165
240
V/mV
155
V/mV
DYNAMIC PERFORMANCE
GBWP
SR
THD+N
ts
Gain-bandwidth Product
G = 100, RL = 100kΩ, CL = 4pF
Slew Rate, VOUT 20% to 80%
G = -1, RL = 2kΩ
Total Harmonic Distortion +
Noise
11
12.5
MHz
23
V/µs
G = 1, f = 1kHz, 4VP-P, RL = 2kΩ
0.0002
%
G = 1, f = 1kHz, 4VP-P, RL = 600Ω
0.0003
%
Settling Time to 0.1%
4V Step; 10% to VOUT
AV = 1, VOUT = 4VP-P, RL = 2kΩ to VCM
0.4
µs
Settling Time to 0.01%
4V Step; 10% to VOUT
AV = 1, VOUT = 4VP-P, RL = 2kΩ to VCM
1
µs
580
nVP-P
14
nV/√Hz
f = 100Hz
7
nV/√Hz
f = 1kHz
6
nV/√Hz
f = 10kHz
6
nV/√Hz
f = 1kHz
9
fA/√Hz
NOISE PERFORMANCE
enP-P
en
in
Peak-to-Peak Input Voltage
Noise
0.1Hz to 10Hz
Input Voltage Noise Spectral
Density
f = 10Hz
Input Current Noise Spectral
Density
OUTPUT CHARACTERISTICS
VOL
Output Voltage Low, VOUT to V-
RL = 10kΩ
0.8
RL = 2kΩ
VOH
Output Voltage High, V+ to VOUT
0.9
RL to GND = 10kΩ
0.8
RL to GND = 2kΩ
ISC
Output Short Circuit Current
0.9
RL = 10Ω to V+. V-
1.0
V
1.1
V
1.1
V
1.2
V
1.0
V
1.1
V
1.1
V
1.2
V
±50
mA
POWER SUPPLY
VSUPPLY
PSRR
Supply Voltage Range
Guaranteed by PSRR
±4.5
Power Supply Rejection Ratio
VS = ± 4.5V to ±5V
102
±20V
115
dB
100
IS
Supply Current/Amplifier
5
V
dB
2.5
2.9
mA
3.8
mA
FN6639.0
September 13, 2010
ISL28110, ISL28210
Electrical Specifications
PARAMETER
VS = ±15V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply
over the operating temperature range, -40°C to +125°C.
DESCRIPTION
CONDITIONS
MIN
(Note 8)
MAX
(Note 8)
UNITS
-300
300
µV
-1300
1300
µV
1
10
µV/C
±2
5
pA
TYP
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
-40°C < TA < +125°C
TCVOS
IB
IOS
CIN-DIFF
Input Offset Voltage Temperature
Coefficient (Grade C)
-40°C < TA < +125°C
Input Bias Current (Note 9)
5
-40°C < TA < +60°C
-350
350
pA
-40°C < TA < +85°C
-700
700
pA
-40°C < TA < +125°C
-3600
3600
pA
2.5
pA
Input Offset Current (Note 9)
-2.5
±0.5
-40°C < TA < +60°C
-285
285
pA
-40°C < TA < +85°C
-445
445
pA
-40°C < TA < +125°C
-2000
2000
pA
8.3
pF
Common Mode Input Capacitance
11.8
pF
Differential Input Resistance
530
GΩ
RIN-CM
Common Mode Input Resistance
560
GΩ
VCMIR
Common Mode Input Voltage Range Guaranteed by CMRR test
CMRR
Common Mode Rejection Ratio
VCM = -13.5V to +13.5V
80
100
dB
Open-loop Gain
RL = 10kΩ to ground
VO = -12.5V to +12.5V
230
290
V/mV
-40°C < TA < +125°C
200
CIN-CM
RIN-DIFF
AVOL
Differential Input Capacitance
V- + 1.5
V+ - 1.5
V
V/mV
DYNAMIC PERFORMANCE
GBWP
SR
THD+N
Gain-bandwidth Product
G =100, RL = 100kΩ, CL = 4pF
Slew Rate, VOUT 20% to 80%
Total Harmonic Distortion + Noise
12.5
MHz
G = -1, RL = 2kΩ
23
V/µs
G = 1, f = 1kHz,
10VP-P, RL = 2kΩ
0.00025
%
0.0003
%
G = 1, f = 1kHz,
10VP-P, RL = 600Ω
ts
11
Settling Time to 0.1%
10V Step; 10% to VOUT
AV = 1, VOUT = 10VP-P, RL = 2kΩ
to VCM
0.9
µs
Settling Time to 0.01%
10V Step; 10% to VOUT
AV = 1, VOUT = 10VP-P, RL = 2kΩ
to VCM
1.2
µs
600
nVP-P
NOISE PERFORMANCE
enP-P
Peak-to-Peak Input Voltage Noise
0.1Hz to 10Hz
en
Input Voltage Noise Spectral Density
f = 10Hz
18
nV/√Hz
f = 100Hz
7.8
nV/√Hz
f = 1kHz
6
nV/√Hz
f = 10kHz
6
nV/√Hz
f = 1kHz
9
fA/√Hz
in
Input Current Noise Spectral Density
6
FN6639.0
September 13, 2010
ISL28110, ISL28210
Electrical Specifications
PARAMETER
VS = ±15V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply
over the operating temperature range, -40°C to +125°C. (Continued)
DESCRIPTION
MIN
(Note 8)
CONDITIONS
TYP
MAX
(Note 8)
UNITS
0.8
1.0
V
1.1
V
1.1
V
1.2
V
1.0
V
1.1
V
1.1
V
1.2
V
OUTPUT CHARACTERISTICS
VOL
Output Voltage Low,
VOUT to V-
RL = 10kΩ
RL = 2kΩ
VOH
Output Voltage High,
V+ to VOUT
0.9
RL to GND = 10kΩ
0.8
RL to GND = 2kΩ
ISC
Output Short Circuit Current
0.9
RL = 10Ω to V+. V-
±50
mA
115
dB
POWER SUPPLY
PSRR
Power Supply Rejection Ratio
VS = ±4.5V to ±20V
102
100
IS
dB
Supply Current/Amplifier
2.55
3.1
mA
3.9
mA
NOTE:
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
9. Limits established by characterization and are not production tested.
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, T = +25°C, unless otherwise
specified.
250
25
200
150
100
50
0
-150
-100
-50
0
50
100
150
VOS (µV)
FIGURE 1. INPUT OFFSET VOLTAGE (VOS)
DISTRIBUTION
7
200
VS = ±15V
TA = -40°C TO +125°C
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS
VS = ±15V
250
20
15
10
5
0
-10
-8
-6
-4
-2
0
2
4
6
8
10
TCVOS(µV/C)
FIGURE 2. TCVOS DISTRIBUTION, -40°C to +125°C
FN6639.0
September 13, 2010
ISL28110, ISL28210
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, T = +25°C, unless otherwise
1.6
100
1.4
0
-100
1.2
-200
INPUT BIAS (pA)
INPUT BIAS CURRENT (pA)
specified. (Continued)
1.0
0.8
0.6
-500
-600
-700
-800
0.2
-900
-1000
5
6
7
8
9
10
11
±VSUPPLY (±V)
12
13
14
15
FIGURE 3. INPUT BIAS CURRENT (IB) vs SUPPLY
VOLTAGE
VS = ±15V
-400
0.4
0
VS = ±5V
-300
-1100
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
120
140
120
140
FIGURE 4. INPUT BIAS CURRENT (IB) vs
TEMPERATURE
20
300
VS = ±5V
VS = ±15V
250
10
IOS CHA
200
IOS CHA
IOS (pA)
IOS (pA)
100
0
-10
150
IOS CHB
100
50
IOS CHB
0
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
NORMALIZED INPUT BIAS CURRENT (pA)
3.5
VS = ±5V
3.0
2.5
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-5
-4
-3
-2
-1
0
1
2
3
4
5
VCM (V)
FIGURE 7. NORMALIZED INPUT BIAS CURRENT (IB) vs
INPUT COMMON MODE VOLTAGE (VCM),
VS = ± 5V
8
-20
0
20
40
60
80
100
TEMPERATURE (°C)
FIGURE 5. ISL28210 INPUT OFFSET CURRENT (IOS) vs
TEMPERATURE, VS = ± 5V
4.0
-50
-40
140
FIGURE 6. ISL28210 INPUT OFFSET CURRENT (IOS) vs
TEMPERATURE, VS = ± 15V
NORMALIZED INPUT BIAS CURRENT (pA)
-20
-40
10
8
VS = ±15V
6
4
2
0
-2
-4
-6
-8
-10
-15
-10
-5
0
5
10
15
VCM (V)
FIGURE 8. NORMALIZED INPUT BIAS CURRENT (IB) vs
INPUT COMMON MODE VOLTAGE (VCM),
VS = ± 15V
FN6639.0
September 13, 2010
ISL28110, ISL28210
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, T = +25°C, unless otherwise
specified. (Continued)
500
400
300
200
100
0
-100
-200
-300
-3
-2
-1
0
1
VCM (V)
2
3
4
0
-100
-200
-300
INPUT NOISE VOLTAGE
100
100
INPUT NOISE CURRENT
10
10
1
0.1
1
10
100
1k
FREQUENCY (Hz)
10k
5
10
15
1000
INPUT NOISE VOLTAGE
100
100
INPUT NOISE CURRENT
10
10
1
10
100
1k
10k
1
100k
FIGURE 12. INPUT NOISE VOLTAGE (en) AND CURRENT
(in) vs FREQUENCY, VS = ±5V
1000
INPUT NOISE VOLTAGE (nVP-P)
400
200
0
-200
-400
-600
-800
1
0
VCM (V)
FREQUENCY (Hz)
600
0
-5
VS = ±5V
1
0.1
VS = ±5V
AV = 10k
800
1000
1
100k
FIGURE 11. INPUT NOISE VOLTAGE (en) AND CURRENT
(in) vs FREQUENCY, VS = ±18V
1000
-10
FIGURE 10. NORMALIZED INPUT OFFSET VOLTAGE
(VOS) vs INPUT COMMON MODE VOLTAGE
(VCM), VS = ± 15V
1000
VS = ±18V
INPUT NOISE CURRENT (fA/√Hz)
INPUT NOISE VOLTAGE (nV/√Hz)
100
-500
-15
5
FIGURE 9. NORMALIZED INPUT OFFSET VOLTAGE
(VOS) vs INPUT COMMON MODE VOLTAGE
(VCM), VS = ± 5V
INPUT NOISE VOLTAGE (nVP-P)
200
INPUT NOISE CURRENT (fA/√Hz)
-4
INPUT NOISE VOLTAGE (nV/√Hz)
-500
-5
-1000
300
-400
-400
1000
VS = ±15V
400
NORMALIZED VOS (uV)
NORMALIZED VOS (uV)
500
VS = ±5V
2
3
4
5
6
7
8
9
TIME (s)
FIGURE 13. 0.1Hz TO 10Hz VP-P NOISE VOLTAGE,
VS =±5V
9
10
VS = ±18V
AV = 10k
800
600
400
200
0
-200
-400
-600
-800
-1000
0
1
2
3
4
5
6
7
8
9
10
TIME (s)
FIGURE 14. 0.1Hz TO 10Hz VP-P NOISE VOLTAGE,
VS = ±18V
FN6639.0
September 13, 2010
ISL28110, ISL28210
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, T = +25°C, unless otherwise
specified. (Continued)
THD + N (%)
0.01
-40°C
+25°C
0.001
-40°C
0.1
VS = ±15V
CL = 4pF
RL = 600
VOUT = 10VP-P
C-WEIGHTED
22Hz to 500kHz
+25°C
+125°C
AV = 10
C-WEIGHTED
22Hz to 500kHz
0.01
THD + N (%)
0.1
VS = ±15V
CL = 4pF
RL = 2k
VOUT = 10VP-P
-40°C
+25°C
+125°C
AV = 10
0.001
+125°C
+25°C
-40°C
+125°C
AV = 1
0.0001
10
100
AV = 1
1k
10k
FREQUENCY (Hz)
100k
FIGURE 15. THD+N vs FREQUENCY vs TEMPERATURE,
AV = 1, 10, VOUT = 10VP-P, RL = 600Ω
1
0.0001
-40°C
5
10
15
VOUT (VP-P)
20
25
30
FIGURE 17. THD+N vs OUTPUT VOLTAGE (VOUT) vs
TEMPERATURE, AV = 1 f = 1kHz, RL = 600Ω
RL_RECEIVE = 10k
50
OVERSHOOT (%)
CROSSTALK (dB)
RL-TRANSMIT = 2k
-60
-80
RL-TRANSMIT = ∞
RL_RECEIVE = ∞
-100
-40°C
0
5
10
15
VOUT (VP-P)
20
25
30
VS = ±15V
VOUT = 100mVP-P
40
AV = -1
30
20
AV = 10
AV = 1
10
-120
-140
+25°C
+125°C
FIGURE 18. THD+N vs OUTPUT VOLTAGE (VOUT) vs
TEMPERATURE, AV = 1 f =1kHz, RL = 2kΩ
60
-40
C-WEIGHTED
22Hz to 22kHz
0.01
0.0001
0
VS = ±15V
-20 CL = 4pF
VCM = 1VP-P
100k
AV = 1
0.001
+125°C
0
10k
VS = ±15V
CL= 4pF
RL= 2k
0.1 f = 1kHz
+25°C
0.001
1k
FREQUENCY (Hz)
1
AV = 1
C-WEIGHTED
22Hz to 22kHz
0.01
100
FIGURE 16. THD+N vs FREQUENCY vs TEMPERATURE,
VOUT = 10VP-P, RL = 2kΩ
THD + N (%)
THD + N (%)
VS = ±15V
CL = 4pF
RL = 600
0.1 f = 1kHz
0.0001
10
1
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
FIGURE 19. CROSSTALK vs FREQUENCY
10
100M
0
0.001
0.01
0.1
1
LOAD CAPACITANCE (nF)
10
100
FIGURE 20. SMALL SIGNAL OVERSHOOT vs LOAD
CAPACITANCE (CL)
FN6639.0
September 13, 2010
ISL28110, ISL28210
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, T = +25°C, unless otherwise
200
180
160
140
120
100
80
60
40
20
0
-20
-40
-60 VS = ±15V
-80 RL=1MΩ
-100
0.1
1
10
70
60
PHASE
ACL = 1000
RF = 100kΩ, RG = 100Ω
RF = 100kΩ, RG = 1kΩ
50
GAIN (dB)
GAIN (dB)
specified. (Continued)
GAIN
40
30
20
10
0
100
1k
ACL = 100
ACL = 10
RF = 100kΩ, RG = 10kΩ
ACL = 1
RF = 0, RG = ∞
-10
1k
10k 100k 1M 10M 100M 1G
VS = ±5V & ±15V
CL = 4pF
RL = OPEN
VOUT = 100mVP-P
10k
100k
120
PSRR-
80
CMRR (dB)
PSRR (dB)
90
70
60
50
40
30
20
10
0
10
VS = ±15V
AV = 1
CL = 4pF
RL = 10k
VCM = 1VP-P
100
PSRR+
1k
10k
100k
1M
10M
130
120
110
100
90
80
70
60
50
40
30
20 VS = ±15V
10 SIMULATION
0
0.1
1
10
FREQUENCY (Hz)
5
15
4
14
VOL
VOH
-40°C
3
+125°C
+25°C
VS = ±5V
1 A =2
V
-1 R = R = 100k
F
G
-2 VIN = 2.5VP-P
-4
0°C
0
10
20
30
40
I-FORCE (mA)
50
60
70
FIGURE 25. OUTPUT VOLTAGE (VOUT) vs OUTPUT
CURRENT (IOUT) vs TEMPERATURE,
VS = ±5V
11
125°C
12
VS = ±15V
AV = 2
RF = RG = 100k
VIN = 7.5VP-P
10
-10
-11
+85°C
100
1k
10k 100k
FREQUENCY (Hz)
1M
10M
100M
-40°C
13
11
-3
-5
100M
FIGURE 24. COMMON-MODE REJECTION RATIO (CMRR)
vs FREQUENCY
VOL
VOH
FIGURE 23. POWER SUPPLY REJECTION RATIO (PSRR)
vs FREQUENCY
2
10M
FIGURE 22. CLOSED LOOP GAIN vs FREQUENCY
FIGURE 21. OPEN LOOP GAIN-PHASE vs FREQUENCY
110
100
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
-12
25°C
85°C
-13
-14
-15
0°C
0
10
20
30
40
I-FORCE (mA)
50
60
70
FIGURE 26. OUTPUT VOLTAGE (VOUT) vs OUTPUT
CURRENT (IOUT) vs TEMPERATURE,
VS = ±15V
FN6639.0
September 13, 2010
ISL28110, ISL28210
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, T = +25°C, unless otherwise
specified. (Continued)
INPUT (mV)
120
OUTPUT
AV = 1
80
8
40
0
0
2
4
6
8
10
12
TIME (µs)
14
16
18
INPUT
-40
-4
-80
-8
-12
-120
OUTPUT
4
-160
0
20
-200
0
2
4
6
8
10
12
14
16
18
-16
-20
20
TIME (µs)
FIGURE 27. POSITIVE OUTPUT OVERLOAD RECOVERY
TIME
FIGURE 28. NEGATIVE OUTPUT OVERLOAD RECOVERY
TIME
30
30
-SR
-SR
25
25
SLEW RATE (V/µs)
SLEW RATE (V/µs)
VS = ±15V
AV = 100
RL = 10k
VIN = 100mVP-P
OVERDRIVE = 1V
OUTPUT (V)
INPUT
160
0
0
INPUT (mV)
20
VS = ±15V
AV = 100
RL = 10k
16
VIN = 100mVP-P
OVERDRIVE = 1V
12
OUTPUT (V)
200
20
+SR
15
10
VS = ±5V
VOUT-PP = 4V
RL = 2k
CL = 4pF
5
0
-1
-2
20
+SR
15
10
VS = ±15V
VOUT-PP = 10V
RL = 2k
CL = 4pF
5
-3
-4
-5
-6
-7
-8
-9
0
-1
-10
-2
-3
-4
-5
GAIN
-6
-7
-8
-9
-10
GAIN
FIGURE 29. SLEW RATE vs INVERTING CLOSED LOOP
GAIN, VS = ±5V
FIGURE 30. SLEW RATE vs INVERTING CLOSED LOOP
GAIN, VS = ±15V
30
30
25
25
-SR
SLEW RATE (V/µs)
SLEW RATE (V/µs)
-SR
20
15
+SR
10
VS = ±5V
VOUT-PP = 4V
RL = 2k
CL = 4pF
5
0
1
2
3
20
+SR
15
10
VS = ±15V
VOUT-PP = 10V
RL = 2k
CL = 4pF
5
4
5
6
GAIN
7
8
9
10
FIGURE 31. SLEW RATE vs NON-INVERTING CLOSED
LOOP GAIN, VS = ±5V
12
0
1
2
3
4
5
6
GAIN
7
8
9
10
FIGURE 32. SLEW RATE vs NON-INVERTING CLOSED
LOOP GAIN, VS = ±15V
FN6639.0
September 13, 2010
ISL28110, ISL28210
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, T = +25°C, unless otherwise
specified. (Continued)
6
0.15
VS = ±15V
AV = 1
RL = 2k
CL = 4pF
0.10
2
VOUT (V)
VOUT (V)
0.05
0
0
-0.05
-2
-0.10
-4
-0.15
0
0.1
VS = ±15V
AV = 1
RL = 2k
CL = 4pF
4
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
-6
1.0
0
1
2
3
4
TIME (µs)
FIGURE 33. SMALL SIGNAL TRANSIENT RESPONSE
8
9
10
VS = ±15V
AV = +10
4 R = 2k
L
CL = 4pF
2
VOUT (V)
2
VOUT (V)
7
FIGURE 34. LARGE SIGNAL UNITY GAIN TRANSIENT
RESPONSE
VS = ±15V
AV = -1
RL = 2k
CL = 4pF
4
0
0
-2
-2
-4
-4
0
1
2
3
4
5
6
TIME (µs)
7
8
9
10
FIGURE 35. LARGE SIGNAL 10V STEP RESPONSE AV =-1
100
-6
0
1000
VS = ±15V
VOUT = 10VP-P
RL = 2kΩ
1
2
3
4
8
9
10
100
G = 10
0.1%
1
10
G = 100
1
0.1
0.1
7
VS = ±15V
0.01%
10
5
6
TIME (µs)
FIGURE 36. LARGE SIGNAL 10V STEP RESPONSE
AV =+10
ZOUT (Ω)
SETTLING TIME (µs)
6
6
6
-6
5
TIME (µs)
1
10
100
CLOSED LOOP GAIN (V/V)
FIGURE 37. SETTLING TIME (tS) vs CLOSED LOOP GAIN
13
0.01
10
G=1
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 38. ZOUT vs FREQUENCY
FN6639.0
September 13, 2010
ISL28110, ISL28210
The ISL28110 and ISL28210 are single and dual 12.5
MHz precision JFET input op amps. These devices are
fabricated in the PR40 Advanced SOI bipolar-JFET
process to ensure latch-free operation. The precision
JFET input stage provides low input offset voltage (300µV
max @ +25°C), low input voltage noise (6nV/√Hz), and
input current noise that is very low with virtually no 1/f
component. A high current complementary NPN/PNP
emitter-follower output stage provides high slew rate and
maintains excellent THD+N performance into heavy
loads (0.0003% @ 10VP-P @ 1kHz into 600Ω).
Operating Voltage Range
The devices are designed to operate over the 9V (±4.5V)
to 40V (±20V) range and are fully characterized at 10V
(±5V) and 30V (±15V). The JFET input stage maintains
high impedance over a maximum input differential
voltage range of ±33V. Internal ESD protection diodes
clamp the non-inverting and inverting inputs to one diode
drop above and below the V+ and V- the power supply
rails (“Pin Descriptions” on page 2, CIRCUIT 1).
Input ESD Diode Protection
The JFET gate is a reverse-biased diode with >33V
reverse breakdown voltage which enables the device to
function reliably in large signal pulse applications without
the need for anti-parallel clamp diodes required on
MOSFET and most bipolar input stage op amps. No
special input signal restrictions are needed for power
supply operation up to ±15V, and input signal distortion
caused by nonlinear clamps under high slew rate
conditions are avoided. For power supply operation
greater than ±16V (>32V), the internal ESD clamp
diodes alone cannot clamp the maximum input
differential signal to the power supply rails without the
risk of exceeding the 33V breakdown of the JFET gate.
Under these conditions, differential input voltage limiting
is necessary to prevent damage to the JFET input stage.
In applications where one or both amplifier input
terminals are at risk of exposure to voltages beyond the
supply rails, current limiting resistors may be needed at
each input terminal (see Figure 39 RIN+, RIN-) to limit
current through the power supply ESD diodes to 20mA.
V+
VINVIN+
RIN-
-
RIN
+
RL
V-
FIGURE 39. INPUT ESD DIODE CURRENT LIMITING
14
The ISL28110, ISL28210 JFET input stage has the linear
gain characteristics of the MOSFET but can operate at
high frequency with much lower noise. The reversedbiased gate PN gate junction has significantly lower gate
capacitance enabling input slew rates that rival op amps
using bipolar input stages. The added advantage for
high impedance, precision amplifiers is the lack of a
significant 1/f component of current noise (Figures 11,
12) as there is virtually no gate current.
The input stage JFETs are bootstrapped to maintain a
constant JFET drain to source voltage which keeps the
JFET gate currents and input stage frequency response
nearly constant over the common mode input range of
the device. These enhancements provide excellent
CMRR, AC performance and very low input distortion
over a wide temperature range. The common mode
input performance for offset voltage and bias current is
shown in FIGURE 40. Note that the input bias current
remains low even after the maximum input stage
common mode voltage is exceeded (as indicated by the
abrupt change in input offset voltage).
10
8
500
VS = ±15V
INPUT OFFSET VOLTAGE (VOS) T = +25°C
400
6
300
4
200
2
100
0
0
-2
-100
-4
-200
-6
-300
INPUT BIAS (IB)
-8
-10
-15
NORMALIZED VOS (uV)
Functional Description
JFET Input Stage Performance
NORMALIZED INPUT BIAS CURRENT (pA)
Applications Information
-400
-10
-5
0
5
10
-500
15
VCM (V)
FIGURE 40. INPUT OFFSET VOLTAGE AND BIAS
CURRENT vs COMMON MODE INPUT
VOLTAGE
Output Drive Capability
The complementary bipolar emitter follower output
stage features low output impedance (Figure 40) and is
capable of substantial current drive over the full
temperature range (Figures 25, 26) while driving the
output voltage close to the supply rails. The output
current is internally limited to approximately ±50mA at
+25°C. The amplifiers can withstand a short circuit to
either rail as long as the power dissipation limits are not
exceeded. This applies to only 1 amplifier at a time for
the dual op amp. Continuous operation under these
conditions may degrade long term reliability.
Output Phase Reversal
Output phase reversal is a change of polarity in the
amplifier transfer function when the input voltage
exceeds the supply voltage. The ISL28110 and ISL28210
are immune to output phase reversal, out to 0.5V
beyond the rail (VABS MAX) limit. Beyond these limits,
the device is still immune to reversal to 1V beyond the
FN6639.0
September 13, 2010
ISL28110, ISL28210
rails but damage to the internal ESD protection diodes
can result unless these input currents are limited.
Maximizing Dynamic Signal Range
The amplifiers maximum undistorted output swing is a
figure of merit for precision, low distortion applications.
Audio amplifiers are a good example of amplifiers that
require low noise and low signal distortion over a wide
output dynamic range. When these applications operate
from batteries, raising the amplifier supply voltage to
overcome poor output voltage swing has the penalty of
increased power consumption and shorter battery life.
Amplifiers whose input and output stages can swing
closest to the power supply rails while providing low
noise and undistorted performance, will provide
maximum useful dynamic signal range and longer
battery life.
Rail-to-rail input and output (RRIO) amplifiers have the
highest dynamic signal range but their added complexity
degrades input noise and amplifier distortion. Many
contain two input pairs, one pair operating to each supply
rail. The trade-offs for these are increased input noise
and distortion caused by non-linear input bias current
and capacitance when amplifying high impedance
sources. Their rail-to-rail output stages swing to within a
few millivolts of the rail, but output impedances are high
so that their output swing decreases and distortion
increases rapidly with increasing load current. At heavy
load currents the maximum output voltage swing of RRO
op amps can be lower than a good emitter follower
output stage.
The ISL28110 and ISL28210 low noise input stage and
high performance output stage are optimized for low
THD+N into moderate loads over the full -40°C to
+125°C temperature range. Figures 17 and 18 show the
1kHz THD+N unity gain performance vs output voltage
swing at load resistances of 2kΩ and 600Ω. Figure 41
shows the unity-gain THD+N performance driving
600Ω from ±5V supplies.
Power Dissipation
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power supply
conditions. It is therefore important to calculate the
maximum junction temperature (TJMAX) for all
applications to determine if power supply voltages, load
conditions, or package type need to be modified to
remain in the safe operating area. These parameters are
related using Equation 1:
T JMAX = T MAX + θ JA xPD MAXTOTAL
(EQ. 1)
where:
• PDMAXTOTAL is the sum of the maximum power
dissipation of each amplifier in the package (PDMAX)
• PDMAX for each amplifier can be calculated using
Equation 2:
V OUTMAX
PD MAX = V S × I qMAX + ( V S - V OUTMAX ) × ---------------------------RL
(EQ. 2)
where:
• TMAX = Maximum ambient temperature
• θJA = Thermal resistance of the package
• PDMAX = Maximum power dissipation of 1 amplifier
• VS = Total supply voltage
• IqMAX = Maximum quiescent supply current of 1
amplifier
• VOUTMAX = Maximum output voltage swing of the
application
• RL = Load resistance
1
VS = ±5V
RL = 600Ω
THD+N (%)
0.1
AV = 1
+125°C
+85°C
+25°C
0.01
0.001
0°C
-40°C
0.0001
0
1
2
3
4
5
6
VP-P (V)
7
8
9
10
FIGURE 41. UNITY-GAIN THD+N vs OUTPUT VOLTAGE
vs TEMPERATURE AT VS = ±5V FOR 600Ω
LOAD
15
FN6639.0
September 13, 2010
ISL28110, ISL28210
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
9/13/10
FN6639.0
CHANGE
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL28110, ISL28210
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
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Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
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For information regarding Intersil Corporation and its products, see www.intersil.com
16
FN6639.0
September 13, 2010
ISL28110, ISL28210
Package Outline Drawing
L8.3x3A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 4, 2/10
( 2.30)
3.00
( 1.95)
A
B
3.00
( 8X 0.50)
6
PIN 1
INDEX AREA
(4X)
(1.50)
( 2.90 )
0.15
PIN 1
TOP VIEW
(6x 0.65)
( 8 X 0.30)
TYPICAL RECOMMENDED LAND PATTERN
SEE DETAIL "X"
2X 1.950
PIN #1
INDEX AREA
0.10 C
0.75 ±0.05
6X 0.65
C
0.08 C
1
SIDE VIEW
6
1.50 ±0.10
8
8X 0.30 ±0.05
8X 0.30 ± 0.10
2.30 ±0.10
C
4
0.10 M C A B
0 . 2 REF
5
0 . 02 NOM.
0 . 05 MAX.
DETAIL "X"
BOTTOM VIEW
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.20mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
7.
Compliant to JEDEC MO-229 WEEC-2 except for the foot length.
either a mold or mark feature.
17
FN6639.0
September 13, 2010
ISL28110, ISL28210
Package Outline Drawing
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 3, 3/10
5
3.0±0.05
A
DETAIL "X"
D
8
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
B
0.65 BSC
GAUGE
PLANE
TOP VIEW
0.55 ± 0.15
0.25
3°±3°
0.85±010
H
DETAIL "X"
C
SEATING PLANE
0.25 - 0.036
0.08 M C A-B D
0.10 ± 0.05
0.10 C
SIDE VIEW 1
(5.80)
NOTES:
(4.40)
(3.00)
1. Dimensions are in millimeters.
(0.65)
(0.40)
(1.40)
TYPICAL RECOMMENDED LAND PATTERN
18
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
FN6639.0
September 13, 2010
ISL28110, ISL28210
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.10 C
0.175 ± 0.075
SIDE VIEW “A
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
(5.40)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5.
The pin #1 identifier may be either a mold or mark feature.
6.
Reference to JEDEC MS-012.
TYPICAL RECOMMENDED LAND PATTERN
19
FN6639.0
September 13, 2010