Intersil ISL80030AFRZ-T7A 3a synchronous buck converter in 2x2 dfn package Datasheet

DATASHEET
3A Synchronous Buck Converter In 2x2 DFN Package
ISL80030, ISL80030A, ISL80031, ISL80031A
The ISL80030, ISL80030A, ISL80031 and ISL80031A are highly
Features
efficient, monolithic, synchronous step-down DC/DC converters
• VIN range 2.7V to 5.5V
that can deliver up to 3A of continuous output current from a 2.7V
to 5.5V input supply. They use peak current mode control
architecture to allow very low duty cycle operation. They operate
at either a 1MHz or 2MHz switching frequency, thereby providing
superior transient response and allowing for the use of small
inductors. They have excellent stability.
• Up to 3A of output current
• Switching frequency is 1MHz or 2MHz (see Table 1 on page 3)
• 35µA quiescent current (ISL80031/A)
• Overcurrent and short-circuit protection
The ISL80030, ISL80030A, ISL80031 and ISL80031A integrate
very low rDS(ON) MOSFETs in order to maximize efficiency. In
addition, since the high-side MOSFET is a PMOS, the need for a
Boot capacitor is eliminated, thereby reducing external
component count. They can operate at 100% duty cycle.
• Over-temperature/thermal protection
The ISL80031, ISL80031A configured for PFM discontinuous
conduction operation, provides high efficiency by reducing
switching losses at light loads.
• Internal soft-start and soft-stop
ISL80030, ISL80030A configured for PWM pulse width
modulation operation, provides a fast transient response,
which helps reduce the output noise and RF interference.
• Up to 95% peak efficiency
• Negative current protection
• Power-good and enable
• 100% duty cycle
• VIN undervoltage lockout and VOUT overvoltage protection
Applications
• General purpose POL
These devices are offered in a space saving 8 pin 2mmx2mm
DFN lead-free package with exposed pad for improved thermal
performance. The complete converter occupies less than
64mm2 area.
3
EN
4
PG
PG
L1
PHASE 8
PGND 6
FB
EPAD
9
93
VOUT
C2
22µF
GND
C3
22pF
R1
200k 1%
5
0.6V R2
100k 1%
87
80
VOUT = 1.8V
73
VOUT = 2.5V
67
VO
R 1 = R 2  ------------ – 1
 VFB

(EQ. 1)
60
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
LOAD (A)
FIGURE 1. TYPICAL APPLICATION CIRCUIT CONFIGURATION
July 20, 2015
FN8766.0
VOUT = 3.3V
+1.8V/3A
PGND 7
EN
• Game console
EFFICIENCY (%)
GND
+2.7V …+5.5V 1
VIN
C1
22µF
2
VIN
• Telecom and networking equipment
100
ISL80030/ISL80031
VIN
• Industrial, instrumentation and medical equipment
1
FIGURE 2. EFFICIENCY vs LOAD, ISL80031, VIN = 5V, TA = +25°C
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL80030, ISL80030A, ISL80031, ISL80031A
Table of Contents
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PFM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Short-circuit Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative Current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable, Disable and Soft-start Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Discharge Mode (Soft-stop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100% Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Derating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
15
15
16
16
16
16
16
16
16
16
17
17
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Inductor and Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
17
17
17
17
18
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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TABLE 1. SUMMARY OF KEY DIFFERENCES
PART#
PWM/PFM MODE
fSW
(MHz)
ISL80030
PWM
1
ISL80030A
PWM
2
ISL80031
PFM
1
ISL80031A
PFM
2
VIN RANGE
(V)
IOUT (MAX)
(A)
PACKAGE
SIZE
2.7 to 5.5
3
8 pin 2mmx2mm DFN
NOTE: In this datasheet, the parts in the table above are collectively called "device".
TABLE 2. COMPONENT VALUE SELECTION TABLE
VOUT
(V)
C1
(µF)
C2
(µF)
C3
(pF)
L1
(µH)
R1
(kΩ)
R2
(kΩ)
0.8
22
22
22
1.0~2.2
33
100
1.2
22
22
22
1.0~2.2
100
100
1.5
22
22
22
1.0~2.2
150
100
1.8
22
22
22
1.0~3.3
200
100
2.5
22
22
22
1.5~3.3
316
100
3.3
22
22
22
1.5~4.7
450
100
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ISL80030, ISL80030A, ISL80031, ISL80031A
Pin Configuration
ISL80030, ISL80030A, ISL80031, ISL80031A
(8 LD 2x2 DFN)
TOP VIEW
VIN
1
VIN
2
EN
3
PG
4
EPAD
(GND)
PAD
8
PHASE
7
PGND
6
PGND
5
FB
Pin Descriptions
PIN NUMBER
PIN NAME
PIN DESCRIPTION
1, 2
VIN
The input supply for the power stage of the PWM regulator and the source for the internal linear regulator that provides
bias for the IC. Place a minimum of 10µF ceramic capacitance from VIN to GND and as close as possible to the IC for
decoupling.
3
EN
Device enable input. When the voltage on this pin rises above 1.4V, the device is enabled. The device is disabled when
the pin is pulled to ground. When the device is disabled, a 100Ω resistor discharges the output through the PHASE pin.
See Figure 3, “Functional Block Diagram” on page 5 for details.
4
PG
Power-good output is pulled to ground during the soft-start interval and also when the output voltage is below regulation
limits. There is an internal 5MΩ internal pull-up resistor on this pin.
5
FB
Feedback pin for the regulator. FB is the negative input to the voltage loop error amplifier. The output voltage is set by
an external resistor divider connected to FB. In addition, the power-good PWM regulator’s power-good and undervoltage
protection circuits use FB to monitor the output voltage.
6, 7
PGND
Power and analog ground connections. Connect directly to the board GROUND plane.
8
PHASE
Power stage switching node for output voltage regulation. Connect to the output inductor. This pin is discharged by an
100Ω resistor when the device is disabled. See Figure 3, “Functional Block Diagram” on page 5 for details.
-
EPAD
The exposed pad must be connected to the PGND pin for proper electrical performance. Place as many vias as possible
under the pad connecting to the PGND plane for optimal thermal performance.
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Functional Block Diagram
27pF
SOFTSoft
START
SHUTDOWN
200kΩ
+
VREF
BANDGAP
VIN
OSCILLATOR
+
EN
+
EAMP
COMP
-
-
P
PWM/PFM
LOGIC
CONTROLLER
PROTECTION
SHUTDOWN
3pF
PHASE
N
HS DRIVER
+
PGND
FB
SLOPE
Slope
COMP
1.15*VREF
6kΩ
+
-
CSA
OV
+
+
OCP
-
0.85*VREF
+
UV
+
VIN
SKIP
5MΩ
PG
1ms
DELAY
-
NEG CURRENT
SENSING
ZERO-CROSS
SENSING
0.3V
SCP
+
100Ω
SHUTDOWN
FIGURE 3. FUNCTIONAL BLOCK DIAGRAM
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Ordering Information
PART NUMBER
(Notes 1, 2, 3)
TAPE AND REEL
QUANTITY
PART
MARKING
TECHNICAL
SPECIFICATIONS
TEMP. RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL80030FRZ-T
1000
030
1MHz, PWM
-40 to +125
8 Ld DFN
L8.2x2E
ISL80030FRZ-T7A
250
030
1MHz, PWM
-40 to +125
8 Ld DFN
L8.2x2E
ISL80030AFRZ-T
1000
30A
2MHz, PWM
-40 to +125
8 Ld DFN
L8.2x2E
ISL80030AFRZ-T7A
250
30A
2MHz, PWM
-40 to +125
8 Ld DFN
L8.2x2E
ISL80031FRZ-T
1000
031
1MHz, PFM
-40 to +125
8 Ld DFN
L8.2x2E
ISL80031FRZ-T7A
250
031
1MHz, PFM
-40 to +125
8 Ld DFN
L8.2x2E
ISL80031AFRZ-T
1000
31A
2MHz, PFM
-40 to +125
8 Ld DFN
L8.2x2E
ISL80031AFRZ-T7A
250
31A
2MHz, PFM
-40 to +125
8 Ld DFN
L8.2x2E
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL80030, ISL80030A, ISL80031, ISL80031A. For more information on
MSL please see techbrief TB363.
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Absolute Maximum Ratings
Thermal Information
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V (DC) or 7V (20ms)
PHASE . . . . . . . . . . . . . . -1.5V (100ns)/-0.3V (DC) to 6V (DC) or 7V (20ms)
EN, PG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN + 0.3V
FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
Junction Temperature Range at 0A . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
ESD Rating
Human Body Model (Tested per JESD22-JS-001). . . . . . . . . . . . . . . . 4kV
Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . 300V
Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . . . 2kV
Latch-up (Tested per JESD78D, Class 2, Level A). . . . ±100mA at +125°C
Thermal Resistance (Typical, Notes 4, 5)
JA (°C/W) JC (°C/W)
2x2 DFN Package . . . . . . . . . . . . . . . . . . . .
70
7
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Operating Junction Temperature Range . . . . . . . . . . . . . .-40°C to +125°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 3A
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379 for details.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications TA= -40°C to +125°C, VIN = 2.7V to 5.5V, unless otherwise noted. Typical values are at TA = +25°C. Boldface
limits apply across the junction operating temperature range, -40°C to +125°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
2.5
2.7
V
INPUT SUPPLY
VIN Undervoltage Lockout Threshold
VUVLO
Rising, no load
Falling, no load
Quiescent Supply Current
IVIN
Shutdown Supply Current
ISD
2.2
2.4
V
ISL80031A, no load at the output
35
60
µA
ISL80030, no load at the output
7
15
mA
ISL80030A, no load at the output
10
22
mA
ISL80031, ISL80031A, VIN = 5.5V, EN = low
1.2
10
µA
0.600
0.606
V
OUTPUT REGULATION
Feedback Voltage
VFB
VFB Bias Current
IVFB
Line Regulation
0.594
TJ = -40°C to +125°C
0.589
0.606
V
VFB = 2.7V. TJ = -40°C to +125°C
-120
50
350
nA
VIN = VO + 0.5V to 5.5V (minimal 2.7V)
Nominal = 3.6V
-0.32
-0.05
0.28
%/V
Soft-start Ramp Time Cycle
1
ms
PROTECTIONS
Positive Peak Current Limit
IPLIMIT
Peak Skip Limit
ISKIP
Zero Cross Threshold
3.6
Negative Current Limit
INLIMIT
5.4
450
ISL80031, ISL80031A
VIN = 3.6, VOUT = 1.8V (See “Applications
Information” on page 17 for more detail)
ISL80031, ISL80031A
4.5
A
mA
-170
-70
30
mA
-2.6
-2
-1
A
Thermal Shutdown
Temperature rising
150
°C
Thermal Shutdown Hysteresis
Temperature falling
25
°C
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Electrical Specifications TA= -40°C to +125°C, VIN = 2.7V to 5.5V, unless otherwise noted. Typical values are at TA = +25°C. Boldface
limits apply across the junction operating temperature range, -40°C to +125°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
COMPENSATION
Error Amplifier Transconductance
40
Transresistance
RT
0.20
0.25
µA/V
0.30
Ω
PHASE
P-Channel MOSFET ON-resistance
VIN = 5V, IO = 200mA
70
mΩ
N-Channel MOSFET ON-resistance
VIN = 5V, IO = 200mA
60
mΩ
100

PHASE Maximum Duty Cycle
PHASE Minimum On-time
ISL80030; ISL80030A
60
80
ns
OSCILLATOR
Nominal Switching Frequency
fSW
ISL80030, ISL80031
850
1000
1150
kHz
ISL80030A, ISL80031A
1700
2000
2300
kHz
0.3
V
2
ms
PG
Output Low Voltage
1mA sinking current
Delay Time (Rising Edge)
0.5
PGOOD Delay Time (Falling Edge)
1
5
PG Pin Leakage Current
PG = VIN
OVP PG Rising Threshold
110
OVP PG Hysteresis
µs
0.01
0.1
117
125
2
UVP PG Rising Threshold
80
UVP PG Hysteresis
85
µA
%
%
90
2
%
%
EN LOGIC
Logic Input Low
Logic Input High
0.4
V
1
µA
1.4
Logic Input Leakage Current
IEN
Pulled up to 5.5V
V
0.1
NOTES:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
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July 20, 2015
ISL80030, ISL80030A, ISL80031, ISL80031A
100
100
93
90
EFFICIENCY (%)
EFFICIENCY (%)
Typical Performance Curves
87
80
VOUT = 1.2V
VOUT = 1.5V
73
80
VOUT = 1.2V
70
VOUT = 1.5V
60
VOUT = 1.8V
VOUT = 1.8V
VOUT = 2.5V
50
67
VOUT = 2.5V
60
0
0.3
0.6
0.9
1.2 1.5 1.8
LOAD (A)
2.1
2.4
2.7
93
90
EFFICIENCY (%)
100
87
80
73
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
FIGURE 5. EFFICIENCY vs LOAD (ISL80030A)
fSW = 2MHz, VIN = 3.3V, PWM, TA = +25°C
100
VOUT = 1.2V
0
LOAD (A)
FIGURE 4. EFFICIENCY vs LOAD (ISL80031A)
fSW = 2MHz, VIN = 3.3V, PFM, TA = +25°C
EFFICIENCY (%)
40
3.0
VOUT = 1.5V
VOUT = 1.8V
67
80
VOUT = 1.2V
70
VOUT = 1.5V
60
VOUT = 1.8V
VOUT = 2.5V
50
VOUT = 2.5V
60
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
40
3.0
0
0.3
0.6
0.9
FIGURE 6. EFFICIENCY vs LOAD (ISL80031)
fSW = 1MHz, VIN = 3.3V, PFM, TA = +25°C
1.8
2.1
100
VOUT = 3.3V
93
2.4
2.7
3.0
VOUT = 3.3V
93
EFFICIENCY (%)
EFFICIENCY (%)
1.5
FIGURE 7. EFFICIENCY vs LOAD (ISL80030)
fSW = 1MHz, VIN = 3.3V, PWM, TA = +25°C
100
87
80
VOUT = 1.2V
VOUT = 1.5V
73
VOUT = 1.8V
67
60
1.2
LOAD (A)
LOAD (A)
VOUT = 2.5V
0
0.3
0.6
0.9
1.2 1.5 1.8
LOAD (A)
2.1
2.4
FIGURE 8. EFFICIENCY vs LOAD (ISL80031A)
fSW = 2MHz, VIN = 5V, PFM, TA = +25°C
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2.7
3.0
80
VOUT = 1.2V
67
VOUT = 1.5V V
OUT = 1.8V
VOUT = 2.5V
53
40
0
0.3
0.6
0.9
1.2 1.5 1.8
LOAD (A)
2.1
2.4
2.7
3.0
FIGURE 9. EFFICIENCY vs LOAD (ISL80030A)
fSW = 2MHz, VIN = 5V, PWM, TA = +25°C
FN8766.0
July 20, 2015
ISL80030, ISL80030A, ISL80031, ISL80031A
Typical Performance Curves
(Continued)
100
100
VOUT = 3.3V
90
EFFICIENCY (%)
EFFICIENCY (%)
93
87
80
VOUT = 1.2V
73
VOUT = 1.5V
VOUT = 1.8V
VOUT = 2.5V
67
60
0
0.3
0.6
0.9
1.2 1.5 1.8
LOAD (A)
2.1
2.4
2.7
80
VOUT = 1.2V
70
VOUT = 1.5V
VOUT = 2.5V
40
0
1.827
OUTPUT VOLTAGE (V)
1.872
1.867
5VIN PFM
1.863
3.3VIN PFM
1.854
0
0.3
0.6
0.9
1.2
1.5
1.8
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
2.1
2.4
2.7
3.0
3.3VIN PWM
1.826
1.825
1.824
5VIN PWM
1.823
1.822
0
0.3
OUTPUT LOAD (A)
FIGURE 12. VOUT REGULATION vs LOAD (ISL80031)
fSW = 1MHz, VOUT = 1.8V, PFM, TA = +25°C
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
OUTPUT LOAD (A)
FIGURE 13. VOUT REGULATION vs LOAD (ISL80030)
fSW = 1MHz, VOUT = 1.8V, PWM, TA = +25°C
PHASE 5V/DIV
PHASE 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
VEN 5V/DIV
VEN 5V/DIV
PG 5V/DIV
PG 5V/DIV
500µs/DIV
FIGURE 14. START-UP AT NO LOAD (ISL80031A)
fSW = 2MHz, VIN = 5V, PFM, TA = +25°C
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0.6
FIGURE 11. EFFICIENCY vs LOAD (ISL80030)
fSW = 1MHz, VIN = 5V, PWM, TA = +25°C
1.828
1.850
0.3
LOAD (A)
1.876
1.859
VOUT = 1.8V
60
50
3.0
FIGURE 10. EFFICIENCY vs LOAD (ISL80031)
fSW = 1MHz, VIN = 5V, PFM, TA = +25°C
OUTPUT VOLTAGE (V)
VOUT = 3.3V
10
500µs/DIV
FIGURE 15. START-UP AT NO LOAD (ISL80030A)
fSW = 2MHz, VIN = 5V, PWM, TA = +25°C
FN8766.0
July 20, 2015
ISL80030, ISL80030A, ISL80031, ISL80031A
Typical Performance Curves
(Continued)
PHASE 5V/DIV
PHASE 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
VEN 5V/DIV
VEN 5V/DIV
PG 5V/DIV
PG 5V/DIV
500µs/DIV
500µs/DIV
FIGURE 16. SHUTDOWN AT NO LOAD (ISL80031A)
fSW = 2MHz, VIN = 5V, PFM, TA = +25°C
FIGURE 17. SHUTDOWN AT NO LOAD (ISL80030A)
fSW = 2MHz, VIN = 5V, PWM, TA = +25°C
VEN 5V/DIV
VEN 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
IL 2A/DIV
IL 2A/DIV
PG 5V/DIV
PG 5V/DIV
500µs/DIV
FIGURE 18. START-UP AT 3A LOAD (ISL80030A)
fSW = 2MHz, VIN = 5V, PWM, TA = +25°C
500µs/DIV
FIGURE 19. SHUTDOWN AT 3A LOAD (ISL80030A)
fSW = 2MHz, VIN = 5V, PWM, TA = +25°C
VEN 5V/DIV
VEN 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
IL 2A/DIV
IL 2A/DIV
PG 5V/DIV
PG 5V/DIV
500µs/DIV
FIGURE 20. START-UP AT 3A LOAD (ISL80031A)
fSW = 2MHz, VIN = 5V, PFM, TA = +25°C
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1ms/DIV
FIGURE 21. SHUTDOWN AT 3A LOAD (ISL80031A)
fSW = 2MHz, VIN = 5V, PFM, TA = +25°C
FN8766.0
July 20, 2015
ISL80030, ISL80030A, ISL80031, ISL80031A
Typical Performance Curves
(Continued)
VIN 5V/DIV
VIN 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
IL 2A/DIV
IL 2A/DIV
PG 5V/DIV
PG 5V/DIV
500µs/DIV
500µs/DIV
FIGURE 22. START-UP VIN AT 3A LOAD (ISL80031A)
fSW = 2MHz, VIN = 5V, PFM, TA = +25°C
PHASE 5V/DIV
FIGURE 23. START-UP VIN AT 3A LOAD (ISL80030A)
fSW = 2MHz, VIN = 5V, PWM, TA = +25°C
PHASE 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
VIN 5V/DIV
VIN 5V/DIV
PG 5V/DIV
PG 5V/DIV
100µs/DIV
FIGURE 24. SHUTDOWN VIN AT 3A LOAD (ISL80031A)
fSW = 2MHz, VIN = 5V, PFM, TA = +25°C
PHASE 5V/DIV
20µs/DIV
FIGURE 25. SHUTDOWN VIN AT 3A LOAD (ISL80030A)
fSW = 2MHz, VIN = 5V, PWM, TA = +25°C
PHASE 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
VIN 5V/DIV
VIN 5V/DIV
PG 5V/DIV
PG 5V/DIV
500µs/DIV
FIGURE 26. START-UP VIN AT NO LOAD (ISL80031A)
fSW = 2MHz, VIN = 5V, PFM, TA = +25°C
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500µs/DIV
FIGURE 27. START-UP VIN AT NO LOAD (ISL80030A)
fSW = 2MHz, VIN = 5V, PWM, TA = +25°C
FN8766.0
July 20, 2015
ISL80030, ISL80030A, ISL80031, ISL80031A
Typical Performance Curves
(Continued)
PHASE 5V/DIV
PHASE 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
VIN 5V/DIV
VIN 5V/DIV
PG 5V/DIV
PG 5V/DIV
2ms/DIV
5ms/DIV
FIGURE 28. SHUTDOWN VIN AT NO LOAD (ISL80031A)
fSW = 2MHz, VIN = 5V, PFM, TA = +25°C
FIGURE 29. SHUTDOWN VIN AT NO LOAD (ISL80030A)
fSW = 2MHz, VIN = 5V, PWM, TA = +25°C
PHASE 1V/DIV
PHASE 1V/DIV
10ns/DIV
10ns/DIV
FIGURE 30. JITTER AT NO LOAD (ISL80030A)
fSW = 2MHz, VIN = 5V, PWM, TA = +25°C
FIGURE 31. JITTER AT FULL LOAD (ISL80030A)
fSW = 2MHz, VIN = 5V, PWM, TA = +25°C
PHASE 5V/DIV
PHASE 5V/DIV
VOUT 20mV/DIV
VOUT 10mV/DIV
IL 0.5A/DIV
IL 0.5A/DIV
50ms/DIV
FIGURE 32. STEADY STATE AT NO LOAD (ISL80031A)
fSW = 2MHz, VIN = 5V, PFM, TA = +25°C
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200ns/DIV
FIGURE 33. STEADY STATE AT NO LOAD (ISL80030A)
fSW = 2MHz, VIN = 5V, PWM, TA = +25°C
FN8766.0
July 20, 2015
ISL80030, ISL80030A, ISL80031, ISL80031A
Typical Performance Curves
(Continued)
PHASE 5V/DIV
PHASE 5V/DIV
VOUT 10mV/DIV
VOUT 10mV/DIV
IL 2A/DIV
IL 2A/DIV
500ns/DIV
FIGURE 34. STEADY STATE AT 3A LOAD (ISL80031A)
fSW = 2MHz, VIN = 5V, PFM, TA = +25°C
VOUT RIPPLE 50mV/DIV
500ns/DIV
FIGURE 35. STEADY STATE AT 3A LOAD (ISL80030A)
fSW = 2MHz, VIN = 5V, PWM, TA = +25°C
VOUT RIPPLE 50mV/DIV
IL 1A/DIV
IL 1A/DIV
200µs/DIV
200µs/DIV
FIGURE 36. LOAD TRANSIENT (ISL80031A)
fSW = 2MHz, VIN = 5V, PFM, TA = +25°C
PHASE 5V/DIV
FIGURE 37. LOAD TRANSIENT (ISL80030A)
fSW = 2MHz, VIN = 5V, PWM, TA = +25°C
VOUT 1V/DIV
IL 2A/DIV
IL 2A/DIV
VOUT 1V/DIV
PG 5V/DIV
PG 5V/DIV
5µs/DIV
FIGURE 38. OUTPUT SHORT-CIRCUIT (ISL80030A)
fSW = 2MHz, VIN = 5V, PWM, TA = +25°C
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500µs/DIV
FIGURE 39. OVERCURRENT PROTECTION (ISL80030A)
fSW = 2MHz, VIN = 5V, PWM, TA = +25°C
FN8766.0
July 20, 2015
ISL80030, ISL80030A, ISL80031, ISL80031A
Typical Performance Curves
(Continued)
PHASE 5V/DIV
VOUT 0.5V/DIV
IL 2A/DIV
PG 2V/DIV
VOUT 2V/DIV
PG 5V/DIV
1ms/DIV
200µs/DIV
FIGURE 40. OVERVOLTAGE PROTECTION (ISL80030A)
fSW = 2MHz, VIN = 5V, PWM, TA = +25°C
Theory of Operation
The device is a step-down switching regulator optimized for battery
powered applications. It operates at a high switching frequency
(1MHz or 2MHz), which enables the use of smaller inductors
resulting in small form factor, while also providing excellent
efficiency. The quiescent current is typically only 1.2µA when the
regulator is shut down.
PWM Control Scheme
The ISL80030, ISL80030A employ the current-mode pulse-width
modulation (PWM) control scheme for fast transient response and
pulse-by-pulse current limiting. See “Functional Block Diagram” on
page 5. The current loop consists of the oscillator, the PWM
comparator, current sensing circuit and the slope compensation for
the current loop stability. The slope compensation is 900mV/Ts,
which changes with frequency. The gain for the current sensing
circuit is typically 250mV/A. The control reference for the current
loop comes from the error amplifier's (EAMP) output.
The PWM operation is initialized by the clock from the oscillator.
The P-channel MOSFET is turned on at the beginning of a PWM
cycle and the current in the MOSFET starts to ramp-up. When the
sum of the current amplifier CSA and the slope compensation
reaches the control reference of the current loop, the PWM
comparator COMP sends a signal to the PWM logic to turn off the
P-FET and turn on the N-Channel MOSFET. The N-FET stays on until
the end of the PWM cycle. Figure 42 shows the typical operating
waveforms during the PWM operation. The dotted lines illustrate
the sum of the slope compensation ramp and the current-sense
amplifier’s CSA output.
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FIGURE 41. OVER-TEMPERATURE PROTECTION
fSW = 2MHz, VIN = 5V, PWM, TA = +150°C
VEAMP
VCSA
DUTY
CYCLE
IL
VOUT
FIGURE 42. PWM OPERATION WAVEFORMS
The reference voltage is 0.6V, which is used by feedback to
adjust the output of the error amplifier, VEAMP. The error
amplifier is a transconductance amplifier that converts the
voltage error signal to a current output. The voltage loop is
internally compensated with the 27pF and 200kΩ RC network.
The maximum EAMP voltage output is precisely clamped to 1.6V.
PFM Operation
The ISL80031, ISL80031A employs a pulse-skipping mode to
minimize the switching loss at light load by reducing the
switching frequency. Figure 43 on page 16 illustrates the
skip-mode operation. A zero-cross sensing circuit shown in
Figure 43 monitors the N-FET current for zero crossing. When 16
consecutive cycles of the inductor current crossing zero are
detected, the regulator enters the skip mode. During the eight
detecting cycles, the current in the inductor is allowed to become
negative. The counter is reset to zero when the current in any
cycle does not cross zero.
FN8766.0
July 20, 2015
ISL80030, ISL80030A, ISL80031, ISL80031A
PWM
PFM
PWM
CLOCK
16 CYCLES
PFM CURRENT LIMIT
IL
LOAD CURRENT
0
NOMINAL +1.5%
VOUT
NOMINAL -1.5%
NOMINAL
FIGURE 43. PFM MODE OPERATION WAVEFORMS
Once the skip mode is entered, the pulse modulation starts being
controlled by the SKIP comparator as shown in the “Functional
Block Diagram” on page 5. Each pulse cycle is still synchronized
by the PWM clock. The P-FET is turned on at the clock's rising
edge and turned off when the output is higher than 1.5% of the
nominal regulation or when its current reaches the peak skip
current limit value. Then the inductor current discharges to 0A
and stays at zero. The internal clock is disabled. The output
voltage reduces gradually due to the load current discharging the
output capacitor. When the output voltage drops to the nominal
voltage, the P-FET will be turned on again at the rising edge of
the internal clock as it repeats the previous operations.
Overcurrent Protection
The overcurrent protection is realized by monitoring the CSA
output with the OCP comparator, as shown in the “Functional
Block Diagram” on page 5. The current sensing circuit has a gain
of 300mV/A, from the P-FET current to the CSA output. When the
CSA output reaches a threshold, the OCP comparator is tripped to
turn off the P-FET immediately. The overcurrent function protects
the switching converter from a shorted output by monitoring the
current flowing through the upper MOSFET.
regulator will be in PFM for 20µs before switching to PWM if
necessary.
PG
PG is an output of a window comparator that continuously monitors
the buck regulator output voltage. PG is actively held low when EN is
low and during the buck regulator soft-start period. After 1ms delay
of the soft-start period, PG becomes high impedance as long as the
output voltage is within nominal regulation voltage set by VFB.
When VFB drops 15% below or raises 15% above the nominal
regulation voltage, the device pulls PG low. Any fault condition forces
PG low until the fault condition is cleared by attempts to soft-start.
There is an internal 5MΩ pull-up resistor to fit most applications. An
external resistor can be added from PG to VIN for more pull-up
strength.
UVLO
When the input voltage is below the Undervoltage Lockout
(UVLO) threshold, the regulator is disabled.
Enable, Disable and Soft-start Up
Upon detection of overcurrent condition, the upper MOSFET will
be immediately turned off and will not be turned on again until
the next switching cycle. If the overcurrent condition goes away,
the output will resume back into the regulation point.
After the VIN pin exceeds its rising POR trip point (nominal 2.5V),
the device begins operation. If the EN pin is held low externally,
nothing happens until this pin is released. Once the EN is
released and above the logic threshold, the internal default
soft-start time is 1ms.
Short-circuit Protection
Discharge Mode (Soft-stop)
The short-circuit protection (SCP) comparator monitors the VFB
pin voltage for output short-circuit protection. When the VFB is
lower than 0.3V, the SCP comparator forces the PWM oscillator
frequency to drop to 1/3 of the normal operation value. This
comparator is effective during start-up or an output short-circuit
event.
When a transition to shutdown mode occurs or the VIN UVLO is set,
the outputs discharge to GND through an internal 100Ω switch.
Negative Current Protection
Similar to the overcurrent, the negative current protection is
realized by monitoring the current across the low-side N-FET, as
shown in the “Functional Block Diagram” on page 5. When the
valley point of the inductor current reaches -2A for 2 consecutive
cycles, both P-FET and N-FET shut off. The 100Ω in parallel to the
N-FET will activate discharging the output into regulation. The
control will begin to switch when output is within regulation. The
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16
100% Duty Cycle
The device features 100% duty cycle operation to maximize the
battery life. When the battery voltage drops to a level that the
device can no longer maintain the regulation at the output, the
regulator completely turns on the P-FET. The maximum dropout
voltage under the 100% duty cycle operation is the product of the
load current and the ON-resistance of the P-FET.
FN8766.0
July 20, 2015
ISL80030, ISL80030A, ISL80031, ISL80031A
Applications Information
Thermal Shutdown
The device has built-in thermal protection. When the internal
temperature reaches +150°C, the regulator is completely shut
down. As the temperature drops to +125°C, the device resumes
operation by stepping through the soft-start.
Power Derating Characteristics
To prevent the device from exceeding the maximum junction
temperature, some thermal analysis is required. The
temperature rise is given by Equation 2:
(EQ. 2)
T RISE =  PD    JA 
Where PD is the power dissipated by the regulator and θJA is the
thermal resistance from the junction of the die to the ambient
temperature. The junction temperature, TJ, is given by
Equation 3:
(EQ. 3)
T j =  T A + T RISE 
Where TA is the ambient temperature. For the DFN package, the
θJA is +70°C/W.
The actual junction temperature should not exceed the absolute
maximum junction temperature of +125°C when considering
the thermal design.
The device delivers full current at ambient temperatures up to
+85°C; if the thermal impedance from the thermal pad
maintains the junction temperature below the thermal shutdown
level, depending on the input voltage/output voltage
combination and the switching frequency. The device power
dissipation must be reduced to maintain the junction
temperature at or below the thermal shutdown level. Figure 44
illustrates the approximate output current derating versus
ambient temperature for the ISL80030EVAL1Z board.
3.5
OUTPUT CURRENT (V)
To consider steady state and transient operations, the device
typically requires a 1µH output inductor. Higher or lower inductor
values can be used to optimize the total converter system
performance. For example, for higher output voltage 3.3V
application, in order to decrease the inductor ripple current and
output voltage ripple, the output inductor value can be increased.
It is recommended to set the inductor ripple current to be
approximately 30% of the maximum output current for optimized
performance. The inductor ripple current can be expressed as
shown in Equation 4:
VO 

V O   1 – ---------
V

IN
I = --------------------------------------L  f SW
(EQ. 4)
The inductor’s saturation current rating needs to be at least
larger than the peak current.
The device uses an internal compensation network and the
output capacitor value is dependent on the output voltage. The
ceramic capacitor is recommended to be X5R or X7R.
Output Voltage Selection
The output voltage of the regulator can be programmed via an
external resistor divider that is used to scale the output voltage
relative to the internal reference voltage and feed it back to the
inverting input of the error amplifier.
The output voltage programming resistor, R1, will depend on the
value chosen for the feedback resistor and the desired output
voltage of the regulator. The value for the feedback resistor is
typically between 10kΩ and 100kΩas shown in Equation 5.
VO
R 1 = R 2  ------------ – 1
 VFB

(EQ. 5)
If the output voltage desired is 0.6V, then R2 is left unpopulated
and R1 is shorted. There is a leakage current from VIN to LX. It is
recommended to preload the output with 10µA minimum. For
better performance, add 22pF in parallel with R1
VIN = 5V, OLFM
3.0
Output Inductor and Capacitor Selection
2.5
2.0
Input Capacitor Selection
1.5
1.0
0.5
0
50
60
70
80
90
100
TEMPERATURE (°C)
110
120
FIGURE 44. DERATING CURVE vs TEMPERATURE
130
The main functions for the input capacitor are to provide
decoupling of the parasitic inductance and to provide filtering
function to prevent the switching current flowing back to the
battery rail. At least two 22µF X5R or X7R ceramic capacitors are
a good starting point for the input capacitor selection.
Output Capacitor Selection
An output capacitor is required to filter the inductor current.
Output ripple voltage and transient response are two critical
factors when considering output capacitance choice. The current
mode control loop allows for the usage of low ESR ceramic
capacitors and thus smaller board layout. Electrolytic and
polymer capacitors may also be used.
Additional consideration applies to ceramic capacitors. While
they offer excellent overall performance and reliability, the actual
in-circuit capacitance must be considered. Ceramic capacitors
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FN8766.0
July 20, 2015
ISL80030, ISL80030A, ISL80031, ISL80031A
are rated using large peak-to-peak voltage swings and with no DC
bias. In the DC/DC converter application, these conditions do not
reflect reality. As a result, the actual capacitance may be
considerably lower than the advertised value. Consult the
manufacturers datasheet to determine the actual in-application
capacitance. Most manufacturers publish capacitance vs DC bias
so this effect can be easily accommodated. The effects of AC
voltage are not frequently published, but an assumption of ~20%
further reduction will generally suffice. The result of these
considerations can easily result in an effective capacitance 50%
lower than the rated value. Nonetheless, they are a very good
choice in many applications due to their reliability and extremely
low ESR.
The following equations allow calculation of the required
capacitance to meet a desired ripple voltage level. Additional
capacitance may be used.
For the ceramic capacitors (low ESR) =
I
V OUTripple = ------------------------------------8 f SW C OUT
Layout Considerations
The PCB layout is a very important converter design step to make
sure the designed converter works well. The power loop is
composed of the output inductor L’s, the output capacitor COUT,
the PHASE’s pins and the PGND pin. It is necessary to make the
power loop as small as possible and the connecting traces
among them should be direct, short and wide. The switching
node of the converter, the PHASE pins and the traces connected
to the node are very noisy, so keep the voltage feedback trace
away from these noisy traces. The input capacitor should be
placed as closely as possible to the VIN pin and the ground of the
input and output capacitors should be connected as closely as
possible. The heat of the IC is mainly dissipated through the
thermal pad. Maximizing the copper area connected to the
thermal pad is preferable. In addition, a solid ground plane is
helpful for better EMI performance. It is recommended to add at
least 4 vias ground connection within the pad for the best
thermal relief.
(EQ. 6)
Where I is the inductor’s peak-to-peak ripple current, fSW is the
switching frequency and COUT is the output capacitor.
If using electrolytic capacitors then:
V OUTripple = I*ESR
(EQ. 7)
Regarding transient response needs, a good starting point is to
determine the allowable overshoot in VOUT if the load is suddenly
removed. In this case, energy stored in the inductor will be
transferred to COUT causing its voltage to rise. After calculating
capacitance required for both ripple and transient needs, choose
the larger of the calculated values. The following equation
determines the required output capacitor value in order to
achieve a desired overshoot relative to the regulated voltage.
I OUT 2 * L
C OUT = -------------------------------------------------------------------------------------------V OUT 2 *  V OUTMAX  V OUT  2 – 1 
(EQ. 8)
Where VOUTMAX/VOUT is the relative maximum overshoot
allowed during the removal of the load. For an overshoot of 5%,
Equation 9 becomes as follows:
I OUT 2 * L
C OUT = ----------------------------------------------------V OUT 2 *  1.05 2 – 1 
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(EQ. 9)
18
FN8766.0
July 20, 2015
ISL80030, ISL80030A, ISL80031, ISL80031A
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
July 20, 2015
FN8766.0
CHANGE
Initial release
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19
FN8766.0
July 20, 2015
ISL80030, ISL80030A, ISL80031, ISL80031A
Package Outline Drawing
L8.2x2E
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE (DFN) WITH E-PAD
Rev 0, 5/15
2.00
6
PIN #1 INDEX AREA
A
B
6
PIN 1
INDEX AREA
8
1
0.50
2.00
1.45±0.050
Exp.DAP
(4X)
0.15
0.10 M C A B
0.25
( 8x0.30 )
TOP VIEW
0.80±0.050
Exp.DAP
BOTTOM VIEW
(8x0.20)
Package Outline
(8x0.30)
SEE DETAIL "X"
(6x0.50)
1.45
2.00
0.10 C
0.90 ±0.10
C
BASE PLANE
SEATING PLANE
0.08 C
SIDE VIEW
(8x0.25)
0.80
2.00
TYPICAL RECOMMENDED LAND PATTERN
C
0.2 REF
0.00 MIN.
0.05 MAX.
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
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20
FN8766.0
July 20, 2015