Maxim MAX9323 One-to-four lvcmos-to-lvpecl output clock and data driver Datasheet

19-2575; Rev 0; 10/02
One-to-Four LVCMOS-to-LVPECL
Output Clock and Data Driver
Applications
Precision Clock Distribution
Features
♦ 1.7psRMS Added Random Jitter
♦ 150ps (max) Part-to-Part Skew
♦ 11ps Output-to-Output Skew
♦ 450ps Propagation Delay
♦ Pin Compatible with ICS8535-01
♦ Consumes Only 25mA (max) Supply Current
(50% Less than ICS8535-01)
♦ Synchronous Output Enable/Disable
♦ Two Selectable LVCMOS Inputs
♦ 3.0V to 3.6V Supply Voltage Range
♦ -40°C to +85°C Operating Temperature Range
Ordering Information
PART
MAX9323EUP
Low-Jitter Data Repeater
Data and Clock Driver and Buffer
Central-Office Backplane Clock Distribution
TEMP RANGE
PIN-PACKAGE
-40°C to +85°C
20 TSSOP
MAX9323ETP*
-40°C to +85°C
20 Thin QFN-EP**
*Future product—Contact factory for availability.
**EP = Exposed paddle.
Functional Diagram and Typical Operating Circuit appear at
end of data sheet.
DSLAM Backplane
Base Station
Hubs
CLK_EN
GND
Q0
Q0
TOP VIEW
CLK_SEL
Pin Configurations
20
19
18
17
16
CLK0 1
15 VCC
N.C. 2
14 Q1
MAX9323
CLK1 3
13 Q1
12 Q2
11 Q2
N.C. 5
19 Q0
CLK_SEL 3
18 VCC
CLK0 4
17 Q1
MAX9323
16 Q1
CLK1 6
15 Q2
N.C. 7
14 Q2
N.C. 8
13 VCC
N.C. 9
12 Q3
VCC 10
11 Q3
10
VCC
9
Q3
8
Q3
7
VCC
N.C.
6
20 Q0
N.C. 5
**EXPOSED PADDLE
N.C. 4
GND 1
CLK_EN 2
THIN QFN-EP** (4mm x 4mm)
**CONNECT EXPOSED PADDLE TO GND.
TSSOP
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX9323
General Description
The MAX9323 low-skew, low-jitter, clock and data driver distributes one of two single-ended LVCMOS inputs
to four differential LVPECL outputs. A single logic control signal (CLK_SEL) selects the input signal to distribute to all outputs. The device operates from 3.0V to
3.6V, making the device ideal for 3.3V systems, and
consumes only 25mA (max) of supply current.
The MAX9323 features low 150ps part-to-part skew, low
11ps output-to-output skew, and low 1.7ps RMS jitter,
making the device ideal for clock and data distribution
across a backplane or board. All outputs are enabled
and disabled synchronously with the clock input to prevent partial output clock pulses.
The MAX9323 is available in space-saving 20-pin
TSSOP and ultra-small 20-pin 4mm ✕ 4mm thin QFN
packages and operates over the extended (-40°C to
+85°C) temperature range. The MAX9323 is pin compatible with Integrated Circuit Systems’ ICS8535-01.
MAX9323
One-to-Four LVCMOS-to-LVPECL
Output Clock and Data Driver
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +4.0V
Q_, Q_, CLK_, CLK_SEL,
CLK_EN to GND .....................................-0.3V to (VCC + 0.3V)
Continuous Output Current .................................................50mA
Surge Output Current........................................................100mA
Continuous Power Dissipation (TA = +70°C)
20-Pin TSSOP (derate 11mW/°C)..............................879.1mW
20-Pin 4mm ✕ 4mm Thin QFN (derate 16.9mW/°C)...1349.1mW
Junction-to-Ambient Thermal Resistance in Still Air
20-Pin TSSOP ............................................................+91°C/W
20-Pin 4mm ✕ 4mm Thin QFN.................................+59.3°C/W
Junction-to-Case Thermal Resistance
20-Pin TSSOP ............................................................+20°C/W
20-Pin 4mm ✕ 4mm Thin QFN......................................+2°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Soldering Temperature (10s) ...........................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, outputs terminated with 50Ω ±1% to (VCC - 2V), CLK_SEL = VCC or GND, CLK_EN = VCC, TA = -40°C to +85°C,
unless otherwise noted. Typical values are at VCC = 3.3V, TA = +25°C.) (Notes 1, 2, and 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INPUTS (CLK0, CLK1, CLK_SEL, CLK_EN)
CLK0, CLK1
2
VCC
CLK_EN, CLK_SEL
2
VCC
CLK0, CLK1
0
1.3
CLK_EN, CLK_SEL
0
0.8
Input High Voltage
VIH
Figure 1
Input Low Voltage
VIL
Figure 1
Input High Current
IIH
Input Low Current
IIL
Input Capacitance
CIN
CLK0, CLK1, CLK_SEL, CLK_EN (Note 4)
Single-Ended Output High
Voltage
VOH
Figure 1
Single-Ended Output Low
Voltage
VOL
Figure 1
Differential Output Voltage
VOD
Figure 1, VOD = VOH - VOL
CLK0, CLK1, CLK_SEL = VCC
CLK_EN = VCC
CLK0, CLK1, CLK_SEL = GND
CLK_EN = GND
150
-5
+5
-5
+5
-150
V
V
µA
µA
4
pF
VCC 1.4
VCC 1.0
V
VCC 2.0
VCC 1.7
V
0.6
0.85
V
25
mA
OUTPUTS (Q_, Q_)
SUPPLY
Supply Current (Note 5)
2
ICC
_______________________________________________________________________________________
One-to-Four LVCMOS-to-LVPECL
Output Clock and Data Driver
(VCC = 3.0V to 3.6V, outputs terminated with 50Ω ±1% to (VCC -2V), fIN < 266MHz, input duty cycle = 50%, input transition time =
1.1ns (20% to 80%), VIH = VCC, VIL = GND, CLK_SEL = VCC or GND, CLK_EN = VCC, TA = -40°C to +85°C, unless otherwise noted.
Typical values are at VCC = 3.3V, TA = +25°C.) (Note 4)
PARAMETER
Switching Frequency
Propagation Delay
SYMBOL
fMAX
tPHL, tPLH
MIN
TYP
VOH - VOL ≥ 0.6V
CONDITIONS
266
800
VOH - VOL ≥ 0.3V
1500
CLK0 or CLK1 to Q_, Q_, Figure 1 (Note 6)
100
UNITS
MHz
600
ps
Output-to-Output Skew
tSKOO
(Note 7)
30
ps
Part-to-Part Skew
tSKPP
(Note 8)
150
ps
Output Rise Time
tR
20% to 80%, Figure 1
100
203
300
ps
Output Fall Time
tF
80% to 20%, Figure 1
100
198
300
ps
48
50
52
%
1.7
3
ps(RMS)
10
ps(P-P)
Output Duty Cycle
ODC
Added Random Jitter
Added Jitter (Note 9)
tRJ
fIN = 266MHz, clock pattern (Note 9)
tAJ
VCC = 3.3V with 25mV superimposed
sinusoidal noise at 100kHz
450
MAX
Measurements are made with the device in thermal equilibrium.
Positive current flows into a pin. Negative current flows out of a pin.
DC parameters are production tested at TA = +25°C and guaranteed by design over the full operating temperature range.
Guaranteed by design and characterization. Limits are set at ±6 sigma.
All pins open except VCC and GND.
Measured from the 50% point of the input to the crossing point of the differential output signal.
Measured between outputs of the same part at the differential signal crosspoint for a same-edge transition.
Measured between outputs of different parts at the differential signal crosspoint under identical conditions for a same-edge
transition.
Note 9: Jitter added to the input signal.
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
_______________________________________________________________________________________
3
MAX9323
AC ELECTRICAL CHARACTERISTICS
Typical Operating Characteristics
(VCC = 3.3V, outputs terminated to (VCC - 2V) through 50Ω, CLK_SEL = VCC or GND, CLK_EN = VCC, TA = +25°C.)
OUTPUT AMPLITUDE (VOH - VOL)
vs. FREQUENCY
SUPPLY CURRENT vs. TEMPERATURE
13.0
12.5
12.0
11.5
11.0
600
500
400
300
200
100
10.5
0
10.0
-15
10
35
60
0
85
200 400 600 800 1000 1200 1400 1600
TEMPERATURE (°C)
FREQUENCY (MHz)
OUTPUT RISE/FALL TIME
vs. TEMPERATURE
PROPAGATION DELAY
vs. TEMPERATURE
500
MAX9323 toc03
230
210
tR
200
190
180
tF
170
490
PROPAGATION DELAY (ps)
220
MAX9323 toc04
-40
480
tPLH
470
460
450
tPHL
440
430
160
420
150
410
400
140
-40
-15
10
35
TEMPERATURE (°C)
4
MAX9323 toc02
700
OUTPUT AMPLITUDE (mV)
13.5
SUPPLY CURRENT (mA)
800
MAX9323 toc01
14.0
OUTPUT RISE/FALL TIME (ps)
MAX9323
One-to-Four LVCMOS-to-LVPECL
Output Clock and Data Driver
60
85
-40
-15
10
35
60
TEMPERATURE (°C)
_______________________________________________________________________________________
85
One-to-Four LVCMOS-to-LVPECL
Output Clock and Data Driver
PIN
TSSOP
QFN
1
18
NAME
GND
FUNCTION
Ground. Provide a low-impedance connection to the ground plane.
2
19
CLK_EN
Synchronous Output Enable. Connect CLK_EN to VCC or leave floating to enable the
differential outputs. Connect CLK_EN to GND to disable the differential outputs. When
disabled, Q_ asserts low and Q_ asserts high. An internal 51kΩ pullup resistor to VCC allows
CLK_EN to be left floating.
3
20
CLK_SEL
Clock Select Input. Connect CLK_SEL to VCC to select the CLK1 input. Connect CLK_SEL to
GND or leave floating to select the CLK0 input. Only the selected CLK_ signal is reproduced
at each output. An internal 51kΩ pulldown resistor to GND allows CLK_SEL to be left floating.
4
1
CLK0
LVCMOS Clock Input. When CLK_SEL = GND, each set of outputs differentially reproduces
CLK0. An internal 51kΩ pulldown resistor to GND forces the outputs (Q_, Q_) to differential low
when CLK0 is left open or at GND, CLK_SEL = GND, and the outputs are enabled.
5, 7, 8, 9
2, 4, 5, 6
N.C.
No Connect. Not internally connected.
6
3
CLK1
LVCMOS Clock Input. When CLK_SEL = VCC, each set of outputs differentially reproduces
CLK1. An internal 51kΩ pulldown resistor to GND forces the outputs (Q_, Q_) to differential low
when CLK1 is left open or at GND, CLK_SEL = VCC, and the outputs are enabled.
10, 13, 18
7, 10, 15
VCC
Positive Supply Voltage. Bypass VCC to GND with three 0.01µF and one 0.1µF ceramic
capacitors. Place the 0.01µF capacitors as close to each VCC input as possible (one per VCC
input). Connect all VCC inputs together, and bypass to GND with a 0.1µF ceramic capacitor.
11
8
Q3
Inverting Differential LVPECL Output. Terminate Q3 to (VCC - 2V) with a 50Ω ±1% resistor.
12
9
Q3
Noninverting Differential LVPECL Output. Terminate Q3 to (VCC - 2V) with a 50Ω ±1% resistor.
14
11
Q2
Inverting Differential LVPECL Output. Terminate Q2 to (VCC - 2V) with a 50Ω ±1% resistor.
15
12
Q2
Noninverting Differential LVPECL Output. Terminate Q2 to (VCC - 2V) with a 50Ω ±1% resistor.
16
13
Q1
Inverting Differential LVPECL Output. Terminate Q1 to (VCC - 2V) with a 50Ω ±1% resistor.
17
14
Q1
Noninverting Differential LVPECL Output. Terminate Q1 to (VCC - 2V) with a 50Ω ±1% resistor.
19
16
Q0
Inverting Differential LVPECL Output. Terminate Q0 to (VCC - 2V) with a 50Ω ±1% resistor.
20
17
Q0
Noninverting Differential LVPECL Output. Terminate Q0 to (VCC - 2V) with a 50Ω ±1% resistor.
Detailed Description
The MAX9323 low-skew, low-jitter, clock and data driver distributes one of two single-ended LVCMOS input
signals to four differential LVPECL outputs. An input
multiplexer allows selection of one of the two input signals. The output drivers operate at frequencies up to
1.5GHz. The MAX9323 operates from 3.0V to 3.6V,
making it ideal for 3.3V systems.
Data Inputs
Single-Ended LVCMOS Inputs
The MAX9323 accepts two single-ended LVCMOS
inputs (CLK0 and CLK1, Figure 1). An internal reference (VCC/2) provides the input thresold voltage for
CLK0 and CLK1. CLK_SEL selects the CLK0 input or
CLK1 input to be converted to four differential LVPECL
signals (see Table 1). Connect CLK_SEL to GND to
select CLK0. Connect CLK_SEL to VCC to select CLK1.
CLK0 and CLK1 are pulled to GND through internal
51kΩ resistors, when not connected.
CLK_EN Input
CLK_EN enables/disables the differential outputs of the
MAX9323. Connect CLK_EN to VCC to enable the differential outputs. The (Q_, Q_) outputs are driven to a differential low condition when CLK_EN = GND. Each
differential output pair disables following successive rising and falling edges on CLK_, after CLK_EN connects to
GND. Both a rising and falling edge on CLK_ are required
to complete the enable/disable function (Figure 2).
CLK_SEL Input
CLK_SEL selects which single-ended LVCMOS input
signal is output differentially as four LVPECL signals.
Connect CLK_SEL to GND to select the CLK0 input.
_______________________________________________________________________________________
5
MAX9323
Pin Description
MAX9323
One-to-Four LVCMOS-to-LVPECL
Output Clock and Data Driver
VIH
50% OF CLK INPUT
CLK0/CLK1
VIL
Q_
VOH
VOD
VOL
Q_
tPLH
tPHL
80%
DIFFERENTIAL
OUTPUT
WAVEFORM
Q_ - Q_
80%
0V
(DIFFERENTIAL)
tR
20%
tF
Figure 1. MAX9323 Clock Input-to-Output Delay and Rise/Fall Time
CLK0 OR
CLK1
DISABLED
ENABLED
CLK_EN
Q_
Q_
Figure 2. MAX9323 CLK_EN Timing Diagram
6
_______________________________________________________________________________________
20%
One-to-Four LVCMOS-to-LVPECL
Output Clock and Data Driver
MAX9323
Table 1. Control Input Table
INPUTS
OUTPUTS
CLK_EN
CLK_SEL
SELECTED SOURCE
Q0–Q3
Q0–Q3
0
0
CLK0
Disabled, pulled to logic low
Disabled, pulled to logic high
0
1
CLK1
Disabled, pulled to logic low
Disabled, pulled to logic high
1
0
CLK0
Enabled
Enabled
1
1
CLK1
Enabled
Enabled
Connect CLK_SEL to VCC to select the CLK1 input. An
internal 51kΩ pulldown resistor to GND allows
CLK_SEL to be left floating.
Applications Information
ance and maximize common-mode noise immunity by
maintaining the distance between differential traces
and avoiding sharp corners. Minimize the number of
vias to prevent impedance discontinuities. Minimize
skew by matching the electrical length of the traces.
Output Termination
Terminate both outputs of each differential pair through
50Ω to (VCC - 2V) or use an equivalent Thevenin termination. Use identical termination on each output for the
lowest output-to-output skew. Terminate both outputs
when deriving a single-ended signal from a differential
output. For example, using Q0 as a single-ended output requires termination for both Q0 and Q0.
Ensure that the output currents do not violate the current limits as specified in the Absolute Maximum
Ratings table. Observe the device’s total thermal limits
under all operating conditions.
Chip Information
TRANSISTOR COUNT: 4430
PROCESS: BiCMOS
Functional Diagram
VCC
VCC
VCC
VCC
Power-Supply Bypassing
Bypass V CC to GND using three 0.01µF ceramic
capacitors and one 0.1µF ceramic capacitor. Place the
0.01µF capacitors (one per VCC input) as close to VCC
as possible (see the Typical Operating Circuit). Use
multiple bypass vias to minimize parasitic inductance.
CLK_EN
Circuit Board Traces
CLK0
Q0
MAX9323
51kΩ
Q0
D
Q
CLK
Q1
Input and output trace characteristics affect the performance of the MAX9323. Connect each input and output
to a 50Ω characteristic impedance trace to minimize
reflections. Avoid discontinuities in differential imped-
Q1
0
51kΩ
GND
Q2
1
CLK1
Q2
51kΩ
GND
Q3
CLK_SEL
Q3
51kΩ
GND
GND
_______________________________________________________________________________________
7
One-to-Four LVCMOS-to-LVPECL
Output Clock and Data Driver
MAX9323
Typical Operating Circuit
3.0V TO
3.6V
0.01µF
0.01µF
0.01µF
0.1µF
VCC
VCC
VCC
ZO = 50Ω
Q0
Q0
ZO = 50Ω
MAX9323
50Ω
50Ω
ZO = 50Ω
CLK_SEL
LVPECL
RECEIVER
Q1
Q1
VCC - 2V
ZO = 50Ω
CLK0
ZO = 50Ω
CLK1
Q2
Q2
ZO = 50Ω
ON
CLK_EN
OFF
ZO = 50Ω
Q3
Q3
GND
8
ZO = 50Ω
_______________________________________________________________________________________
One-to-Four LVCMOS-to-LVPECL
Output Clock and Data Driver
PACKAGE OUTLINE
12,16,20,24L QFN THIN, 4x4x0.8 mm
21-0139
A
_______________________________________________________________________________________
9
MAX9323
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
MAX9323
One-to-Four LVCMOS-to-LVPECL Output Clock
and Data Driver
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
12,16,20,24L QFN THIN, 4x4x0.8 mm
21-0139
10
______________________________________________________________________________________
A
One-to-Four LVCMOS-to-LVPECL Output Clock
and Data Driver
TSSOP4.40mm.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
MAX9323
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)