[ /Title (CD74 HC688 , CD74 HCT68 8) /Subject (High Speed CMOS Data sheet acquired from Harris Semiconductor SCHS196 CD74HC688, CD74HCT688 September 1997 High Speed CMOS Logic 8-Bit Magnitude Comparator Features Description • Cascadable The Harris CD74HC688 and CD74HCT688 are 8-bit magnitude comparators designed for use in computer and logic applications that require the comparison of two 8-bit binary words. When the compared words are equal the output (Y) is low and can be used as the enabling input for the next device in a cascaded application. • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC Ordering Information • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs PART NUMBER TEMP. RANGE (oC) PKG. NO. PACKAGE • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V CD74HC688E -55 to 125 20 Ld PDIP E20.3 CD74HCT688E -55 to 125 20 Ld PDIP E20.3 CD74HC688M -55 to 125 20 Ld SOIC M20.3 • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH CD74HCT688M -55 to 125 20 Ld SOIC M20.3 CD54HC688 -55 to 125 Wafer NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. Pinout CD74HC688, CD74HCT688 (PDIP, SOIC) TOP VIEW E 1 A0 2 19 Y B0 3 18 B7 A1 4 17 A7 B1 5 16 B6 A2 6 15 A6 B2 7 14 B5 A3 8 13 A5 B3 9 12 B4 GND 10 11 A4 20 VCC CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1997 1 File Number 1646.1 CD74HC688, CD74HCT688 Functional Diagram A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 2 4 6 8 11 13 15 17 Y 3 19 5 7 9 12 14 16 18 1 E TRUTH TABLE INPUTS OUPUTS A, B E Y A=B L L A≠B L H X H H NOTES: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care 2 CD74HC688, CD74HCT688 Logic Diagram A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 E 1 10 GND 20 VCC 19 Y 3 CD74HC688, CD74HCT688 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 3) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. θJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) VIH - - 2 1.5 - - 1.5 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V MIN TYP MAX MIN MAX MIN MAX UNITS - 1.5 - V HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads VIL VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current - 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V - - - - - - - - - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V - - - - - - - - - V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V II VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 6 - - 8 - 80 - 160 µA 4 CD74HC688, CD74HCT688 DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER SYMBOL VI (V) IO (mA) High Level Input Voltage VIH - - Low Level Input Voltage VIL - High Level Output Voltage CMOS Loads VOH VIH or VIL 25oC VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 to 5.5 2 - - 2 - 2 - V - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II VCC and GND 0 5.5 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA ∆ICC (Note) VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS Enable 0.7 Data Inputs 0.35 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g., 360µA max at 25oC. Switching Specifications Input tr, tf = 6ns PARAMETER TEST SYMBOL CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 170 - 210 - 255 ns 4.5 - - 34 - 42 - 51 ns CL =15pF 5 - 14 - - - - - ns CL = 50pF 6 - - 29 - 36 - 43 ns CL = 50pF 2 - - 170 - 210 - 255 ns 4.5 - - 34 - 42 - 51 ns CL =15pF 5 - 14 - - - - - ns CL = 50pF 6 - - 29 - 36 - 43 ns HC TYPES Propagation Delay (Figure 1) An to Output Bn to Output tPLH, tPHL tPLH, tPHL CL = 50pF 5 CD74HC688, CD74HCT688 Switching Specifications Input tr, tf = 6ns (Continued) TEST SYMBOL CONDITIONS PARAMETER -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 120 - 150 - 180 ns 4.5 - - 24 - 30 - 36 ns CL =15pF 5 - 9 - - - - - ns CL = 50pF 6 - - 20 - 26 - 30 ns tTLH, tTHL CL = 50pF 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns E to Output tPLH, tPHL Output Transition Time (Figure 1) 25oC VCC (V) CL = 50pF Input Capacitance CIN CL = 50pF - - - 10 - 10 - 10 pF Power Dissipation Capacitance (Notes 4, 5) CPD CL =15pF 5 - 22 - - - - - pF tPLH, tPHL CL = 50pF 4.5 - - 34 - 42 - 51 ns CL =15pF 5 - 14 - - - - - ns tPLH, tPHL CL = 50pF 4.5 - - 34 - 42 - 51 ns CL =15pF 5 - 14 - - - - - ns tPLH, tPHL CL = 50pF 4.5 - - 24 - 30 - 36 ns CL =15pF 5 - 9 - - - - - ns 4.5 - - 15 - 19 - 22 ns HCT TYPES Propagation Delay (Figure 1) An to Output Bn to Output E to Output Output Transition Time (Figure 1) tTLH, tTHL CL = 50pF Input Capacitance CIN CL = 50pF - - - 10 - 10 - 10 pF Power Dissipation Capacitance (Notes 4, 5) CPD CL =15pF 5 - 22 - - - - - pF NOTES: 4. CPD is used to determine the dynamic power consumption, per gate. 5. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Test Circuit and Waveform tr = 6ns tf = 6ns ANY INPUT A OR B 90% INPUT LEVEL VS 10% GND tPHL tPLH OUTPUT Y VS tTLH tTHL FIGURE 1. PROPAGATION DELAY AMD TRANSITION TIMES 6 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. 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