Ordering number : ENA2046B LC87FBG08A CMOS IC 8K-byte FROM and 256-byte RAM integrated http://onsemi.com 8-bit 1-chip Microcontroller Overview The LC87FBG08A is an 8-bit microcontroller that, integrates on a single chip a number of hardware features such as 8K-byte flash ROM, 256-byte RAM, an On-chip-debugger, 16-bit timers/counters, a 16-bit timer/counter, two 8-bit timers, a base timer serving as a time-of-day clock, a synchronous SIO interface, an asynchronous/synchronous SIO interface, a UART interface, two 12-bit PWM channels, a 9-channel AD converter, a system clock frequency divider, an internal high-accuracy oscillator, a reference voltage generator circuit, an internal reset and an interrupt feature. unit : mm (typ) 3287 6.5 24 0.5 6.4 4.4 RAM • 256 × 9 bits 12 1 0.5 0.15 0.22 (0.5) • SSOP24 (275mil) : Lead-/Halogen-free type (build-to-order) • VCT24 (3×3) : Lead-/Halogen-free type 1.5max Package Form • SSOP24 (225mil) : Lead-/Halogen-free type 13 (1.3) Flash ROM • 8192 × 8 bits • Capable of On-board programming with wide range (2.2 to 5.5V) of voltage source. • Block-erasable in 128 byte units • Writable in 2-byte units Package Dimensions 0.1 Features SANYO : SSOP24(225mil) * This product is licensed from Silicon Storage Technology, Inc. (USA). Semiconductor Components Industries, LLC, 2013 May, 2013 Ver.1.01 70412HKIM 20120618-S00002 No.A2046-1/30 LC87FBG08A Package Dimensions Package Dimensions unit : mm (typ) 3175C (build-to-order ) unit : mm (typ) 3366 TOP VIEW 7.8 24 SIDE VIEW BOTTOM VIEW 13 3.0 0.4 0.5 5.6 7.6 (C0.14) 12 1 0.65 24 0.15 2 1 0.19 0.22 0.4 (0.5) (0.035) 0.8 1.5max SIDE VIEW 0.1 (1.3) (0.33) (0.09) (0.125) 3.0 SANYO : VCT24(3.0X3.0) SANYO : SSOP24(275mil) Minimum Bus Cycle • 83.3ns (12MHz at VDD=2.7V to 5.5V, Ta=-40°C to +85°C) • 100ns (10MHz at VDD=2.2V to 5.5V, Ta=-40°C to +85°C) • 250ns ( 4MHz at VDD=1.8V to 5.5V, Ta=-40°C to +85°C) Note: The bus cycle time here refers to the ROM read speed. Minimum Instruction Cycle Time • 250ns (12MHz at VDD=2.7V to 5.5V, Ta=-40°C to +85°C) • 300ns (10MHz at VDD=2.2V to 5.5V, Ta=-40°C to +85°C) • 750ns ( 4MHz at VDD=1.8V to 5.5V, Ta=-40°C to +85°C) Ports • Normal withstand voltage I/O ports Ports I/O direction can be designated in 1-bit units Ports I/O direction can be designated in 4-bit units • Dedicated oscillator ports/input ports • Reset pin • Power pins 12 (P1n, P20, P21, P70, CF2/XT2) 8 (P0n) 1 (CF1/XT1) 1 (RES) 2 (VSS1, VDD1) Timers • Timer 0: 16-bit timer/counter with a capture register. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) Mode 3: 16-bit counter (with a 16-bit capture register) • Timer 1: 16-bit timer/counter that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/ counter with an 8-bit prescaler (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM) No.A2046-2/30 LC87FBG08A • Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs) • Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs) • Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. 2) Interrupts are programmable in 5 different time schemes High-speed Clock Counter • Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz). • Can generate output real time. SIO • SIO0: 8-bit synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle =4/3 tCYC) 3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of data transmission possible in 1 byte units) • SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect) ■UART1 • Full duplex • 7/8/9 bit data bits selectable • 1 stop bit (2-bit in continuous data transmission) • Built-in baudrate generator Note: UART1 and PWM use the same pins (P20 and P21), so they cannot be used at the same time. AD converter: 12 bits/8 bits × 9 channels • Successive approximation • 12 bits/8 bits AD converter resolution selectable • Port input: 8 channels, Reference voltage input: 1 channel PWM: Multifrequency 12-bit PWM × 2 channels Note: UART1 and PWM use the same pins (P20 and P21), so they cannot be used at the same time. Reference voltage generator circuit (VREF17) • Capable of monitoring the power supply voltage by AD conversion of frequency variable RC oscillator circuit’s reference voltage. Remote Control Receiver Circuit (sharing pins with P15, SCK1, INT3, and T0IN) • Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC) Clock Output Function • Capable generating clock outputs with a frequency of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 of the source clock selected as the system clock. • Capable of generating the source clock for the subclock. Watchdog Timer • Capable of generating an internal reset on an overflow of a timer running on the low-speed RC oscillator clock or subclock. • Operating mode at standby is selectable from 3 modes (continue counting/stop operation/stop counting with a count value held). No.A2046-3/30 LC87FBG08A Interrupts • 19 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. Vector Address Level Interrupt Source 1 00003H X or L INT0 2 0000BH X or L INT1 3 00013H H or L INT2/T0L/INT4 4 0001BH H or L INT3/base timer 5 00023H H or L T0H 6 0002BH H or L T1L/T1H 7 00033H H or L SIO0/UART1 receive 8 0003BH H or L SIO1/UART1 transmit 9 00043H H or L ADC/T6/T7/ PWM4, PWM5 10 0004BH H or L Port 0 • Priority levels X > H > L • Of interrupts of the same level, the one with the smallest vector address takes precedence. Subroutine Stack Levels: 128levels (The stack is allocated in RAM.) High-speed Multiplication/Division Instructions • 16 bits × 8 bits (5 tCYC execution time) • 24 bits × 16 bits (12 tCYC execution time) • 16 bits ÷ 8 bits (8 tCYC execution time) • 24 bits ÷ 16 bits (12 tCYC execution time) Oscillation Circuits • Internal oscillation circuits Low-speed RC oscillation circuit (SRC): For system clock / For Watchdog timer (100kHz) Medium-speed RC oscillation circuit (RC): For system clock (1MHz) Frequency variable RC oscillation circuit (MRC): For system clock (8MHz ± 1.5%, Ta=-10°C to +85°C) • External oscillation circuits Hi-speed CF oscillation circuit (CF): For system clock, with internal Rf Low speed crystal oscillation circuit (X’tal): For low-speed system clock / For Watchdog timer, with internal Rf 1) The CF and crystal oscillation circuits share the same pins. The active circuit is selected under program control. 2) Both the CF and crystal oscillator circuits stop operation on a system reset. After reset is released, oscillation is stopped so start the oscillation operation by program. System Clock Divider Function • Can run on low current. • The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, and 76.8μs (at a main clock rate of 10MHz). Internal Reset Function • Power-on reset (POR) function 1) POR reset is generated only at power-on time. 2) The POR release level can be selected from 8 levels (1.67V, 1.97V, 2.07V, 2.37V, 2.57V, 2.87V, 3.86V, and 4.35V) through option configuration. • Low-voltage detection reset (LVD) function 1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls below a certain level. 2) The use or disuse of the LVD function and the low voltage threshold level (7 levels: 1.91V, 2.01V, 2.31V, 2.51V, 2.81V, 3.79V, 4.28V) can be selected by optional configuration. No.A2046-4/30 LC87FBG08A Standby Function • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) There are four ways of resetting the HALT mode. (1) Setting the reset pin to the low level (2) System resetting by low-voltage detection (3) System resetting by watchdog timer (4) Occurrence of an interrupt • HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The CF, low-/medium-/ Frequency variable RC, and crystal oscillators automatically stop operation. Note: The oscillation of the low-speed RC oscillator is also controlled directly by the watchdog timer and its standby-mode-time oscillation is also controlled. 2) There are five ways of resetting the HOLD mode. (1) Setting the reset pin to the lower level. (2) System resetting by low-voltage detection (3) System resetting by watchdog timer (4) Having an interrupt source established at either INT0, INT1, INT2, INT4 * INT0 and INT1 HOLD mode reset is available only when level detection is set. (5) Having an interrupt source established at port 0. • X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer. 1) The CF, low-/medium-/ Frequency variable RC oscillators automatically stop operation. Note: The oscillation of the low-speed RC oscillator is also controlled directly by the watchdog timer and its standby-mode-time oscillation is also controlled. 2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained. 3) There are six ways of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level. (2) System resetting by watchdog timer or low-voltage detection. (3) System resetting by watchdog timer or low-voltage detection. (4) Having an interrupt source established at either INT0, INT1, INT2, INT4 * INT0 and INT1 HOLD mode reset is available only when level detection is set. (5) Having an interrupt source established at port 0. (6) Having an interrupt source established in the base timer circuit. Note: Available only when X’tal oscillation is selected. Onchip Debugger (flash versions only) • Supports software debugging with the microcontroller mounted on the target board. • Software break setting • Stepwise execution of instructions • Real time RAM data monitoring function All the RAM data map contents can be monitored and rewritten on the screen when the program is running. (Part of the SFR data cannot be rewritten.) • Two channels of on-chip debugger pins are available to be compatible with small pin count devices. DBGP0 (P0), DBGP1 (P1) Data Security Function (flash versions only) • Protects the program data stored in flash memory from unauthorized read or copy. Note: This data security function does not necessarily provide absolute data security. No.A2046-5/30 LC87FBG08A Development Tools • On-chip-debugger : (1) TCB87 TypeB + LC87FBG08A (2) TCB87 TypeC (3 wire version) + LC87FBG08A Flash ROM Programming Boards Package Programming boards SSOP24(225mil) W87F2GS SSOP24(275mil) (build-to-order ) VCT24(3×3) W87FBGV Flash ROM Programmer Maker Model Single AF9709/AF9709B/AF9709C Programmer (Including Ando Electric Co., Ltd. models) Gang (Including Ando Electric Co., Ltd. models) Flash Support Group, Inc. (FSG) AF9723/AF9723B(Main body) Programmer AF9833(Unit) (Including Ando Electric Co., Ltd. models) Flash Support Group, Inc. (FSG) + Our company Device Rev 03.28 or later 87F008SU - - - - (Note 2) - AF9101/AF9103(Main body) In-circuit Programmer (FSG models) SIB87(Inter Face Driver) (Our company model) (Note 1) Our company Supported version Single/Gang SKK / SKK Type B / SKK Type C Programmer (SanyoFWS) 1.07 or later In-circuit/Gang SKK-DBG Type B / SKK-DBG Type C Chip Data Version Programmer (SanyoFWS) 2.38 or later Application Version LC87FBG08 For information about AF-Series: Flash Support Group, Inc. TEL: +81-53-459-1050 E-mail: [email protected] Note1: On-board-programmer from FSG (AF9101/AF9103) and serial interface driver from Our company (SIB87) together can give a PC-less, standalone on-board-programming capabilities. Note2: It needs a special programming devices and applications depending on the use of programming environment. Please ask FSG or Our company for the information. No.A2046-6/30 LC87FBG08A Pin Assignment P70/INT0/T0LCP/AN8 1 24 P07/T7O/DBGP02 RES 2 23 P06/AN6/T6O/DBGP01 VSS1 3 22 P05/AN5/CKO/DBGP00 CF1/XT1 4 21 P04/AN4 CF2/XT2 5 20 P03/AN3 VDD1 6 19 P02/AN2 P10/SO0 7 18 P01/AN1 P11/SI0/SB0 8 17 P00/AN0 P12/SCK0 9 16 P21/URX/INT4/T1IN/PWM5 P13/SO1/DBGP12 10 15 P20/UTX/INT4/T1IN/PWM4 P14/SI1/SB1/DBGP11 11 14 P17/T1PWMH/BUZ/INT1/T0HCP P15/SCK1/INT3/T0IN/DBGP10 12 13 P16/T1PWML/INT2/T0IN LC87FBG08A Top view SSOP24(225mil) “Lead-/Halogen-free Type” SSOP24(275mil) “Lead-/Halogen-free Type” SSOP24 NAME SSOP24 NAME 1 P70/INT0/T0LCP/AN8 13 P16/T1PWML/INT2/T0IN 2 RES 14 P17/T1PWMH/BUZ/INT1/T0HCP 3 VSS1 15 P20/UTX/INT4/T1IN/PWM4 4 CF1/XT1 16 P21/URX/INT4/T1IN/PWM5 5 CF2/XT2 17 P00/AN0 6 VDD1 18 P01/AN1 7 P10/SO0 19 P02/AN2 8 P11/SI0/SB0 20 P03/AN3 9 P12/SCK0 21 P04/AN4 10 P13/SO1/DBGP12 22 P05/AN5/CKO/DBGP00 11 P14/SI1/SB1/DBGP11 23 P06/AN6/T6O/DBGP01 12 P15/SCK1/INT3/T0IN/DBGP10 24 P07/T7O/DBGP02 No.A2046-7/30 13 P20/UTX/INT4/T1IN/PWM4 14 P21/URX/INT4/T1IN/PWM5 15 P00/AN0 16 P01/AN1 17 P02/AN2 18 P03/AN3 LC87FBG08A 12 P17/T1PWMH/BUZ/INT1/T0HCP P04/AN4 19 11 P16/T1PWML/INT2/T0IN P05/AN5/CKO/DBGP00 20 P06/AN6/T6O/DBGP01 21 P07/T7O/DBGP02 22 10 P15/SCK1/INT3/T0IN/DBGP10 LC87FBG08A 9 P14/SI1/SB1/DBGP11 8 P13/SO1/DBGP12 P70/INT0/T0LCP/AN8 23 RES 24 P11/SI0/SB0 6 P10/SO0 5 VDD1 4 CF2/XT2 3 CF1/XT1 2 VSS1 1 7 P12/SCK0 Top view VCT24(3×3) “Lead-/Halogen-free Type” VCT24 NAME VCT24 1 VSS1 13 NAME P20/UTX/INT4/T1IN/PWM4 2 CF1/XT1 14 P21/URX/INT4/T1IN/PWM5 3 CF2/XT2 15 P00/AN0 4 VDD1 16 P01/AN1 5 P10/SO0 17 P02/AN2 6 P11/SI0/SB0 18 P03/AN3 7 P12/SCK0 19 P04/AN4 8 P13/SO1/DBGP12 20 P05/AN5/CKO/DBGP00 9 P14/SI1/SB1/DBGP11 21 P06/AN6/T6O/DBGP01 10 P15/SCK1/INT3/T0IN/DBGP10 22 P07/T7O/DBGP02 11 P16/T1PWML/INT2/T0IN 23 P70/INT0/T0LCP/AN8 12 P17/T1PWMH/BUZ/INT1/T0HCP 24 RES No.A2046-8/30 LC87FBG08A System Block Diagram Interrupt control IR Flash ROM SRC Clock generator Standby control CF/ X’tal PLA PC RC MRC Reference voltage generator circuit ACC WDT Reset circuit (LVD/POR) Reset control RES B register C register SIO0 Bus interface SIO1 Port 0 Timer 0 Port 1 Timer 1 Port 2 Timer 6 Port 7 Timer 7 ADC Base timer INT0 to 2 INT3 (Noise filter) UART1 Port 2 INT4 PWM4 PWM5 ALU PSW RAR RAM Stack pointer On-chip debugger No.A2046-9/30 LC87FBG08A Pin Function Chart Pin Name I/O Description Option VSS1 - - Power supply pin No VDD1 - + Power supply pin No Port 0 I/O • 8-bit I/O port • I/O specifiable in 4-bit units P00 to P07 • Pull-up resistors can be turned on and off in 4-bit units. • HOLD reset input • Port 0 interrupt input • Pin functions Yes P05: System clock output P06: Timer 6 toggle output P07: Timer 7 toggle output P00(AN0) to P06(AN6): AD converter input P05(DBGP00) to P07(DBGP02): On-chip debugger 0 port Port 1 I/O • 8-bit I/O port • I/O specifiable in 1-bit units P10 to P17 • Pull-up resistors can be turned on and off in 1-bit units. • Pin functions P10: SIO0 data output P11: SIO0 data input/bus I/O P12: SIO0 clock I/O P13: SIO1 data output P14: SIO1 data input / bus I/O P15: SIO1 clock I/O / INT3 input (with noise filter) / timer 0 event input / timer 0H capture input P16: Timer 1PWML output / INT2 input/HOLD reset input/timer 0 event input / timer 0L capture input Yes P17: Timer 1PWMH output / beeper output / INT1 input / HOLD reset input / timer 0H capture input P15(DBGP10) to P13(DBGP12): On-chip-debugger 1 port Interrupt acknowledge type Port 2 I/O Rising & Rising Falling INT1 enable enable disable enable enable INT2 enable enable enable disable disable INT3 enable enable enable disable disable Falling H level L level • 2-bit I/O port • I/O specifiable in 1-bit units P20 to P21 • Pull-up resistors can be turned on and off in 1-bit units. • Pin functions P20: UART transmit / PWM4 output P21: UART receive / PWM5 output P20 to P21: INT4 input / HOLD reset input / timer 1 event input / timer 0L capture input / timer Yes 0H capture input Interrupt acknowledge types INT4 Port 7 P70 I/O Rising Falling enable enable Rising & Falling enable H level L level disable disable • 1-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units. • Pin functions P70: INT0 input / HOLD reset input / timer 0L capture input P70(AN8): AD converter input No Interrupt acknowledge types INT0 Rising Falling enable enable Rising & Falling disable H level L level enable enable Continued on next page. No.A2046-10/30 LC87FBG08A Continued from preceding page. Pin Name RES CF1/XT1 I/O Description I/O Option External reset input / internal reset output No • Ceramic resonator or 32.768kHz crystal oscillator input pin I • Pin function No General-purpose input port CF2/XT2 • Ceramic resonator or 32.768kHz crystal oscillator output pin I/O • Pin function No General-purpose I/O port Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name Option selected in units of Option type P00 to P07 1 bit 1 P10 to P17 1 bit P20 to P21 1 bit Output type Pull-up resistor CMOS Programmable (Note 1) 2 Nch-open drain No 1 CMOS Programmable 2 Nch-open drain Programmable 1 CMOS Programmable 2 Nch-open drain Programmable Nch-open drain Programmable Ceramic resonator/32.768kHz crystal resonator No P70 - No CF2/XT2 - No output Nch-open drain (N-channel open drain when set to general-purpose output port) Note 1: The control of the presence or absence of the programmable pull-up resistors for port 0 and the switching between low-and high-impedance pull-up connection is exercised in nibble (4-bit) units (P00 to 03 or P04 to 07). User Option Table Option Name Port output type Mask version Flash-ROM Option Selected in *1 Version Units of P00 to P07 1 bit CMOS P10 to P17 1 bit CMOS P20 to P21 1 bit CMOS Option to be Applied on Option Selection Nch-open drain Nch-open drain Nch-open drain Program start - address Low-voltage × - - *2 Detect function 01E00h detection reset function Power-on reset 00000h Enable:Use Disable:Not Used Detect level - 7-level Power-On reset level - 8-level function *1: Mask option selection - No change possible after mask is completed. *2: Program start address of the mask version is 00000h. No.A2046-11/30 LC87FBG08A Recommended Unused Pin Connections Recommended Unused Pin Connections Port Name Board Software P00 to P07 Open Output low P10 to P17 Open Output low P20 to P21 Open Output low P70 Open Output low CF1/XT1 Pulled low with a 100kΩ resistor or less General-purpose input port CF2/XT2 Pulled low with a 100kΩ resistor or less General-purpose input port On-chip Debugger Pin Connection Requirements For the treatment of the on-chip debugger pins, refer to the separately available documents entitled "RD87 on-chip debugger installation manual". Power Pin Treatment Recommendations (VDD1, VSS1) Connect bypass capacitors that meet the following conditions between the VDD1 and VSS1 pins: • Connect among the VDD1 and VSS1 pins and bypass capacitors C1 and C2 with the shortest possible heavy lead wires, making sure that the impedances between the both pins and the bypass capacitors are as possible (L1=L1’ , L2=L2’). • Connect a large-capacity capacitor C1 and a small-capacity capacitor C2 in parallel. The capacitance of C2 should approximately 0.1μF. L2 L1 VSS1 C1 C2 VDD1 L1’ L2’ No.A2046-12/30 LC87FBG08A Absolute Maximum Ratings at Ta = 25°C, VSS1 =0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Maximum supply VDD max VDD1 Input voltage VI CF1 Input/output VIO Ports 0, 1, 2, voltage voltage High level output current Peak output P70, CF2, RES IOPH Mean output IOMH Ports 0, 1, 2 typ max -0.3 +6.5 -0.3 VDD+0.3 -0.3 VDD+0.3 unit V CMOS output select Per 1 applicable pin current -10 CMOS output select Per 1 applicable pin -7.5 (Note 1-1) Total output ΣIOAH(1) Ports 0, 1, 2 Total of all applicable pins current Peak output -25 IOPL(1) current Low level output current Ports 0, 1, 2 current min Mean output Total output 20 P00, P01 Per 1 applicable pin 30 IOPL(3) P70, CF2 Per 1 applicable pin 10 IOML(1) P02 to P07 Per 1 applicable pin IOML(2) P00, P01 Per 1 applicable pin 20 IOML(3) P70, CF2 Per 1 applicable pin 7.5 ΣIOAL(1) Ports 0, 1, Total of all applicable pins 70 Ports 2, 7, CF2 Pd max(1) SSOP24(225mil) dissipation Ta=-40 to +85°C 111 Package only Pd max(2) Ta=-40 to +85°C Package with thermal 334 resistance board (Note 1-2) Pd max(3) VCT24(3 × 3) mW Ta=-40 to +85°C 66 Package only Pd max(4) mA 15 Ports 1, 2 current Power Per 1 applicable pin IOPL(2) current (Note 1-1) P02 to P07 Ports 1, 2 Ta=-40 to +85°C Package with thermal 335 resistance board (Note 1-3) Operating ambient Topr temperature Storage ambient temperature Tstg -40 +85 -55 +125 °C Note 1-1: The mean output current is a mean value measured over 100ms. Note 1-2: SEMI standards thermal resistance board (size: 76.1×114.3×1.6tmm, glass epoxy) is used. Note 1-3: Thermal resistance board (size: 40×50×0.8tmm, glass epoxy, 4-layer(2S2P)) is used. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. No.A2046-13/30 LC87FBG08A Allowable Operating Conditions at Ta = -40°C to +85°C, VSS1 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] max unit 2.7 5.5 VDD(2) 0.294μs ≤ tCYC ≤ 200μs 2.2 5.5 VDD(3) 0.735μs ≤ tCYC ≤ 200μs 1.8 5.5 VDD(1) supply voltage Memory typ 0.245μs ≤ tCYC ≤ 200μs Operating (Note 2-1) min VHD VDD1 VDD1 RAM and register contents sustained in HOLD mode. sustaining 1.6 supply voltage High level VIH(1) Ports 1, 2, 7 1.8 to 5.5 0.3VDD+0.7 VDD input voltage VIH(2) Ports 0 1.8 to 5.5 0.3VDD+0.7 VDD VIH(3) CF1, CF2, RES 1.8 to 5.5 0.75VDD VDD Low level VIL(1) Ports 1, 2, 7 4.0 to 5.5 VSS 0.1VDD+0.4 1.8 to 4.0 VSS 0.2VDD 4.0 to 5.5 VSS 0.15VDD+0.4 1.8 to 4.0 VSS 0.2VDD 1.8 to 5.5 VSS 0.25VDD input voltage VIL(2) Ports 0 VIL(3) CF1, CF2, RES High level IOH(1) Ports 0, 1, 2 4.5 to 5.5 -1.0 output current IOH(2) 2.7 to 4.5 -0.35 IOH(3) 1.8 to 2.7 -0.15 4.5 to 5.5 -6.0 2.7 to 4.5 -1.4 1.8 to 2.7 -0.8 IOH(4) P05 (System clock Per 1 applicable pin Per 1 applicable pin V output function IOH(5) used) IOH(6) IOH(1) Ports 0, 1, 2 Total of all applicable pins IOH(2) IOH(3) Per 1 applicable pin -25 2.7 to 4.5 -8.0 1.8 to 2.7 -3.5 Low level IOL(1) output current IOL(2) 2.7 to 4.5 1 IOL(3) 1.8 to 2.7 0.5 2.7 to 5.5 1 1.8 to 2.7 0.5 IOL(4) Ports 0, 1, 2 4.5 to 5.5 P70, CF2 Per 1 applicable pin P00, P01 Per 1 applicable pin IOL(5) IOL(6) 4.5 to 5.5 15 2.7 to 4.5 2 IOL(8) 1.8 to 2.7 1 Ports 0 Total of all applicable pins 4.5 to 5.5 40 IOL(2) 2.7 to 4.5 10 IOL(3) 1.8 to 2.7 5 4.5 to 5.5 70 2.7 to 4.5 21 1.8 to 2.7 10.5 IOL(4) Ports 0, 1, 2, CF2 Total of all applicable pins IOL(5) IOL(6) IOL(7) Ports 7 Total of all applicable pins 2.7 to 5.5 1 IOL(8) 1.8 to 2.7 0.5 tCYC 2.7 to 5.5 0.245 200 2.2 to 5.5 0.294 200 1.8 to 5.5 0.735 200 2.7 to 5.5 0.1 12 1.8 to 5.5 0.1 4 3.0 to 5.5 0.2 24.4 2.0 to 5.5 0.2 8 cycle time (Note 2-2) External system clock frequency 7 IOL(7) IOL(1) Instruction 4.5 to 5.5 FEXCF CF1 • CF2 pin open • System clock frequency division ratio=1/1 • External system clock duty=50±5% • CF2 pin open • System clock frequency division ratio=1/2 • External system clock duty=50±5% mA μs MHz Note 2-1: VDD must be held greater than or equal to 2.2V in the flash ROM onboard programming mode. Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Continued on next page. No.A2046-14/30 LC87FBG08A Continued from preceding page. Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Oscillation FmCF(1) CF1, CF2 frequency range 12MHz ceramic oscillation. See Fig. 1. FmCF(2) CF1, CF2 (Note 2-3) 10MHz ceramic oscillation. See Fig. 1. FmCF(3) CF1, CF2 min typ max 2.7 to 5.5 12 2.2 to 5.5 10 1.8 to 5.5 4 2.2 to 5.5 4 unit 4MHz ceramic oscillation. CF oscillation normal amplifier size selected. (CFLAMP=0) See Fig. 1. 4MHz ceramic oscillation. CF oscillation low amplifier size selected. (CFLAMP=1) MHz See Fig. 1. FmMRC(1) Frequency variable RC oscillation. (Note 2-4) FmMRC(2) 1.8 to 5.5 7.84 8.0 8.16 1.8 to 5.5 7.88 8.0 8.12 Frequency variable RC oscillation. • Ta=-10 to +85°C (Note 2-4) FmRC Internal medium-speed RC oscillation 1.8 to 5.5 0.5 1.0 2.0 FmSRC Internal low-speed RC oscillation 1.8 to 5.5 50 100 200 FsX’tal XT1, XT2 32.768kHz crystal oscillation See Fig. 1. Oscillation tmsMRC kHz 1.8 to 5.5 32.768 When Frequency variable RC stabilization oscillation state is switched from time stopped to enabled. 1.8 to 5.5 100 μs See Fig. 3. Note 2-3: See Tables 1 and 2 for the oscillation constants. Note 2-4: When switching the system clock, allow an oscillation stabilization time of 100μs or longer after the frequency variable RC oscillator circuit transmits from the "oscillation stopped" to "oscillation enabled" state. No.A2046-15/30 LC87FBG08A Electrical Characteristics at Ta = -40°C to +85°C, VSS1 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] High level input IIH(1) current Ports 0, 1, 2, Output disabled P70, RES Pull-up resistor off VIN=VDD (Including output Tr's off leakage min typ max unit 1.8 to 5.5 1 1.8 to 5.5 1 1.8 to 5.5 15 current) IIH(2) CF1, CF2 Input port selected VIN=VDD IIH(3) CF1 Reset state VIN=VDD Low level input IIL(1) current Ports 0, 1, 2, Output disabled P70, RES Pull-up resistor off VIN=VSS (Including output Tr's off leakage 1.8 to 5.5 μA -1 current) IIL(2) CF1, CF2 Input port selected 1.8 to 5.5 VIN=VSS Ports 0, 1, 2 -1 High level output VOH(1) IOH=-1mA 4.5 to 5.5 VDD-1 voltage VOH(2) IOH=-0.35mA 2.7 to 5.5 VDD-0.4 VOH(3) IOH=-0.15mA 1.8 to 5.5 VDD-0.4 VOH(4) P05 (System IOH=-6mA 4.5 to 5.5 VDD-1 VOH(5) clock output IOH=-1.4mA 2.7 to 5.5 VDD-0.4 IOH=-0.8mA 1.8 to 5.5 VDD-0.4 VOH(6) Low level output VOL(1) voltage function used) IOL=7mA 4.5 to 5.5 1.5 VOL(2) IOL=1mA 2.7 to 5.5 0.4 VOL(3) IOL=0.5mA 1.8 to 5.5 0.4 VOL(4) Ports 0, 1, 2 P70, CF2 IOL=1mA 2.7 to 5.5 0.4 IOL=0.5mA 1.8 to 5.5 0.4 IOL=15mA 4.5 to 5.5 1.5 VOL(7) IOL=2mA 2.7 to 5.5 0.4 VOL(8) IOL=1mA 1.8 to 5.5 0.4 VOH=0.9VDD When Port 0 selected 4.5 to 5.5 15 35 80 low-impedance pull-up. 1.8 to 4.5 18 50 230 VOH=0.9VDD When Port 0 selected 1.8 to 5.5 VOL(5) VOL(6) Pull-up resistance Rpu(1) Rpu(2) Rpu(3) P00, P01 Ports 0, 1, 2 P70 Port 0 V kΩ 100 200 400 high-impedance pull-up. Hysteresis voltage Pin capacitance VHYS(1) Ports 1, 2, P70, 2.7 to 5.5 0.1VDD VHYS(2) RES 1.8 to 2.7 0.07VDD CP All pins 1.8 to 5.5 10 V For pins other than that under test: VIN=VSS f=1MHz pF Ta=25°C No.A2046-16/30 LC87FBG08A SIO0 Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = 0V (Note 4-1-1) Parameter Symbol Frequency tSCK(1) Low level tSCKL(1) Specification Pin/ Conditions Remarks SCK0(P12) VDD[V] • See Fig. 5. Input clock tSCKH(1) 1.8 to 5.5 pulse width tCYC 4 • See Fig. 5. Output clock (Note 4-1-2) Frequency tSCK(2) Low level tSCKL(2) SCK0(P12) • CMOS output selected 4/3 • See Fig. 5. 1/2 pulse width tSCK High level tSCKH(2) pulse width tSCKHA(2) 1/2 1.8 to 5.5 • Continuous data transmission/reception mode tSCKH(2) +2tCYC • See Fig. 5. Serial input unit 1 • Continuous data tSCKHA(1) • CMOS output selected Data setup time tsDI(1) SB0(P11), SI0(P11) Data hold time • Must be specified with respect to rising edge of SIOCLK. thDI(1) Input clock tdD0(1) time SO0(P10), SB0(P11) • Continuous data (1/3)tCYC transmission/reception mode +0.08 • Synchronous 8-bit mode 1tCYC 1.8 to 5.5 Output clock tCYC tCYC 0.05 (Note 4-1-3) tdD0(3) +(10/3) 0.05 (Note 4-1-3) tdD0(2) tSCKH(2) 1.8 to 5.5 • See Fig. 5. Output delay Serial output max 1 transmission/reception mode Serial clock typ 2 pulse width High level min μs +0.08 (Note 4-1-3) (1/3)tCYC +0.08 Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 5. No.A2046-17/30 LC87FBG08A SIO1 Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = 0V (Note 4-2-1) Input clock Symbol Frequency tSCK(3) Low level tSCKL(3) Specification Pin/ Conditions Remarks SCK1(P15) VDD[V] • See Fig. 5. tSCK(4) Low level tSCKL(4) tCYC SCK1(P15) • CMOS output selected 2 • See Fig. 5. 1/2 1.8 to 5.5 tSCK tSCKH(4) 1/2 Serial input pulse width Data setup time tsDI(2) SI1(P14), SB1(P14) Data hold time • Must be specified with respect to rising edge of SIOCLK. thDI(2) (1/3)tCYC 1.8 to 5.5 tdD0(4) SO1(P13), Serial output SB1(P14) +0.01 0.01 • See Fig. 5. Output delay time unit 1 pulse width High level max 1 tSCKH(3) Frequency typ 2 1.8 to 5.5 pulse width High level min pulse width Output clock Serial clock Parameter • Must be specified with respect to μs falling edge of SIOCLK. • Must be specified as the time to the beginning of output state (1/2)tCYC 1.8 to 5.5 +0.05 change in open drain output mode. • See Fig. 5. Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] High/low level tPIH(1) INT0(P70), • Interrupt source flag can be set. pulse width tPIL(1) INT1(P17), • Event inputs for timer 0 or 1 are INT2(P16), enabled. min typ 1.8 to 5.5 1 1.8 to 5.5 2 max unit INT4(P20 to P21) tPIH(2) INT3(P15) when noise • Interrupt source flag can be set. tPIL(2) filter time constant is • Event inputs for timer 0 are 1/1 enabled. tPIH(3) INT3(P15) when noise • Interrupt source flag can be set. tPIL(3) filter time constant is • Event inputs for timer 0 are 1/32 INT3(P15) when noise • Interrupt source flag can be set. tPIL(4) filter time constant is • Event inputs for timer 0 are tPIL(5) RES 1.8 to 5.5 64 1.8 to 5.5 256 1.8 to 5.5 200 nabled. tPIH(4) 1/128 tCYC enabled. • Resetting is enabled. μs No.A2046-18/30 LC87FBG08A AD Converter Characteristics at VSS1 = 0V <12bits AD Converter Mode/Ta = -40°C to +85°C > Specification Parameter Symbol Pin/Remarks Resolution N AN0(P00) to Absolute ET AN6(P06), VDD[V] 1.8 to 5.5 (Note 6-1) AN8(P70) accuracy Conversion time Conditions • See Conversion time calculation TCAD formulas. (Note 6-2) Analog input VAIN min typ max unit 12 bit 2.7 to 5.5 ±16 1.8 to 5.5 ±20 2.7 to 5.5 32 115 2.2 to 5.5 134 215 1.8 to 5.5 400 430 VSS VDD 1.8 to 5.5 voltage range Analog port IAINH VAIN=VDD 1.8 to 5.5 input current IAINL VAIN=VSS 1.8 to 5.5 LSB μs V 1 μA -1 <8bits AD Converter Mode/Ta = -40°C to +85°C > Specification Parameter Symbol Pin/Remarks Resolution N AN0(P00) to Absolute ET AN6(P06), VDD[V] 1.8 to 5.5 (Note 6-1) 1.8 to 5.5 • See Conversion time calculation 2.7 to 5.5 TCAD formulas. (Note 6-2) Analog input min typ max VAIN unit 8 bit ±1.5 AN8(P70) accuracy Conversion time Conditions 20 90 2.2 to 5.5 80 135 1.8 to 5.5 245 265 VSS VDD 1.8 to 5.5 voltage range Analog port IAINH VAIN=VDD 1.8 to 5.5 input current IAINL VAIN=VSS 1.8 to 5.5 LSB 1 -1 μs V μA Conversion time calculation formulas: 12bits AD Converter Mode: TCAD(Conversion time) = ((52/(AD division ratio))+2)×(1/3)×tCYC 8bits AD Converter Mode: TCAD(Conversion time) = ((32/(AD division ratio))+2)×(1/3)×tCYC External Operating supply oscillation voltage range (FmCF) (VDD) CF-12MHz CF-8MHz CF-4MHz System division ratio Cycle time (SYSDIV) (tCYC) 2.7V to 5.5V 1/1 2.7V to 5.5V AD division AD conversion time (TCAD) ratio (ADDIV) 12bit AD 250ns 1/8 34.8μs 21.5μs 1/1 375ns 1/8 52.25μs 32.25μs 2.2V to 5.5V 1/1 375ns 1/32 208.25μs 128.25μs 2.7V to 5.5V 1/1 750ns 1/8 104.5μs 64.5μs 2.2V to 5.5V 1/1 750ns 1/16 208.5μs 128.5μs 1.8V to 5.5V 1/1 750ns 1/32 416.5μs 256.5μs 8bit AD Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog input channel. Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. The conversion time is 2 times the normal-time conversion time when: • The first AD conversion is performed in the 12-bit AD conversion mode after a system reset. • The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit conversion mode. No.A2046-19/30 LC87FBG08A Reference voltage (VREF17) Characteristics at Ta = -40°C to +85°C, VSS1 = 0V Parameter Symbol Output voltage VOVREF Reference voltage operation IDDVREF Pin/Remarks Conditions min typ 1.67 2.0 to 5.5 current (Note 7-1) Operation stabilization time Specification VDD[V] 2.0 to 5.5 tVRW max 1.75 V μA 110 2.0 to 5.5 (Note 7-2) unit 1.83 μs 100 Note 7-1: IDDVREF denotes the currents that only flow to multivariable RC oscillator circuit’s reference voltage circuit. Note 7-2: tVRW denotes the stabilization time from starting multivariable RC oscillator. Power-on Reset (POR) Characteristics at Ta = -40°C to +85°C, VSS1 = 0V Specification Parameter Symbol Pin/Remarks Conditions Option selected voltage POR release PORRL voltage Detection voltage typ max • Select from option. 1.67V 1.55 1.66 1.77 (Note 8-1) 1.97V 1.85 1.96 2.07 2.07V 1.93 2.05 2.17 2.37V 2.23 2.35 2.47 2.57V 2.43 2.55 2.67 2.87V 2.71 2.85 2.99 3.86V 3.65 3.83 4.00 4.35V 4.12 4.32 4.50 0.7 0.95 • See Fig. 7. POUKS unknown state Power supply rise min (Note 8-2) • Power supply rise PORIS time 100 time from 0V to 1.6V. unit V ms Note8-1: The POR release level can be selected out of 8 levels only when the LVD reset function is disabled. Note8-2: POR is in an unknown state before transistors start operation. Low Voltage Detection Reset (LVD) Characteristics at Ta = -40°C to +85°C, VSS1=0V Specification Parameter Symbol Pin/Remarks Conditions Option selected voltage LVD reset voltage LVDET (Note 9-2) LVD hysteresis width Detection voltage LVUKS minimum width max 1.91V 1.81 1.91 2.01 2.01V 1.90 2.00 2.10 (Note 9-3) 2.31V 2.20 2.30 2.40 • See Fig. 8. 2.51V 2.40 2.50 2.60 2.81V 2.68 2.80 2.92 3.79V 3.62 3.78 3.94 4.28V 4.09 4.27 4.45 1.91V 50 2.01V 50 2.31V 50 2.51V 50 2.81V 50 3.79V 50 4.28V 50 • See Fig. 8. 0.7 (Note 9-4) TLVDW typ (Note 9-1) LVHYS unknown state Low voltage detection • Select from option. min unit V mV 0.95 V • LVDET-0.5V • See Fig. 9. 0.2 ms (Reply sensitivity) Note9-1: The LVD reset level can be selected out of 7 levels only when the LVD reset function is enabled. Note9-2: LVD reset voltage specification values do not include hysteresis voltage. Note9-3: LVD reset voltage may exceed its specification values when port output state changes and/or when a large current flows through port. Note9-4: LVD is in an unknown state before transistors start operation. No.A2046-20/30 LC87FBG08A Consumption Current Characteristics at Ta = -40°C to +85°C, VSS1 = 0V Parameter Normal mode Symbol IDDOP(1) Specification Pin/ Conditions Remarks VDD1 VDD[V] min typ max unit • FmCF=12MHz ceramic oscillation mode consumption • System clock set to 12MHz side current • Internal low speed and medium speed RC 2.7 to 5.5 5.1 9.3 2.7 to 3.6 3.1 5.6 3.0 to 5.5 5.2 10 3.0 to 3.6 3.3 6.2 2.2 to 5.5 4.4 8.4 2.2 to 3.6 2.8 5.5 1.8 to 5.5 2.3 5.3 1.8 to 3.6 1.6 3.0 2.2 to 5.5 0.97 2.4 2.2 to 3.6 0.55 1.2 1.8 to 5.5 0.44 1.5 1.8 to 3.6 0.28 0.80 1.8 to 5.5 3.4 5.5 1.8 to 3.6 2.4 4.6 1.8 to 5.5 51 163 1.8 to 3.6 38 103 5.0 51 136 3.3 38 99 2.5 36 94 oscillation stopped. (Note 10-1) • Frequency variable RC oscillation stopped. (Note 10-2) • 1/1 frequency division ratio IDDOP(2) • CF1=24MHz external clock • System clock set to CF1 side • Internal low speed and medium speed RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/2 frequency division ratio IDDOP(3) • FmCF=10MHz ceramic oscillation mode • System clock set to 10MHz side • Internal low speed and medium speed RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/1 frequency division ratio IDDOP(4) • FmCF=4MHz ceramic oscillation mode • System clock set to 4MHz side • Internal low speed and medium speed RC oscillation stopped. • Frequency variable RC oscillation stopped. mA • 1/1 frequency division ratio IDDOP(5) • CF oscillation low amplifier size selected. (CFLAMP=1) • FmCF=4MHz ceramic oscillation mode • System clock set to 4MHz side • Internal low speed and medium speed RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/4 frequency division ratio IDDOP(6) • FsX’tal=32.768kHz crystal oscillation mode • Internal low speed RC oscillation stopped. • System clock set to internal medium speed RC oscillation. • Frequency variable RC oscillation stopped. • 1/2 frequency division ratio IDDOP(7) • FsX’tal=32.768kHz crystal oscillation mode • Internal low speed and medium speed RC oscillation stopped. • System clock set to 8MHz with frequency variable RC oscillation • 1/1 frequency division ratio IDDOP(8) • External FsX’tal and FmCF oscillation stopped. • System clock set to internal low speed RC oscillation. • Internal medium speed RC oscillation sopped. • Frequency variable RC oscillation stopped. • 1/1 frequency division ratio IDDOP(9) μA • External FsX’tal and FmCF oscillation stopped. • System clock set to internal low speed RC oscillation. • Internal medium speed RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/1 frequency division ratio • Ta=-10 to +50°C Note10-1: Values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. Note10-2: The consumption current values do not include operational current of LVD function if not specified. Continued on next page. No.A2046-21/30 LC87FBG08A Continued from preceding page. Parameter Normal mode Symbol IDDOP(10) Specification Pin/ Conditions Remarks VDD1 VDD[V] consumption • System clock set to 32.768kHz side current • Internal low speed and medium speed RC (Note 10-1) min typ max unit • FsX’tal=32.768kHz crystal oscillation mode 1.8 to 5.5 34 97 1.8 to 3.6 14 44 5.0 34 88 3.3 14 36 2.5 9.1 22 2.7 to 5.5 2.6 4.8 2.7 to 3.6 1.4 2.4 3.0 to 5.5 2.7 5.3 3.0 to 3.6 1.6 2.9 2.2 to 5.5 2.2 4.3 2.2 to 3.6 1.2 2.2 1.8 to 5.5 1.3 3.3 1.8 to 3.6 0.56 1.2 2.2 to 5.5 0.74 1.8 2.2 to 3.6 0.34 0.68 1.8 to 5.5 0.32 0.90 1.8 to 3.6 0.21 0.44 oscillation stopped. • Frequency variable RC oscillation stopped. (Note 10-2) • 1/2 frequency division ratio IDDOP(11) μA • FsX’tal=32.768kHz crystal oscillation mode • System clock set to 32.768kHz side • Internal low speed and medium speed RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/2 frequency division ratio • Ta=-10 to +50°C HALT mode IDDHALT(1) • HALT mode consumption • FmCF=12MHz ceramic oscillation mode current • System clock set to 12MHz side (Note 10-1) • Internal low speed and medium speed RC (Note 10-2) oscillation stopped. • Frequency variable RC oscillation stopped. • 1/1 frequency division ratio IDDHALT(2) • HALT mode • CF1=24MHz external clock • System clock set to CF1 side • Internal low speed and medium speed RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/2 frequency division ratio IDDHALT(3) • HALT mode • FmCF=10MHz ceramic oscillation mode • System clock set to 10MHz side • Internal low speed and medium speed RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/1 frequency division ratio IDDHALT(4) • HALT mode • FmCF=4MHz ceramic oscillation mode • System clock set to 4MHz side mA • Internal low speed and medium speed RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/1 frequency division ratio IDDHALT(5) • HALT mode • CF oscillation low amplifier size selected. (CFLAMP=1) • FmCF=4MHz ceramic oscillation mode • System clock set to 4MHz side • Internal low speed and medium speed RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/4 frequency division ratio IDDHALT(6) • HALT mode • FsX’tal=32.768kHz crystal oscillation mode • Internal low speed RC oscillation stopped. • System clock set to internal medium speed RC oscillation • Frequency variable RC oscillation stopped. • 1/2 frequency division ratio Note10-1: Values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. Note10-2: The consumption current values do not include operational current of LVD function if not specified. Continued on next page. No.A2046-22/30 LC87FBG08A Continued from preceding page. Parameter HALT mode Symbol IDDHALT(7) Specification Pin/ Conditions remarks VDD1 VDD[V] consumption • FsX’tal=32.768kHz crystal oscillation mode current • Internal low speed and medium speed RC (Note 10-1) min typ max unit • HALT mode 1.8 to 5.5 1.3 2.3 oscillation stopped. mA • System clock set to 8MHz with (Note 10-2) frequency variable RC oscillation 1.8 to 3.6 0.91 1.5 1.8 to 5.5 18 68 1.8 to 3.6 11 35 5.0 18 46 3.3 11 27 2.5 7.4 19 1.8 to 5.5 24 98 1.8 to 3.6 8.0 35 5.0 24 63 • 1/1 frequency division ratio IDDHALT(8) • HALT mode • External FsX’tal and FmCF oscillation stopped. • System clock set to internal low speed RC oscillation. • Internal medium speed RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/1 frequency division ratio IDDHALT(9) • HALT mode • External FsX’tal and FmCF oscillation stopped. • System clock set to internal low speed RC oscillation. • Internal medium speed RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/1 frequency division ratio • Ta=-10 to +50°C IDDHALT(10) • HALT mode • FsX’tal=32.768kHz crystal oscillation mode • System clock set to 32.768kHz side • Internal low speed and medium speed RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/2 frequency division ratio IDDHALT(11) • HALT mode • FsX’tal=32.768kHz crystal oscillation mode • System clock set to 32.768kHz side μA • Internal low speed and medium speed RC oscillation stopped. 3.3 8.0 23 2.5 3.5 11 • Frequency variable RC oscillation stopped. • 1/2 frequency division ratio • Ta=-10 to +50°C HOLD mode IDDHOLD(1) consumption current (Note 10-1) IDDHOLD(2) (Note 10-2) HOLD mode 1.8 to 5.5 0.019 23 • CF1=VDD or open (External clock mode) 1.8 to 3.6 0.011 11 HOLD mode 5.0 0.019 1.2 • CF1=VDD or open (External clock mode) 3.3 0.011 0.59 2.5 0.010 0.30 1.8 to 5.5 2.6 26 1.8 to 3.6 2.0 13 5.0 2.6 3.8 3.3 2.0 2.8 • Ta=-10 to +50°C IDDHOLD(3) HOLD mode • CF1=VDD or open (External clock mode) • LVD option selected IDDHOLD(4) HOLD mode • CF1=VDD or open (External clock mode) • Ta=-10 to +50°C • LVD option selected Timer HOLD IDDHOLD(5) mode consumption current (Note 10-1) (Note 10-2) IDDHOLD(6) 2.5 1.7 2.5 Timer HOLD mode 1.8 to 5.5 22 84 • FsX’tal=32.768kHz crystal oscillation mode 1.8 to 3.6 6.5 30 5.0 22 53 3.3 6.5 16 2.5 2.7 7.2 Timer HOLD mode • FsX’tal=32.768kHz crystal oscillation mode • Ta=-10 to +50°C Note10-1: Values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. Note10-2: The consumption current values do not include operational current of LVD function if not specified. No.A2046-23/30 LC87FBG08A F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Onboard IDDFW(1) VDD1 min typ max unit • Only current of the Flash block. programming 2.2 to 5.5 5 10 mA 20 30 ms 40 60 μs current Programming tFW(1) • Erasing time time tFW(2) • Programming time 2.2 to 5.5 UART (Full Duplex) Operating Conditions at Ta = -40°C to +85°C, VSS1 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Transfer rate UBR P20, P21 1.8 to 5.5 min typ max 16/3 8192/3 unit tCYC Data length: 7/8/9 bits (LSB first) Stop bits: 1 bit (2-bit in continuous data transmission) Parity bits: None Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data=55H) Start bit Start of transmission Stop bit Transmit data (LSB first) End of transmission UBR Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data=55H) Stop bit Start bit Start of reception Receive data (LSB first) End of reception UBR No.A2046-24/30 LC87FBG08A Characteristics of a Sample Main System Clock Oscillation Circuit Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a Our designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator • CF oscillation normal amplifier size selected (CFLAMP=0) MURATA Nominal Frequency 12MHz Circuit Constant Operating Oscillation Voltage Stabilization Time Type Oscillator Name [pF] [pF] [Ω] [Ω] SMD CSTCE12M0G52-R0 (10) (10) Open 680 SMD CSTCE10M0G52-R0 (10) (10) Open 680 2.1 to 5.5 0.02 0.3 CSTLS10M0G53-B0 (15) (15) Open 680 2.4 to 5.5 0.02 0.3 CSTLS10M0G53095-B0 (15) (15) Open 680 2.0 to 5.5 0.01 0.15 CSTCE8M00G52-R0 (10) (10) Open 1k 2.1 to 5.5 0.02 0.3 CSTLS8M00G53-B0 (15) (15) Open 1k 2.2 to 5.5 0.02 0.3 CSTLS8M00G53095-B0 (15) (15) Open 1k 1.9 to 5.5 0.01 0.15 CSTCR6M00G53-R0 (15) (15) Open 1.5k 2.0 to 5.5 0.02 0.3 CSTCR6M00G53093-R0 (15) (15) Open 1.5k 1.8 to 5.5 0.01 0.15 10MHz C1 C2 Rf Rd Range typ max [V] [ms] [ms] 2.6 to 5.5 0.02 0.3 Remarks LEAD SMD 8MHz LEAD Internal C1, C2 SMD 6MHz CSTLS6M00G53-B0 (15) (15) Open 1.5k 2.0 to 5.5 0.02 0.3 CSTLS6M00G53095-B0 (15) (15) Open 1.5k 1.8 to 5.5 0.01 0.15 SMD CSTCR4M00G53-R0 (15) (15) Open 1.5k 1.8 to 5.5 0.03 0.45 LEAD CSTLS4M00G53-B0 (15) (15) Open 1.5k 1.8 to 5.5 0.02 0.3 LEAD 4MHz • CF oscillation low amplifier size selected (CFLAMP=1) MURATA Nominal Frequency 12MHz Circuit Constant Type Oscillator Name Operating Oscillation Voltage Stabilization Time C1 C2 Rf Rd Range typ max [pF] [pF] [Ω] [Ω] [V] [ms] [ms] 0.45 SMD CSTCE12M0G52-R0 (10) (10) Open 470 3.9 to 5.5 0.03 SMD CSTCE10M0G52-R0 (10) (10) Open 470 2.9 to 5.5 0.03 0.45 CSTLS10M0G53-B0 (15) (15) Open 470 3.6 to 5.5 0.03 0.45 CSTLS10M0G53095-B0 (15) (15) Open 470 2.7 to 5.5 0.02 0.3 CSTCE8M00G52-R0 (10) (10) Open 680 2.7 to 5.5 0.03 0.45 10MHz Remarks LEAD SMD 8MHz CSTLS8M00G53-B0 (15) (15) Open 680 3.0 to 5.5 0.03 0.45 CSTLS8M00G53095-B0 (15) (15) Open 680 2.5 to 5.5 0.01 0.15 CSTCR6M00G53-R0 (15) (15) Open 1k 2.6 to 5.5 0.03 0.45 CSTCR6M00G53095-R0 (15) (15) Open 1k 2.2 to 5.5 0.02 0.3 CSTLS6M00G53-B0 (15) (15) Open 1k 2.7 to 5.5 0.03 0.45 CSTLS6M00G53095-B0 (15) (15) Open 1k 2.2 to 5.5 0.01 0.15 CSTCR4M00G53-R0 (15) (15) Open 1k 2.1 to 5.5 0.04 0.6 CSTCR4M00G53095-R0 (15) (15) Open 1k 1.8 to 5.5 0.02 0.3 LEAD SMD Internal C1, C2 6MHz LEAD SMD 4MHz CSTLS4M00G53-B0 (15) (15) Open 1k 2.1 to 5.5 0.02 0.3 CSTLS4M00G53095-B0 (15) (15) Open 1k 1.8 to 5.5 0.01 0.15 LEAD The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized in follwing cases (see Figure 3). • The time interval that is required for the oscillation to get stabilized after the instruction for starting the mainclock oscillation circuit is executed. • The time interval that is required for the oscillation to get stabilized after the HOLD mode is reset and oscillation is started. • The time interval that is required for the oscillation to get stabilized after the X’tal Hold mode, under the state which the main clock oscillation is enabled, is reset and oscillation is started. No.A2046-25/30 LC87FBG08A Characteristics of a Sample Subsystem Clock Oscillator Circuit Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a Our designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator EPSON TOYOCOM Nominal Type Frequency 32.768kHz SMD Circuit Constant Oscillator Name MC-306 Operating Oscillation Voltage Stabilization Time C1 C2 Rf Rd Range typ max [pF] [pF] [Ω] [Ω] [V] [s] [s] 9 9 Open 330k 1.8 to 5.5 1.4 4.0 Remarks Applicable CL value = 7.0pF SEIKO INSTRUMENTS Nominal Type Frequency 32.768kHz SMD Circuit Constant Oscillator Name SSP-T7-F Operating Oscillation Voltage Stabilization Time C1 C2 Rf Rd Range typ max [pF] [pF] [Ω] [Ω] [V] [s] [s] 18 22 Open 330k 1.8 to 5.5 0.75 2.0 Remarks Applicable CL value = 12.5pF The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD goes above the operating voltage lower limit (see Figure 3). • The time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is executed. • The time interval that is required for the oscillation to get stabilized after the Hold mode, under the state which the subclock oscillation is enabled, is reset and oscillation is started. (Notes on the implementation of the oscillator circuit) • Oscillation is influenced by the circuit pattern layout of printed circuit board. Place the oscillation-related components as close to the CPU chip and to each other as possible with the shortest possible pattern length. • Keep the signal lines whose state changes suddenly or in which large current flows as far away from the oscillator circuit as possible and make sure that they do not cross one another. • Be sure to insert a current limiting resistor (Rd) so that the oscillation amplitude never exceeds the input voltage level that is specified as the absolute maximum rating. • The oscillator circuit constants shown above are sample characteristic values that are measured using the Our designated oscillation evaluation board. Since the accuracy of the oscillation frequency and other characteristics vary according to the board on which the IC is installed, it is recommended that the user consult the resonator vendor for oscillation evaluation of the IC on a user's production board when using the IC for applications that require high oscillation accuracy. For further information, contact your resonator vendor or Our company sales representative serving your locality. • It must be noted, when replacing the flash ROM version of a microcontroller with a mask ROM version, that their operating voltage ranges may differ even when the oscillation constant of the external oscillator is the same. CF2/XT2 CF1/XT1 Rf Rd C1 CF/X’tal C2 Figure 1 CF and XT Oscillator Circuit 0.5VDD Figure 2 AC Timing Measurement Point No.A2046-26/30 LC87FBG08A VDD Operating VDD lower limit 0V Power supply Reset time RES Internal medium speed RC oscillation tmsCF/tmsXtal CF1/XT1 CF2/XT2 tmsMRC Frequency variable RC oscillation Instruction for enabling oscillation executed Operating mode Unpredictable Reset Instruction execution Reset Time and Oscillation Stabilization Time HOLD reset signal HOLD reset signal absent HOLD reset signal valid HALT reset signal valid Internal medium speed RC oscillation or low speed RC oscillation tmsCF/tmsXtal CF1/XT1, CF2/XT2 (Note) tmsMRC Frequency variable RC oscillation Instruction for enabling oscillation executed State HOLD HALT Instruction execution HOLD Reset Signal and Oscillation Stabilization Time Note: External oscillation circuit is selected. Figure 3 Oscillation Stabilization Times No.A2046-27/30 LC87FBG08A VDD Note: External circuits for reset may vary depending on the usage of POR and LVD. Please refer to the user’s manual for more information. RRES RES CRES Figure 4 Reset Circuit SIOCLK: DATAIN: DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 Data RAM transfer period (SIO0 only) tSCK tSCKL tSCKH SIOCLK: tsDI thDI DATAIN: tdDO DATAOUT: Data RAM transfer period (SIO0 only) tSCKHA tSCKL SIOCLK: tsDI thDI DATAIN: tdDO DATAOUT: Figure 5 Serial I/O Output Waveforms tPIL tPIH Figure 6 Pulse Input Timing Signal Waveform No.A2046-28/30 LC87FBG08A (a) POR release voltage (PORRL) (b) VDD Reset period 100μs or longer Reset period Unknown-state (POUKS) RES Figure 7 Waveform observed when only POR is used (LVD not used) (RESET pin: Pull-up resistor RRES only) • The POR function generates a reset only when power is turned on starting at the VSS level. • No stable reset will be generated if power is turned on again when the power level does not go down to the VSS level as shown in (a). If such a case is anticipated, use the LVD function together with the POR function or implement an external reset circuit. • A reset is generated only when the power level goes down to the VSS level as shown in (b) and power is turned on again after this condition continues for 100μs or longer. LVD hysteresis width (LVHYS) LVD release voltage (LVDET+LVHYS) VDD LVD reset voltage (LVDET) Reset period Reset period Reset period Unknown-state (LVUKS) RES Figure 8 Waveform observed when both POR and LVD functions are used (RESET pin: Pull-up resistor RRES only) • Resets are generated both when power is turned on and when the power level lowers. • A hysteresis width (LVHYS) is provided to prevent the repetitions of reset release and entry cycles near the detection level. No.A2046-29/30 LC87FBG08A VDD LVD release voltage LVD reset voltage LVDET-0.5V TLVDW VSS Figure 9 Low voltage detection minimum width (Example of momentary power loss/Voltage variation waveform) ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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