Micro Linear ML5824 Ml5824 2.4ghz to 5.8ghz frequency translator Datasheet

ML5824
ML5824 2.4GHz to 5.8GHz Frequency Translator
Final Datasheet
GENERAL DESCRIPTION
FEATURES
The ML5824 is a high integration 2.4GHz - 5.8GHz
frequency translator (transverter). It upconverts 2.4GHz
signals to 5.8GHz and downconverts received 5.8GHz
signals to 2.4GHz. Transmit and receive utilize the
same low noise fixed local oscillator (LO). It is intended
to be used in conjunction with a 2.4GHz transceiverbased solution to quickly and easily develop a 5.8GHz
solution while fully leveraging previous development.
The ML5824 receive chain contains a Low Noise
Amplifier (LNA), bandpass filter and image reject down
conversion mixer. A digitally controlled 18dB gain step
in the receive chain provides an innovative solution for
optimizing IIP3 (low gain mode) and Noise Figure (high
gain mode). On the transmit side, the ML5824 buffers
and upconverts a differential 2.4GHz signal to 5.8GHz,
where it is filtered and amplified.
The ML5824’s PLL accepts two industry-standard input
clock frequencies. The ML5824’s low STANDBY MODE
current maximizes battery life. Power supply regulation
is included in the ML5824, providing circuit isolation
and consistent performance over supply voltages
between 2.8V-3.6V.
ƒ
High Integration 2.4GHz to 5.8GHz Transverter
ƒ
Receive LNA, Image Reject Filter & Mixer
ƒ
Transmit Pre-Driver, Filters & Mixers
ƒ
Fully Integrated PLL-Based Synthesizer
ƒ
Selectable Receive Gain Optimizes NF and IIP3
ƒ
Interfaces Directly with Many 2.4GHz Transceivers
ƒ
4dB (typ. High Gain Mode) Noise Figure
ƒ
-14dBm Input IP3 (Low Gain Mode)
ƒ
Selectable Transmit Output Power
ƒ
10µA Standby Mode
ƒ
Space-saving 28 pin LPCC package
APPLICATIONS
ƒ
5.8GHz Digital Cordless Telephones
ƒ
5.8GHz Streaming Audio & Video
ƒ
Upconverted 2.4GHz Standards
VTXB
TXO
VBG1
VREG4
Top View
RXI
VLNA
PIN CONFIGURATION
PIN 1
VMIX
VSSMX
o
Bluetooth
o
Zigbee/802.15.4
BLOCK DIAGRAM
TXISET
TXIN
*
RXON
TXIP
RXOP
VREG3
RFISET
QPO VTUNE
2
TXIN, TXIP
2380-2505 MHz
VBG2
VSSLO
TXON
REFSEL
VSSPLL
QPO
FREF
VREG1
XCEN
XCEN
VTUNE
TXON
VREG2
VCCA
REFSEL
RXGN
TXO
5725-5850 MHz
Control
Logic
FREF
TX Subsystem
Supply
Regulation
& Voltage
Reference
PLL
* GROUND/RETURN ON EXPOSED PADDLE
ORDERING INFORMATION
PART NUMBER TEMP RANGE
ML5824EM
PACKAGE
o
PACK (QTY)
ML5824EM-T -10 C to +70 C 28LPCC 4x5x0.9 mm Tape & Reel (2500)
DS5824-F-01
VCCA
VBG1
VBG2
VREGn
RFISET
RX Subsystem
GAIN
CONTROL
RXI
5725-5850 MHz
-10oC to +70oC 28LPCC 4x5x0.9 mm Antistatic Tray (490)
o
TXISET
2
RXGN
RXON, RXOP
2380-2505 MHz
AUGUST 2004
TABLE OF CONTENTS
GENERAL DESCRIPTION ........................................................................................................................................... 1
PIN CONFIGURATION ................................................................................................................................................. 1
ORDERING INFORMATION ........................................................................................................................................ 1
FEATURES ................................................................................................................................................................... 1
APPLICATIONS ............................................................................................................................................................ 1
BLOCK DIAGRAM ........................................................................................................................................................ 1
TABLE OF CONTENTS ................................................................................................................................................ 2
SIMPLIFIED APPLICATIONS DIAGRAM ..................................................................................................................... 2
ELECTRICAL CHARACTERISTICS............................................................................................................................. 3
PIN DESCRIPTIONS.................................................................................................................................................... 5
FUNCTIONAL DESCRIPTION ..................................................................................................................................... 9
MODES OF OPERATION............................................................................................................................................. 9
PHYSICAL DIMENSIONS .......................................................................................................................................... 11
WARRANTY................................................................................................................................................................ 12
SIMPLIFIED APPLICATIONS DIAGRAM
Figure 1: ML5824 Typical Application Schematic
DS5824-F-01
FINAL DATASHEET
AUGUST 2004
2
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional device operation is not implied. Operating the device for any
length of time beyond the operating conditions may degrade device performance and/or shorten operating lifetime.
VCCA.......................................................................................................................................................................... 3.6 V
Maximum Receive RF Input Power....................................................................................................................... +13dBm
Maximum Transmit RF Input Power........................................................................................................................ +3dBm
Junction Temperature............................................................................................................................................... 150°C
Storage Temperature Range ...................................................................................................................... -65°C to 150°C
Lead Temperature (Soldering, 10s).......................................................................................................................... 260°C
Thermal Resistance (θJA) ........................................................................................................................................ 39°C/W
OPERATING CONDITIONS
Ambient Temperature Range ....................................................................................................................... -10°C to 70°C
VCCA Range ...................................................................................................................................................2.8V to 3.6V
Unless otherwise specified, VCCA=3.2V, TA=-10°C to +70°C, XCEN=VIH, PINRX=-40dBm, PINTX=-3dBm, PLL Loop Filter
Bandwidth=40 KHz, and gain control in either state.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
2.8
3.2
3.6
V
10
µA
POWER SUPPLIES
VCCA
ISTBY
Analog supply voltage
Supply current, STANDBY mode
VCCA=3.6V, XCEN=VIL,
TXON= VIL OR VIH
IRX
ITX
Supply current, RECEIVE mode
TXON= VIL
60
mA
at -10dBm max RF input
TXON= VIL,TA=50°C
55
mA
TXON= VIL, TA=25°C
50
mA
Supply current, TRANSMIT mode
TXON= VIH RTXISET=7.5KΩ
95
110
mA
RTXISET=5.5KΩ
100
115
mA
95
105
mA
100
110
mA
TXON= VIH RTXISET=7.5KΩ, TA=50°C
RTXISET=5.5KΩ, TA=50°C
SUPPLY REGULATION
VR27
Regulated Output Voltage
Pins 12, 19, 26
2.7
V
VR25
Regulated Output Voltage
Pin 17
2.5
V
VBG
Bandgap Voltage
Pins 18 & 25
1.25
V
3343.68
MHz
SYNTHESIZER
fLO
IP
Local Oscillator Frequency
FOUT = FIN+/- FLO
Charge Pump sink/source current
This is a function of VTUNE to
compensate for the change in KV
VTUNE =1.2V
0.49
KV
FPULL
Phase noise at driver output
0.71
mA
mA
400mVp-p sine wave reference
fo=10KHz offset from fc
-65
fo=1.2MHz offset from fc
-115
-110
dBc/Hz
230
350
MHz/V
VCO Tuning sensitivity
Frequency pulling
DS5824-F-01
0.60
0.38
VTUNE =1.9V
ΦN
mA
0.90
VTUNE =0.3V
100
+/-20
70µs after PIN –50dBm to +12dBm
FINAL DATASHEET
AUGUST 2004
dBc/Hz
KHz
3
SYMBOL
FPTR
PARAMETER
CONDITIONS
Frequency pulling TX to RX
70µs after transition
MIN
TYP
MAX
UNITS
+/-20
KHz
<.5
MHz/V
and RX to TX
FPUSH
Frequency pushing
Vary VCCA from 2.9V to 3.6V
tWAKE
Lock up time from standby
XCEN=VIH, to within 10KHz,
fFREF
Reference signal frequency
VFREF
Reference signal level
200
µs
REFSEL=VIL
10.368
MHz
REFSEL=VIH
13.824
MHz
AC coupled
400
1200
mVp-p
RECEIVER
FRXI
Receiver Input Frequency Range
FRXO
Receiver Output Frequency Range
ZRIN
Receiver Input Impedance
Over FRXI
ZRXO
Receiver Output Impedance
Input noise figure
NF
GRX
RX Power Gain
High Gain Mode
High Gain Mode
High Gain Mode
Low Gain Mode
IIP3
P1dB
PRXI
PSPUR
Input IP3
GHz
2.380-2.505
GHz
37 + j2
Ω
Differential Impedance RXON/RXOP
Over FRXO
100
Ω
High Gain Mode
4.0
7.0
dB
Low Gain Mode
14
22
dB
Pin=-50dBm, TA=25°C
10.5
Pin=-50dBm, TA=50°C
9.5
Pin=-50dBm
Pin=-30dBm
Low Gain Mode
For Pin=-30dBm each tone spaced
+/1MHz from 5800MHz
RX conducted emissions from RF input
port
dB
dB
-8
For Pin=-50dBm each tone spaced
+/-1MHz from 5800MHz
RX Input 1dB compression
13
8
High Gain Mode
dBm
-25
dBm
-14
High Gain Mode
-35
dBm
Low Gain Mode
-25
dBm
RXI terminated in 50 ohm
-50
dBm
Out of Band Spurious,
Spurs outside Receive Output Frequency
Range
High Gain Mode
Low Gain Mode
IRR
5.725-5.850
RX Image Rejection
From RXI to RXO, Pin=-50dBm,
FRXI= 835-965MHz
-25
dBc
-5
dBc
20
dB
TRANSMITTER
FTXI
Transmitter Input Frequency Range
2.380-2.505
GHz
FTXO
Transmitter Output Frequency Range
5.725-5.850
GHz
ZTXI
Transmitter Input Impedance
Differential Impedance TXIN/TXIP Over
FTXI
100
Ω
ZTXO
Transmitter Output Impedance
Over FTXO
43 + j88
Ω
POUT
P50C
RTXH
TX buffer output power at 5.85 GHz
RTXISET=7.5KΩ, Pin=-6dBm
3.5
dBm
Matched into 50 ohms, -10°C<TA<70°C
RTXISET=5.5KΩ, Pin=-3dBm
5.5
dBm
TX buffer output power at 5.85 GHz
RTXISET=7.5KΩ, Pin=-6dBm
5
dBm
Matched into 50 ohms, -10°C<TA<50°C
RTXISET=5.5KΩ, Pin=-3dBm
7
dBm
Transmit harmonic output rejection
50 Ohm load
<-20
dBc
See Note 1
RLO
Transmit LO feed thru
DS5824-F-01
Measured at TXO port with CW signal at
FTXI and PTXI
FINAL DATASHEET
-30
AUGUST 2004
dBc
4
SYMBOL
RRFIF
R2LO
PARAMETER
CONDITIONS
MIN
Transmit IF feed thru
Measured at TXO port with CW signal at
FTXI and PTXI
-30
Transmit 2xLO feed thru
Measured at TXO port with CW signal at
FTXI and PTXI
<-30
dBc
Measured at TXO port with CW signal at
FTXI and PTXI
<-20
dBc
Measured at TXO port with CW signal at
FTXI and PTXI
<-20
dBc
See Note 1
R3LO
Transmit 3xLO feed thru
See Note 1
R4LO
Transmit 4xLO feed thru
See Note 1
RTSB
RMXN
Transmit lower sideband rejection
From TXI to TXO ports at PTXI for
FTXO= 835-960MHz
Mixer products rejection at output port
From TXI to TXO ports at PTXI for
FTXO= 960-970MHz
See Note 1
TYP
MAX
UNITS
dBc
25
dBc
>55
dBc
INTERFACE LOGIC LEVELS
Input pins (XCEN, TXON, RXGN, REFSEL)
VIH
Input high voltage
VCCA*0.7
VCCA+0.4
V
VIL
Input low voltage
-0.4
VCCA*0.3
V
IB
Input bias current
All states
-5
5
µA
CIN
Input capacitance
1MHz test frequency
4
pF
Note 1: Typical specs represent a 3 sigma data point at sample test.
PIN DESCRIPTIONS
PIN
NAME
I/O
FUNCTION
DIAGRAM
POWER & GROUND
2
VSSMX
7
VCCA
14
VSSPLL
15
VSSLO
24
VTXB
X
VSSDB
GROUND
Mixer Ground
N/A
Regulated External Supply, Requires Proper Decoupling Components
N/A
GROUND
PLL Ground
N/A
GROUND
VCO and LO Ground
N/A
POWER
INPUT
GROUND
TX Buffer Supply Voltage, Connect to Pin 7
N/A
Exposed Paddle. Ground/Return
N/A
2.7V Supply Decoupling Point, Connect to Pin 26
N/A
SUPPLY REGULATION
1
VMIX
INPUT
12
VREG1
OUTPUT
2.7V Regulated Supply Output
N/A
17
VREG2
OUTPUT
2.5V Regulated Supply Output
N/A
18
VBG2
OUTPUT
1.24V Bandgap2 Supply Decoupling Point
N/A
19
VREG3
OUTPUT
2.7V Regulated Supply Decoupling Point
N/A
25
VBG1
OUTPUT
1.24V Bandgap1 Supply Decoupling Point
N/A
26
VREG4
OUTPUT
2.7V Regulated Supply Output, Connect to Pins 1 and 28
N/A
28
VLNA
2.7V LNA Supply Decoupling Point, Connect to Pin 26
N/A
DS5824-F-01
INPUT
FINAL DATASHEET
AUGUST 2004
5
RF TRANSMIT/RECEIVE DATA
27
RXI
I (analog)
5.8GHz RX Input. A simple matching network is required for optimum
noise figure. This input connects to the base of an NPN transistor and
should be AC coupled.
VLNA
28
0.7V
3.9K
RXI
27
VSSDB
23
TXO
O (analog)
5.8GHz TX Output into a matched load over the 5725 to 5850 MHz
range.
VTXB
24
TXO
23
VSSDB
4
RXOP
3
RXON
O (analog)
Differential 2.4GHz RX Output.
VCCA
7
56Ω
RXOP
4
2
VSSMX
20
TXIP
21
TXIN
I (analog)
Differential 2.4GHz TX Input
VCCA
7
22Ω
TXIP
20
TXIN
21
DS5824-F-01
FINAL DATASHEET
VSSDB
AUGUST 2004
82Ω
2
X
VSSMX
VSSDB
6
RF CONTROL & OTHERS
11
XCEN
I (CMOS)
Transceiver Enable Input. Enables the bandgap reference and voltage
regulators when high. Consumes only leakage current in STANDBY
mode when low. This is a CMOS input, and the thresholds are
referenced to VCCA and VSSMX.
VCCA
7
XCEN
11
168Ω
2
VSSMX
10
TXON
I (CMOS)
TX/RX Control Input. Switches the transceiver between TRANSMIT and
RECEIVE modes. Circuits are powered up and signal paths reconfigured
according to the operating mode. This is a CMOS input, and the
thresholds are referenced to VCCA and VSSMX.
VCCA
7
TXON
10
168Ω
2
VSSMX
5
RFISET
I (analog)
Connect to a 255Ω +/-1% resistor to ground.
VCCA
7
RFISET
5
2
VSSMX
6
RXGN
I (CMOS)
Gain Step Input Control. Switches the receiver between high gain (when
HIGH) and low gain (when LOW). This dual-gain design allows the
system designer to achieve low noise figure for low input signals while
maintaining a good IIP3 under high input signal conditions. This is a
CMOS input, and the thresholds are referenced to VCCA and VSSMX.
VCCA
7
RXGN
6
168Ω
2
VSSMX
DS5824-F-01
FINAL DATASHEET
AUGUST 2004
7
13
QPO
O (analog)
Charge Pump Output. This output is connected to the external PLL loop
filter. Sources current when the LO frequency is lower than desired.
VREG1
12
QPO
13
9.2Ω
14
VSSPLL
16
VTUNE
I (analog)
VCO Tuning Voltage. This input from the PLL loop filter determines the
output frequency and is very sensitive to noise coupling and leakage
currents.
VREG3
19
VTUNE
VREG2
16
17
10Ω
15
VSSLO
22
TXISET
I (analog)
A resistor between this pin and ground establishes the PA output power
compression point by setting a bias current.
VTXB
24
VCCA
7
TXISET
22
522Ω
2
VSSMX
8
FREF
I (analog)
Input Reference Frequency. Depending on the state of the REFSEL pin
this input is divided by 3 or 4 to generate the PLL reference frequency.
VCCA
7
VREG1
12
FREF
8
2
VSSMX
14
VSSPLL
9
REFSEL
I (CMOS)
Reference Divider Control. If REFSEL is HIGH, FREF is divided by 4,
otherwise FREF is divided by 3. This is a CMOS input, and the
thresholds are referenced to VCCA and VSSMX.
VCCA
7
REFSEL
9
168Ω
2
VSSMX
DS5824-F-01
FINAL DATASHEET
AUGUST 2004
8
FUNCTIONAL DESCRIPTION
The ML5824 is a monolithic, bilateral 2.4GHz to 5.8GHz frequency translator. It provides a simple and straightforward
solution for designers of 2.4GHz products who want to develop advanced products for the relatively interference-free
5.8GHz band, especially digital cordless telephones. The ML5824 can implement “dual band” solutions that use both
the 2.4GHz and 5.8GHz bands as well as “hybrid” products where one link (say, basestation transmission) is at 5.8GHz,
while the other link (basestation receive) is at 2.4GHz.
5.8GHz signals enter the RXI pin and then are fed to an LNA and bandpass filter. An image-reject downconvert mixer
translates the signal to the 2.4GHz ISM band where it is then buffered and sent off chip differentially on RXON/RXOP.
The receive signal path can be configured for either a “High Gain” mode (about 14dB) or “Low Gain” mode (-4dB). Gain
mode is selected via the RXGN digital input pin. High Gain mode is used for low-level input signals to minimize Noise
Figure while Low Gain mode optimizes input IP3 for stronger signals.
2.4GHz signals come into the ML5824 differentially on the TXIP/TXIN pins, where they are upconverted to 5.8GHz,
bandpass filtered, and then amplified and exit via TXO. The predriver/buffer output power compression point is
programmed by an external resistor that sets the preamp bias level.
A fully integrated phase locked loop (PLL) generates the fixed local oscillator (LO) at 3343.68MHz which is used for
upconverting and downconverting the RF signals. The comparison frequency of the PLL is derived from the frequency
reference present on the FREF pin and the state of REFSEL as shown in Table 1. The PLL loop filter is external to the
ML5824 so that lock time and in-band phase noise can be optimized for the system of interest.
REFSEL
REFERENCE
DIVISION
FREF
VIL
3
10.368MHz
VIH
4
13.824MHz
Table 1: ML5824 Frequency References
The ML5824 contains two separate bandgap references and several low dropout (LDO) voltage regulators to insure
consistent performance over supply voltage and minimize crosstalk on chip. The device is enabled by bringing XCEN to
VIH and is placed in transmit mode by setting TXON to VIH. With XCEN at VIL the ML5824 enters a low power standby
mode.
MODES OF OPERATION
The ML5824 has three key modes of operation. The two operational modes are RECEIVE and TRANSMIT, controlled
by TXON. XCEN is the chip enable/disable control pin, which sets the device in operational or STANDBY modes. The
relationship between the parallel control lines and the mode of operation of the IC is summarized in Table 2.
XCEN
TXON
MODE NAME
FUNCTION
0
X
STANDBY
Standby. All circuits powered down
1
0
RECEIVE
Receive Chain Active
1
1
TRANSMIT
Transmit Chain Active
Table 2: Modes of Operation
STANDBY MODE
In STANDBY mode, the ML5824 transverter is powered down. When exiting STANDBY mode, the transmitter is
disabled for 200µs. However, the receive path is not similarly locked out and so will receive invalid data for up to 200µs.
Therefore, the system should wait 200µs after exiting STANDBY mode before actively processing signals to allow the
PLL to lock. A timing diagram for the ML5824 is shown in Figure 2.
DS5824-F-01
FINAL DATASHEET
AUGUST 2004
9
VCCA
200uS
XCEN
TXON
170uS
350uS
200uS
Data
Output
(RX & TX)
100uS
RX Valid
Data
Output
TX Valid
Data
Output
Supply and
PLL Settling
200uS
PLL Settling
100uS
100uS
TX Valid
Data
Output
Supply Settling
And TX Timer
170uS
Time to valid TX
data is 400uS
RX Valid
Data
Output
PLL Settling
100uS
Figure 2: ML5824 Control Timing Diagram, assuming a 40 KHz loop bandwidth.
RECEIVE MODE
In RECEIVE mode, the received signal at 5.8GHz is amplified, filtered, and downconverted to 2.4GHz. The receiver has
two gain modes; High Gain (about 14dB) and Low Gain (about -4dB). Gain mode is set via the state of the RXGN input,
with High Gain Mode corresponding to a logic “1” on RXGN.
TRANSMIT MODE
In TRANSMIT mode, the transmitted signal at 2.4GHz is upconverted, filtered, and amplified at 5.8GHz. The transmit
output power compression point is programmable via an external resistor on the TXISET pin.
DS5824-F-01
FINAL DATASHEET
AUGUST 2004
10
PHYSICAL DIMENSIONS
Figure 3: 28 Leadless Plastic Chip Carrier (LPCC) Dimensions
DS5824-F-01
FINAL DATASHEET
AUGUST 2004
11
WARRANTY
Micro Linear makes no representations or warranties with respect to the accuracy, utility, or completeness of the
contents of this publication and reserves the right to make changes to specifications and product descriptions at any
time without notice. No license, express or implied, by estoppel or otherwise, to any patents or other intellectual
property rights is granted by this document. The circuits contained in this document are offered as possible applications
only. Particular uses or applications may invalidate some of the specifications and/or product descriptions contained
herein. The customer is urged to perform its own engineering review before deciding on a particular application. Micro
Linear assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of
Micro Linear products including liability or warranties relating to merchantability, fitness for a particular purpose, or
infringement of any intellectual property right. Micro Linear products are not designed for use in medical, life saving, or
life sustaining applications.
If this document is “Advance”, its contents describe a Micro Linear product that is currently under development. All
detailed specifications including pinouts and electrical specifications may be changed without notice. If this document is
“Preliminary”, its contents are based on early silicon measurements. Typical data is representative of the product but is
subject to change without notice. Pinout and mechanical dimensions are final. Preliminary documents supersede all
Advance documents and all previous Preliminary versions. If this document is “Final”, its contents are based on a
characterized product, and it is believed to be accurate at the time of publication. Final Data Sheets supersede all
previously published versions. This document is Preliminary.
© 2004 Micro Linear Corporation. All rights reserved. All other trademarks are the property of their respective owners.
Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026;
5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761;
5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151;
5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999;
5,818,207; 5,818,669; 5,825,165; 5,825,223; 5,838,723; 5.844,378; 5,844,941. Japan: 2,598,946; 2,619,299;
2,704,176; 2,821,714. Other patents are pending.
Micro Linear Corporation
2050 Concourse Drive
San Jose, CA 95131
Tel: (408) 433-5200
Fax: (408) 432-1627
www.microlinear.com
DS5824-F-01
FINAL DATASHEET
AUGUST 2004
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