K1B6416B6C UtRAM Document Title 4Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory Revision History Revision No. History Draft Date Remark 0.0 Initial Draft - Design target March 11, 2004 Advance 0.1 Revised - Deleted Deep Power Down Mode support April 19, 2004 Advance 0.2 Revised - Changed product code from K1B6416B7C into K1B6416B6C May 10, 2004 Advance 0.3 Revised September 1, 2004 Preliminary - Filled out Package type(54ball FBGA 6.0mm x 8.0mm) - Changed Hi-Z parameters(tCHZ, tOHZ, tBHZ, tWZ) from Max.7ns into Max.12ns and changed tHZ from Max.10ns into Max.12ns - Updated "Fig.17 TIMING WAVEFORM OF WRITE CYCLE(1)" in page 23 - Added comment on standby current(ISB1) measure condition as "Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measured after 60ms from the time when standby mode is set up." - Added comment on restriction of the transition between Asynchronous Write operation and Fully Synchronous bus operation(Page 10,11) - Filled out ISB1 value, ISBP value and ICC2 value in Table 17(DC AND OPERATING CHARACTERISTICS) - Added Synchronous Operating Current(ICC3, Max.40mA) - Added tCSHP(A)(CS high pulse width) parameter as Min.10ns in the ASYNCHRONOUS AC CHARACTERISTICS 0.4 Revised October 12, 2004 - Changed ISB1(< 40°C) and ISBP(3/4 block, < 40°C) from 100µA into 120µA - Changed ISBP(1/2 block and 1/4 block, < 40°C) from 95µA into 115µA Preliminary 1.0 Finalized Final January 20, 2005 The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. -1- Revision 1.0 January 2005 K1B6416B6C UtRAM 4M x 16 bit Synchronous Burst Uni-Transistor CMOS RAM FEATURES GENERAL DESCRIPTION • • • • • • • The world is moving into the mobile multi-media era and therefore the mobile handsets need much bigger memory capacity to handle the multi-media data. SAMSUNG’s UtRAM products are designed to meet all the request from the various customers who want to cope with the fast growing mobile market. UtRAM is the perfect solution for the mobile market with its low cost, high density and high performance feature. K1B6416B6C is fabricated by SAMSUNG′s advanced CMOS technology using one transistor memory cell. The device supports the traditional SRAM like asynchronous bus operation(asynchronous page read and asynchronous write), the NOR flash like synchronous bus operation(synchronous burst read and asynchronous write) and the fully synchronous bus operation(synchronous burst read and synchronous burst write). These three bus operation modes are defined through the mode register setting. The device also supports the special features for the standby power saving. Those are the Partial Array Refresh(PAR) mode and internal Temperature Compensated Self Refresh(TCSR) mode. The optimization of output driver strength is possible through the mode register setting to adjust for the different data loadings. Through this driver strength optimization, the device can minimize the noise generated on the data bus during read operation. Process Technology: CMOS Organization: 4M x16 bit Power Supply Voltage: 1.7~2.0V Three State Outputs Supports MRS (Mode Register Set) MRS control - MRS Pin Control Supports Power Saving modes - Partial Array Refresh mode Internal TCSR • Supports Driver Strength Optimization for system environment power saving. • Supports Asynchronous 4-Page Read and Asynchronous Write Operation • Supports Synchronous Burst Read and Asynchronous Write Operation(Address Latch Type and Low ADV Type) • Supports Synchronous Burst Read and Synchronous Burst Write Operation • Synchronous Burst(Read/Write) Operation - Supports 4 word / 8 word / 16 word and Full Page(256 word) burst - Supports Linear Burst type & Interleave Burst type - Latency support : Latency 5 @ 66MHz(tCD 10ns) Latency 4 @ 54MHz(tCD 10ns) - Supports Burst Read Suspend in No Clock toggling - Supports Burst Write Data Masking by /UB & /LB pin control - Supports WAIT pin function for indicating data availability. • Max. Burst Clock Frequency : 66MHz • Package Type : 54 ball FBGA 6.0mm x 8.0mm Table 1. PRODUCT FAMILY Product Family Operating Temp. Vcc Range K1B6416B6C-I Industrial(-40~85°C) 1.7~2.0V Current Consumption Clock Async. Standby(Max) Standby(Max) Operating Freq.(Max) Speed(tAA) (ISB1, <40°C) (ISB1, <85°C) (ICC2, ICC3, Max.) 66MHz 70ns 120µA 180µA 40mA SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. -2- Revision 1.0 January 2005 K1B6416B6C UtRAM Table 2. PIN DESCRIPTION Fig.1 PIN DESCRIPTION 1 2 3 4 5 6 A LB OE A0 A1 A2 MRS B I/O8 UB A3 A4 CS I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D VSSQ I/O11 A17 A7 I/O3 Vcc E VCCQ I/O12 A21 A16 I/O4 Vss F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 A19 A12 A13 WE I/O7 H A18 A8 A9 A10 A11 A20 J WAIT CLK ADV NC NC NC Name Function Name Function CLK Clock Input I/O0~I/O15 Data Inputs/Outputs ADV Address Input Valid VCC/VCCQ Power Supply MRS Mode Register set Vss/VSSQ CS Chip Select OE Output Enable Input WE Write Enable Input A0~A21 Address Inputs Ground UB Upper Byte(I/O8~15) LB Lower Byte(I/O0~7) WAIT Data Availability NC Not Connected 54-FBGA: Top View(Ball Down) -3- Revision 1.0 January 2005 K1B6416B6C UtRAM CONTENTS Page Revision History Features and General Description Pin Description Power Up Sequence Functional Description Mode Register Setting Operation Mode Register Setting Timing Asynchronous Operation Asynchronous 4 Page Read Operation Asynchronous Write Operation Asynchronous Write Operation in Synchronous Mode Synchronous Burst Operation Synchronous Burst Read Operation Synchronous Burst Write Operation Synchronous Burst Operation Terminology Clock Latency Count Burst Length Burst Stop WAIT Control Burst Type Low Power Features Internal TCSR Driver Strength Optimization Partial Array Refresh(PAR) Mode Product List Absolute Maximum Ratings Recommended DC Operating Conditions Capacitance DC and Operating Characteristics Asynchronous AC Characteristics Asynchronous Timing Waveforms Synchronous AC Characteristics Synchronous Timing Waveforms Transition Timing Waveforms Package Dimension 1 2 3 8 9 11 12 13 13 13 13 13 13 13 14 14 14 14 14 15 15 17 17 17 17 18 18 18 19 18 20 21 30 31 40 46 -4- Revision 1.0 January 2005 K1B6416B6C UtRAM LIST of TABLES Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Page Product Family Pin Description Asynchronous 4 Page Read & Asynchronous Write Mode Truth Table Synchronous Burst Read & Asynchronous Write Mode Truth Table Synchronous Burst Read & Synchronous Burst Write Mode Truth Table Mode Register Setting according to Field of Function Mode Register Set MRS AC Characteristics Latency Count Support Number of Clocks for 1st Data Burst Sequence PAR Mode Characteristics Product List Absolute Maximum Ratings Recommended DC Operating Conditions Capacitance DC and Operating Characteristics Asynchronous AC Characteristics Asynchronous Read AC Characteristics Asynchronous Page Read AC Characteristics Asynchronous Write AC Characteristics(WE Controlled) Asynchronous Write AC Characteristics(UB & LB Controlled) Asynch. Write in Synch. Mode AC Characteristics(Address Latch Type, WE Controlled) Asynch. Write in Synch. Mode AC Characteristics(Address Latch Type, UB & LB Controlled) Asynch. Write in Synch. Mode AC Characteristics(Low ADV Type, WE Controlled) Asynch. Write in Synch. Mode AC Characteristics(Low ADV Type, UB & LB Controlled) Asynch. Write in Synch. Mode AC Characteristics(Low ADV Type Multiple Write, WE Controlled) Synchronous AC Characteristics Burst Operation AC Characteristics Burst Read AC Characteristics(CS Toggling Consecutive Burst) Burst Read AC Characteristics(CS Low Holding Consecutive Burst) Burst Read AC Characteristics(Last Data Sustaining) Burst Write AC Characteristics(CS Toggling Consecutive Burst) Burst Write AC Characteristics(CS Low Holding Consecutive Burst) Burst Read Stop AC Characteristics Burst Write Stop AC Characteristics Burst Read Suspend AC Characteristics Burst Read to Asynch. Write(Address Latch Type) AC Characteristics Burst Read to Asynch. Write(Low ADV Type) AC Characteristics Asynch. Write(Address Latch Type) to Burst Read AC Characteristics Asynch. Write(Low ADV Type) to Burst Read AC Characteristics Burst Read to Burst Write AC Characteristics Burst Write to Burst Read AC Characteristics -5- 2 3 9 9 10 11 11 12 14 14 16 17 18 18 18 19 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 Revision 1.0 January 2005 K1B6416B6C UtRAM LIST of FIGURES Page Figure 1. Pin Description Figure 2. Functional Block Diagram Figure 3. Power Up Timing Figure 4. Standby Mode State Machine Figure 5. Mode Register Setting Timing Figure 6. Asynchronous 4-Page Read Figure 7. Asynchronous Write Figure 8. Synchronous Burst Read Figure 9. Synchronous Burst Write Figure 10. Latency Configuration(Read) Figure 11. WAIT Control and Read/Write Latency Control Figure 13. PAR Mode Execution and Exit Figure 14. AC Output Load Circuit(Asynchronous) Figure 15. Timing Waveform of Asynchronous Read Cycle Figure 16. Timing Waveform of Page Read Cycle Figure 17. Timing Waveform of Write Cycle(Asynchronous, WE Controlled) Figure 18. Timing Waveform of Write Cycle(Asynchronous, UB & LB Controlled) Figure 19. Timing Waveform of Write Cycle(Asynchronous, Address Latch Type, WE Controlled) Figure 20. Timing Waveform of Write Cycle(Asynchronous, Address Latch Type, UB & LB Controlled) Figure 21. Timing Waveform of Write Cycle(Asynchronous, Low ADV Type, WE Controlled) Figure 22. Timing Waveform of Write Cycle(Asynchronous, Low ADV Type, UB & LB Controlled) Figure 23. Timing Waveform of Multiple Write Cycle(Asynchronous, Low ADV Type, WE Controlled ) Figure 24. AC Output Load Circuit(Synchronous) Figure 25. Timing Waveform of Basic Burst Operation Figure 26. Timing Waveform of Burst Read Cycle(CS Toggling Consecutive Burst Read) Figure 27. Timing Waveform of Burst Read Cycle(CS Low Holding Consecutive Burst Read) Figure 28. Timing Waveform of Burst Read Cycle(Last Data Sustaining) Figure 29. Timing Waveform of Burst Write Cycle(CS Toggling Consecutive Burst Write) Figure 30. Timing Waveform of Burst Write Cycle(CS Low Holding Consecutive Burst Write) Figure 31. Timing Waveform of Burst Read Stop by CS Figure 32. Timing Waveform of Burst Write Stop by CS Figure 33. Timing Waveform of Burst Read Suspend Cycle Figure 34. Synch. Burst Read to Asynch. Write(Address Latch Type) Timing Waveform Figure 35. Synch. Burst Read to Asynch. Write(Low ADV Type) Timing Waveform Figure 36. Asynch. Write(Address Latch Type) to Synch. Burst Read Timing Waveform Figure 37. Asynch. Write(Low ADV Type) to Synch. Burst Read Timing Waveform Figure 38. Synch. Burst Read to Synch. Burst Write Timing Waveform Figure 39. Synch. Burst Write to Synch. Burst Read Timing Waveform -6- 3 7 8 8 12 13 13 13 13 14 15 17 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 Revision 1.0 January 2005 K1B6416B6C UtRAM Fig.2 FUNCTIONAL BLOCK DIAGRAM CLK generator Precharge circuit. Vcc Vss Row Addresses I/O0~I/O7 Row select Memory array Data controller I/O Circuit Column select Data controller I/O8~I/O15 Data controller Column Addresses CLK ADV MRS CS OE Control Logic WE UB LB WAIT -7- Revision 1.0 January 2005 K1B6416B6C UtRAM POWER UP SEQUENCE After applying VCC upto minimum operating voltage(1.7V), drive CS High first and then drive MRS High. Then the device gets into the Power Up mode. Wait for minimum 200µs to get into the normal operation mode. During the Power Up mode, the standby current can not be guaranteed. To get the stable standby current level, at least one cycle of active operation should be implemented regardless of wait time duration. To get the appropriate device operation, be sure to keep the following power up sequence. 1. Apply power. 2. Maintain stable power(Vcc min.=1.7V) for a minimum 200µs with CS and MRS high. Fig.3 POWER UP TIMING 200µs ~ VCC(Min) VCC ≈ Min. 0ns MRS Min. 200µs Min. 0ns ≈ CS Power Up Mode Normal Operation (Note) 1. After VCC reaches VCC(Min.), wait 200µs with CS and MRS high. Then the device gets into the normal operation. Fig.4 STANDBY MODE STATE MACHINES CS=VIH MRS=VIH Power On Initial State (Wait 200µs) CS=UB=LB=VIL, WE=VIL, MRS=VIL MRS Setting CS=VIL, UB or LB=VIL MRS=VIH Active CS=VIH Standby Mode MRS=VIH MRS=VIL PAR Mode MRS Setting CS=VIL, WE=VIL, MRS=VIL Default mode after power up is Asynchronous mode(4 Page Read and Asynchronous Write). But this default mode is not 100% guaranteed so MRS setting sequence is highly recommended after power up. For entry to PAR mode, drive MRS pin into VIL for over 0.5µs(suspend period) during standby mode after MRS setting has been completed(A4=1, A3=0). If MRS pin is driven into VIH during PAR mode, the device gets back to the standby mode without wake up sequence. -8- Revision 1.0 January 2005 K1B6416B6C UtRAM FUNCTIONAL DESCRIPTION Table 3. ASYNCHRONOUS 4 PAGE READ & ASYNCHRONOUS WRITE MODE(A15/A14=0/0) CS MRS OE WE H H X H L X1) X1) L H H H X L H X1) X1) H H 1) X 1) LB UB I/O0~7 I/O8~15 Mode Power 1) 1) High-Z High-Z Deselected Standby X1) X1) High-Z High-Z Deselected PAR 1) 1) X X X High-Z High-Z Output Disabled Active High-Z High-Z Output Disabled Active L H L H L H Dout High-Z Lower Byte Read Active L H L H H L High-Z Dout Upper Byte Read Active L H L H L L Dout Dout Word Read Active L H H L L H Din High-Z Lower Byte Write Active L H H L H L High-Z Din Upper Byte Write Active L H H L L L Din Din Word Write Active L L H L L L High-Z High-Z Mode Register Set Active 1. X must be low or high state. 2. In asynchronous mode, Clock and ADV are ignored. 3. /WAIT pin is High-Z in Asynchronous mode. Table 4. SYNCHRONOUS BURST READ & ASYNCHRONOUS WRITE MODE(A15/A14=0/1) CS MRS OE WE LB UB I/O0~7 I/O8~15 CLK ADV Mode Power H H X1) X1) X1) X1) High-Z High-Z X2) X2) Deselected Standby H L X1) X1) X1) X1) High-Z High-Z X2) X2) Deselected PAR L H H H X1) X1) High-Z High-Z X2) H Output Disabled Active L H X1) X1) H H High-Z High-Z X2) H L H X1) H X1) X1) High-Z High-Z L H L H L H Dout High-Z H Lower Byte Read Active L H L H H L High-Z Dout H Upper Byte Read Active L H L H L L Dout Dout H Word Read Active L H H L L H Din L H H L H L High-Z L H H L L L L L H L L L Output Disabled Active Read Command Active High-Z X 2) or Lower Byte Write Active Din X2) or Upper Byte Write Active Din Din X 2) or Word Write Active High-Z High-Z X2) or Mode Register Set Active 1. X must be low or high state. 2. X means "Don’t care"(can be low, high or toggling). 3. /WAIT is device output signal so does not have any affect to the mode definition. Please refer to each timing diagram for /WAIT pin function. -9- Revision 1.0 January 2005 K1B6416B6C UtRAM Table 5. SYNCHRONOUS BURST READ & SYNCHRONOUS BURST WRITE MODE(A15/A14=1/0) CS MRS OE H H X H L X1) X1) 1) WE X 1) LB UB I/O0~7 I/O8~15 1) 1) High-Z High-Z X1) X1) High-Z High-Z 1) 1) X L H H H X L H X1) X1) H L H X 1) L H L L H L H L H X X X H CLK Mode Power X X 2) Deselected Standby X2) X2) Deselected PAR 2) 2) ADV High-Z High-Z X H Output Disabled Active High-Z High-Z X2) H Output Disabled Active H X High-Z High-Z Read Command Active H L H Dout High-Z H Lower Byte Read Active L H H L High-Z Dout H Upper Byte Read Active L H L L Dout Dout H Word Read Active High-Z High-Z Write Command Active 1) L or X 1) 1) X X 1) 1) L H H X L H H X1) L H H X1) L L Din Din L L H L or L L High-Z High-Z 1) L H Din High-Z H Lower Byte Write Active H L High-Z Din H Upper Byte Write Active H Word Write Active Mode Register Set Active 1. X must be low or high state. 2. X means "Don’t care"(can be low, high or toggling). 3. /WAIT is device output signal so does not have any affect to the mode definition. Please refer to each timing diagram for /WAIT pin function. 4. The last data written in the previous Asynchronous write mode is not valid. To make the lastly written data valid, then implement at least one dummy write cycle before change mode into synchronous burst read and synchronous burst write mode. 5. The data written in Synchronous burst write operation can be corrupted by the next Asynchronous write operation. So the transition from Synchronous burst write operation to Asynchronous write operation is prohibited. - 10 - Revision 1.0 January 2005 K1B6416B6C UtRAM MODE REGISTER SETTING OPERATION The device has several modes : Asynchronous Page Read mode, Asynchronous Write mode, Synchronous Burst Read mode, Synchronous Burst Write mode, Standby mode and Partial Array Refresh(PAR) mode. Partial Array Refresh(PAR) mode is defined through Mode Register Set(MRS) option. Mode Register Set(MRS) option also defines Burst Length, Burst Type, Wait Polarity and Latency Count at Synchronous Burst Read/Write mode. Mode Register Set (MRS) The mode register stores the data for controlling the various operation modes of UtRAM. It programs Partial Array Refresh(PAR), Burst Length, Burst Type, Latency Count and various vendor specific options to make UtRAM useful for a variety of different applications. The default values of mode register are defined, therefore when the reserved address is input, the device runs at default modes. The mode register is written by driving CS, ADV, WE, UB, LB and MRS to VIL and driving OE to VIH during valid address. The mode register is divided into various fields depending on the fields of functions. The Partial Array Refresh(PAR) field uses A0~A4, Burst Length field uses A5~A7, Burst Type uses A8, Latency Count uses A9~A11, Wait Polarity uses A13, Operation Mode uses A14~A15 and Driver Strength uses A16~A17. Refer to the Table below for detailed Mode Register Setting. A18~A21 addresses are "Don’t care" in Mode Register Setting. Table 6. Mode Register Setting according to field of function Address A17~A16 A15~A14 A13 A12 A11~A9 A8 A7~A5 A4~A3 A2 A1~A0 Function DS MS WP RFU Latency BT BL PAR PARA PARS NOTE : DS(Driver Strength), MS(Mode Select), WP(Wait Polarity), Latency(Latency Count), BT(Burst Type), BL(Burst Length), PAR(Partial Array Refresh), PARA(Partial Array Refresh Array), PARS(Partial Array Refresh Size), RFU(Reserved for Future Use) Table 7. Mode Register Set Driver Strength Mode Select A17 A16 DS A15 0 0 Full Drive 0 1 1/2 Drive 1 0 1/4 Drive 1 WAIT Polarity A14 MS* 0 0 Async. 4 Page Read / Async. Write 0 1 Sync. Burst Read / Async. Write 0 Sync. Burst Read / Sync. Burst Write RFU Latency Count Burst Type Burst Length A13 WP A12 RFU A11 A10 A9 Latency A8 BT A7 A6 A5 BL 0 Low Enable 0 Must 0 0 0 3 0 Linear 0 1 0 4 word 1 High Enable 1 - 1 Interleave Partial Array Refresh 0 0 1 4 0 1 1 8 word 0 1 0 5 1 0 0 16 word 0 1 1 6 1 1 1 Full(256 word) PAR Array PAR Size A4 A3 PAR A2 PARA A1 A0 PARS 1 0 PAR Enable 0 Bottom Array 0 0 Full Array 1 1 PAR Disable 1 Top Array 0 1 3/4 Array 1 0 1/2 Array 1 1 1/4 Array NOTE : The address bits other than those listed in the table above are reserved. For example, Burst Length address bits(A7:A6:A5) have 4 sets of reserved bits like 0:0:0, 0:0:1, 1:0:1 and 1:1:0. If the reserved address bits are input, then the mode will be set into the default mode. Each field has its own default mode and these default modes are written in blue-bold in the table above. But this default mode is not 100% guaranteed so MRS setting sequence is highly recommended after power up. A12 is a reserved bit for future use. A12 must be set as "0". Not all the mode settings are tested. Per the mode settings to be tested, please contact Samsung Product Planning team. 256 word Full page burst mode needs to meet tBC(Burst Cycle time) parameter as max. 2500ns. * The last data written in the previous Asynchronous write mode is not valid. To make the lastly written data valid, then implement at least one dummy write cycle before change mode into synchronous burst read and synchronous burst write mode. * The data written in Synchronous burst write operation can be corrupted by the next Asynchronous write operation. So the transition from Synchronous burst write operation to Asynchronous write operation is prohibited. - 11 - Revision 1.0 January 2005 K1B6416B6C UtRAM MRS pin Control Type Mode Register Setting Timing In this device(K1B6416B6C), MRS pin is used for two purposes. One is to get into the mode register setting and the other one is to execute Partial Array Refresh mode. To get into the Mode Register Setting, the system must drive MRS pin to VIL and immediately(within 0.5µs) issue a write command(drive CS, ADV, UB, LB and WE to VIL and drive OE to VIH during valid address). If the subsequent write command(WE signal input) is not issued within 0.5µs, then the device might get into the PAR mode. Fig.5 MODE REGISTER SETTING TIMING(OE=VIH) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 CLK ADV tWC Address tCW CS tAW tBW UB, LB tWP WE tAS tWU tMW MRS Register Update Complete Register Write Complete Register Write Start (MRS SETTING TIMING) 1. Clock input is ignored. Table 8. MRS AC CHARACTERISTICS (VCC=1.7~2.0V, TA=-40 to 85°C, Maximum Main Clock Frequency=66MHz) Parameter List MRS Speed Symbol Units Min Max MRS Enable to Register Write Start tMW 0 500 ns End of Write to MRS Disable tWU 0 - ns - 12 - Revision 1.0 January 2005 K1B6416B6C UtRAM ASYNCHRONOUS OPERATION SYNCHRONOUS BURST OPERATION Asynchronous 4 Page Read Operation Asynchronous normal read operation starts when CS, OE and UB or LB are driven to VIL under the valid address without toggling page addresses(A0, A1). If the page addresses(A0, A1) are toggled under the other valid address, the first data will be out with the normal read cycle time(tRC) and the second, the third and the fourth data will be out with the page cycle time(tPC). (MRS and WE should be driven to VIH during the asynchronous (page) read operation) Clock, ADV, WAIT signals are ignored during the asynchronous (page) read operation. Burst mode operations enable the system to get high performance read and write operation. The address to be accessed is latched on the rising edge of clock or ADV(whichever occurs first). CS should be setup before the address latch. During this first clock rising edge, WE indicates whether the operation is going to be a Read(WE High) or a Write(WE Low). For the optimized Burst Mode to each system, the system should determine how many clock cycles are required for the first data of each burst access(Latency Count), how many words the device outputs at an access(Burst Length) and which type of burst operation(Burst Type : Linear or Interleave) is needed. The Wait Polarity should also be determined.(See Table "Mode Register Set") Asynchronous Write Operation Synchronous Burst Read Operation Asynchronous write operation starts when CS, WE and UB or LB are driven to VIL under the valid address.(MRS and OE should be driven to VIH during the asynchronous write operation.) Clock, ADV, WAIT signals are ignored during the asynchronous (page) read operation. The Synchronous Burst Read command is implemented when the clock rising is detected during the ADV low pulse. ADV and CS should be set up before the clock rising. During Read command, WE should be held in VIH. The multiple clock risings(during low ADV period) are allowed but the burst operation starts from the first clock rising. The first data will be out with Latency count and tCD. Asynchronous Write Operation in Synchronous Mode A write operation starts when CS, WE and UB or LB are driven to VIL under the valid address. Clock input does not have any affect to the write operation(MRS and OE should be driven to VIH during write operation. ADV can be either toggling for address latch or held in VIL). Clock, ADV, WAIT signals are ignored during the asynchronous (page) read operation. Fig.6 ASYNCHRONOUS 4-PAGE READ Synchronous Burst Write Operation The Synchronous Burst Write command is implemented when the clock rising is detected during the ADV and WE low pulse. ADV, WE and CS should be set up before the clock rising. The multiple clock risings(during low ADV period) are allowed but the burst operation starts from the first clock rising. The first data will be written in the Latency clock with tDS. Fig.8 SYNCHRONOUS BURST READ(Latency 5, BL 4, WP : Low Enable) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CLK A21~A2 ADV A1~A0 Addr. CS CS UB, LB UB, LB OE OE Data out Data out WAIT Fig.9 SYNCHRONOUS BURST WRITE(Latency 5, BL 4, WP : Low Enable) Fig.7 ASYNCHRONOUS WRITE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 CLK Address ADV CS Addr. UB, LB CS UB, LB WE WE Data in High-Z Data out High-Z Data in High-Z WAIT - 13 - Revision 1.0 January 2005 K1B6416B6C UtRAM SYNCHRONOUS BURST OPERATION TERMINOLOGY Clock(CLK) The clock input is used as the reference for synchronous burst read and write operation of UtRAM. The synchronous burst read and write operation is synchronized to the rising edge of the clock. The clock transitions must swing between VIL and VIH. Latency Count The Latency Count configuration tells the device how many clocks must elapse from the burst command before the first data should be available on its data pins. This value depends on the input clock frequency. The supported Latency Count is as follows. Table 9. Latency Count support : 3, 4, 5 Clock Frequency Upto 66MHz Upto 54MHz Upto 40MHz Latency Count 5 4 3 Set Latency Latency 3 Latency 4 Latency 5 # of Clocks for 1st data(Read) 4 5 6 # of Clocks for 1st data(Write) 2 3 4 Table 10. Number of Clocks for 1st Data Fig.10 Latency Configuration(Read) T Clock ADV Address Latency 3 DQ1 Data out DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 Latency 4 Data out Latency 5 Data out Latency 6 Data out NOTE : The first data will always keep the Latency. From the second data, some period of wait time might be caused by WAIT pin. Burst Length Burst Length identifies how many data the device outputs at an access. The device supports 4 word, 8 word, 16 word and 256 word burst read or write. 256 word Full page burst mode needs to meet tBC(Burst Cycle time) parameter as max. 2500ns. The first data will be out with the set Latency + tCD. From the second data, the data will be out with tCD from each clock. Burst Stop Burst stop is used when the system wants to stop burst operation on special purpose. If driving CS to VIH during the burst read operation, then the burst operation will be stopped. During the burst read operation, the new burst operation can not be issued. The new burst operation can be issued only after the previous burst operation is finished. The burst stop feature is very useful because it enables the user to utilize the un-supported burst length such as 1 burst or 2 burst which accounts for big portion in usage for the mobile handset application environment. - 14 - Revision 1.0 January 2005 K1B6416B6C UtRAM SYNCHRONOUS BURST OPERATION TERMINOLOGY WAIT Control(WAIT) The WAIT signal is the device’s output signal which indicates to the host system when the device’s data-out or data-in is valid. To be compatible with the Flash interfaces of various microprocessor types, the WAIT polarity(WP) can be configured. The polarity can be programmed to be either low enable or high enable. For the timing of WAIT signal, the WAIT signal should be set active one clock prior to the data regardless of Read or Write cycle. Fig.11 WAIT Control and Read/Write Latency Control(LATENCY : 5, Burst Length : 4, WP : Low Enable) 0 1 2 3 4 5 6 7 8 9 DQ0 DQ1 DQ2 DQ3 D2 D3 10 11 12 13 CLK ADV Latency 5 CS Read Data out WAIT High-Z Latency 5 Write Data in WAIT D0 D1 High-Z Burst Type The device supports Linear type burst sequence and Interleave type burst sequence. Linear type burst sequentially increments the burst address from the starting address. The detailed Linear and Interleave type burst address sequence is shown in burst sequence table in next page. - 15 - Revision 1.0 January 2005 K1B6416B6C UtRAM Table 11. Burst Sequence Burst Address Sequence(Decimal) Start Addr. Wrap1) 4 word Burst 8 word Burst 16 word Burst Full Page(256 word) Linear Interleave Linear Interleave Linear Interleave Linear 0 0-1-2-3 0-1-2-3 0-1-...-5-6-7 0-1-2-...-6-7 0-1-2-...-14-15 0-1-2-3-4...14-15 0-1-2-...-254-255 1 1-2-3-0 1-0-3-2 1-2-...-6-7-0 1-0-3-...-7-6 1-2-3-...-15-0 1-0-3-2-5...15-14 1-2-3-...-255-0 2 2-3-0-1 2-3-0-1 2-3-...-7-0-1 2-3-0-...-4-5 2-3-4-...-0-1 2-3-0-1-6...12-13 2-3-4-...-255-0-1 3 3-0-1-2 3-2-1-0 3-4-...-0-1-2 3-2-1-...-5-4 3-4-5-...-1-2 3-2-1-0-7...13-12 3-4-5-...-255-0-1-2 4 4-5-...-1-2-3 4-5-6-...-2-3 4-5-6-...-2-3 4-5-6-7-0...10-11 4-5-6-...-255-0-1-2-3 5 5-6-...-2-3-4 5-4-7-...-3-2 5-6-7-...-3-4 5-4-7-6-1...11-10 5-6-7-...-255-...-3-4 6 6-7-...-3-4-5 6-7-4-...-0-1 6-7-8-...-4-5 6-7-4-5-2...8-9 6-7-8-...-255-...-4-5 7 7-0-...-4-5-6 7-6-5-...-1-0 7-8-9-...-5-6 7-6-5-4-3...9-8 7-8-9-...-255-...-5-6 ~ ~ ~ ~ 14 14-15-0-...-12-13 14-15-12-...-0-1 14-15-...-255-...-12-13 15 15-0-1-...-13-14 15-14-13-...-1-0 15-16-...-255-...-13-14 ~ ~ 255 255-0-1-...-253-254 1. Wrap : Burst Address wraps within word boundary and ends after fulfilled the burst length. 2. 256 word Full page burst mode needs to meet tBC(Burst Cycle time) parameter as max. 2500ns. - 16 - Revision 1.0 January 2005 K1B6416B6C UtRAM LOW POWER FEATURES Partial Array Refresh(PAR) mode Driver Strength Optimization The PAR mode enables the user to specify the active memory array size. UtRAM consists of 4 blocks and user can select 1 block, 2 blocks, 3 blocks or all blocks as active memory array through Mode Register Setting. The active memory array is periodically refreshed whereas the disabled array is not going to be refreshed and so the previously stored data will get lost. Even though PAR mode is enabled through the Mode Register Setting, PAR mode execution by MRS pin is still needed. The normal operation can be executed even in refresh-disabled array as long as MRS pin is not driven to low for over 0.5µs. Driving MRS pin to high makes the device to get back to the normal operation mode from PAR executed mode, Refer to Fig.13 and Table 12 for PAR operation and PAR address mapping. The optimization of output driver strength is possible through the mode register setting to adjust for the different data loadings. Through this driver strength optimization, the device can minimize the noise generated on the data bus during read operation. The device supports full drive, 1/2 drive and 1/4 drive. Fig.13 PAR MODE EXECUTION and EXIT 0.5µs MRS ≈ Normal Operation Suspend The internal Temperature Compensated Self Refresh(TCSR) feature is a very useful tool for reducing standby current in room temperature(below 40°C). DRAM cell has weak refresh characteristics in higher temperature. So high temperature requires more refresh cycles, which lead to standby current increase. Without internal TCSR, the refresh cycle should be set as worst condition so as to cover high temperature(85°C) refresh characteristics. But with internal TCSR, the refresh cycle below 40°C can be optimized, so the standby current in room temperature can be highly reduced. This feature is really beneficial to mobile phone because most of mobile phones are used at below 40°C in the phone standby mode. Normal Operation ≈ MODE PAR mode Internal TCSR CS Table 12. PAR MODE CHARACTERISTIC Power Mode Address (Bottom Array)2) Address (Top Array)2) Standby(Full Array) 000000h ~ 3FFFFFh 000000h ~ 3FFFFFh Valid1) 120µA 180µA 0 Partial Refresh(3/4 Block) 000000h ~ 2FFFFFh 100000h ~ 3FFFFFh Valid1) 120µA 180µA 0 Partial Refresh(1/2 Block) 000000h ~ 1FFFFFh 200000h ~ 3FFFFFh Valid1) 115µA 165µA 0 Partial Refresh(1/4 Block) 000000h ~ 0FFFFFh 300000h ~ 3FFFFFh 1) 115µA 165µA 0 Memory Standby3) Standby3) Cell Data (ISB1, <40°C) (ISB1, <85°C) Valid Wait Time(µs) 1. Only the data in the refreshed block are valid 2. PAR Array can be selected through Mode Register Set(See Page 11) 3. Standby mode is supposed to be set up after at least one active operation.after power up. ISB1 is measured after 60ms from the time when standby mode is set up. - 17 - Revision 1.0 January 2005 K1B6416B6C UtRAM Table 13. PRODUCT LIST Industrial Temperature Products(-40~85°C) Part Name Function K1B6416B6C 1.8V, 70ns, 66MHz Table 14. ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Symbol Ratings Unit VIN, VOUT -0.2 to VCC+0.3V V VCC -0.2 to 2.5V V Power supply voltage relative to Vss PD 1.0 W TSTG -65 to 150 °C TA -40 to 85 °C Power Dissipation Storage temperature Operating Temperature 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reliability. Table 15. RECOMMENDED DC OPERATING CONDITIONS1) Symbol Min Typ Max Unit Power supply voltage Item VCC 1.7 1.85 2.0 V Ground Vss 0 0 0 V Input high voltage VIH 0.8 x VCC - VCC+0.22) V Input low voltage VIL - 0.4 V -0.2 3) 1. TA=-40 to 85°C, otherwise specified. 2. Overshoot: VCC+1.0V in case of pulse width ≤20ns. 3. Undershoot: -1.0V in case of pulse width ≤20ns. 4. Overshoot and undershoot are sampled, not 100% tested. - 18 - Revision 1.0 January 2005 K1B6416B6C UtRAM Table 16. CAPACITANCE1)(f=1MHz, TA=25°C) Item Symbol Test Condition Min Max Unit Input capacitance CIN VIN=0V - 8 pF Input/Output capacitance CIO VIO=0V - 10 pF 1. Capacitance is sampled, not 100% tested. Table 17. DC AND OPERATING CHARACTERISTICS Min Typ Max Unit Input Leakage Current Item ILI VIN=Vss to VCCQ Test Conditions -1 - 1 µA Output Leakage Current Symbol ILO CS=VIH, MRS=VIH, OE=VIH or WE=VIL, VIO=Vss to VCCQ -1 - 1 µA Average Operating Current(Async) ICC2 Cycle time=tRC+3tPC, IIO=0mA, 100% duty, CS=VIL, MRS=VIH, VIN=VIL or VIH - - 40 mA Average Operating Current(Sync) ICC3 Burst Length 4, Latency 5, 66MHz, IIO=0mA, Address transition 1 time, CS=VIL, MRS=VIH, VIN=VIL or VIH - - 40 mA Output Low Voltage VOL IOL=0.1mA - - 0.2 V Output High Voltage VOH IOH=-0.1mA ISB12) CS≥VCCQ-0.2V, MRS≥VCCQ-0.2V, Other inputs=Vss to VCCQ Standby Current(CMOS) 1.4 - - V < 40°C - - 120 µA < 85°C µA < 40°C Partial Refresh Current ISBP1) MRS≤0.2V, CS≥VCCQ-0.2V Other inputs=Vss to VCCQ < 85°C - - 180 3/4 Block - - 120 1/2 Block - - 115 1/4 Block - - 115 3/4 Block - - 180 1/2 Block - - 165 1/4 Block - - 165 µA µA 1. Full Array Partial Refresh Current(ISBP) is same as Standby Current(ISB1). 2. Standby mode is supposed to be set up after at least one active operation.after power up. ISB1 is measured after 60ms from the time when standby mode is set up. - 19 - Revision 1.0 January 2005 K1B6416B6C UtRAM Figure 14. AC Output Load Circuit AC OPERATING CONDITIONS Vtt=0.5 x VCC TEST CONDITIONS(Test Load and Test Input/Output Reference) 50Ω Input pulse level: 0.2 to VCC-0.2V Input rising and falling time: 3ns Input and output reference voltage: 0.5 x VCC Output load: CL=30pF Dout Z0=50Ω 30pF Table 18. ASYNCHRONOUS AC CHARACTERISTICS (VCC=1.7~2.0V, TA=-40 to 85°C) Parameter List Common Async. (Page) Read CS High Pulse Width Units Min Max tCSHP(A) 10 - ns Read Cycle Time tRC 70 - ns Page Read Cycle Time tPC 25 - ns Address Access Time tAA - 70 ns Page Access Time tPA - 20 ns Chip Select to Output tCO - 70 ns Output Enable to Valid Output tOE - 35 ns UB, LB Access Time tBA - 35 ns Chip Select to Low-Z Output tLZ 10 - ns UB, LB Enable to Low-Z Output tBLZ 5 - ns Output Enable to Low-Z Output tOLZ 5 - ns Chip Disable to High-Z Output tCHZ 0 12 ns UB, LB Disable to High-Z Output tBHZ 0 12 ns Output Disable to High-Z Output tOHZ 0 12 ns Output Hold tOH 3 - ns Write Cycle Time tWC 70 - ns Chip Select to End of Write tCW 60 - ns ADV Minimum Low Pulse Width tADV 7 - ns Address Set-up Time to Beginning of Write tAS 0 - ns tAS(A) 0 - ns Address Set-up Time to ADV Falling Async. Write Speed Symbol Address Hold Time from ADV Rising tAH(A) 7 - ns CS Setup Time to ADV Rising tCSS(A) 10 - ns Address Valid to End of Write tAW 60 - ns UB, LB Valid to End of Write tBW 60 - ns Write Pulse Width tWP 551) - ns WE High Pulse Width tWHP 5 ns Latency-1 clock - tWR 0 - ns tWLRL 1 - clock Data to Write Time Overlap tDW 30 - ns Data Hold from Write Time tDH 0 - ns Write Recovery Time WE Low to Read Latency 1. tWP(min)=70ns for continuous write operation over 50 times. - 20 - Revision 1.0 January 2005 K1B6416B6C UtRAM ASYNCHRONOUS READ TIMING WAVEFORM Fig.15 TIMING WAVEFORM OF ASYNCHRONOUS READ CYCLE (MRS=VIH, WE=VIH, WAIT=High-Z) tRC Address tAA tCSHP(A) tOH tCO CS tCHZ tBA UB, LB tBHZ tOE OE tOLZ tBLZ High-Z Data out tOHZ tLZ Data Valid (ASYNCHRONOUS READ CYCLE) 1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tCHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 3. In asynchronous read cycle, Clock, ADV and WAIT signals are ignored. Table 19. ASYNCHRONOUS READ AC CHARACTERISTICS Speed Symbol Min Units Speed Symbol Max Units Min Max tRC 70 - ns tOLZ 5 - ns tAA - 70 ns tBLZ 5 - ns tCO - 70 ns tLZ 10 - ns tBA - 35 ns tCHZ 0 12 ns tOE - 35 ns tBHZ 0 12 ns tOHZ 0 12 ns tOH 3 - ns tCSHP(A) 10 - ns - 21 - Revision 1.0 January 2005 K1B6416B6C UtRAM ASYNCHRONOUS READ TIMING WAVEFORM Fig.16 TIMING WAVEFORM OF PAGE READ CYCLE(MRS=VIH, WE=VIH, WAIT=High-Z) tRC Valid Address A21~A2 tOH tAA Valid Address Valid Address A1~A0 Valid Address Valid Address tPC tCO CS tBA UB, LB tBHZ tOE OE tLZ High Z Data out tOLZ tBLZ tCHZ tOHZ tPA Data Valid Data Valid Data Valid Data Valid (ASYNCHRONOUS 4 PAGE READ CYCLE) 1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tCHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 3. In asynchronous 4 page read cycle, Clock, ADV and WAIT signals are ignored. Table 20. ASYNCHRONOUS PAGE READ AC CHARACTERISTICS Speed Symbol tRC Units Min Max 70 - ns Speed Symbol Units Min Max tOH 3 - ns ns tAA - 70 ns tOLZ 5 - tPC 25 - ns tBLZ 5 - ns tPA - 20 ns tLZ 10 - ns tCO - 70 ns tCHZ 0 12 ns tBA - 35 ns tBHZ 0 12 ns tOE - 35 ns tOHZ 0 12 ns - 22 - Revision 1.0 January 2005 K1B6416B6C UtRAM ASYNCHRONOUS WRITE TIMING WAVEFORM Fig.17 TIMING WAVEFORM OF WRITE CYCLE(1)(MRS=VIH, OE=VIH, WAIT=High-Z, WE Controlled) tWC tWC Address tAW tCW tWR tCSHP(A) tWR tAW tCW CS tBW tBW UB, LB tWHP tWP WE tWP tAS tAS tDH tDW Data Valid tDH tDW Data Valid Data in Data out High-Z High-Z (ASYNCHRONOUS WRITE CYCLE - WE Controlled) 1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high or WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high. 5. In asynchronous write cycle, Clock, ADV and WAIT signals are ignored. 6. Condition for continuous write operation over 50 times : tWP(min)=70ns Table 21. ASYNCHRONOUS WRITE AC CHARACTERISTICS(WE Controlled) Speed Symbol Units Min Max tWC 70 - ns tCW 60 - ns tAW 60 - ns tBW 60 - ns - ns tWP 55 1) Speed Symbol Units Min Max tAS 0 - ns tWR 0 - ns tDW 30 - ns tDH 0 - ns tCSHP(A) 10 - ns 1. tWP(min)=70ns for continuous write operation over 50 times. - 23 - Revision 1.0 January 2005 K1B6416B6C UtRAM ASYNCHRONOUS WRITE TIMING WAVEFORM Fig.18 TIMING WAVEFORM OF WRITE CYCLE(2)(MRS=VIH, OE=VIH, WAIT=High-Z, UB & LB Controlled) tWC Address tWR tCW CS tAW tBW UB, LB tAS tWP WE tDH tDW Data Valid Data in High-Z Data out High-Z (ASYNCHRONOUS WRITE CYCLE - UB & LB Controlled) 1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high or WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high. 5. In asynchronous write cycle, Clock, ADV and WAIT signals are ignored. Table 22. ASYNCHRONOUS WRITE AC CHARACTERISTICS(UB & LB Controlled) Speed Symbol Units Speed Symbol Units Min Max tWC 70 - ns tAS tCW 60 - ns tWR 0 - ns tAW 60 - ns tDW 30 - ns tBW 60 - ns tDH 0 - ns - ns tWP 55 1) Min Max 0 - ns 1. tWP(min)=70ns for continuous write operation over 50 times. - 24 - Revision 1.0 January 2005 K1B6416B6C UtRAM ASYNCHRONOUS WRITE TIMING WAVEFORM in SYNCHRONOUS MODE Fig.19 TIMING WAVEFORM OF WRITE CYCLE(Address Latch Type)(MRS=VIH, OE=VIH, WAIT=High-Z, WE Controlled) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CLK tADV ADV tAS(A) tAH(A) Address Valid tCSS(A) tCW CS tAW tBW UB, LB tWLRL tWP WE tAS tDW Data in tDH Data Valid Read Latency 5 High-Z High-Z Data out (ADDRESS LATCH TYPE ASYNCHRONOUS WRITE CYCLE - WE Controlled) 1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for word operation. A write ends at the earliest transition when CS goes high or WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tAW is measured from the address valid to the end of write. In this address latch type write timing, tWC is same as tAW. 3. tCW is measured from the CS going low to the end of write. 4. tBW is measured from the UB and LB going low to the end of write. 5. Clock input does not have any affect to the write operation if the parameter tWLRL is met. Table 23. ASYNCH. WRITE IN SYNCH. MODE AC CHARACTERISTICS(Address Latch Type, WE Controlled) Speed Symbol Units Speed Symbol Min Max tADV 7 - ns tBW Units Min Max 60 - ns tAS(A) 0 - ns tWP 55 - ns tAH(A) 7 - ns tWLRL 1 - clock tCSS(A) 10 - ns tAS 0 - ns tCW 60 - ns tDW 30 - ns tAW 60 - ns tDH 0 - ns 1) 1. tWP(min)=70ns for continuous write operation over 50 times. - 25 - Revision 1.0 January 2005 K1B6416B6C UtRAM ASYNCHRONOUS WRITE TIMING WAVEFORM in SYNCHRONOUS MODE Fig.20 TIMING WAVEFORM OF WRITE CYCLE(Address Latch Type)(MRS=VIH, OE=VIH, WAIT=High-Z, UB & LB Controlled) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CLK tADV ADV tAS(A) tAH(A) Address Valid tCSS(A) tCW CS tAW tBW UB, LB tAS tWLRL tWP WE tDW Data in tDH Data Valid Read Latency 5 High-Z High-Z Data out (ADDRESS LATCH TYPE ASYNCHRONOUS WRITE CYCLE - UB & LB Controlled) 1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for word operation. A write ends at the earliest transition when CS goes or and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tAW is measured from the address valid to the end of write. In this address latch type write timing, tWC is same as tAW. 3. tCW is measured from the CS going low to the end of write. 4. tBW is measured from the UB and LB going low to the end of write. 5. Clock input does not have any affect to the write operation if the parameter tWLRL is met. Table 24. ASYNCH. WRITE IN SYNCH. MODE AC CHARACTERISTICS(Address Latch Type, UB & LB Controlled) Speed Symbol Units Min Max Speed Symbol Units Min Max tADV 7 - ns tBW 60 - tAS(A) 0 - ns tWP 551) - ns tAH(A) 7 - ns tWLRL 1 - clock tCSS(A) 10 - ns tAS 0 - ns tCW 60 - ns tDW 30 - ns tAW 60 - ns tDH 0 - ns ns 1. tWP(min)=70ns for continuous write operation over 50 times. - 26 - Revision 1.0 January 2005 K1B6416B6C UtRAM ASYNCHRONOUS WRITE TIMING WAVEFORM in SYNCHRONOUS MODE Fig.21 TIMING WAVEFORM OF WRITE CYCLE(Low ADV Type)(MRS=VIH, OE=VIH, WAIT=High-Z, WE Controlled) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CLK ADV tWC Address tWR tCW CS tAW tBW UB, LB tWLRL WE tWP tAS tDH tDW Data Valid Data in Read Latency 5 Data out High-Z High-Z (LOW ADV TYPE WRITE CYCLE - WE Controlled) 1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high or WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high. 5. Clock input does not have any affect to the write operation if the parameter tWLRL is met. Table 25. ASYNCH. WRITE IN SYNCH. MODE AC CHARACTERISTICS(Low ADV Type, WE Controlled) Speed Symbol Units Min Max tWC 70 - ns tCW 60 - ns tAW 60 - tBW 60 tWP 551) Speed Symbol Units Min Max tWLRL 1 - clock tAS 0 - ns ns tWR 0 - ns - ns tDW 30 - ns - ns tDH 0 - ns 1. tWP(min)=70ns for continuous write operation over 50 times. - 27 - Revision 1.0 January 2005 K1B6416B6C UtRAM ASYNCHRONOUS WRITE TIMING WAVEFORM in SYNCHRONOUS MODE Fig.22 TIMING WAVEFORM OF WRITE CYCLE(Low ADV Type)(MRS=VIH, OE=VIH, WAIT=High-Z, UB & LB Controlled) 0 1 2 3 4 5 6 7 8 10 9 11 12 13 14 CLK ADV tWC Address tWR tCW CS UB, LB tAW tBW tAS tWLRL tWP WE tDH tDW Data Valid Data in Read Latency 5 Data out High-Z High-Z (LOW ADV TYPE WRITE CYCLE - UB & LB Controlled) 1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high or WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high. 5. Clock input does not have any affect to the write operation if the parameter tWLRL is met. Table 26. ASYNCH. WRITE IN SYNCH. MODE AC CHARACTERISTICS(Low ADV Type, UB & LB Controlled) Speed Symbol Units Min Max tWC 70 - ns tCW 60 - tAW 60 - tBW 60 tWP 551) Speed Symbol Units Min Max tWLRL 1 - clock ns tAS 0 - ns ns tWR 0 - ns - ns tDW 30 - ns - ns tDH 0 - ns 1. tWP(min)=70ns for continuous write operation over 50 times. - 28 - Revision 1.0 January 2005 K1B6416B6C UtRAM ASYNCHRONOUS WRITE TIMING WAVEFORM in SYNCHRONOUS MODE Fig.23 TIMING WAVEFORM OF MULTIPLE WRITE CYCLE(Low ADV Type)(MRS=VIH, OE=VIH, WAIT=High-Z, WE Controlled) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CLK ADV tWC tWC Address tWR tAW tCW tWR tAW tCW CS tBW tBW UB, LB tWHP tWP WE tWP tAS tAS tDH tDW Data Valid tDH tDW Data Valid Data in Data out High-Z High-Z (LOW ADV TYPE MULTIPLE WRITE CYCLE) 1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high or WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high. 5. Clock input does not have any affect to the asynchronous multiple write operation if tWHP is shorter than (Read Latency - 1) clock duration. 6. tWP(min)=70ns for continuous write operation over 50 times. Table 27. ASYNCH. WRITE IN SYNCH. MODE AC CHARACTERISTICS(Low ADV Type Multiple Write, WE Controlled) Speed Symbol Units Min Max Speed Symbol Units Min Max tWC 70 - ns tWHP 5ns Latency-1 clock - tCW 60 - ns tAS 0 - ns tAW 60 - ns tWR 0 - ns tBW 60 - ns tDW 30 - ns tWP 551) - ns tDH 0 - ns 1. tWP(min)=70ns for continuous write operation over 50 times. - 29 - Revision 1.0 January 2005 K1B6416B6C UtRAM Figure 24. AC Output Load Circuit AC OPERATING CONDITIONS Vtt=0.5 x VCC TEST CONDITIONS(Test Load and Test Input/Output Reference) 50Ω Input pulse level: 0.2 to VCC-0.2V Input rising and falling time: 3ns Input and output reference voltage: 0.5 x VCC Output load: CL=30pF Dout Z0=50Ω 30pF Table 28. SYNCHRONOUS AC CHARACTERISTICS (VCC=1.7~2.0V, TA=-40 to 85°C, Maximum Main Clock Frequency=66MHz) Parameter List Speed Symbol Min Burst Operation (Common) Burst Read Operation Burst Write Operation Units Max Clock Cycle Time T 15 200 ns Burst Cycle Time tBC - 2500 ns Address Set-up Time to ADV Falling(Burst) tAS(B) 0 - ns Address Hold Time from ADV Rising(Burst) tAH(B) 7 - ns ADV Setup Time tADVS 5 - ns ADV Hold Time tADVH 7 - ns CS Setup Time to Clock Rising(Burst) tCSS(B) 5 - ns Burst End to New ADV Falling tBEADV 7 - ns Burst Stop to New ADV Falling tBSADV 12 - ns CS Low Hold Time from Clock tCSLH 7 - ns CS High Pulse Width tCSHP 5 - ns ADV High Pulse Width tADHP 5 - ns Chip Select to WAIT Low tWL - 10 ns ADV Falling to WAIT Low tAWL - 10 ns Clock to WAIT High tWH - 12 ns Chip De-select to WAIT High-Z tWZ - 12 ns UB, LB Enable to End of Latency Clock tBEL 1 - Clock Output Enable to End of Latency Clock tOEL 1 - Clock UB, LB Valid to Low-Z Output tBLZ 5 - ns Output Enable to Low-Z Output tOLZ 5 - ns ns Latency Clock Rising Edge to Data Output tCD - 10 Output Hold tOH 3 - ns Burst End Clock to Output High-Z tHZ - 12 ns Chip De-select to Output High-Z tCHZ - 12 ns Output Disable to Output High-Z tOHZ - 12 ns UB, LB Disable to Output High-Z tBHZ - 12 ns WE Set-up Time to Command Clock tWES 5 - ns WE Hold Time from Command Clock tWEH 5 - ns WE High Pulse Width tWHP 5 - ns UB, LB Set-up Time to Clock tBS 5 - ns UB, LB Hold Time from Clock tBH 5 - ns Byte Masking Set-up Time to Clock tBMS 7 - ns Byte Masking Hold Time from Clock tBMH 7 - ns Data Set-up Time to Clock tDS 5 - ns Data Hold Time from Clock tDHC 3 - ns - 30 - Revision 1.0 January 2005 K1B6416B6C UtRAM SYNCHRONOUS BURST OPERATION TIMING WAVEFORM Fig.25 TIMING WAVEFORM OF BASIC BURST OPERATION [Latency=5,Burst Length=4](MRS=VIH) 0 1 2 3 4 5 6 7 8 9 T 10 11 12 13 14 15 ∼ CLK tADVH tADVS ADV tBEADV tAS(B) Address tBEADV tAH(B) Valid Don’t Care Valid tCSS(B) tBC CS Data out Undefined Data in D0 D1 DQ0 DQ1 D2 D3 DQ2 Burst Command Clock DQ3 D0 Burst Read End Clock Burst Write End Clock Table 29. BURST OPERATION AC CHARACTERISTICS Speed Symbol T Units Min Max 15 200 ns Speed Symbol Units Min Max tAS(B) 0 - ns tBC - 2500 ns tAH(B) 7 - ns tADVS 5 - ns tCSS(B) 5 - ns tADVH 7 - ns tBEADV 7 - ns - 31 - Revision 1.0 January 2005 K1B6416B6C UtRAM SYNCHRONOUS BURST READ TIMING WAVEFORM Fig.26 TIMING WAVEFORM OF BURST READ CYCLE(1) [Latency=5,Burst Length=4,WP=Low enable](WE=VIH, MRS=VIH) - CS Toggling Consecutive Burst Read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 T ∼ CLK tADVH tADVS ADV tBEADV tAH(B) tAS(B) Address Valid Don’t Care Valid tCSS(B) tCSHP tBC CS tBHZ tBEL LB, UB tBLZ tOHZ tOEL OE tOLZ Latency 5 tCD Data out Undefined tWL WAIT tCHZ tHZ tOH DQ0 DQ1 DQ2 DQ3 tWZ tWH tWH tWL High-Z (SYNCHRONOUS BURST READ CYCLE - CS Toggling Consecutive Burst Read) 1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. 2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge) 3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 4. Burst Cycle Time(tBC) should not be over 2.5µs. Table 30. BURST READ AC CHARACTERISTICS(CS Toggling Consecutive Burst) Speed Symbol Units Min Max tCSHP 5 - ns tBEL 1 - clock tOEL 1 - clock tBLZ 5 - ns tOLZ 5 - ns tHZ - 12 tCHZ - 12 Speed Symbol Units Min Max tOHZ - 12 ns tBHZ - 12 ns tCD - 10 ns tOH 3 - ns tWL - 10 ns ns tWH - 12 ns ns tWZ - 12 ns - 32 - Revision 1.0 January 2005 K1B6416B6C UtRAM SYNCHRONOUS BURST READ TIMING WAVEFORM Fig.27 TIMING WAVEFORM OF BURST READ CYCLE(2) [Latency=5,Burst Length=4,WP=Low enable](WE=VIH, MRS=VIH) - CS Low Holding Consecutive Burst Read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 T ∼ CLK tADVH tADVS ADV tBEADV tAH(B) tAS(B) Address Valid Don’t Care Valid tCSS(B) tBC CS tBEL LB, UB tBLZ tOEL OE tOLZ Latency 5 tCD Data out Undefined tWL WAIT tOH DQ0 DQ1 tHZ DQ2 DQ3 tAWL tWH tWH High-Z (SYNCHRONOUS BURST READ CYCLE - CS Low Holding Consecutive Burst Read) 1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. 2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge) 3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 4. The consecutive multiple burst read operation with holding CS low is possible through issuing only new ADV and address. 5. Burst Cycle Time(tBC) should not be over 2.5µs. Table 31. BURST READ AC CHARACTERISTICS(CS Low Holding Consecutive Burst) Speed Symbol Units Min Max Speed Symbol Units Min Max tBEL 1 - clock tCD - 10 ns tOEL 1 - clock tOH 3 - ns tBLZ 5 - ns tWL - 10 ns tOLZ 5 - ns tAWL - 10 ns tHZ - 12 ns tWH - 12 ns - 33 - Revision 1.0 January 2005 K1B6416B6C UtRAM SYNCHRONOUS BURST READ TIMING WAVEFORM Fig.28 TIMING WAVEFORM OF BURST READ CYCLE(3) [Latency=5,Burst Length=4,WP=Low enable](WE=VIH, MRS=VIH) - Last Data Sustaining 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 T CLK tADVH tADVS ADV tAH(B) tAS(B) Address Valid Don’t Care tCSS(B) tBC CS tBEL LB, UB tBLZ tOEL OE tOLZ Latency 5 tOH tCD Data out Undefined tWL DQ0 DQ1 DQ2 DQ3 tWH High-Z WAIT (SYNCHRONOUS BURST READ CYCLE - Last Data Sustaining) 1. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge) 2. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 3. Burst Cycle Time(tBC) should not be over 2.5µs. Table 32. BURST READ AC CHARACTERISTICS(Last Data Sustaining) Speed Symbol Units Min Max Speed Symbol Units Min Max tBEL 1 - clock tCD - 10 ns tOEL 1 - clock tOH 3 - ns tBLZ 5 - ns tWL - 10 ns tOLZ 5 - ns tWH - 12 ns - 34 - Revision 1.0 January 2005 K1B6416B6C UtRAM SYNCHRONOUS BURST WRITE TIMING WAVEFORM Fig.29 TIMING WAVEFORM OF BURST WRITE CYCLE(1) [Latency=5,Burst Length=4,WP=Low enable](OE=VIH, MRS=VIH) - CS Toggling Consecutive Burst Write 0 1 2 3 4 5 6 7 8 T 9 10 11 12 13 ∼ CLK tADVH tADVS ADV tBEADV tAH(B) tAS(B) Address Valid Valid Don’t Care tCSS(B) tCSHP tBC CS tBS tBMS tBH tBMH LB, UB tWEH tWHP tWES WE tDS Latency 5 Data in D0 tWL tDHC tDHC D1 D2 Latency 5 D3 D0 tWZ tWH tWH tWL High-Z WAIT (SYNCHRONOUS BURST WRITE CYCLE - CS Toggling Consecutive Burst Write) 1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. 2. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 3. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge) 4. D2 is masked by UB and LB. 5. Burst Cycle Time(tBC) should not be over 2.5µs. Table 33. BURST WRITE AC CHARACTERISTICS(CS Toggling Consecutive Burst) Speed Symbol Units Min Max tCSHP 5 - ns tBS 5 - ns tBH 5 - ns Speed Symbol Units Min Max tWHP 5 - ns tDS 5 - ns tDHC 3 - ns tBMS 7 - ns tWL - 10 ns tBMH 7 - ns tWH - 12 ns tWES 5 - ns tWZ - 12 ns tWEH 5 - ns - 35 - Revision 1.0 January 2005 K1B6416B6C UtRAM SYNCHRONOUS BURST WRITE TIMING WAVEFORM Fig.30 TIMING WAVEFORM OF BURST WRITE CYCLE(2) [Latency=5,Burst Length=4,WP=Low enable](OE=VIH, MRS=VIH) - CS Low Holding Consecutive Burst Write 0 1 2 3 4 5 6 7 8 T 9 10 11 12 13 ∼ CLK tADVH tADVS ADV tBEADV tAH(B) tAS(B) Address Valid Valid Don’t Care tCSS(B) tBC CS tBS tBMS tBH tBMH LB, UB tWEH tWHP tWES WE tDS Latency 5 Data in D0 tWL tDHC tDHC D1 D2 Latency 5 D3 D0 tAWL tWH tWH High-Z WAIT (SYNCHRONOUS BURST WRITE CYCLE - CS Low Holding Consecutive Burst Write) 1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. 2. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 3. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge) 4. D2 is masked by UB and LB. 5. The consecutive multiple burst read operation with holding CS low is possible through issuing only new ADV and address. 6. Burst Cycle Time(tBC) should not be over 2.5µs. Table 34. BURST WRITE AC CHARACTERISTICS(CS Low Holding Consecutive Burst) Speed Symbol Units Min Max Speed Symbol Units Min Max tBS 5 - ns tWHP 5 - ns tBH 5 - ns tDS 5 - ns tBMS 7 - ns tDHC 3 - ns tBMH 7 - ns tWL - 10 ns tWES 5 - ns tAWL - 10 ns tWEH 5 - ns tWH - 12 ns - 36 - Revision 1.0 January 2005 K1B6416B6C UtRAM SYNCHRONOUS BURST READ STOP TIMING WAVEFORM Fig.31 TIMING WAVEFORM OF BURST READ STOP by CS [Latency=5,Burst Length=4,WP=Low enable](WE=VIH, MRS=VIH) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 T ∼ CLK tADVH tADVS ADV tBSADV tAH(B) tAS(B) Address Valid Don’t Care Valid tCSHP tCSS(B) tCSLH CS tBEL LB, UB tBLZ tOEL OE tOLZ Latency 5 tOH tCD Data Undefined DQ0 tCHZ DQ1 tWZ tWL tWL tWH High-Z WAIT High-Z (SYNCHRONOUS BURST READ STOP TIMING) 1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBSADV should be met 2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge) 3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 4. The burst stop operation should not be repeated for over 2.5µs. Table 35. BURST READ STOP AC CHARACTERISTICS Speed Symbol Units Min Max tBSADV 12 - ns tCSLH 7 - ns tCSHP 5 - ns Speed Symbol Units Min Max tCD - 10 tOH 3 - ns tCHZ - 12 ns ns tBEL 1 - clock tWL - 10 ns tOEL 1 - clock tWH - 12 ns tBLZ 5 - ns tWZ - 12 ns tOLZ 5 - ns - 37 - Revision 1.0 January 2005 K1B6416B6C UtRAM SYNCHRONOUS BURST WRITE STOP TIMING WAVEFORM Fig.32 TIMING WAVEFORM OF BURST WRITE STOP by CS [Latency=5,Burst Length=4,WP=Low enable](OE=VIH, MRS=VIH) 0 1 2 3 4 5 6 7 T 8 9 10 11 12 13 D0 D1 D2 ∼ CLK tADVH tADVS ADV Address tBSADV tAH(B) tAS(B) Don’t Care Valid Valid tCSHP tCSS(B) tCSLH CS tBS tBH LB, UB tWHP tWEH tWES WE tDS tDHC Latency 5 Data in D0 Latency 5 D1 tWZ tWL tWL tWH High-Z WAIT tWH High-Z (SYNCHRONOUS BURST WRITE STOP TIMING) 1. The new burst operation can be issued only after the previous burst operation is finished. 2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge) 3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 4. The burst stop operation should not be repeated for over 2.5µs. Table 36. BURST WRITE STOP AC CHARACTERISTICS Speed Symbol Units Min Max tBSADV 12 - ns Speed Symbol Units Min Max tWHP 5 - ns ns tCSLH 7 - ns tDS 5 - tCSHP 5 - ns tDHC 3 - ns tBS 5 - ns tWL - 10 ns tBH 5 - ns tWH - 12 ns tWES 5 - ns tWZ - 12 ns tWEH 5 - ns - 38 - Revision 1.0 January 2005 K1B6416B6C UtRAM SYNCHRONOUS BURST READ SUSPEND TIMING WAVEFORM Fig.33 TIMING WAVEFORM OF BURST READ SUSPEND CYCLE(1) [Latency=5,Burst Length=4,WP=Low enable](WE=VIH, MRS=VIH) 0 1 2 3 4 5 6 7 8 9 10 11 T ∼ CLK tADVH tADVS ADV tAH(B) tAS(B) Address Valid Don’t Care tCSS(B) tBC CS tBEL LB, UB tBLZ tOEL OE tOLZ Latency 5 Data out Undefined tWL WAIT tOHZ tCD tOLZ tOH tHZ DQ0 DQ1 High-Z DQ1 DQ2 DQ3 tWZ tWH High-Z (SYNCHRONOUS BURST READ SUSPEND CYCLE) 1. If clock input is halted during burst read operation, the data out will be suspended. During the burst read suspend period, OE high drives data out to high-Z. If clock input is resumed, the suspended data will be out first. 2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge) 3. During suspend period, OE high drives DQ to High-Z and OE low drives DQ to Low-Z. If OE stays low during suspend period, the previous data will be sustained. 4. Burst Cycle Time(tBC) should not be over 2.5µs. Table 37. BURST READ SUSPEND AC CHARACTERISTICS Speed Symbol Units Min Max Speed Symbol Units Min Max tBEL 1 - clock tHZ - 12 ns tOEL 1 - clock tOHZ - 12 ns tBLZ 5 - ns tWL - 10 ns tOLZ 5 - ns tWH - 12 ns tCD - 10 ns tWZ - 12 ns tOH 3 - ns - 39 - Revision 1.0 January 2005 K1B6416B6C UtRAM TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE Fig.34 SYNCH. BURST READ to ASYNCH. WRITE(Address Latch Type) TIMING WAVEFORM [Latency=5, Burst Length=4](MRS=VIH) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 T CLK tADVH tADVS ADV tADV tAH(A) tBEADV tAH(B) tAS(B) Address Valid tAS(A) Don’t Care tCSS(B) Valid tBC tAW tCSS(A) tCW CS tWLRL tWP WE tAS tOEL OE tBEL tBW LB, UB tDW Data Valid Data in Latency 5 Data out tDH tCD High-Z tOH tHZ High-Z DQ0 DQ1 DQ2 DQ3 tWL tWZ tWH WAIT High-Z High-Z Read Latency 5 (SYNCHRONOUS BURST READ CYCLE) 1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. 2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge) 3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 4. Burst Cycle Time(tBC) should not be over 2.5µs. (ADDRESS LATCH TYPE ASYNCHRONOUS WRITE CYCLE - WE controlled) 1. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clock in write timing is just a reference to WE low going for proper write operation. Table 38. BURST READ to ASYNCH. WRITE(Address Latch Type) AC CHARACTERISTICS Speed Symbol tBEADV Units Min Max 7 - ns Speed Symbol tWLRL - 40 - Units Min Max 1 - clock Revision 1.0 January 2005 K1B6416B6C UtRAM TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE Fig.35 SYNCH. BURST READ to ASYNCH. WRITE(Low ADV Type) TIMING WAVEFORM [Latency=5, Burst Length=4](MRS=VIH) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 T CLK tADVH tADVS ADV Address tBEADV tAH(B) tAS(B) Valid Don’t Care Valid Address tBC CS tWR tAW tCW tCSS(B) tWLRL WE tWP tAS tOEL OE tBW tBEL LB, UB tDW Data Valid Data in Latency 5 Data out tDH tCD High-Z tOH tHZ High-Z DQ0 DQ1 DQ2 DQ3 tWL tWZ tWH WAIT High-Z High-Z Read Latency 5 (SYNCHRONOUS BURST READ CYCLE) 1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. 2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge) 3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 4. Burst Cycle Time(tBC) should not be over 2.5µs. (LOW ADV TYPE ASYNCHRONOUS WRITE CYCLE - WE controlled) 1. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clock in write timing is just a reference to WE low going for proper write operation. Table 39. BURST READ to ASYNCH. WRITE(Low ADV Type) AC CHARACTERISTICS Speed Symbol tBEADV Units Min Max 7 - ns Speed Symbol tWLRL - 41 - Units Min Max 1 - clock Revision 1.0 January 2005 K1B6416B6C UtRAM TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE Fig.36 ASYNCH. WRITE(Address Latch Type) to SYNCH. BURST READ TIMING WAVEFORM [Latency=5, Burst Length=4](MRS=VIH) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 T CLK tADVH tADVS ADV tADV tAH(A) tAS(A) Address tAH(B) tAS(B) Don’t Care Valid Don’t Care Valid tAW tCSS(A) CS tBC tCSS(B) tCW tWLRL tWP WE tAS tOEL OE tBW tBEL LB, UB tDW tDH Data Valid Data in Latency 5 High-Z Read Latency 5 Data out tCD tOH tHZ DQ0 DQ1 DQ2 DQ3 tWL tWH tWZ High-Z WAIT (SYNCHRONOUS BURST READ CYCLE) 1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. 2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge) 3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 4. Burst Cycle Time(tBC) should not be over 2.5µs. (ADDRESS LATCH TYPE ASYNCHRONOUS WRITE CYCLE - WE controlled) 1. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clock in write timing is just a reference to WE low going for proper write operation. Table 40. ASYNCH. WRITE(Address Latch Type) to BURST READ AC CHARACTERISTICS Speed Symbol tWLRL Units Min Max 1 - Speed Symbol Min Units Max clock - 42 - Revision 1.0 January 2005 K1B6416B6C UtRAM TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE Fig.37 ASYNCH. WRITE(Low ADV Type) to SYNCH. BURST READ TIMING WAVEFORM [Latency=5, Burst Length=4](MRS=VIH) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 T CLK tADVH tADVS tADHP ADV tAH(B) tAS(B) tWC Address Valid Don’t Care Valid tAW tCW tWR tBC tCSS(B) CS tWLRL tWP WE tAS tOEL OE tBEL tBW LB, UB tDW tDH Data Valid Data in Latency 5 tCD High-Z Data out tOH tHZ DQ0 DQ1 DQ2 DQ3 tWL tWH tWZ High-Z WAIT Read Latency 5 (SYNCHRONOUS BURST READ CYCLE) 1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. 2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge) 3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 4. Burst Cycle Time(tBC) should not be over 2.5µs. (LOW ADV TYPE ASYNCHRONOUS WRITE CYCLE - WE controlled) 1. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clock in write timing is just a reference to WE low going for proper write operation. Table 41. ASYNCH. WRITE(Low ADV Type) to BURST READ AC CHARACTERISTICS Speed Symbol tWLRL Units Min Max 1 - clock Speed Symbol tADHP - 43 - Units Min Max 5 - ns Revision 1.0 January 2005 K1B6416B6C UtRAM TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE Fig.38 SYNCH. BURST READ to SYNCH. BURST WRITE TIMING WAVEFORM [Latency=5, Burst Length=4](MRS=VIH) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 T CLK tADVH tADVS ADV tBEADV tAH(B) tAS(B) Address Valid tAS(B) Don’t Care tCSS(B) tAH(B) Valid tBC tBC tCSS(B) CS tWES tWEH WE tOEL OE tBS tBH tBEL LB, UB tDS Latency 5 High-Z Data in Latency 5 Data out tOH tWZ tWH D1 D2 D3 tHZ High-Z DQ0 DQ1 DQ2 DQ3 tWL WAIT tCD High-Z tDHC D0 tWL tWH tWZ High-Z (SYNCHRONOUS BURST READ & WRITE CYCLE) 1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. 2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge) 3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 4. Burst Cycle Time(tBC) should not be over 2.5µs. Table 42. BURST READ to BURST WRITE AC CHARACTERISTICS Speed Symbol tBEADV Units Min Max 7 - Speed Symbol Min Units Max ns - 44 - Revision 1.0 January 2005 K1B6416B6C UtRAM TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE Fig.39 SYNCH. BURST WRITE to SYNCH. BURST READ TIMING WAVEFORM [Latency=5, Burst Length=4](MRS=VIH) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 T CLK tADVH tADVS ADV tBEADV tAH(B) tAS(B) Address Valid tAS(B) Don’t Care tCSS(B) tAH(B) Valid tBC tBC tCSS(B) CS tWES tWEH WE tOEL OE tBS tBH tBEL LB, UB tDS Latency 5 tDHC D0 Data in D1 D2 High-Z D3 Latency 5 Data out tOH tHZ DQ0 DQ1 DQ2 DQ3 tWZ tWH tWL WAIT tCD High-Z tWH tWL High-Z (SYNCHRONOUS BURST READ & WRITE CYCLE) 1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. 2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge) 3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 4. Burst Cycle Time(tBC) should not be over 2.5µs. Table 43. BURST WRITE to BURST READ AC CHARACTERISTICS Speed Symbol tBEADV Units Min Max 7 - Speed Symbol Min Units Max ns - 45 - Revision 1.0 January 2005 K1B6416B6C UtRAM PACKAGE DIMENSION Unit: millimeters 54 BALL FINE PITCH BGA(0.75mm ball pitch) Top View Bottom View B B1 B 6 5 4 3 2 1 A #A1 B C E C C1 C D C1/2 F G H J B/2 Detail A Side View A Y 0.55/Typ. E1 E 0.35/Typ. E2 D C Min Typ Max A - 0.75 - B 5.90 6.00 6.10 1. Bump counts: 54(9 row x 6 column) B1 - 3.75 - 2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.) C 7.90 8.00 8.10 C1 - 5.25 - D 0.40 0.45 0.50 E - 0.90 1.00 E1 - 0.55 - E2 0.30 0.35 0.40 Y - - 0.10 Notes. 3. All tolerence are ±0.050 unless specified beside figures. 4. Typ : Typical 5. Y is coplanarity: 0.10(Max) - 46 - Revision 1.0 January 2005